WO2021253486A1 - 显示装置 - Google Patents

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Publication number
WO2021253486A1
WO2021253486A1 PCT/CN2020/099103 CN2020099103W WO2021253486A1 WO 2021253486 A1 WO2021253486 A1 WO 2021253486A1 CN 2020099103 W CN2020099103 W CN 2020099103W WO 2021253486 A1 WO2021253486 A1 WO 2021253486A1
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WO
WIPO (PCT)
Prior art keywords
signal
rising edge
frame period
generated
data enable
Prior art date
Application number
PCT/CN2020/099103
Other languages
English (en)
French (fr)
Inventor
罗斯建
吴常志
许育民
Original Assignee
厦门天马微电子有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 厦门天马微电子有限公司 filed Critical 厦门天马微电子有限公司
Priority to US17/443,240 priority Critical patent/US11676521B2/en
Publication of WO2021253486A1 publication Critical patent/WO2021253486A1/zh
Priority to US18/139,054 priority patent/US20230267866A1/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • This application relates to the field of display technology, for example, to a display device.
  • LCD liquid crystal display
  • OLED organic light emitting diode
  • the related art display device includes a display area and a frame area around the display area.
  • the gate drive circuit integrated in the frame area controls the opening or closing of the thin film transistor, and when the thin film transistor is turned on, the source drive circuit integrated in the frame area provides grayscale signals to the pixels in the display area. Control the row of pixels to display the screen.
  • the timing controller generates the gate control signal according to the data enable signal, the gate control signal may be abnormal.
  • the present application provides a display device, which avoids the generation of abnormal gate control signals.
  • An embodiment of the present application provides a display device, including:
  • a gate driving circuit electrically connected to the plurality of scan lines
  • the timing controller is electrically connected to the gate drive circuit, and is configured to receive a plurality of data enable signals in each frame period of a plurality of frame periods, generate a gate control signal according to the data enable signal, and The gate control signal is provided to the gate drive circuit; the gate drive circuit is configured to provide a scan signal to the plurality of scan lines according to the gate control signal; the gate control signal includes A start signal, a first clock signal, and a second clock signal;
  • each frame period includes a valid period and a vertical blanking period, and the data enable signal is only located in the valid period;
  • the timing controller generates the rising edge of the start signal in the vertical blanking period of the N-1th frame period, and the falling edge of the last data enable signal of the N-1th frame period and
  • the time interval between the rising edges of the start signal is T, T is greater than 0 and less than the first preset time interval or T is greater than 0 and equal to the first preset time interval, and the first preset time interval is less than all The vertical blanking period or,
  • the timing controller generates the rising edge and the falling edge of the start signal in the time interval for forming the rising edge and the falling edge of the first data enable signal of the Nth frame period;
  • N 2.
  • FIG. 1 is a schematic diagram of a top view structure of a display device provided by an embodiment of the application
  • FIG. 2 is a schematic diagram of a gate driving circuit provided by an embodiment of the application.
  • FIG. 3 is a schematic diagram of a shift register provided by an embodiment of the application.
  • Figure 4 is a drive timing diagram of the display device in a related design
  • FIG. 5 is a driving timing diagram of a display device provided by an embodiment of the application.
  • FIG. 6 is a driving timing diagram of another display device provided by an embodiment of the application.
  • FIG. 7 is a driving timing diagram of another display device provided by an embodiment of the application.
  • FIG. 8 is a driving timing diagram of another display device provided by an embodiment of the application.
  • FIG. 9 is a driving timing diagram of another display device provided by an embodiment of the application.
  • FIG. 10 is a driving timing diagram of another display device provided by an embodiment of the application.
  • FIG. 11 is a driving timing diagram of another display device provided by an embodiment of the application.
  • FIG. 12 is a driving timing diagram of another display device provided by an embodiment of the application.
  • FIG. 13 is a schematic diagram of another gate driving circuit provided by an embodiment of the application.
  • FIG. 14 is a driving timing diagram of another display device provided by an embodiment of the application.
  • 15 is a driving timing diagram of another display device provided by an embodiment of the application.
  • FIG. 16 is a driving timing diagram of another display device provided by an embodiment of the application.
  • FIG. 17 is a driving timing diagram of another display device provided by an embodiment of the application.
  • FIG. 18 is a schematic top view of another display device according to an embodiment of the application.
  • FIG. 1 is a schematic diagram of a top view structure of a display device provided by an embodiment of the application
  • FIG. 2 is a schematic diagram of a gate driving circuit provided by an embodiment of the application
  • FIG. 3 is a shift register provided by an embodiment of the application
  • the display device includes a plurality of scan lines 21, a gate driving circuit 30, and a timing controller 40.
  • the gate driving circuit 30 is electrically connected to the plurality of scan lines 21 and is configured to provide scan signals to the plurality of scan lines 21.
  • the timing controller 40 is electrically connected to the gate drive circuit 30 and is configured to receive a data enable signal, generate a gate control signal according to the data enable signal, and provide the gate control signal to the gate drive circuit 30.
  • the gate control signal includes a start signal, a first clock signal, and a second clock signal.
  • Each frame period includes a valid period and a vertical blanking period, and the data enable signal is only located in the valid period.
  • the gate driving circuit 30 includes a start signal line 310 for transmitting the start signal STV, a first clock signal line 311 for transmitting the first clock signal CKV1, and a first clock signal line 311 for transmitting the first clock signal CKV1.
  • the second clock signal line 312 of the two clock signal CKV2 and a plurality of cascaded shift registers 320, each stage of shift register 320 includes a shift input terminal IN, an output terminal OUT, a first signal terminal CLK1, a second signal terminal CLK2 And the cascade signal terminal NXT.
  • the plurality of shift registers 320 includes a first dummy shift register Dummy1 and a first stage scanning shift register 321, and the first stage scanning shift register 321 is cascaded with the first dummy shift register Dummy1.
  • the first signal terminal CLK1 of the first dummy shift register Dummy1 is connected to the second clock signal line 312, and the second signal terminal CLK2 of the first dummy shift register Dummy1 is connected to the first clock signal line 311.
  • the first signal terminal CLK1 of the scanning shift register 321 of the first stage is connected to the first clock signal line 311, and the second signal terminal CLK2 of the scanning shift register 321 of the first stage is connected to the second clock signal line 312.
  • the shift input terminal IN of the first dummy shift register Dummy1 is connected to the start signal line 310, and the shift input terminal IN of the first stage scanning shift register 321 is connected to the cascade signal terminal NXT of the first dummy shift register Dummy1 .
  • the gate driving circuit 30 may further include a reset signal line 313 for transmitting a reset signal.
  • Each stage of the shift register 320 may also include a reset terminal RST, and the reset terminals RST of all shift registers 320 are electrically connected to the reset signal line 313.
  • the circuit structure of the shift register 320 may include, for example, a latch circuit 3201, a NAND circuit 3202, and a buffer circuit 3203. The latch circuit 3201 and the NAND circuit 3202 are electrically connected.
  • the NAND circuit 3202 and the buffer circuit 3203 are electrically connected.
  • the latch circuit 3201 includes a shift input terminal IN and a first signal terminal CLK1.
  • the output terminal of the latch circuit 3201 is the cascade signal terminal NXT (that is, the input terminal electrically connected to the NAND circuit 3202 and the latch circuit 3201), and the other input terminal of the NAND circuit 3202 is the second signal terminal CLK2.
  • the input signals of the two input terminals of the circuit 3202 are NANDed in the NAND circuit 3202.
  • the output terminal of the NAND circuit 3202 is electrically connected to the input terminal of the buffer circuit 3203, and the output terminal of the buffer circuit 3203 is the output terminal OUT of the shift register 320.
  • the circuit structure of the shift register 320 may further include a reset circuit 3204, the input terminal of the reset circuit 3204 is the reset terminal RST, and the output terminal of the reset circuit 3204 is electrically connected to the latch circuit 3201.
  • the start signal input from the shift input terminal IN is The STV is latched into the latch circuit 3201, and the cascade signal terminal NXT changes from low to high at the rising edge of the second clock signal CKV2, and continues until the next high level of the second clock signal CKV2 rises along.
  • the signal input from the cascade signal terminal NXT and the first clock signal CKV1 input from the second signal terminal CLK2 are NANDed in the NAND circuit 3202, and the result of the NAND operation is output to the buffer circuit 3203.
  • the output terminal OUT outputs, and the buffer circuit 3203 is used to enhance the driving capability of the signal.
  • the working process of the scanning shift register 321 of the first stage is similar to that of the first dummy shift register Dummy1, except that the signal input from the cascade signal terminal NXT in the scanning shift register 321 of the first stage is input to the second signal terminal CLK2.
  • the second clock signal CKV2 is NANDed in the NAND circuit 3202, which will not be repeated here.
  • the display device further includes a substrate 10, a plurality of data lines 22 and a driving chip 50.
  • the plurality of scan lines 21, the plurality of data lines 22, the gate driving circuit 30 and the timing controller 40 are located on the same side of the substrate 10.
  • the plurality of scan lines 21 and the plurality of data lines 22 are insulated and crossed, and the plurality of scan lines 21 and the plurality of data lines 22 intersect to define a plurality of pixels 20.
  • a plurality of pixels 20 are arranged in an array in the display area AA.
  • the timing controller 40 is integrated in the driving chip 50, and the driving chip 50 may further include a source driving circuit (not shown in FIG. 1) for providing gray-scale voltage to the data line 22. In other embodiments, the timing controller 40 may also be provided outside the driving chip 50, which is not limited in this application.
  • FIG. 4 is a driving timing diagram of the display device in a related design.
  • the timing controller 40 generates the rising and falling edges of the start signal STV in the vertical blanking period V-blanking of the N-1th frame period.
  • the rising edge of the start signal STV is close to the rising edge of the first data enable signal of the Nth frame period, and the falling edge of the start signal STV is generated when the rising edge of the first data enable signal of the Nth frame period is generated. . That is, the time when the rising edge of the start signal STV is generated is close to the time when the rising edge of the first data enable signal of the Nth frame period is generated.
  • the rising edge of the start signal STV cannot be accurately generated with reference to the data enable signal DE.
  • the rising edge of the start signal STV can only be estimated based on the width of the last data enable signal DE in the N-1th frame period.
  • the width of the last data enable signal DE of the N-1th frame period is T-last. After the 100th T-last time width is counted by the counter, the rising edge of the start signal STV is generated. Due to factors such as clock jitter, the width T-last of the last data enable signal DE in the N-1th frame period also fluctuates accordingly, causing the gate control signal to be normal in some time periods, but in other time periods abnormal.
  • the embodiment of the present application provides a display device, which can avoid the problem of "accurately estimating the rising edge of the start signal STV", that is, the embodiment of the present application avoids abnormalities by designing the start signal STV In the case of the gate control signal.
  • FIG. 5 is a driving timing diagram of a display device provided by an embodiment of the application.
  • the timing controller 40 generates the rising edge of the start signal STV in the vertical blanking period V-blanking of the N-1th frame period.
  • the time interval between the falling edge of the last data enable signal DE of the N-1th frame period and the rising edge of the start signal STV is T, T is greater than 0 and less than the first preset time interval or T is greater than 0
  • the first preset time interval is less than the vertical blanking period Among them, N ⁇ 2.
  • expressions such as “within”, “within”, and “within” include endpoint values, for example, the start signal is generated in the vertical blanking period V-blanking of the N-1th frame period
  • the rising edge of STV refers to when the falling edge of the last data enable signal DE of the N-1 frame period is generated and after the falling edge of the last data enable signal DE of the N-1 frame period is generated and The rising edge of the start signal STV is generated when the rising edge of the first data enable signal DE in the Nth frame period is generated and before the rising edge of the first data enable signal DE in the Nth frame period is generated.
  • the expressions “after”, “after”, “before”, and “before” refer to the sequence of time. For example, generating B after A means that A is generated first and then B is generated in chronological order. Generating B before A means that in chronological order, B is generated first and then A is generated.
  • FIG. 6 is a driving timing diagram of a display device provided by an embodiment of this application.
  • the timing controller 40 forms a time interval between the rising edge and the falling edge of the first data enable signal DE in the Nth frame period.
  • N the rising edge of the start signal STV is generated when the rising edge of the first data enable signal DE in the Nth frame period is generated, or the rising edge of the first data enable signal DE in the Nth frame period is generated.
  • the rising edge of the start signal STV is generated.
  • the falling edge of the start signal STV is generated when the falling edge of the first data enable signal DE in the Nth frame period is generated, or it is generated before the falling edge of the first data enable signal DE in the Nth frame period The falling edge of the start signal STV.
  • the gate driving circuit 30 includes a plurality of cascaded shift registers 320 , And the first shift register 320 can be set as the first dummy shift register Dummy1. After the first dummy shift register Dummy1, a plurality of scanning shift registers are cascaded.
  • the first shift register 320 after the first dummy shift register Dummy1 is the first stage scanning shift register 321, and the first stage scanning shift register 321 provides scanning signals to the first row of scanning lines 21.
  • a row of buffers can be provided inside the driver chip 50 to reduce costs.
  • the rise of the second data enable signal DE in the Nth frame period When the falling edge of the start signal is generated in the time interval between the edge and the falling edge, the line of data sent by the source driver circuit will be delayed to the rising edge and the falling edge of the third data enable signal DE in the Nth frame period to form the time interval It is sent out internally, causing the problem that the timing of the scan signal and the gray-scale signal are not synchronized.
  • the rising edge of the start signal STV can be generated in the vertical blanking period V-blanking of the N-1th frame period, and the last data enable signal of the N-1th frame period
  • the time interval between the falling edge of DE and the rising edge of the start signal STV is less than that of the vertical blanking period Therefore, the time interval between the falling edge of the last data enable signal DE of the N-1th frame period and the rising edge of the start signal STV is shorter than in the related design, even if the last data of the N-1th frame period is
  • the width of the energy signal DE fluctuates in the multi-frame period, which has little effect on the time of the rising edge of the start signal STV, so the problem of "accurately estimating the rising edge of the start signal STV" can be avoided.
  • the rising edge and the falling edge of the start signal STV may also be generated within the time interval for forming the rising edge and the falling edge of the first data enable signal DE in the Nth frame period, thereby starting
  • the rising edge of the start signal STV can be accurately generated with reference to the first data enable signal DE of the Nth frame period, so the problem of "accurately estimating the rising edge of the start signal STV" can be avoided.
  • the embodiment of the present application avoids the generation of abnormal gate control signals by designing the start signal STV.
  • the timing controller 40 when the timing controller 40 generates the rising edge of the start signal STV in the vertical blanking period V-blanking of the N-1th frame period, it uses the last data in the N-1th frame period.
  • the rising edge of the start signal STV is generated after the falling edge of the energy signal DE. That is to say, in time sequence, the falling edge of the last data enable signal DE of the N-1th frame period is generated first, and the falling edge of the last data enable signal DE of the N-1th frame period is generated for a period of time. After that, the rising edge of the start signal STV is generated.
  • the timing controller 40 when the timing controller 40 generates the rising edge of the start signal STV in the vertical blanking period V-blanking of the N-1th frame period, the falling edge of the start signal STV is at the N-1th frame period. Generated in the vertical blanking period V-blanking of the frame period.
  • the rising edge and the falling edge of the start signal STV are both generated in the vertical blanking period V-blanking of the N-1th frame period.
  • FIG. 7 is a driving timing diagram of another display device provided by an embodiment of the application.
  • the timing controller 40 generates the rise of the start signal STV in the vertical blanking period V-blanking of the N-1th frame period.
  • the falling edge of the start signal STV is generated in the time interval formed by the rising edge and the falling edge of the first data enable signal DE in the Nth frame period.
  • the falling edge of the start signal STV may be aligned with the rising edge of the first data enable signal DE of the Nth frame period, or the falling edge of the start signal STV may be aligned with the first edge of the Nth frame period.
  • the falling edge of the data enable signal DE is aligned, or the falling edge of the start signal STV can be located at the time when the rising edge of the first data enable signal DE of the Nth frame period is generated and the first data enable of the Nth frame period. Between the time when the falling edge of the energy signal DE is generated.
  • the falling edge of the start signal STV since the falling edge of the start signal STV is generated within the time interval for forming the rising edge and the falling edge of the first data enable signal DE in the Nth frame period, the falling edge of the start signal STV may be based on the first The first data enable signal DE of the N frame period is generated, which reduces the difficulty of controlling the falling edge of the start signal STV.
  • FIG. 8 is a driving timing diagram of another display device provided by an embodiment of the application.
  • the timing controller 40 generates the rise of the start signal STV in the vertical blanking period V-blanking of the N-1th frame period.
  • P second clock signals CKV2 are generated in the N-1th frame period.
  • the time interval between the falling edge of the last data enable signal DE of the N-1 frame period and the falling edge of the P-1 second clock signal CKV2 is T-start, where T is greater than T-start, and P ⁇ 2 .
  • the first P-1 of the P second clock signals CKV2 are generated first, and then the rising edge of the start signal STV is generated, so that the N-1th is completed before the rising edge of the start signal STV is generated. Scanning of the frame period.
  • the time interval between the falling edge of the last data enable signal DE in the N-1th frame period and the falling edge of the first second clock signal CKV2 is T- start is not a limitation to the embodiment of this application.
  • P 3, and when three second clock signals CKV2 are generated in the N-1th frame period, the falling edge of the last data enable signal DE in the N-1th frame period and the second The time interval between the falling edges of the second clock signal CKV2 is T-start, and T is greater than T-start.
  • P 10, when 10 second clock signals CKV2 are generated in the N-1th frame period, the falling edge of the last data enable signal DE in the N-1th frame period and the 9th The time interval between the falling edges of the second clock signal CKV2 is T-start, and T is greater than T-start.
  • FIG. 9 is a driving timing diagram of another display device provided by an embodiment of the application.
  • the timing controller 40 generates the rise of the start signal STV in the vertical blanking period V-blanking of the N-1th frame period.
  • the falling edge of the first clock signal CKV1 is generated when the falling edge of the first data enable signal DE of the Nth frame period is generated.
  • the rising edge of the clock signal CKV1 is generated in the time interval formed by the falling edge of the start signal STV and the rising edge of the first data enable signal DE of the Nth frame period.
  • the rising edge of the first clock signal CKV1 is generated when the falling edge of the start signal STV is generated, or the rising edge of the first clock signal CKV1 is generated by the first data enable signal DE of the Nth frame period.
  • the rising edge of the first clock signal CKV1 is generated, or the rising edge of the first clock signal CKV1 is generated between the generation time of the falling edge of the start signal STV and the generation time of the rising edge of the first data enable signal DE in the Nth frame period.
  • the first row scan line 21 The high-level time of the upper signal Gate_1 (that is, the signal transmitted by the output terminal OUT in the first-stage scanning shift register 321) will also be delayed to the third data enable signal DE, causing the gray-scale signal to be misaligned by one line.
  • the grayscale signals of one row are displayed in the pixels 20 of the second row.
  • the timing controller 40 When the timing controller 40 generates the rising edge of the start signal STV in the vertical blanking period V-blanking of the N-1th frame period, for the first first clock signal CKV1 of the Nth frame period, in the Nth frame period
  • the falling edge of the first data enable signal DE When the falling edge of the first data enable signal DE is generated, the falling edge of the first clock signal CKV1 is generated, which ensures the timing synchronization of the scanning signal and the gray-scale signal.
  • the driving timing diagram shown in FIG. 9 corresponds to an even number of scan shift registers, which is only an example, and is not a limitation of the present application. In other embodiments, the drive timing for odd scan shift registers also meets the above-mentioned embodiments.
  • the last data enable signal DE in the N-1th frame period The time interval between the falling edge of STV and the rising edge of the start signal STV is T, where T is greater than 0 and less than the first preset time interval, or T is greater than 0 and equal to the first preset time interval, and the first preset time interval is less than Vertical blanking period
  • the first preset time interval is less than half of the vertical blanking period.
  • a smaller range is set for the first preset time interval, so that the falling edge of the last data enable signal DE of the N-1th frame period is different from the rising edge of the start signal STV
  • the time interval between is limited to a smaller time range, so as to ensure that the timing controller 40 does not generate abnormal gate control signals.
  • the timing controller 40 when the timing controller 40 generates the rising edge and the falling edge of the start signal STV during the period of time between the rising edge and the falling edge of the first data enable signal DE in the Nth frame period,
  • the rising edge of the start signal STV is generated when the rising edge of the first data enable signal DE in the Nth frame period is generated.
  • the rising edge of the first data enable signal DE in the Nth frame period is aligned with the rising edge of the start signal STV, that is, the rising edge of the first data enable signal DE in the Nth frame period is aligned with the rising edge of the first data enable signal DE in the Nth frame period.
  • the rising edge of the start signal STV is generated at the same time.
  • the rising edge of the start signal STV since the rising edge of the start signal STV is generated within the time interval for forming the rising edge and the falling edge of the first data enable signal DE in the Nth frame period, the rising edge of the start signal STV can be based on the first The first data enable signal DE of the N frame period is generated, which reduces the difficulty of controlling the rising edge of the start signal STV.
  • FIG. 10 is a driving timing diagram of another display device provided by an embodiment of the application.
  • the timing controller 40 forms a time interval at the rising edge and the falling edge of the first data enable signal DE in the Nth frame period
  • the rising edge of the start signal STV is generated after the rising edge of the first data enable signal DE in the Nth frame period. That is, in time sequence, the rising edge of the first data enable signal DE of the Nth frame period is generated first, and the rising edge of the first data enable signal DE of the Nth frame period is generated for a period of time, and then Generate the rising edge of the start signal STV.
  • the rising edge of the start signal STV is generated after the rising edge of the first data enable signal DE of the Nth frame period, the rising edge of the start signal STV is the same as the first one of the Nth frame period.
  • the rising edges of the data enable signal DE are generated at different times, so it is possible to avoid switching of multiple signals at the same time, which is beneficial to avoid electromagnetic interference.
  • FIG. 11 is a driving timing diagram of another display device provided by an embodiment of the application.
  • the timing controller 40 forms a time interval between the rising edge and the falling edge of the first data enable signal DE in the Nth frame period
  • the rising and falling edges of the first clock signal CKV1 are generated within the time interval for forming the rising and falling edges of the first data enable signal DE in the Nth frame period . That is, the rising edge of the first clock signal CKV1 is generated when the rising edge of the first data enable signal DE in the Nth frame period is generated, or the first data enable signal DE in the Nth frame period is generated.
  • the rising edge of the first clock signal CKV1 is generated after the rising edge of.
  • the falling edge of the first clock signal CKV1 is generated when the falling edge of the first data enable signal DE in the Nth frame period is generated, or before the falling edge of the first data enable signal DE in the Nth frame period The falling edge of the first clock signal CKV1 is generated.
  • the timing controller 40 when the timing controller 40 generates the rising edge and the falling edge of the start signal STV in the period between the rising edge and the falling edge of the first data enable signal DE in the Nth frame period, and the timing controller 40 is in the first
  • the rising edge of the start signal STV is generated in the vertical blanking period V-blanking of the N-1 frame period, it needs to be within the forming time interval of the rising edge and the falling edge of the first data enable signal DE in the Nth frame period
  • the falling edge of the first clock signal CKV1 is generated.
  • the falling edge of the first clock signal CKV1 of the Nth frame period is generated within the time interval formed by the rising and falling edges of the second data enable signal DE, the high voltage of the signal Gate_1 on the first row scan line 21
  • the flat time will also be delayed to the third data enable signal DE, causing the gray-scale signal to be misaligned by one row, and the gray-scale signal of the first row will be displayed in the second row of pixels 20.
  • the timing controller 40 When the timing controller 40 generates the rising edge and the falling edge of the start signal STV in the period between the rising edge and the falling edge of the first data enable signal DE in the Nth frame period, at the first one of the Nth frame period The rising edge and the falling edge of the data enable signal DE generate the rising edge and the falling edge of the first clock signal CKV1 in the time interval for forming the first clock signal CKV1, which ensures that the scan signal is synchronized with the gray scale signal timing.
  • the rising edge of the first clock signal CKV1 is generated by the falling edge of the second clock signal CKV2 After along. That is, in time sequence, the falling edge of the second clock signal CKV2 is generated first, and the rising edge of the first clock signal CKV1 is generated after a period of time after the falling edge of the second clock signal CKV2 is generated.
  • the shift register 320 in the gate driving circuit 30 includes a NAND circuit 3202
  • one of the input signals of the NAND circuit 3202 is the first clock signal CKV1 or the second clock signal CKV2, and the NAND circuit 3202
  • the other input signal of the input signal of the circuit 3202 (for example, the signal input from the shift input terminal IN of the shift register is latched by the latch circuit 3201 and output to the cascade signal terminal NXT terminal of the NAND circuit 3202) is also A clock signal CKV1 and a second clock signal CKV2 are directly related.
  • the rising edge of the first clock signal CKV1 is aligned with the falling edge of the second clock signal CKV2, since the rising edge and the falling edge of the actual timing require a certain amount of time, it is not directly converted from a low level to a high level, nor is it caused by The high level is directly converted to the low level, and glitches will occur during NAND operation, and the output will be unstable.
  • the timing controller 40 when the timing controller 40 generates the rising edge and the falling edge of the start signal STV in the period of time between the rising edge and the falling edge of the first data enable signal DE in the Nth frame period, Within the time interval formed by the rising and falling edges of the first data enable signal DE in the Nth frame period, the falling edge of the start signal STV is generated before the rising edge of the first clock signal CKV1, or the start signal STV The falling edge is generated when the rising edge of the first clock signal CKV1 is generated.
  • the rising and falling edges of the start signal STV are generated first, and then the first A rising edge and falling edge of a clock signal CKV1.
  • FIG. 12 is a driving timing diagram of another display device provided by an embodiment of the application.
  • the timing controller 40 forms a time interval between the rising edge and the falling edge of the first data enable signal DE in the Nth frame period
  • the rising edge and the falling edge of the start signal STV are generated in the N-th frame period
  • the falling edge of the start signal STV is generated in the first data enable signal DE
  • the clock signal CKV1 After the falling edge of the clock signal CKV1, or the falling edge of the start signal STV is generated when the falling edge of the first clock signal CKV1 is generated.
  • the first clock signal CKV1 is generated in the time interval when the rising and falling edges of the start signal STV are formed. The rising and falling edges of.
  • the timing controller 40 generates the rising edge and the falling edge of the start signal STV in the time interval for forming the rising edge and the falling edge of the first data enable signal DE in the Nth frame period.
  • the width of the first clock signal CKV1 generated in the time interval between the rising and falling edges of the first data enable signal DE in the Nth frame period is smaller than that of the first data enable signal DE in the Nth frame period
  • the width of the first clock signal CKV1 generated outside.
  • the width of the second clock signal CKV2 generated during the time interval formed by the rising and falling edges of the first data enable signal DE in the Nth frame period is smaller than that generated outside the first data enable signal DE in the Nth frame period
  • the first clock signal CKV1 and the second clock signal CKV2 generated in the time interval between the rising edge and the falling edge of the first data enable signal DE in the Nth frame period are used to generate the first dummy shift.
  • the output signal Dummy_1 of the bit register, the width of the first clock signal CKV1 and the width of the second clock signal CKV2 generated in the period of time between the rising and falling edges of the first data enable signal DE in the Nth frame period are smaller than normal
  • the width of the first clock signal CKV1 and the width of the second clock signal CKV2 during display (for example, the width of the first clock signal CKV1 and the width of the second clock signal CKV2 during normal display may be equal to the width of the data enable signal DE)
  • the width of the first clock signal CKV1 and the width of the second clock signal CKV2 generated in the time interval for forming the rising and falling edges of the first data enable signal DE becomes smaller, so that the width of the signal D
  • the width of the first clock signal CKV1 and the width of the second clock signal CKV2 generated in the time interval for forming the rising and falling edges of the first data enable signal DE becomes smaller, so that the signal Dummy_1
  • the start signal STV, the first clock signal CKV1, and the second clock signal CKV2 are all located within the time interval formed by the rising and falling edges of the first data enable signal DE in the Nth frame period, so that the The rising edge and the falling edge of the second data enable signal DE in the N frame period form a time interval to send one row of data to the data line 22 through the source drive circuit in the drive chip 50.
  • the timing controller 40 generates the rising edge and the falling edge of the start signal STV in the time interval for forming the rising edge and the falling edge of the first data enable signal DE in the Nth frame period.
  • the width of the first clock signal CKV1 generated in the period between the rising and falling edges of the first data enable signal DE in the Nth frame period is smaller than that of the second data enable signal DE in the Nth frame period.
  • the rising and falling edges of the forming the width of the first clock signal CKV1 generated in the time interval, the rising and falling edges of the first data enable signal DE in the Nth frame period form the second clock signal generated in the time interval
  • the width of CKV2 is smaller than the width of the second clock signal CKV2 generated during the period in which the rising edge and the falling edge of the second data enable signal DE are formed in the Nth frame period.
  • the rising edge and the falling edge of the second clock signal CKV2 are generated in the time interval when the rising edge and the falling edge of the start signal STV are formed. That is, the rising edge of the second clock signal CKV2 is generated when the rising edge of the start signal STV is generated, or the rising edge of the second clock signal CKV2 is generated after the rising edge of the start signal STV.
  • the falling edge of the second clock signal CKV2 is generated when the falling edge of the start signal STV is generated, or the falling edge of the second clock signal CKV2 is generated before the falling edge of the start signal STV.
  • the rising edge and the falling edge of the second clock signal CKV2 are generated during the rising and falling edges of the start signal STV, and the rising and falling edges of the start signal STV form the first in the time period.
  • the second clock signal CKV2 is used as the transmission start signal of the first dummy shift register. Only when the second clock signal CKV2 is at a high level, the input of the first dummy shift register (that is, the start signal STV) is transmitted to the inside.
  • the rising edge of the second clock signal CKV2 is generated after the rising edge of the start signal STV, and the second The falling edge of the clock signal CKV2 is generated before the falling edge of the start signal STV.
  • the rising edge and the falling edge of the second clock signal CKV2 are both located between the rising edge generation time of the start signal STV and the falling edge generation time of the start signal STV.
  • the width of the second clock signal CKV2 is smaller than the width of the start signal STV.
  • the rising edge of the second clock signal CKV2 does not overlap with the rising edge of the start signal STV, and the falling edge of the second clock signal CKV2 does not overlap with the falling edge of the start signal STV. Since the start signal STV is collected at the rising edge of the second clock signal CKV2, the rising edge actually has a process, that is, the rising edge will go through a period of time.
  • the rising edge of the second clock signal CKV2 is generated after the rising edge of the start signal STV, and the falling edge of the second clock signal CKV2 is generated before the falling edge of the start signal STV, so it is avoided
  • the start signal STV is collected at the rising edge of the clock signal CKV2, thereby improving the accuracy of sampling the start signal STV.
  • the driving timing diagrams shown in FIG. 11 and FIG. 12 correspond to an even number of scan shift registers, which are only an example and are not a limitation of the present application.
  • the drive timing for odd scan shift registers also meets the above-mentioned embodiments.
  • the timing controller 40 performs the first data in the Nth frame period.
  • the rising edge and the falling edge of the enable signal DE generate the rising edge and the falling edge of the start signal STV during the formation time interval.
  • FIG. 13 is a schematic diagram of another gate driving circuit provided by an embodiment of the application.
  • the gate driving circuit 30 includes a start signal line 310 for transmitting the start signal STV, and for transmitting the first clock signal
  • the plurality of shift registers 320 includes a first dummy shift register Dummy1, a first stage scanning shift register 321 to an M-th stage scanning shift register 32M (that is, the first stage scanning shift register 321, the second stage scanning shift register 322,..., M-th stage scanning shift register 32M), the first stage scanning shift register 321 and the first dummy shift register Dummy1 are cascaded, M ⁇ 2.
  • the first signal terminal CLK1 of the first dummy shift register Dummy1 and the even-stage scanning shift register (for example, the second-stage scanning shift register 322) is connected to the second clock signal line 312, the first dummy shift register Dummy1 and the even-stage scanning shift register
  • the second signal terminal CLK2 of the scan shift register is connected to the first clock signal line 311.
  • the first signal terminal CLK1 of the odd-numbered scan shift register (for example, the first-stage scan shift register 321) is connected to the first clock signal line 311, and the second signal terminal CLK2 of the odd-numbered scan shift register is connected to the second clock signal Line 312.
  • the shift input terminal IN of the first dummy shift register Dummy1 is connected to the start signal line STV, and each stage of scanning shift registers (including the first stage of scanning shift register 321, the second stage of scanning shift register 322, ...,
  • the shift input terminal IN of the M-th stage scan shift register 32M) is connected to the cascade signal terminal NXT of the previous stage shift register 320.
  • the gate driving circuit 30 may further include a second dummy shift register Dummy2.
  • the shift input terminal IN of the second dummy shift register Dummy2 is connected to the cascade of the M-th stage scanning shift register 32M.
  • the signal terminal NXT and the cascade signal terminal NXT of the second dummy shift register Dummy2 can be connected to an external circuit.
  • M being an odd number is taken as an example for illustration, which is not a limitation of the present application. In other embodiments, M may also be an even number.
  • FIG. 14 is a driving timing diagram of another display device provided by an embodiment of the application.
  • the timing controller 40 generates a start signal in the vertical blanking period V-blanking of the N-1th frame period.
  • the working principle of the first dummy shift register Dummy1 is: The distance between the first data enable signal DE of the Nth frame period and the first data enable signal DE of the Nth frame period needs to be within the time interval formed by the rising and falling edges of the start signal STV The latest second clock signal CKV2 is pulled high.
  • the rising edge of the cascade signal terminal NXT transmission signal NXT_D1 in the first dummy shift register Dummy1 is generated when the rising edge of the second clock signal CKV2 is generated, and the pulse width of the signal NXT_D1 Relatively wide.
  • the shift input terminal IN of the first dummy shift register Dummy1 is opened, and at this time, the start signal STV is input from the shift input terminal IN, the start signal STV is the input signal of the first dummy shift register Dummy1. Therefore, when the rising edge of the second clock signal CKV2 is generated, the signal of the start signal STV is latched into the first dummy shift register Dummy1.
  • the signal NXT_D1 will last until the rising edge of the next second clock signal CKV2 (that is, the rising and falling edges of the second data enable signal of the Nth frame period form the second clock signal CKV2 in the time interval), and then When the rising edge and falling edge of the second clock signal CKV2 are generated in the time interval of the second data enable signal in the Nth frame period, the start signal STV is checked. At this time, the start signal STV has become Low level, the signal NXT_D1 will be pulled down to low level.
  • the signal Dummy_1 transmitted by the output terminal OUT in the first dummy shift register Dummy1 is generated by the AND operation of the signal NXT_D1 and the signal input from the second signal terminal CLK2 (ie, the first clock signal CKV1).
  • the rising edge of the signal Dummy_1 is at It is generated when the rising edge of the first clock signal CKV1 is generated.
  • the timing controller 40 when the timing controller 40 generates the rising edge of the start signal STV in the vertical blanking period V-blanking of the N-1th frame period, the first stage scans the shift register 321
  • the working principle is similar to that of the first dummy shift register Dummy1.
  • the rising edge of the cascade signal terminal NXT transmission signal NXT_1 in the first stage scan shift register 321 is generated in the Nth frame period.
  • the rising edge and the falling edge of the first data enable signal DE form the first clock signal CKV1 in the time interval. When the rising edge of is generated.
  • the shift input terminal IN transmission signal NXT_D1 of the first stage scanning shift register 321 is latched into the first stage scanning shift register 321, and the signal NXT_1 continues until the next The rising edge of the first clock signal CKV1 (that is, the rising edge and the falling edge of the third data enable signal DE of the Nth frame period generate the first clock signal CKV1 in the time interval), and then the rising edge of the first clock signal CKV1 in the Nth frame period.
  • the rising edge and falling edge of the data enable signal DE generate the rising edge of the first clock signal CKV1 during the formation time interval, check the signal NXT_D1.
  • the signal Gate_1 transmitted by the output terminal OUT in the first stage scan shift register 321 is generated by the AND operation of the signal NXT_1 and the signal input from the second signal terminal CLK2 (ie, the second clock signal CKV2).
  • the rising edge of the signal Gate_1 It is generated when the rising edge of the second clock signal CKV2 is generated.
  • the transmission signal of the cascade signal terminal NXT in the M-th scan shift register 32M is the signal NXT_M
  • the output terminal OUT transmission signal in the M-th scan shift register 32M is Gate_M
  • the transmission signal of the cascade signal terminal NXT in the second dummy shift register Dummy2 is the signal NXT_D2
  • the transmission signal of the output terminal OUT in the second dummy shift register Dummy2 is Dummy_2.
  • the working principle of the M-th scanning shift register 32M and the second dummy shift register Dummy2 is similar to the working principle of the first dummy shift register Dummy1, and will not be repeated here.
  • the driving timing diagram shown in FIG. 14 corresponds to an even number of scan shift registers, which is only an example, and is not a limitation of the present application.
  • the driving timing of the odd number of scan shift registers also meets the above-mentioned embodiments.
  • the same parts in the corresponding timing sequence of the odd-numbered scan shift registers and the even-numbered shift registers have been described in the foregoing embodiment, and will not be repeated.
  • the embodiment of the present application introduces the different parts in the corresponding timing sequence of the odd-numbered scan shift registers and the even-numbered shift registers.
  • a first clock signal CKV1 after a data enable signal DE is separated, a first clock signal CKV1 is generated after the 2L data enable signal DE, and then a data enable signal DE is generated, and a first clock signal is generated.
  • a second clock signal CKV2 is generated during the formation period of the rising edge and falling edge of the 2L-2th data enable signal DE of the N-1th frame period.
  • a second clock signal CKV2 is generated during the time interval formed by the rising edge and the falling edge of the enable signal DE, and after an interval of a data enable signal DE, a second clock signal CKV2 is generated.
  • the rising edge of the start signal STV is generated, and the rising and falling edges of the start signal STV form a time interval
  • the second second clock signal CKV2 in the vertical blanking period V-blanking is generated within.
  • the rising edge of the signal NXT_M is generated when the rising edge and the falling edge of the last data enable signal DE of the N-1th frame period are generated when the rising edge of the second clock signal CKV2 is generated in the time interval, and continues to the next first The rising edge of the second clock signal CKV2.
  • the signal Gate_M is generated in the time interval between the rising and falling edges of the first first clock signal CKV1 in the vertical blanking period V-blanking in the N-1th frame period.
  • the rising edge of the signal NXT_D2 is generated when the rising edge of the first first clock signal CKV1 in the vertical blanking period V-blanking in the N-1th frame period is generated, and continues to the rising of the next first clock signal CKV1 along.
  • the signal Dummy_2 is generated in the time interval between the rising and falling edges of the first second clock signal CKV2 in the vertical blanking period V-blanking in the N-1th frame period.
  • the rising edge of the start signal STV is generated after the falling edge of the second clock signal CKV2.
  • FIG. 15 is a driving timing diagram of another display device provided by an embodiment of the application.
  • M odd number of scan shift registers
  • a first clock signal CKV1 is generated in the time interval formed by the rising and falling edges of the data enable signal DE, and after an interval of a data enable signal DE, a first clock signal CKV1 is generated.
  • a second clock signal CKV2 is generated during the formation period of the rising edge and the falling edge of the 2L-2 data enable signal DE in the N-1th frame period.
  • the second clock signal CKV2 After an interval of the data enable signal DE, the second clock signal CKV2 After a data enable signal DE, a second clock signal CKV2 is generated, and after an interval of a data enable signal DE, a second clock signal CKV2 is generated. After the second second clock signal CKV2 in the vertical blanking period V-blanking of the N-1th frame period, the rising edge of the start signal STV is generated, and the rising and falling edges of the start signal STV form a time interval The third second clock signal CKV2 in the vertical blanking period V-blanking is generated within.
  • the rising edge of the signal NXT_M is generated when the rising edge and the falling edge of the last data enable signal DE in the N-1th frame period are generated when the rising edge of the first clock signal CKV1 is generated in the interval, and continues to the next first clock signal CKV1.
  • the signal Gate_M is generated in the time interval between the rising and falling edges of the first second clock signal CKV2 in the vertical blanking period V-blanking in the N-1th frame period.
  • the rising edge of the signal NXT_D2 is generated at the rising edge of the first second clock signal CKV2 in the vertical blanking period V-blanking in the N-1th frame period, and continues to the rising edge of the next second clock signal CKV2 .
  • the signal Dummy_2 is generated in the period of time between the rising and falling edges of the first first clock signal CKV1 in the vertical blanking period V-blanking in the N-1th frame period.
  • the rising edge of the start signal STV is generated after the falling edge of the second clock signal CKV2.
  • FIG. 16 is a driving timing diagram of another display device provided by an embodiment of the application.
  • the timing controller 40 is at the rising and falling edges of the first data enable signal DE in the Nth frame period.
  • the working principle of the first dummy shift register Dummy1 and the first stage scanning shift register 321 is perpendicular to that of the timing controller 40 in the N-1th frame period. It is the same when the rising edge of the start signal STV is generated in the blanking period V-blanking, and will not be repeated here.
  • the timing controller 40 When the timing controller 40 generates the rising edge and the falling edge of the start signal STV in the time interval between the rising edge and the falling edge of the first data enable signal DE of the Nth frame period, the first data of the Nth frame period
  • the width of the first clock signal CKV1 and the width of the second clock signal CKV2 in the time interval formed by the rising edge and the falling edge of the enable signal DE are shortened.
  • the width of the scanning shift register 321 of the first stage to the scanning shift register 32M of the M-th stage remains unchanged, and the time width during which the multiple scanning lines 21 are turned on remains unchanged compared with related designs.
  • the first dummy shift register Dummy1 is dummy, and the various signals output by the first dummy shift register Dummy1 only serve the function of trigger transmission, and therefore will not affect the normal display of the display device.
  • the driving timing diagram shown in FIG. 16 corresponds to an even number of scan shift registers, which is only an example and is not a limitation of the present application.
  • the driving timing of the odd number of scan shift registers also meets the above-mentioned embodiments.
  • the same parts in the corresponding timing sequence of the odd-numbered scan shift registers and the even-numbered shift registers have been described in the foregoing embodiment, and will not be repeated.
  • the embodiment of the present application introduces the different parts in the corresponding timing sequence of the odd-numbered scan shift registers and the even-numbered shift registers.
  • a first clock signal CKV1 after a data enable signal DE is separated, a first clock signal CKV1 is generated after the 2L data enable signal DE, and then a data enable signal DE is generated, and a first clock signal is generated.
  • a second clock signal CKV2 is generated during the formation period of the rising edge and falling edge of the 2L-2th data enable signal DE in the N-1th frame period.
  • a second clock signal CKV2 is generated during the time interval formed by the rising edge and the falling edge of the enable signal DE, and after an interval of a data enable signal DE, a second clock signal CKV2 is generated.
  • the rising edge of the signal NXT_M is generated when the rising edge and the falling edge of the last data enable signal DE of the N-1th frame period are generated when the rising edge of the second clock signal CKV2 is generated in the time interval, and continues to the next first The rising edge of the second clock signal CKV2.
  • the signal Gate_M is generated in the time interval between the rising and falling edges of the first first clock signal CKV1 in the vertical blanking period V-blanking in the N-1th frame period.
  • the rising edge of the signal NXT_D2 is generated at the rising edge of the first first clock signal CKV1 in the vertical blanking period V-blanking in the N-1th frame period, and continues to the next rising edge of the first clock signal CKV1.
  • the signal Dummy_2 is generated in the time interval between the rising and falling edges of the first second clock signal CKV2 in the vertical blanking period V-blanking in the N-1th frame period.
  • FIG. 17 is a driving timing diagram of another display device provided by an embodiment of the application.
  • M odd number of scan shift registers
  • a first clock signal CKV1 is generated in the time interval formed by the rising and falling edges of the data enable signal DE, and after an interval of a data enable signal DE, a first clock signal CKV1 is generated.
  • a second clock signal CKV2 is generated during the formation period of the rising and falling edges of the 2L-2th data enable signal DE of the N-1th frame period.
  • a second clock signal is generated.
  • a second clock signal CKV2 is generated.
  • the rising edge of the signal NXT_M is generated when the rising edge and the falling edge of the last data enable signal DE in the N-1th frame period are generated when the rising edge of the first clock signal CKV1 is generated in the interval, and continues to the next first clock signal CKV1.
  • the signal Gate_M is generated in the time interval between the rising and falling edges of the first second clock signal CKV2 in the vertical blanking period V-blanking in the N-1th frame period.
  • the rising edge of the signal NXT_D2 is generated when the rising edge of the first second clock signal CKV2 in the vertical blanking period V-blanking in the N-1th frame period is generated, and continues to the rise of the next second clock signal CKV2 along.
  • the signal Dummy_2 is generated in the period of time between the rising and falling edges of the first first clock signal CKV1 in the vertical blanking period V-blanking in the N-1th frame period.
  • FIG. 18 is a schematic top view of another display device according to an embodiment of the application.
  • the display device includes a plurality of scan lines 21, a gate driving circuit 30 and a timing controller 40.
  • the display device can be a mobile phone, a tablet computer, a smart wearable device, etc.

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  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种显示装置，包括：多条扫描线（21）；栅极驱动电路（30），与多条扫描线（21）电连接；时序控制器（40），与栅极驱动电路（30）电连接，被配置为接收多个帧周期中每一帧周期内的多个数据使能信号（DE），根据数据使能信号（DE）产生栅极控制信号，并将栅极控制信号提供至栅极驱动电路（30）；栅极驱动电路（30）被配置为根据栅极控制信号向多条扫描线（21）提供扫描信号；栅极控制信号包括起始信号（STV）、第一时钟信号（CKV1）和第二时钟信号（CKV2）；其中，每一帧周期包括有效周期（V-avtive）以及垂直消隐周期（V-blanking），数据使能信号（DE）仅位于有效周期（V-avtive）内；时序控制器（40）在第N-1帧周期的垂直消隐周期（V-blanking）内产生起始信号（STV）的上升沿，且第N-1帧周期的最后一个数据使能信号（DE）的下降沿与起始信号（STV）的上升沿之间的时间间隔为T，T大于0且小于第一预设时间间隔或者T大于0且等于第一预设时间间隔，第一预设时间间隔小于垂直消隐周期（V-blanking）的2/3，或者，时序控制器（40）在第N帧周期的第一个数据使能信号（DE）的上升沿和下降沿形成时间区间内产生起始信号（STV）的上升沿以及下降沿；其中，N≥2。

Description

显示装置
本申请要求在2020年06月16日提交中国专利局、申请号为202010548868.0的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，例如涉及一种显示装置。
背景技术
随着显示技术的发展，液晶显示(Liquid Crystal Display，LCD)面板和有机发光二极管(Organic Light Emitting Diode，0LED)显示面板逐渐成为显示领域的两大主流显示面板，LCD面板和OLED显示面板被广泛应用于电脑、手机、穿戴设备、车载等本领域技术人员可知的可集成显示功能的设备(包括显示装置)或场景中。
相关技术的显示装置，包括显示区域和位于该显示区域四周的边框区域。该显示装置中，通过集成在边框区域的栅极驱动电路控制薄膜晶体管打开或者关闭，并在薄膜晶体管打开时，通过集成在边框区域的源极驱动电路向显示区域的像素提供灰阶信号，来控制该行像素进行画面的显示。然而在时序控制器根据数据使能信号产生栅极控制信号时，栅极控制信号可能产生异常。
发明内容
本申请提供一种显示装置，避免了产生异常的栅极控制信号的情况。
本申请实施例提供一种显示装置，包括：
多条扫描线；
栅极驱动电路，与所述多条扫描线电连接；
时序控制器，与所述栅极驱动电路电连接，被配置为接收多个帧周期中每一帧周期内的多个数据使能信号，根据所述数据使能信号产生栅极控制信号，并将所述栅极控制信号提供至所述栅极驱动电路；所述栅极驱动电路被配置为根据所述栅极控制信号向所述多条扫描线提供扫描信号；所述栅极控制信号包括起始信号、第一时钟信号和第二时钟信号；
其中，每一帧周期包括有效周期以及垂直消隐周期，所述数据使能信号仅位于所述有效周期内；
所述时序控制器在第N-1帧周期的所述垂直消隐周期内产生所述起始信号的上升沿，且第N-1帧周期的最后一个所述数据使能信号的下降沿与所述起始信号的上升沿之间的时间间隔为T，T大于0且小于第一预设时间间隔或者T大于0且等于第一预设时间间隔，所述第一预设时间间隔小于所述垂直消隐周期的
Figure PCTCN2020099103-appb-000001
或者，
所述时序控制器在第N帧周期的第一个数据使能信号的上升沿和下降沿形成时间区间内产生所述起始信号的上升沿以及下降沿；
其中，N≥2。
附图说明
图1为本申请实施例提供的一种显示装置的俯视结构示意图；
图2为本申请实施例提供的一种栅极驱动电路的示意图；
图3为本申请实施例提供的一种移位寄存器的示意图；
图4为相关设计中显示装置的驱动时序图；
图5为本申请实施例提供的一种显示装置的驱动时序图；
图6为本申请实施例提供的另一种显示装置的驱动时序图；
图7为本申请实施例提供的另一种显示装置的驱动时序图；
图8为本申请实施例提供的另一种显示装置的驱动时序图；
图9为本申请实施例提供的另一种显示装置的驱动时序图；
图10为本申请实施例提供的另一种显示装置的驱动时序图；
图11为本申请实施例提供的另一种显示装置的驱动时序图；
图12为本申请实施例提供的另一种显示装置的驱动时序图；
图13为本申请实施例提供的另一种栅极驱动电路的示意图；
图14为本申请实施例提供的另一种显示装置的驱动时序图；
图15为本申请实施例提供的另一种显示装置的驱动时序图；
图16为本申请实施例提供的另一种显示装置的驱动时序图；
图17为本申请实施例提供的另一种显示装置的驱动时序图；
图18为本申请实施例提供的另一种显示装置的俯视结构示意图。
具体实施方式
下面结合附图和实施例对本申请进行说明。此处所描述的实施例仅仅用于解释本申请，而非对本申请的限定。另外，为了便于描述，附图中仅示出了与本申请相关的部分而非全部结构。
图1为本申请实施例提供的一种显示装置的俯视结构示意图，图2为本申请实施例提供的一种栅极驱动电路的示意图，图3为本申请实施例提供的一种移位寄存器的示意图，参考图1、图2和图3，图1中省略了显示装置的部分结构，显示装置包括多条扫描线21、栅极驱动电路30和时序控制器40。栅极驱动电路30与多条扫描线21电连接，被配置为向多条扫描线21提供扫描信号。时序控制器40与栅极驱动电路30电连接，被配置为接收数据使能信号，根据数据使能信号产生栅极控制信号，并将栅极控制信号提供至栅极驱动电路30。栅极控制信号包括起始信号、第一时钟信号和第二时钟信号。每一帧周期包括有效周期以及垂直消隐周期，数据使能信号仅位于有效周期内。
参考图1、图2和图3，栅极驱动电路30包括用于传输起始信号STV的起始信号线310、用于传输第一时钟信号CKV1的第一时钟信号线311、用于传输第二时钟信号CKV2的第二时钟信号线312和级联的多个移位寄存器320，每级移位寄存器320包括移位输入端IN、输出端OUT、第一信号端CLK1、第二信号端CLK2和级联信号端NXT。多个移位寄存器320包括第一虚设移位寄存器Dummy1和第一级扫描移位寄存器321，第一级扫描移位寄存器321与第一虚设移位寄存器Dummy1级联。第一虚设移位寄存器Dummy1的第一信号端CLK1连接于第二时钟信号线312，第一虚设移位寄存器Dummy1的第二信号端CLK2连接于第一时钟信号线311。第一级扫描移位寄存器321的第一信号端CLK1连接于第一时钟信号线311，第一级扫描移位寄存器321的第二信号端CLK2连接 于第二时钟信号线312。第一虚设移位寄存器Dummy1的移位输入端IN连接于起始信号线310，第一级扫描移位寄存器321的移位输入端IN连接于第一虚设移位寄存器Dummy1的级联信号端NXT。示例性地，栅极驱动电路30还可以包括用于传输复位信号的复位信号线313。每级移位寄存器320还可以包括复位端RST，所有移位寄存器320的复位端RST均与复位信号线313电连接。移位寄存器320的电路结构例如可以包括锁存电路3201、与非电路3202和缓存电路3203。锁存电路3201和与非电路3202电连接。与非电路3202和缓存电路3203电连接。锁存电路3201包括移位输入端IN和第一信号端CLK1。锁存电路3201的输出端为级联信号端NXT(即，与非电路3202和锁存电路3201电连接的输入端)，与非电路3202的另一个输入端为第二信号端CLK2，与非电路3202的两个输入端的输入信号在与非电路3202中进行与非运算。与非电路3202的输出端与缓存电路3203的的输入端电连接，缓存电路3203的输出端为移位寄存器320的输出端OUT。示例性地，移位寄存器320的电路结构还可以包括复位电路3204，复位电路3204的输入端为复位端RST，复位电路3204的输出端与锁存电路3201电连接。
示例性地，参考图2和图3，对于第一虚设移位寄存器Dummy1来说，第一信号端CLK1输入的第二时钟信号CKV2为高电平时，将移位输入端IN输入的起始信号STV锁存到锁存电路3201中，级联信号端NXT在第二时钟信号CKV2的上升沿处由低电平变为高电平，并持续到下一个第二时钟信号CKV2高电平的上升沿。级联信号端NXT输入的信号与第二信号端CLK2输入的第一时钟信号CKV1在与非电路3202中进行与非运算，并将与非运算的结果输出至缓存电路3203，由缓存电路3203的输出端OUT输出，缓存电路3203用于增强信号的驱动能力。第一级扫描移位寄存器321的工作过程与第一虚设移位寄存器Dummy1类似，不同的是，第一级扫描移位寄存器321中的级联信号端NXT输入的信号与第二信号端CLK2输入的第二时钟信号CKV2在与非电路3202中进行与非运算，在此不再赘述。示例性地，参考图1，显示装置还包括基板10、多条数据线22和驱动芯片50。多条扫描线21、多条数据线22、栅极驱动电路30和时序控制器40位于基板10的同一侧。多条扫描线21与多条数据线22绝缘交叉，多条扫描线21与多条数据线22交叉限定出多个像素20。多个像素20在显示区AA内阵列排布。时序控制器40集成于驱动芯片50中，驱动芯片50 还可以包括用于向数据线22提供灰阶电压的源极驱动电路(图1中未示出)。在其他实施方式中，时序控制器40还可以设置于驱动芯片50外，本申请对此不作限制。
图4为相关设计中显示装置的驱动时序图，参考图4，时序控制器40在第N-1帧周期的垂直消隐周期V-blanking内产生起始信号STV的上升沿以及下降沿，起始信号STV的上升沿临近第N帧周期的第一个数据使能信号的上升沿，起始信号STV的下降沿产生于第N帧周期的第一个数据使能信号的上升沿产生之时。也就是说，起始信号STV的上升沿产生的时间接近第N帧周期的第一个数据使能信号的上升沿的产生时间。由于数据使能信号DE仅位于有效周期V-avtive内，数据使能信号DE不位于垂直消隐周期V-blanking内，因此起始信号STV的上升沿无法参考数据使能信号DE来准确产生，起始信号STV的上升沿只能根据第N-1帧周期的最后一个数据使能信号DE的宽度估算得出。例如，第N-1帧周期的最后一个数据使能信号DE的宽度为T-last，在通过计数器计数到第100个T-last的时间宽度后，产生起始信号STV的上升沿。由于时钟抖动等因素，第N-1帧周期的最后一个数据使能信号DE的宽度T-last也产生相应的波动，造成栅极控制信号在一些时间段中正常，但是在另一些时间段中异常。
本申请实施例提供了一种显示装置，该显示装置可以避开“准确估算起始信号STV的上升沿”的问题，即，本申请实施例通过对起始信号STV的设计，避免了产生异常的栅极控制信号的情况。
图5为本申请实施例提供的一种显示装置的驱动时序图，参考图5，时序控制器40在第N-1帧周期的垂直消隐周期V-blanking内产生起始信号STV的上升沿，且第N-1帧周期的最后一个数据使能信号DE的下降沿与起始信号STV的上升沿之间的时间间隔为T，T大于0且小于第一预设时间间隔或者T大于0且等于第一预设时间间隔，第一预设时间间隔小于垂直消隐周期的
Figure PCTCN2020099103-appb-000002
其中，N≥2。本申请的多个实施例中，“内”、“之内”以及“以内”等的表述包括端点值，例如，在第N-1帧周期的垂直消隐周期V-blanking内产生起始信号STV的上升沿指的是，在第N-1帧周期的最后一个数据使能信号DE的下降沿产生之 时以及在第N-1帧周期最后一个数据使能信号DE的下降沿产生之后且在第N帧周期的第一个数据使能信号DE的上升沿产生之时以及在第N帧周期的第一个数据使能信号DE的上升沿产生之前产生起始信号STV的上升沿。本申请多个实施例中，“之后”、“后”、“前”以及“之前”等的表述，指的是在时间顺序上的先后。例如，在A之后产生B，指的是在时间顺序上，先产生A再产生B。在A之前产生B，指的是在时间顺序上，先产生B再产生A。
图6为本申实施例提供的一种显示装置的驱动时序图，参考图6，时序控制器40在第N帧周期的第一个数据使能信号DE的上升沿和下降沿形成时间区间内产生起始信号STV的上升沿以及下降沿。其中，N≥2。也就是说，在第N帧周期的第一个数据使能信号DE的上升沿产生之时产生起始信号STV的上升沿，或者，在第N帧周期的第一个数据使能信号DE的上升沿之后产生起始信号STV的上升沿。在第N帧周期的第一个数据使能信号DE的下降沿产生之时产生起始信号STV的下降沿，或者，在第N帧周期的第一个数据使能信号DE的下降沿之前产生起始信号STV的下降沿。
示例性地，参考图1和图2，对于将栅极驱动电路30集成于显示面板(即Gate in Panel，GIP)的显示装置来说，栅极驱动电路30包括多个级联移位寄存器320，且可以将第一个移位寄存器320设置为第一虚设移位寄存器Dummy1。第一虚设移位寄存器Dummy1后还级联设置多个扫描移位寄存器。第一虚设移位寄存器Dummy1后的第一个移位寄存器320为第一级扫描移位寄存器321，第一级扫描移位寄存器321向第一行扫描线21提供扫描信号。在驱动芯片50内部可以设置一行缓存器，以降低成本，此时，需要在第N帧周期的第二个数据使能信号DE的上升沿和下降沿形成时间区间内通过第一行扫描线21(在扫描线21上的信号为高电平时)将与第一行扫描线21电连接的一行薄膜晶体管导通，将数据线22上的信号通过该行薄膜晶体管传输到一行子像素的像素电极中。
参考图6，为了保证在第N帧周期的第二个数据使能信号DE的上升沿和下降沿形成时间区间内将一行数据通过驱动芯片50中的源极驱动电路送出至数据线22，需要在第N帧周期的第一个数据使能信号DE的上升沿和下降沿形成时 间区间内产生起始信号STV的上升沿以及下降沿。如果在第N帧周期的第一个数据使能信号DE的上升沿和下降沿形成时间区间内产生起始信号STV的上升沿，在第N帧周期的第二个数据使能信号DE的上升沿和下降沿形成时间区间内产生起始信号的下降沿，则源极驱动电路送出的一行数据会延迟到第N帧周期的第三个数据使能信号DE的上升沿和下降沿形成时间区间内送出，导致扫描信号与灰阶信号出现时序不同步的问题。
本申请实施例提供的显示装置中，可以在第N-1帧周期的垂直消隐周期V-blanking内产生起始信号STV的上升沿，且第N-1帧周期的最后一个数据使能信号DE的下降沿与起始信号STV的上升沿之间的时间间隔小于垂直消隐周期的
Figure PCTCN2020099103-appb-000003
从而第N-1帧周期的最后一个数据使能信号DE的下降沿与起始信号STV的上升沿之间的时间间隔较相关设计中更短，即便第N-1帧周期的最后一个数据使能信号DE的宽度在多帧周期中发生波动，对起始信号STV的上升沿产生时间影响不大，因此可以避开“准确估算起始信号STV的上升沿”的问题。本申请实施例提供的显示装置中，还可以在第N帧周期的第一个数据使能信号DE的上升沿和下降沿形成时间区间内产生起始信号STV的上升沿以及下降沿，从而起始信号STV的上升沿可以参考第N帧周期的第一个数据使能信号DE来准确产生，因此可以避开“准确估算起始信号STV的上升沿”的问题。本申请实施例通过对起始信号STV的设计，避免了产生异常的栅极控制信号的情况。
可选地，参考图5，时序控制器40在第N-1帧周期的垂直消隐周期V-blanking内产生起始信号STV的上升沿时，在第N-1帧周期的最后一个数据使能信号DE的下降沿之后产生起始信号STV的上升沿。也就是说，在时间顺序上，先产生第N-1帧周期的最后一个数据使能信号DE的下降沿，在产生第N-1帧周期的最后一个数据使能信号DE的下降沿一段时间后，再产生起始信号STV的上升沿。
可选地，参考图5，时序控制器40在第N-1帧周期的垂直消隐周期V-blanking 内产生起始信号STV的上升沿时，起始信号STV的下降沿在第N-1帧周期的垂直消隐周期V-blanking内产生。本申请实施例中，起始信号STV的上升沿以及下降沿均在第N-1帧周期的垂直消隐周期V-blanking内产生。
图7为本申请实施例提供的另一种显示装置的驱动时序图，参考图7，时序控制器40在第N-1帧周期的垂直消隐周期V-blanking内产生起始信号STV的上升沿时，起始信号STV的下降沿在第N帧周期的第一个数据使能信号DE的上升沿和下降沿形成时间区间内产生。也就是说，起始信号STV的下降沿可以与第N帧周期的第一个数据使能信号DE的上升沿对齐，或者，起始信号STV的下降沿可以与第N帧周期的第一个数据使能信号DE的下降沿对齐，或者，起始信号STV的下降沿可以位于第N帧周期的第一个数据使能信号DE的上升沿产生时间与第N帧周期的第一个数据使能信号DE的下降沿产生时间之间。本申请实施例中，由于起始信号STV的下降沿在第N帧周期的第一个数据使能信号DE的上升沿和下降沿形成时间区间内产生，起始信号STV的下降沿可以依据第N帧周期的第一个数据使能信号DE来产生，降低了起始信号STV的下降沿的控制难度。
图8为本申请实施例提供的另一种显示装置的驱动时序图，参考图8，时序控制器40在第N-1帧周期的垂直消隐周期V-blanking内产生起始信号STV的上升沿时，在第N-1帧周期内产生P个第二时钟信号CKV2。第N-1帧周期的最后一个数据使能信号DE的下降沿与第P-1个第二时钟信号CKV2的下降沿之间的时间间隔为T-start，T大于T-start，P≥2。本申请实施例中，先产生P个第二时钟信号CKV2中的前P-1个，然后再产生起始信号STV的上升沿，从而在产生起始信号STV的上升沿之前完成第N-1帧周期的扫描。图8中以P＝2为例进行解释说明，第N-1帧周期的最后一个数据使能信号DE的下降沿与第1个第二时钟信号CKV2的下降沿之间的时间间隔为T-start，并非对本申请实施例的限定。在一实施方式中，P＝3，在第N-1帧周期内产生3个第二时钟信号CKV2时，第N-1帧周期的最后一个数据使能信号DE的下降沿与第2个第二时钟信号CKV2的下降沿之间的时间间隔为T-start，T大于T-start。在另一实施方式中，P＝10，在第N-1帧周期内产生10个第二时钟信号CKV2时，第N-1帧周期的最后一个数据使能信号DE的下降沿与第9个第二时钟信号CKV2的下降沿之间的时间间隔为T-start，T大于T-start。
图9为本申请实施例提供的另一种显示装置的驱动时序图，参考图9，时序控制器40在第N-1帧周期的垂直消隐周期V-blanking内产生起始信号STV的上升沿时，对于第N帧周期的第一个第一时钟信号CKV1，在第N帧周期的第一个数据使能信号DE的下降沿产生之时产生第一时钟信号CKV1的下降沿，第一时钟信号CKV1的上升沿产生于起始信号STV的下降沿与第N帧周期的第一个数据使能信号DE的上升沿形成时间区间内。也就是说，第一时钟信号CKV1的上升沿产生于起始信号STV的下降沿产生之时，或者，第一时钟信号CKV1的上升沿产生于第N帧周期的第一个数据使能信号DE的上升沿产生之时，或者，第一时钟信号CKV1的上升沿产生于起始信号STV的下降沿产生时间与第N帧周期的第一个数据使能信号DE的上升沿产生时间之间。本申请实施例中，如果将第N帧周期的第一个时钟信号CKV1的下降沿产生于第二个数据使能信号DE的上升沿和下降沿形成时间区间内，则第一行扫描线21上信号Gate_1(即第一级扫描移位寄存器321中输出端OUT传输的信号)的高电平时间也会相应延后到第三个数据使能信号DE，导致灰阶信号错位了一行，第一行的灰阶信号会显示到第二行像素20中去。时序控制器40在第N-1帧周期的垂直消隐周期V-blanking内产生起始信号STV的上升沿时，对于第N帧周期的第一个第一时钟信号CKV1，在第N帧周期的第一个数据使能信号DE的下降沿产生之时产生第一时钟信号CKV1的下降沿，保证了扫描信号与灰阶信号时序同步。图9中所示驱动时序图对应于偶数个扫描移位寄存器，仅为一种示例，并非对本申请的限定。在其他实施方式中，对于奇数个扫描移位寄存器的驱动时序也满足上述实施例，例如，对于奇数个扫描移位寄存器的驱动时序中，第N-1帧周期的最后一个数据使能信号DE的下降沿与起始信号STV的上升沿之间的时间间隔为T，T大于0且小于第一预设时间间隔或者T大于0且等于第一预设时间间隔， 第一预设时间间隔小于垂直消隐周期的
Figure PCTCN2020099103-appb-000004
可选地，参考图5、图7、图8和图9，第一预设时间间隔小于垂直消隐周期的一半。本申请实施例中，为第一预设时间间隔设定了一个更小的范围，从而使得第N-1帧周期的最后一个数据使能信号DE的下降沿与起始信号STV的上升沿之间的时间间隔被限定在一个更小的时间范围内，从而保障时序控制器40不会产生异常的栅极控制信号。
可选地，参考图6，时序控制器40在第N帧周期的第一个数据使能信号DE的上升沿和下降沿形成时间区间内产生起始信号STV的上升沿以及下降沿时，在第N帧周期的第一个数据使能信号DE的上升沿产生之时产生起始信号STV的上升沿。本申请实施例中，第N帧周期的第一个数据使能信号DE的上升沿与起始信号STV的上升沿对齐，即第N帧周期的第一个数据使能信号DE的上升沿与起始信号STV的上升沿同时产生。本申请实施例中，由于起始信号STV的上升沿在第N帧周期的第一个数据使能信号DE的上升沿和下降沿形成时间区间内产生，起始信号STV的上升沿可以依据第N帧周期的第一个数据使能信号DE来产生，降低了起始信号STV的上升沿的控制难度。
图10为本申请实施例提供的另一种显示装置的驱动时序图，参考图10，时序控制器40在第N帧周期的第一个数据使能信号DE的上升沿和下降沿形成时间区间内产生起始信号STV的上升沿以及下降沿时，在第N帧周期的第一个数据使能信号DE的上升沿之后产生起始信号STV的上升沿。就是说，在时间顺序上，先产生第N帧周期的第一个数据使能信号DE的上升沿，在产生第N帧周期的第一个数据使能信号DE的上升沿一段时间后，再产生起始信号STV的上升沿。本申请实施例中，由于起始信号STV的上升沿在第N帧周期的第一个数据使能信号DE的上升沿之后产生，起始信号STV的上升沿与第N帧周期的第一个数据使能信号DE的上升沿产生于不同的时刻，因此可以避免同一时刻多个信号发生切换，有利于避免电磁干扰。
图11为本申请实施例提供的另一种显示装置的驱动时序图，参考图11，时序控制器40在第N帧周期的第一个数据使能信号DE的上升沿和下降沿形成时间区间内产生起始信号STV的上升沿以及下降沿时，在第N帧周期的第一个数据使能信号DE的上升沿和下降沿形成时间区间内产生第一时钟信号CKV1的 上升沿和下降沿。也就是说，在第N帧周期的第一个数据使能信号DE的上升沿产生之时产生第一时钟信号CKV1的上升沿，或者，在第N帧周期的第一个数据使能信号DE的上升沿之后产生第一时钟信号CKV1的上升沿。在第N帧周期的第一个数据使能信号DE的下降沿产生之时产生第一时钟信号CKV1的下降沿，或者，在第N帧周期的第一个数据使能信号DE的下降沿之前产生第一时钟信号CKV1的下降沿。可见，时序控制器40在第N帧周期的第一个数据使能信号DE的上升沿和下降沿形成时间区间内产生起始信号STV的上升沿以及下降沿时，与时序控制器40在第N-1帧周期的垂直消隐周期V-blanking内产生起始信号STV的上升沿时，都需要在第N帧周期的第一个数据使能信号DE的上升沿和下降沿形成时间区间内产生第一时钟信号CKV1的下降沿。如果将第N帧周期的第一个时钟信号CKV1的下降沿产生于第二个数据使能信号DE的上升沿和下降沿形成时间区间内，则第一行扫描线21上信号Gate_1的高电平时间也会相应延后到第三个数据使能信号DE，导致灰阶信号错位了一行，第一行的灰阶信号会显示到第二行像素20中去。时序控制器40在第N帧周期的第一个数据使能信号DE的上升沿和下降沿形成时间区间内产生起始信号STV的上升沿以及下降沿时，在第N帧周期的第一个数据使能信号DE的上升沿和下降沿形成时间区间内产生第一时钟信号CKV1的上升沿和下降沿，保证了扫描信号与灰阶信号时序同步。
可选地，参考图11，在第N帧周期的第一个数据使能信号DE的上升沿和下降沿形成时间区间内，第一时钟信号CKV1的上升沿产生于第二时钟信号CKV2的下降沿之后。也就是说，在时间顺序上，先产生第二时钟信号CKV2的下降沿，在产生第二时钟信号CKV2的下降沿一段时间之后，再产生第一时钟信号CKV1的上升沿。结合参考图3，由于栅极驱动电路30中的移位寄存器320的内部包含一个与非电路3202，与非电路3202的输入信号之一为第一时钟信号CKV1或第二时钟信号CKV2，与非电路3202的输入信号的另一个输入信号(例如移位寄存器的移位输入端IN输入的信号被锁存电路3201锁存且输出至与非电路3202的级联信号端NXT端的信号)也和第一时钟信号CKV1以及第二时钟信号CKV2直接相关。如果第一时钟信号CKV1的上升沿和第二时钟信号CKV2的下降沿对齐，由于实际的时序中上升沿和下降沿需要一定的时间，并非由低电平直接转化为高电平，也并非由高电平直接转化为低电平，与非操 作时就会产生毛刺，输出不稳定。
可选地，参考图11，时序控制器40在第N帧周期的第一个数据使能信号DE的上升沿和下降沿形成时间区间内产生起始信号STV的上升沿以及下降沿时，在第N帧周期的第一个数据使能信号DE的上升沿和下降沿形成时间区间内，起始信号STV的下降沿产生于第一时钟信号CKV1的上升沿之前，或者，起始信号STV的下降沿产生于第一时钟信号CKV1的上升沿产生之时。也就是说，在第N帧周期的第一个数据使能信号DE的上升沿和下降沿形成时间区间内，在时间顺序上，先产生起始信号STV的上升沿以及下降沿，再产生第一时钟信号CKV1的上升沿以及下降沿。
图12为本申请实施例提供的另一种显示装置的驱动时序图，参考图12，时序控制器40在第N帧周期的第一个数据使能信号DE的上升沿和下降沿形成时间区间内产生起始信号STV的上升沿以及下降沿时，在第N帧周期的第一个数据使能信号DE的上升沿和下降沿形成时间区间内，起始信号STV的下降沿产生于第一时钟信号CKV1的下降沿之后，或者，起始信号STV的下降沿产生于第一时钟信号CKV1的下降沿产生之时。也就是说，在第N帧周期的第一个数据使能信号DE的上升沿和下降沿形成时间区间内，在起始信号STV的上升沿和下降沿形成时间区间内产生第一时钟信号CKV1的上升沿以及下降沿。
可选地，参考图11和图12，时序控制器40在第N帧周期的第一个数据使能信号DE的上升沿和下降沿形成时间区间内产生起始信号STV的上升沿以及下降沿时，在第N帧周期中第一个数据使能信号DE的上升沿和下降沿形成时间区间内产生的第一时钟信号CKV1的宽度小于在第N帧周期中第一个数据使能信号DE外产生的第一时钟信号CKV1的宽度。在第N帧周期中第一个数据使能信号DE的上升沿和下降沿形成时间区间内产生的第二时钟信号CKV2的宽度小于在第N帧周期中第一个数据使能信号DE外产生的第二时钟信号CKV2的宽度。本申请实施例中，在第N帧周期中第一个数据使能信号DE的上升沿和下降沿形成时间区间内产生的第一时钟信号CKV1以及第二时钟信号CKV2用于产生第一虚设移位寄存器的输出信号Dummy_1，在第N帧周期中第一个数据使能信号DE的上升沿和下降沿形成时间区间内产生的第一时钟信号CKV1的宽度以及第二时钟信号CKV2的宽度小于正常显示时第一时钟信号CKV1的宽度以及第二时钟信号CKV2的宽度(例如，正常显示时第一时钟信号CKV1 的宽度以及第二时钟信号CKV2的宽度可以等于数据使能信号DE的宽度)，在第N帧周期中第一个数据使能信号DE的上升沿和下降沿形成时间区间内产生的第一时钟信号CKV1的宽度以及第二时钟信号CKV2的宽度变小，使得信号Dummy_1的宽度变小，由于信号Dummy_1不用于驱动像素20，因此不会影响显示装置的正常显示。另外，在第N帧周期中第一个数据使能信号DE的上升沿和下降沿形成时间区间内产生的第一时钟信号CKV1的宽度以及第二时钟信号CKV2的宽度变小，使得信号Dummy_1的宽度变小，起始信号STV、第一时钟信号CKV1以及第二时钟信号CKV2都位于第N帧周期中第一个数据使能信号DE的上升沿和下降沿形成时间区间内，从而可以在第N帧周期的第二个数据使能信号DE的上升沿和下降沿形成时间区间内将一行数据通过驱动芯片50中的源极驱动电路送出至数据线22。
示例性地，参考图11和图12，时序控制器40在第N帧周期的第一个数据使能信号DE的上升沿和下降沿形成时间区间内产生起始信号STV的上升沿以及下降沿时，在第N帧周期中第一个数据使能信号DE的上升沿和下降沿形成时间区间内产生的第一时钟信号CKV1的宽度小于在第N帧周期中第二个数据使能信号DE的上升沿和下降沿形成时间区间内产生的第一时钟信号CKV1的宽度，在第N帧周期中第一个数据使能信号DE的上升沿和下降沿形成时间区间内产生的第二时钟信号CKV2的宽度小于在第N帧周期中第二个数据使能信号DE的上升沿和下降沿形成时间区间内产生的第二时钟信号CKV2的宽度。
可选地，参考图9、图11和图12，在起始信号STV的上升沿和下降沿形成时间区间内产生第二时钟信号CKV2的上升沿和下降沿。也就是说，第二时钟信号CKV2的上升沿产生于起始信号STV的上升沿产生之时，或者,第二时钟信号CKV2的上升沿产生于起始信号STV的上升沿之后。第二时钟信号CKV2的下降沿产生于起始信号STV的下降沿产生之时，或者,第二时钟信号CKV2的下降沿产生于起始信号STV的下降沿之前。本申请实施例中，在起始信号STV的上升沿和下降沿形成时间区间内产生第二时钟信号CKV2的上升沿和下降沿，起始信号STV的上升沿和下降沿形成时间区间内的第二时钟信号CKV2作为第一虚设移位寄存器的传输启动信号，只有第二时钟信号CKV2为高电平时，才会将第一虚设移位寄存器的输入(即起始信号STV)传输到内部。
可选地，参考图9、图11和图12，起始信号STV的上升沿和下降沿形成时 间区间内，第二时钟信号CKV2的上升沿在起始信号STV的上升沿之后产生，第二时钟信号CKV2的下降沿在起始信号STV的下降沿之前产生。第二时钟信号CKV2的上升沿以及下降沿均位于起始信号STV的上升沿产生时间和起始信号STV的下降沿产生时间之间。第二时钟信号CKV2的宽度小于起始信号STV的宽度。第二时钟信号CKV2的上升沿与起始信号STV的上升沿产生时间不交叠，第二时钟信号CKV2的下降沿与起始信号STV的下降沿产生时间不交叠。由于在第二时钟信号CKV2的上升沿处去采集起始信号STV，而上升沿实际上会有一个过程，即上升沿会经历一段时间。本申请实施例中，第二时钟信号CKV2的上升沿在起始信号STV的上升沿之后产生，第二时钟信号CKV2的下降沿在起始信号STV的下降沿之前产生，所以避免了在第二时钟信号CKV2上升沿处采集起始信号STV，从而提高了对起始信号STV采样的准确性。
图11和图12中所示驱动时序图对应于偶数个扫描移位寄存器，仅为一种示例，并非对本申请的限定。在其他实施方式中，对于奇数个扫描移位寄存器的驱动时序也满足上述实施例，例如，对于奇数个扫描移位寄存器的驱动时序中，时序控制器40在第N帧周期的第一个数据使能信号DE的上升沿和下降沿形成时间区间内产生起始信号STV的上升沿以及下降沿。
图13为本申请实施例提供的另一种栅极驱动电路的示意图，参考图13，栅极驱动电路30包括用于传输起始信号STV的起始信号线310、用于传输第一时钟信号CKV1的第一时钟信号线311、用于传输第二时钟信号CKV2的第二时钟信号线312和级联的多个移位寄存器320，每级移位寄存器320包括移位输入端IN、输出端OUT、第一信号端CLK1、第二信号端CLK2和级联信号端NXT。多个移位寄存器320包括第一虚设移位寄存器Dummy1、第一级扫描移位寄存器321至第M级扫描移位寄存器32M(即第一级扫描移位寄存器321、第二级扫描移位寄存器322、……、第M级扫描移位寄存器32M)，第一级扫描移位寄存器321与第一虚设移位寄存器Dummy1级联，M≥2。第一虚设移位寄存器Dummy1以及偶数级扫描移位寄存器(例如第二级扫描移位寄存器322)的第一信号端CLK1连接于第二时钟信号线312，第一虚设移位寄存器Dummy1以及偶数级扫描移位寄存器的第二信号端CLK2连接于第一时钟信号线311。奇数级扫描移位寄存器(例如第一级扫描移位寄存器321)的第一信号端CLK1连接于第一时钟信号线311，奇数级扫描移位寄存器的第二信号端CLK2连接于第二时 钟信号线312。第一虚设移位寄存器Dummy1的移位输入端IN连接于起始信号线STV，每级扫描移位寄存器(包括第一级扫描移位寄存器321、第二级扫描移位寄存器322、……、第M级扫描移位寄存器32M)的移位输入端IN连接于上一级移位寄存器320的级联信号端NXT。
示例性地，参考图13，栅极驱动电路30还可以包括第二虚设移位寄存器Dummy2，第二虚设移位寄存器Dummy2的移位输入端IN连接于第M级扫描移位寄存器32M的级联信号端NXT，第二虚设移位寄存器Dummy2的级联信号端NXT可以连接于外部电路。图13中以M为奇数为例进行示意，并非对本申请的限制，在其他实施方式中，M还可以为偶数。
图14为本申请实施例提供的另一种显示装置的驱动时序图，参考图13和图14，时序控制器40在第N-1帧周期的垂直消隐周期V-blanking内产生起始信号STV的上升沿时，第一虚设移位寄存器Dummy1的工作原理为：在起始信号STV的上升沿和下降沿形成时间区间内需要把与第N帧周期的第一个数据使能信号DE距离最近的第二时钟信号CKV2拉高，第一虚设移位寄存器Dummy1中级联信号端NXT传输信号NXT_D1的上升沿在该第二时钟信号CKV2的上升沿产生之时产生，且信号NXT_D1的脉冲宽度比较宽。第二时钟信号CKV2由低电平变到高电平的时候，第一虚设移位寄存器Dummy1的移位输入端IN被打开，此时从移位输入端IN输入起始信号STV，起始信号STV为第一虚设移位寄存器Dummy1的输入信号。所以，在第二时钟信号CKV2的上升沿产生的时候，把起始信号STV的信号锁存到第一虚设移位寄存器Dummy1中。信号NXT_D1会持续到下一个第二时钟信号CKV2(即第N帧周期的第2个数据使能信号的上升沿和下降沿形成时间区间内的第二时钟信号CKV2)的上升沿，然后，在第N帧周期的第2个数据使能信号的上升沿和下降沿形成时间区间内产生第二时钟信号CKV2的上升沿的时候，检查起始信号STV，此时，起始信号STV已经变为低电平，信号NXT_D1会被拉低至低电平。第一虚设移位寄存器Dummy1中输出端OUT传输的信号Dummy_1由信号NXT_D1和第二信号端CLK2输入的信号(即第一时钟信号CKV1)做“与”的操作产生的，信号Dummy_1的上升沿在第一时钟信号CKV1的上升沿产生之时产生。
示例性地，参考图13和图14，时序控制器40在第N-1帧周期的垂直消隐周期V-blanking内产生起始信号STV的上升沿时，第一级扫描移位寄存器321 的工作原理与第一虚设移位寄存器Dummy1的工作原理类似。第一级扫描移位寄存器321中级联信号端NXT传输信号NXT_1的上升沿产生于第N帧周期的第一个数据使能信号DE的上升沿和下降沿形成时间区间内第一时钟信号CKV1的上升沿产生之时。在第一时钟信号CKV1的上升沿产生的时候，把第一级扫描移位寄存器321的移位输入端IN传输信号NXT_D1锁存到第一级扫描移位寄存器321中，信号NXT_1持续到下一个第一时钟信号CKV1(即第N帧周期的第三个数据使能信号DE的上升沿和下降沿形成时间区间内产生第一时钟信号CKV1)的上升沿，然后在第N帧周期的第三个数据使能信号DE的上升沿和下降沿形成时间区间内产生第一时钟信号CKV1的上升沿时，检查信号NXT_D1，此时，信号NXT_D1已经变为低电平，信号NXT_1也会被拉低至低电平。第一级扫描移位寄存器321中输出端OUT传输的信号Gate_1由信号NXT_1和第二信号端CLK2输入的信号(即第二时钟信号CKV2)做“与”的操作产生的，信号Gate_1的上升沿在第二时钟信号CKV2的上升沿产生之时产生。
示例性地，参考图13和图14，第M级扫描移位寄存器32M中级联信号端NXT传输信号为信号NXT_M，第M级扫描移位寄存器32M中输出端OUT传输信号为Gate_M。第二虚设移位寄存器Dummy2中级联信号端NXT传输信号为信号NXT_D2，第二虚设移位寄存器Dummy2中输出端OUT传输信号为Dummy_2。第M级扫描移位寄存器32M以及第二虚设移位寄存器Dummy2的工作原理与第一虚设移位寄存器Dummy1的工作原理类似，在此不再赘述。
图14中所示驱动时序图对应于偶数个扫描移位寄存器，仅为一种示例，并非对本申请的限定。在其他实施方式中，对于奇数个扫描移位寄存器的驱动时序也满足上述实施例。对于奇数个扫描移位寄存器与偶数个移位寄存器对应时序中相同的部分在上述实施例中已经进行了描述，不再重复。本申请实施例对奇数个扫描移位寄存器与偶数个移位寄存器对应时序中不同的部分做了介绍。
示例性地，参考图14，对于偶数个扫描移位寄存器(M＝2L)：在第N-1帧周期的第2L-1个数据使能信号DE的上升沿和下降沿形成时间区间内产生一个第一时钟信号CKV1，间隔一个数据使能信号DE后，在第2L个数据使能信号DE之后又产生一个第一时钟信号CKV1，然后再间隔一个数据使能信号DE后，又产生一个第一时钟信号CKV1。在第N-1帧周期的垂直消隐周期V-blanking内存在两个第一时钟信号CKV1。在第N-1帧周期的第2L-2个数据使能信号DE 的上升沿和下降沿形成时间区间内产生一个第二时钟信号CKV2，间隔一个数据使能信号DE后，在第2L个数据使能信号DE的上升沿和下降沿形成时间区间内又产生一个第二时钟信号CKV2，间隔一个数据使能信号DE后，又产生一个第二时钟信号CKV2。在第N-1帧周期的垂直消隐周期V-blanking内第一个第二时钟信号CKV2之后，产生起始信号STV的上升沿，并在起始信号STV的上升沿和下降沿形成时间区间内产生垂直消隐周期V-blanking内的第二个第二时钟信号CKV2。信号NXT_M的上升沿产生于第N-1帧周期的最后一个数据使能信号DE的上升沿和下降沿形成时间区间内的第二时钟信号CKV2的上升沿产生之时，并延续至下一个第二时钟信号CKV2的上升沿。对应地，信号Gate_M产生于第N-1帧周期中垂直消隐周期V-blanking内的第一个第一时钟信号CKV1的上升沿和下降沿形成时间区间内。信号NXT_D2的上升沿产生于第N-1帧周期中垂直消隐周期V-blanking内的第一个第一时钟信号CKV1的上升沿产生之时，并延续至下一个第一时钟信号CKV1的上升沿。信号Dummy_2产生于第N-1帧周期中垂直消隐周期V-blanking内的第一个第二时钟信号CKV2的上升沿和下降沿形成时间区间内。图14中，P＝2，第N-1帧周期的最后一个数据使能信号DE的下降沿与第1个第二时钟信号CKV2的下降沿之间的时间间隔为T-start，在第1个第二时钟信号CKV2的下降沿之后产生起始信号STV的上升沿。
图15为本申请实施例提供的另一种显示装置的驱动时序图，参考图15，对于奇数个扫描移位寄存器(M＝2L-1)：在第N-1帧周期的第2L-1个数据使能信号DE的上升沿和下降沿形成时间区间内产生一个第一时钟信号CKV1，间隔一个数据使能信号DE后，又产生一个第一时钟信号CKV1。在第N-1帧周期的垂直消隐周期V-blanking内存在一个第一时钟信号CKV1。在第N-1帧周期的第2L-2个数据使能信号DE的上升沿和下降沿形成时间区间内产生一个第二时钟信号CKV2，间隔一个数据使能信号DE后，在第2L-1个数据使能信号DE之后又产生一个第二时钟信号CKV2，间隔一个数据使能信号DE后，又产生一个第二时钟信号CKV2。在第N-1帧周期的垂直消隐周期V-blanking内第二个第二时钟信号CKV2之后，产生起始信号STV的上升沿，并在起始信号STV的上升沿和下降沿形成时间区间内产生垂直消隐周期V-blanking内的第三个第二时钟信号CKV2。信号NXT_M的上升沿产生于第N-1帧周期的最后一个数据使能信 号DE的上升沿和下降沿形成时间区间内的第一时钟信号CKV1的上升沿产生之时，并延续至下一个第一时钟信号CKV1的上升沿。对应地，信号Gate_M产生于第N-1帧周期中垂直消隐周期V-blanking内的第一个第二时钟信号CKV2的上升沿和下降沿形成时间区间内。信号NXT_D2的上升沿产生于第N-1帧周期中垂直消隐周期V-blanking内的第一个第二时钟信号CKV2的上升沿之时，并延续至下一个第二时钟信号CKV2的上升沿。信号Dummy_2产生于第N-1帧周期中垂直消隐周期V-blanking内的第一个第一时钟信号CKV1的上升沿和下降沿形成时间区间内。图15中，P＝3，第N-1帧周期的最后一个数据使能信号DE的下降沿与第2个第二时钟信号CKV2的下降沿之间的时间间隔为T-start，在第2个第二时钟信号CKV2的下降沿之后产生起始信号STV的上升沿。
图16为本申请实施例提供的另一种显示装置的驱动时序图，参考图13和图16，时序控制器40在第N帧周期的第一个数据使能信号DE的上升沿和下降沿形成时间区间内产生起始信号STV的上升沿以及下降沿时，第一虚设移位寄存器Dummy1、第一级扫描移位寄存器321的工作原理与时序控制器40在第N-1帧周期的垂直消隐周期V-blanking内产生起始信号STV的上升沿时相同，在此不再赘述。时序控制器40在第N帧周期的第一个数据使能信号DE的上升沿和下降沿形成时间区间内产生起始信号STV的上升沿以及下降沿时，第N帧周期的第一个数据使能信号DE的上升沿和下降沿形成时间区间内的第一时钟信号CKV1的宽度和第二时钟信号CKV2的宽度缩短。第一级扫描移位寄存器321至第M级扫描移位寄存器32M的宽度不变，多条扫描线21打开的时间宽度与相关设计相比未发生变化。第一虚设移位寄存器Dummy1是虚设的，第一虚设移位寄存器Dummy1输出的多种信号仅起到触发传递的作用，因此不会影响显示装置的正常显示。
图16中所示驱动时序图对应于偶数个扫描移位寄存器，仅为一种示例，并非对本申请的限定。在其他实施方式中，对于奇数个扫描移位寄存器的驱动时序也满足上述实施例。对于奇数个扫描移位寄存器与偶数个移位寄存器对应时序中相同的部分在上述实施例中已经进行了描述，不再重复。本申请实施例对奇数个扫描移位寄存器与偶数个移位寄存器对应时序中不同的部分做了介绍。
示例性地，参考图16，对于偶数个扫描移位寄存器(M＝2L)：在第N-1帧周期的第2L-1个数据使能信号DE的上升沿和下降沿形成时间区间内产生一 个第一时钟信号CKV1，间隔一个数据使能信号DE后，在第2L个数据使能信号DE之后又产生一个第一时钟信号CKV1，然后再间隔一个数据使能信号DE后，又产生一个第一时钟信号CKV1。在第N-1帧周期的垂直消隐周期V-blanking内存在两个第一时钟信号CKV1。在第N-1帧周期的第2L-2个数据使能信号DE的上升沿和下降沿形成时间区间内产生一个第二时钟信号CKV2，间隔一个数据使能信号DE后，在第2L个数据使能信号DE的上升沿和下降沿形成时间区间内又产生一个第二时钟信号CKV2，间隔一个数据使能信号DE后，又产生一个第二时钟信号CKV2。信号NXT_M的上升沿产生于第N-1帧周期的最后一个数据使能信号DE的上升沿和下降沿形成时间区间内的第二时钟信号CKV2的上升沿产生之时，并延续至下一个第二时钟信号CKV2的上升沿。对应地，信号Gate_M产生于第N-1帧周期中垂直消隐周期V-blanking内的第一个第一时钟信号CKV1的上升沿和下降沿形成时间区间内。信号NXT_D2的上升沿产生于第N-1帧周期中垂直消隐周期V-blanking内的第一个第一时钟信号CKV1的上升沿处，并延续至下一个第一时钟信号CKV1的上升沿。信号Dummy_2产生于第N-1帧周期中垂直消隐周期V-blanking内的第一个第二时钟信号CKV2的上升沿和下降沿形成时间区间内。
图17为本申请实施例提供的另一种显示装置的驱动时序图，参考图17，对于奇数个扫描移位寄存器(M＝2L-1)：在第N-1帧周期的第2L-1个数据使能信号DE的上升沿和下降沿形成时间区间内产生一个第一时钟信号CKV1，间隔一个数据使能信号DE后，又产生一个第一时钟信号CKV1。在第N-1帧周期的垂直消隐周期V-blanking内存在一个第一时钟信号CKV1。在第N-1帧周期的第2L-2个数据使能信号DE的上升沿和下降沿形成时间区间内产生一个第二时钟信号CKV2，间隔一个数据使能信号DE后，又产生一个第二时钟信号CKV2。再间隔一个数据使能信号DE后，又产生一个第二时钟信号CKV2。在第N-1帧周期的垂直消隐周期V-blanking内存在两个第二时钟信号CKV2。信号NXT_M的上升沿产生于第N-1帧周期的最后一个数据使能信号DE的上升沿和下降沿形成时间区间内的第一时钟信号CKV1的上升沿产生之时，并延续至下一个第一时钟信号CKV1的上升沿。对应地，信号Gate_M产生于第N-1帧周期中垂直消隐周期V-blanking内的第一个第二时钟信号CKV2的上升沿和下降沿形成时间区间内。信号NXT_D2的上升沿产生于第N-1帧周期中垂直消隐周期 V-blanking内的第一个第二时钟信号CKV2的上升沿产生之时，并延续至下一个第二时钟信号CKV2的上升沿。信号Dummy_2产生于第N-1帧周期中垂直消隐周期V-blanking内的第一个第一时钟信号CKV1的上升沿和下降沿形成时间区间内。
图18为本申请实施例提供的另一种显示装置的俯视结构示意图，参考图1和图18，显示装置包括多条扫描线21、栅极驱动电路30和时序控制器40。显示装置可以为手机、平板电脑以及智能可穿戴设备等。

Claims (17)

  1. 一种显示装置，包括：
    多条扫描线；栅极驱动电路，与所述多条扫描线电连接；时序控制器，与所述栅极驱动电路电连接，被配置为接收多个帧周期中每一帧周期内的多个数据使能信号，根据所述数据使能信号产生栅极控制信号，并将所述栅极控制信号提供至所述栅极驱动电路；
    所述栅极驱动电路被配置为根据所述栅极控制信号向所述多条扫描线提供扫描信号；
    所述栅极控制信号包括起始信号、第一时钟信号和第二时钟信号；
    其中，每一帧周期包括有效周期以及垂直消隐周期，所述数据使能信号仅位于所述有效周期内；
    所述时序控制器在第N-1帧周期的所述垂直消隐周期内产生所述起始信号的上升沿，且第N-1帧周期的最后一个所述数据使能信号的下降沿与所述起始信号的上升沿之间的时间间隔为T，T大于0且小于第一预设时间间隔或者T大于0且等于第一预设时间间隔，所述第一预设时间间隔小于所述垂直消隐周期的
    Figure PCTCN2020099103-appb-100001
    或者，所述时序控制器在第N帧周期的第一个数据使能信号的上升沿和下降沿形成时间区间内产生所述起始信号的上升沿以及下降沿；
    其中，N≥2。
  2. 根据权利要求1所述的显示装置，其中，所述时序控制器在第N-1帧周期的所述垂直消隐周期内产生所述起始信号的上升沿的情况下，在第N-1帧周期的最后一个所述数据使能信号的下降沿之后产生所述起始信号的上升沿。
  3. 根据权利要求1所述的显示装置，其中，所述时序控制器在第N-1帧周期的所述垂直消隐周期内产生所述起始信号的上升沿的情况下，所述起始信号的下降沿在第N-1帧周期的所述垂直消隐周期内产生。
  4. 根据权利要求1所述的显示装置，其中，所述时序控制器在第N-1帧周期的所述垂直消隐周期内产生所述起始信号的上升沿的情况下，所述起始信号的下降沿在第N帧周期的第一个数据使能信号的上升沿和下降沿形成时间区间内 产生。
  5. 根据权利要求1所述的显示装置，其中，所述时序控制器在第N-1帧周期的所述垂直消隐周期内产生所述起始信号的上升沿的情况下，在第N-1帧周期内产生P个所述第二时钟信号；
    第N-1帧周期内的最后一个所述数据使能信号的下降沿与第P-1个所述第二时钟信号的下降沿之间的时间间隔为T-start，T大于T-start，P≥2。
  6. 根据权利要求1所述的显示装置，其中，所述时序控制器在第N-1帧周期的所述垂直消隐周期内产生所述起始信号的上升沿的情况下，在第N帧周期的第一个数据使能信号的下降沿产生之时产生所述第N帧周期的第一个第一时钟信号的下降沿，所述第N帧周期的第一个第一时钟信号的上升沿产生于所述起始信号的下降沿与第N帧周期的第一个数据使能信号的上升沿形成时间区间内。
  7. 根据权利要求1所述的显示装置，其中，所述第一预设时间间隔小于所述垂直消隐周期的一半。
  8. 根据权利要求1所述的显示装置，其中，所述时序控制器在第N帧周期的第一个数据使能信号的上升沿和下降沿形成时间区间内产生所述起始信号的上升沿以及下降沿的情况下，在第N帧周期的第一个数据使能信号的上升沿产生之时产生所述起始信号的上升沿。
  9. 根据权利要求1所述的显示装置，其中，所述时序控制器在第N帧周期的第一个数据使能信号的上升沿和下降沿形成时间区间内产生所述起始信号的上升沿以及下降沿的情况下，在第N帧周期的第一个数据使能信号的上升沿之后产生所述起始信号的上升沿。
  10. 根据权利要求1所述的显示装置，其中，所述时序控制器在第N帧周期的第一个数据使能信号的上升沿和下降沿形成时间区间内产生所述起始信号的上升沿以及下降沿的情况下，在第N帧周期的第一个数据使能信号的上升沿和下降沿形成时间区间内产生所述第一时钟信号的上升沿和下降沿。
  11. 根据权利要求10所述的显示装置，其中，在第N帧周期的第一个数据使能信号的上升沿和下降沿形成时间区间内，所述第一时钟信号的上升沿产生 于所述第二时钟信号的下降沿之后。
  12. 根据权利要求1所述的显示装置，其中，所述时序控制器在第N帧周期的第一个数据使能信号的上升沿和下降沿形成时间区间内产生所述起始信号的上升沿以及下降沿的情况下，在第N帧周期的第一个数据使能信号的上升沿和下降沿形成时间区间内，所述起始信号的下降沿产生于所述第一时钟信号的上升沿之前，或者，所述起始信号的下降沿产生于所述第一时钟信号的上升沿产生之时。
  13. 根据权利要求1所述的显示装置，其中，所述时序控制器在第N帧周期的第一个数据使能信号的上升沿和下降沿形成时间区间内产生所述起始信号的上升沿以及下降沿的情况下，在第N帧周期的第一个数据使能信号的上升沿和下降沿形成时间区间内，所述起始信号的下降沿产生于所述第一时钟信号的下降沿之后，或者，所述起始信号的下降沿产生于所述第一时钟信号的下降沿产生之时。
  14. 根据权利要求1所述的显示装置，其中，所述时序控制器在第N帧周期的第一个数据使能信号的上升沿和下降沿形成时间区间内产生所述起始信号的上升沿以及下降沿的情况下，第N帧周期中第一个数据使能信号的上升沿和下降沿形成时间区间内产生的所述第一时钟信号的宽度小于第N帧周期中第一个数据使能信号的上升沿和下降沿形成时间区间之外产生的所述第一时钟信号的宽度，第N帧周期中第一个数据使能信号的上升沿和下降沿形成时间区间内产生的所述第二时钟信号的宽度小于第N帧周期中第一个数据使能信号的上升沿和下降沿形成时间区间之外产生的所述第二时钟信号的宽度。
  15. 根据权利要求1所述的显示装置，其中，在所述起始信号的上升沿和下降沿形成时间区间内产生所述第二时钟信号的上升沿和下降沿。
  16. 根据权利要求1所述的显示装置，其中，在所述起始信号的上升沿和下降沿形成时间区间内，所述第二时钟信号的上升沿在所述起始信号的上升沿之后产生，所述第二时钟信号的下降沿在所述起始信号的下降沿之前产生。
  17. 根据权利要求1所述的显示装置，其中，所述栅极驱动电路包括用于传输所述起始信号的起始信号线、用于传输所述第一时钟信号的第一时钟信号线、 用于传输所述第二时钟信号的第二时钟信号线和级联的多个移位寄存器，每级所述移位寄存器包括移位输入端、输出端、第一信号端、第二信号端和级联信号端；所述多个移位寄存器包括第一虚设移位寄存器、第一级扫描移位寄存器至第M级扫描移位寄存器，所述第一级扫描移位寄存器与所述第一虚设移位寄存器级联，M≥2；
    所述第一虚设移位寄存器以及偶数级扫描移位寄存器的第一信号端连接于所述第二时钟信号线，所述第一虚设移位寄存器以及偶数级扫描移位寄存器的第二信号端连接于所述第一时钟信号线；
    奇数级扫描移位寄存器的第一信号端连接于所述第一时钟信号线，奇数级扫描移位寄存器的第二信号端连接于所述第二时钟信号线；
    所述第一虚设移位寄存器的移位输入端连接于所述起始信号线，每级扫描移位寄存器的移位输入端连接于所述每级扫描移位寄存器的上一级移位寄存器的级联信号端。
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