WO2017020526A1 - 显示面板及其驱动方法及显示装置 - Google Patents

显示面板及其驱动方法及显示装置 Download PDF

Info

Publication number
WO2017020526A1
WO2017020526A1 PCT/CN2015/100137 CN2015100137W WO2017020526A1 WO 2017020526 A1 WO2017020526 A1 WO 2017020526A1 CN 2015100137 W CN2015100137 W CN 2015100137W WO 2017020526 A1 WO2017020526 A1 WO 2017020526A1
Authority
WO
WIPO (PCT)
Prior art keywords
timing
signal
control signals
timing control
group
Prior art date
Application number
PCT/CN2015/100137
Other languages
English (en)
French (fr)
Inventor
李付强
樊君
陈小川
董学
Original Assignee
京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 鄂尔多斯市源盛光电有限责任公司 filed Critical 京东方科技集团股份有限公司
Priority to US15/129,650 priority Critical patent/US10210789B2/en
Publication of WO2017020526A1 publication Critical patent/WO2017020526A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0205—Simultaneous scanning of several lines in flat panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0218—Addressing of scan or signal lines with collection of electrodes in groups for n-dimensional addressing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present disclosure relates to a display panel, a driving method thereof, and a display device.
  • liquid crystal displays have been widely used in electronic display products such as televisions, computers, mobile phones and personal digital assistants.
  • the liquid crystal display includes a data driver (Source Driver), a gate driver (Gate Driver), a liquid crystal display panel, and the like.
  • the liquid crystal display panel has a pixel array, and the gate driving device is configured to sequentially open corresponding pixel rows in the pixel array to transmit the pixel data output by the data driver to the pixels, thereby displaying the image to be displayed.
  • the gate driving device is generally formed on the array substrate of the liquid crystal display by an array process, that is, a Gate Driver on Array (GOA) process.
  • GAA Gate Driver on Array
  • This integrated process not only saves cost, but also achieves a symmetrical aesthetic design on both sides of the LCD panel.
  • it also eliminates the Bonding area of the integrated circuit (IC) and the fan-out area.
  • the wiring space of the (Fan-out) area enables the design of a narrow bezel.
  • this integrated process also eliminates the Bonding process in the direction of the gate scan line, thereby increasing throughput and yield.
  • the gate driving device is generally composed of a plurality of cascaded shift registers, and each of the shift registers corresponds to a gate line for sequentially outputting scan signals to the respective gate lines in the scanning direction.
  • embodiments of the present disclosure provide a display panel, a driving method thereof, and a display device.
  • the display panel can reduce the resolution in a specific case, thereby reducing the power consumption of the display panel.
  • a display panel provided by an embodiment of the present disclosure includes 4N gate lines located at the display panel a first gate driving circuit connected to the 4n+1th gate line on one side and a third gate driving circuit connected to the 4n+3th gate line on the other side of the display panel and 4n+ a second gate driving circuit connected to the two gate lines and a fourth gate driving circuit connected to the 4n+4 gate lines, and at least one output to each gate driving circuit connected to each gate driving circuit a corresponding set of timing control signal driving control circuit; wherein n is an integer greater than and equal to 0 and less than N, each set of timing control signals includes at least a trigger signal and a clock signal, and each group of timing control signals trigger signals Each of the gate driving circuits is configured to sequentially output a scan signal to the corresponding gate line under the control of the received corresponding group timing control signal; and further includes: a mode switching circuit connected to the driving control circuit;
  • the mode switching circuit is configured to, when receiving the first mode control signal, control the driving control circuit to drive all the gate driving circuits to sequentially follow the two adjacent gate lines as a first gate line group in the scanning direction.
  • the first gate line group outputs a scan signal;
  • the mode switching circuit is configured to, when receiving the second mode control signal, control the driving control circuit to drive all the gate driving circuits to sequentially follow the four adjacent gate lines as a second gate line group in the scanning direction.
  • the second gate line group outputs a scan signal.
  • the mode switching circuit when receiving the first mode control signal, the mode switching circuit may be used to:
  • the timing of each signal in the first group of timing control signals is the same as the timing of the corresponding signals in the second group of timing control signals, and the timing of each signal in the third group of timing control signals and the fourth group of timing control The timings of the corresponding signals in the signal are the same, and the timing of each of the signals in the third group of timing control signals is delayed by one trigger signal width than the timing of the corresponding signals in the first group of timing control signals.
  • the mode switching circuit when receiving the second mode control signal, the mode switching circuit may be used to:
  • the circuit outputs a third group of timing control signals, and the fourth group outputs to the fourth gate driving circuit Timing control signal; among them,
  • Timing of each signal in the first set of timing control signals and timing of corresponding signals in the second set of timing control signals, timing of corresponding signals in the third set of timing control signals, and fourth set of timing control The timing of the corresponding signals in the signal is the same.
  • the mode switching circuit is further configured to:
  • the drive control circuit When receiving the third mode control signal, the drive control circuit is controlled to drive all of the gate drive circuits to sequentially output scan signals to the N gate lines in the scan direction.
  • the mode switching circuit when receiving the third mode control signal, the mode switching circuit may be used to:
  • Controlling the driving control circuit to sequentially output a first group of timing control signals to the first gate driving circuit, and output a second group of timing control signals to the second gate driving circuit to the third gate driving
  • the circuit outputs a third group of timing control signals, and outputs a fourth group of timing control signals to the fourth gate driving circuit;
  • timing of each signal in the second set of timing control signals is delayed by one-half of a trigger signal width than a timing of a corresponding signal in the first set of timing control signals; timing of each signal in the third set of timing control signals Delaying a timing of one-half of a trigger signal width than a timing of a corresponding signal in the second set of timing control signals; timing of each signal in the fourth set of timing control signals is greater than a corresponding signal in the third set of timing control signals The timing delay is one-half of the trigger signal width.
  • the display panel provided by the embodiment of the present disclosure is a liquid crystal display panel or an organic electroluminescence display panel.
  • the embodiment of the present disclosure further provides a driving method of any one of the foregoing display panels provided by the embodiment of the present disclosure, including:
  • the driving control circuit When the mode switching circuit receives the first mode control signal, the driving control circuit is driven to drive all the gate driving circuits to sequentially follow the two adjacent gate lines as a first gate line group in the scanning direction.
  • the first gate line group outputs a scan signal
  • the driving control circuit When the mode switching circuit receives the second mode control signal, the driving control circuit is driven to drive all the gate driving circuits to sequentially follow the four adjacent gate lines as a second gate line group in the scanning direction.
  • the second grid line group outputs a scanning signal
  • the driving control circuit is controlled to drive all the gate driving circuits to sequentially output the scanning signals to the N gate lines in the scanning direction.
  • the mode switching circuit controls the driving control circuit to drive all the gate driving circuits to have two adjacent gate lines as a first gate line along the scanning direction.
  • the group sequentially outputs a scan signal to each of the first gate line groups, which may be:
  • the mode switching circuit controls a second set of timing control signals output by the driving control circuit to the first gate driving circuit while outputting a first group of timing control signals to the second gate driving circuit, to the a fourth group of timing control signals outputted to the fourth gate driving circuit while the third gate driving circuit outputs the third group timing control signal;
  • the timing of each signal in the first group of timing control signals is the same as the timing of the corresponding signals in the second group of timing control signals, and the timing of each signal in the third group of timing control signals and the fourth group of timing control The timings of the corresponding signals in the signal are the same, and the timing of each of the signals in the third group of timing control signals is delayed by one trigger signal width than the timing of the corresponding signals in the first group of timing control signals.
  • the mode switching circuit controls the driving control circuit to drive all the gate driving circuits to use the adjacent four gate lines as a second gate line group along the scanning direction. And sequentially outputting a scan signal to each of the second gate line groups, which may be:
  • the circuit outputs a third group of timing control signals, and outputs a fourth group of timing control signals to the fourth gate driving circuit;
  • Timing of each signal in the first set of timing control signals and timing of corresponding signals in the second set of timing control signals, timing of corresponding signals in the third set of timing control signals, and fourth set of timing control The timing of the corresponding signals in the signal is the same.
  • the mode switching circuit controls the driving control circuit to drive all the gate driving circuits to sequentially output scan signals to the N gate lines in the scanning direction, which may be :
  • each signal in the second set of timing control signals is delayed by one-half of a trigger signal width than a timing of a corresponding signal in the first set of timing control signals; each of the third set of timing control signals The timing of the signal is delayed by one-half of the trigger signal width than the timing of the corresponding signal in the second set of timing control signals; the timing of each of the fourth set of timing control signals is greater than the timing of the third set of timing control signals The timing of the corresponding signal is delayed by one-half of the trigger signal width.
  • the embodiment of the present disclosure further provides a display device, including any of the above display panels provided by the embodiments of the present disclosure.
  • the driving method, the display panel and the display device of the display panel provided by the embodiment of the present disclosure further include a mode switching circuit connected to the driving control circuit, and the mode switching circuit is configured to receive the image display circuit.
  • the control driving control circuit drives all the gate driving circuits to sequentially output the scanning signals to the first gate line groups in the scanning direction by the adjacent two gate lines as a first gate line group; and/or
  • the mode switching circuit is configured to, when receiving the second mode control signal, control the driving control circuit to drive all the gate driving circuits to sequentially follow the four adjacent gate lines to the second gate line group in the scanning direction.
  • the scan signal is output.
  • the mode control signal can be sent to the mode switching circuit of the display panel as needed, and the resolution of the display panel can be reduced to 1/2 resolution or reduced to 1/4 resolution, thereby reducing the performance of the display panel. Consumption, extend standby time.
  • 1a is a schematic structural view of a known display panel
  • FIG. 1b is a timing diagram of input and output corresponding to the display panel shown in FIG. 1a;
  • FIG. 2 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure
  • 3a is a timing diagram of controlling four sets of timing control signals output by the driving control circuit when the mode switching circuit receives the first mode control signal in the display panel according to an embodiment of the present disclosure
  • FIG. 3b is a timing diagram of scan signals on a gate line corresponding to each group of timing control signals in the display panel according to the embodiment of the present disclosure
  • 4a is a timing diagram of controlling four sets of timing control signals output by a driving control circuit when a mode switching circuit receives a second mode control signal in a display panel according to an embodiment of the present disclosure
  • 4b is a timing diagram of scan signals on a gate line corresponding to each group of timing control signals in the display panel according to the embodiment of the present disclosure, as shown in FIG. 4a;
  • FIG. 5 is a schematic structural diagram of a gate driving circuit according to an embodiment of the present disclosure.
  • FIG. 5b is a timing diagram of input and output of a first gate driving circuit provided by an embodiment of the present disclosure
  • FIG. 6 is a flowchart of a driving method of a display panel according to an embodiment of the present disclosure.
  • Fig. 1a shows a schematic structural view of a known display panel.
  • the display panel includes 4N gate lines, and the first gate driving circuits GOA1 and 4n connected to the 4n+1th gate lines (gate1, gate5, gate9, ...) on one side of the display panel.
  • Each of the gate driving circuits is configured to sequentially output a scan signal to the corresponding gate line under the control of the received corresponding group timing control signal.
  • the first group of timing control signals outputted by the drive control circuit 1 to the first gate drive circuit GOA1 in sequence includes: a first trigger signal STV1, a first clock signal CK1 and a second clock signal CKB1; and outputs to the second gate drive circuit GOA2
  • the second set of timing control signals includes: a second trigger signal STV2, a third clock signal CK2, and a fourth clock signal CKB2
  • a third group of timing control signals outputted to the third gate driving circuit GOA3 includes: a third trigger signal STV3
  • the fifth clock signal CK3 and the sixth clock signal CKB3; and the fourth group of timing control signals outputted to the fourth gate driving circuit GOA4 include a fourth trigger signal STV4, a seventh clock signal CK4, and an eighth clock signal CKB4.
  • the driving control circuit 1 delays the timing of each signal in the second group of timing control signals from the timing of the corresponding signals in the first group of timing control signals in order to drive all the gate driving circuits to sequentially output scanning signals to the N gate lines in the scanning direction.
  • One-half of the trigger signal width; the timing of each signal in the third group of timing control signals is delayed by one-half of the trigger signal width of the corresponding signal in the second group of timing control signals; each of the fourth group of timing control signals The timing of the signal is delayed by one-half of the trigger signal width than the timing of the corresponding signal in the third set of timing control signals; and the two clock signals of the respective sets of timing control signals differ in timing by one trigger signal width.
  • each group of timing control signals and the scan signals on the gate lines (gate1, gate2, gate3, ...) is as shown in FIG. 1b, wherein only the timing of the scan signals on the first 8 gate lines is shown in FIG. 1b, and the remaining The traced signals on the grid lines are analogous.
  • each gate driving circuit can only realize the function of scanning the gate line progressively under the control of the driving control circuit 1.
  • the resolution of the display panel is relatively high, the power consumption increases as the resolution increases, resulting in a greatly reduced standby time.
  • the present disclosure is a display panel based on the above connection method, and provides a display panel which can reduce power consumption according to requirements.
  • FIG. 2 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure.
  • the display panel includes 4N gate lines, and a first gate driving circuit GOA1 connected to the 4n+1th gate lines (gate1, gate5, gate9, ...) on one side of the display panel and
  • the third gate driving circuit GOA3 connected to the 4n+3 gate lines (gate3, gate7, gate11...) is connected to the 4n+2 gate lines (gate2, gate6, gate10%) on the other side of the display panel.
  • the second gate driving circuit GOA2 and the fourth gate driving circuit GOA4 connected to the 4n+4th gate lines (gate4, gate8, gate12, ...), and the respective gate driving circuits (GOA1, GOA2, GOA3, and GOA4) a drive control circuit 1 connected to at least one set of timing control signals for outputting respective gate drive circuits (GOA1, GOA2, GOA3, and GOA4), wherein n is an integer greater than and equal to 0 and less than N .
  • Each group of timing control signals includes at least a trigger signal and a clock signal, and the widths of the trigger signals in each group of timing control signals are the same, and each gate driving circuit (GOA1, GOA2, GOA3, and GOA4) is used for receiving the corresponding group timing control signal.
  • the scan signal is sequentially output to the corresponding gate line under the control of the control.
  • the display panel further includes a mode switching circuit 2 connected to the drive control circuit 1.
  • the mode switching circuit 2 can be configured to control the drive control circuit 1 to drive all of the gate drive circuits (GOA1, GOA2, GOA3, and GOA4) in the scanning direction when the first mode control signal is received.
  • the adjacent two gate lines are a first gate line group and sequentially output scan signals to the respective first gate line groups, that is, the display panel is simultaneously scanned by two gate lines, and the resolution of the display panel is reduced to 1/2 resolution. rate.
  • the mode switching circuit 2 may be further configured to control the driving control circuit 1 to drive all the gate driving circuits (GOA1, GOA2, GOA3, and GOA4) upon receiving the second mode control signal.
  • Scanning signals are sequentially output to the respective second gate line groups in the scanning direction by the adjacent four gate lines as a second gate line group, that is, the display panel is simultaneously scanned by four gate lines, and the resolution of the display panel is reduced to 1/ 4 resolution.
  • the above display panel provided by the embodiment of the present disclosure shown in FIG. 2 further includes a mode switching circuit 2 connected to the driving control circuit 1 as compared with the display panel shown in FIG.
  • the control driving control circuit 1 drives all the gate driving circuits to sequentially scan the first gate line group as the first gate line group in the scanning direction along the two adjacent gate lines.
  • the signal switching circuit 2 and/or the mode switching circuit 2 is configured to control the driving control circuit 1 to drive all the gate driving circuits in the scanning direction with the adjacent four gate lines as a second gate line group in sequence when receiving the second mode control signal.
  • a scan signal is output to each of the second gate line groups.
  • the mode control signal can be sent to the mode switching circuit 2 of the display panel as needed, and the resolution of the display panel can be reduced to 1/2 resolution or reduced to 1/4 resolution, so that the display panel can be made. Reduced power consumption and extended standby time.
  • the mode switching circuit 2 when receiving the first mode control signal, can be used to:
  • FIG. 3a is a timing diagram showing four sets of timing control signals output by the control driving control circuit when the mode switching circuit 2 receives the first mode control signal in the display panel provided by the embodiment of the present disclosure.
  • the timing of each of the first set of timing control signals (including at least the first trigger signal STV1, the first clock signal CK1, and the second clock signal CKB1) and the second set of timing control signals (including at least the second The timings of the corresponding signals in the trigger signal STV2, the third clock signal CK2, and the fourth clock signal CKB2) are the same, and the third group of timing control signals (including at least the third trigger signal STV3, the fifth clock signal CK3, and the sixth clock signal CKB3)
  • the timing of each of the signals is the same as the timing of the corresponding signal in the fourth group of timing control signals (including at least the fourth trigger signal STV4, the seventh clock signal CK4, and the eighth clock signal CKB4), and each of the signals in the third group of timing control signals
  • the timing is delayed by one trigger signal width than the timing of the corresponding signal in the first set of timing control signals.
  • timing of the four sets of timing control signals that are known to implement progressive driving is changed to coincide with the timing of the first group of timing control signals
  • the timing of the fourth group of timing control signals is changed to coincide with the timing of the third group of timing control signals.
  • FIG. 3b is a timing diagram of the timing signals of the sets of timing control signals in the display panel provided by the embodiment of the present disclosure, as shown in FIG. 3a, the timing of the scan signals on the gate lines (gate1, gate2, gate3, ...) in the corresponding display panel.
  • the mode switching circuit 2 can be used to: when receiving the second mode control signal:
  • the control signal is a fourth set of timing control signals output to the fourth gate driving circuit.
  • FIG. 4a is a timing diagram showing four sets of timing control signals output by the drive control circuit 1 when the mode switching circuit 2 receives the second mode control signal in the display panel provided by the embodiment of the present disclosure.
  • the timing of each of the first set of timing control signals including at least the first trigger signal STV1, the first clock signal CK1, and the second clock signal CKB1 and the second set of timing control signals (including at least the second The timing of the corresponding signal in the trigger signal STV2, the third clock signal CK2, and the fourth clock signal CKB2), and the third group of timing control signals (including at least the third trigger signal STV3, the fifth clock signal CK3, and the sixth clock signal CKB3)
  • the timing of the corresponding signal and the timing of the corresponding signals in the fourth group of timing control signals including at least the fourth trigger signal STV4, the seventh clock signal CK4, and the eighth clock signal CKB4) are all the same. That is, it is equivalent to setting the timings of the four sets of timing control signals to be consistent on the basis of the known four sets
  • FIG. 4b is a timing diagram of timing signals of each group in the display panel provided by the embodiment of the present disclosure, as shown in FIG. 4a, the timing of the scan signals on the gate lines (gate1, gate2, gate3, ...) in the corresponding display panel. .
  • the mode switching circuit 2 can also be used to:
  • the control drive control circuit 1 drives all of the gate drive circuits to sequentially output scan signals to the N gate lines in the scanning direction.
  • the mode switching circuit 2 is connected When the third mode control signal is received, it can be used to:
  • the control driving control circuit 1 sequentially outputs a first group timing control signal to the first gate driving circuit, a second group timing control signal outputted to the second gate driving circuit, and outputs a third group timing control to the third gate driving circuit. Signal, a fourth set of timing control signals output to the fourth gate drive circuit.
  • the timing diagram at this time is consistent with the timing of the known four sets of timing control signals that drive progressively.
  • the timing of each of the second group of timing control signals (including at least the second trigger signal STV2, the third clock signal CK2, and the fourth clock signal CKB2) is later than the first group of timing control signals (including at least the first The timing of the corresponding signal in the trigger signal STV1, the first clock signal CK1 and the second clock signal CKB1) is delayed by one-half of the trigger signal width;
  • the third group of timing control signals including at least the third trigger signal STV3, the fifth clock signal The timing of each signal in the CK3 and the sixth clock signal CKB3) is delayed by one-half of the trigger signal width than the timing of the corresponding signal in the second group of timing control signals;
  • the fourth group of timing control signals (including at least the fourth trigger signal STV4, The timing of each of the seventh clock signal CK4 and the eighth clock signal CKB4) is delayed by one-half of the trigger signal width from the timing of the corresponding signal in the
  • the user can send a mode control signal to the mode switching circuit 2 through the operation interface of the display panel according to actual needs, which is not limited herein.
  • the control of a gate drive circuit by a set of timing control signals is exemplified by a specific embodiment.
  • FIG. 5a is a schematic structural diagram of a gate driving circuit according to an embodiment of the present disclosure.
  • the gate driving circuit is composed of a plurality of cascaded shift registers: SR(1), SR(2)...SR(m)...SR(N-1), SR(N) (total N One shift register, 1 ⁇ m ⁇ N). Except for the last stage shift register SR(N), the output terminals Output_m (1 ⁇ m ⁇ N) of each of the shift register SR(m) are respectively shifted to the next-stage shift register SR adjacent thereto ( m+1) provides the input signal Input.
  • the input signal Input of the first stage shift register SR(1) is a trigger signal received by the gate driving circuit; the gate driving circuit sequentially outputs to the corresponding gate line through the output terminal Output_m of each stage shift register SR(m) Scan the signal.
  • the driving control circuit inputs the first trigger signal STV1 to the first stage shift register SR(1), and inputs the first clock signal CK1 to the shift registers SR(m), respectively.
  • the scan signal is output to the first gate line gate1 when the first valid pulse signal of the first clock signal CK1 is started to be received; the scan signal outputted by the first stage shift register SR(1) is used as the second stage shift register SR ( 2)
  • the input signal Input when the second stage shift register SR(2) receives the scan signal output by the first stage shift register SR(1), starts to receive the first valid pulse of the second clock signal CKB1
  • the scan signal is output to the fifth gate line gate5;
  • the scan signal outputted by the second stage shift register SR(2) is used as the input signal Input of the third stage shift register SR(3), when the third stage shift register
  • SR(3) outputs a scan signal to the ninth gate line gate9 when starting to receive the first valid pulse signal of the first clock signal CK1;
  • the scan signal output from the three-stage shift register SR(3) is used as the input signal Input of the fourth stage shift register
  • Fig. 5b shows an input/output timing diagram corresponding to the first gate driving circuit. It should be noted that, in the display panel provided by the embodiment of the present disclosure, in the first mode control signal, the second mode control signal, and the third mode control signal, the sustain duration of each mode control signal is used for scanning 4N gate lines. An integer multiple of the duration, and the switching point between any two mode control signals is synchronized with the starting point of the scanning gate line.
  • the working principles of the second gate driving circuit, the third gate driving circuit, and the fourth gate driving circuit are the same as those of the first gate driving circuit, and are not described herein.
  • the display panel provided by the embodiment of the invention may be a liquid crystal display panel or an organic electroluminescence display panel, which is not limited herein.
  • an embodiment of the present disclosure further provides a display device, including any of the above display panels provided by the embodiments of the present disclosure.
  • the display device can be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display function such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • an embodiment of the present disclosure further provides a driving method of the above display panel.
  • FIG. 6 is a flow chart showing a driving method of a display panel provided by an embodiment of the present disclosure.
  • the driving method of the display panel includes the following working processes:
  • step S601 when the mode switching circuit receives the first mode control signal, the control driving control circuit drives all the gate driving circuits to sequentially follow the two adjacent gate lines as a first gate line group in the scanning direction.
  • a raster line group outputs a scan signal;
  • step S602 when the mode switching circuit receives the second mode control signal, the control driving control circuit drives all the gate driving circuits to sequentially follow the four adjacent gate lines as a second gate line group in the scanning direction.
  • the gate line group outputs a scan signal
  • step S603 when the mode switching circuit receives the third mode control signal, the control driving control circuit drives all of the gate driving circuits to sequentially output the scanning signals to the N gate lines in the scanning direction.
  • step S601, step S602, and step S603 are alternatively selected relationships, and which step is determined according to the mode control signal received by the mode switching circuit.
  • the mode switching circuit controls the driving control circuit to drive all the gate driving circuits to sequentially follow the two adjacent gate lines as a first gate line group in the scanning direction.
  • the first gate line group outputs a scan signal, which can be implemented as follows:
  • the mode switching circuit outputs a second set of timing control signals to the second gate driving circuit while controlling the driving control circuit to output the first group of timing control signals to the first gate driving circuit, and outputs the second group to the third gate driving circuit a fourth group of timing control signals simultaneously outputted to the fourth gate driving circuit by the three sets of timing control signals;
  • the timing of each signal in the first group of timing control signals is the same as the timing of the corresponding signals in the second group of timing control signals, and the timing of each signal in the third group of timing control signals is the same as the timing of the corresponding signals in the fourth group of timing control signals.
  • the timing of each of the third set of timing control signals is delayed by one trigger signal width from the timing of the corresponding one of the first set of timing control signals.
  • the mode switching circuit controls the driving control circuit to drive all the gate driving circuits to sequentially follow the four adjacent gate lines as a second gate line group in the scanning direction.
  • the output signal of the second grid line group can be implemented as follows:
  • Controlling the drive control circuit to output a third set of timing control signals to the second gate drive circuit while outputting the first set of timing control signals to the first gate drive circuit, and outputting a third set of timing control to the third gate drive circuit a fourth set of timing control signals output to the fourth gate driving circuit;
  • Timing of each signal in the first set of timing control signals and timing of corresponding signals in the second set of timing control signals, timing of corresponding signals in the third set of timing control signals, and fourth set of timing control signals The timing of the corresponding signals is the same.
  • the mode switching circuit controls the driving control circuit to drive all the gate driving circuits to sequentially output the scanning signals to the N gate lines in the scanning direction, which can be implemented as follows:
  • the timing of each signal in the second group of timing control signals is delayed by one-half of the trigger signal width than the timing of the corresponding signals in the first group of timing control signals; the timing of each signal in the third group of timing control signals is compared with the second group of timing controls The timing of the corresponding signal in the signal is delayed by one-half of the trigger signal width; the timing of each signal in the fourth group of timing control signals is delayed by one-half of the trigger signal width than the timing of the corresponding signal in the third group of timing control signals.
  • a display panel, a driving method thereof, and a display device further include a mode switching circuit connected to a driving control circuit, and a mode switching circuit for receiving the first a mode control signal, the control drive control circuit drives all the gate drive circuits to sequentially output the scan signals to the first gate line groups in the scan direction with the adjacent two gate lines as a first gate line group; and/or mode
  • the switching circuit is configured to, when receiving the second mode control signal, control the driving control circuit to drive all the gate driving circuits to sequentially output the second gate line group to the second gate line group in the scanning direction. Scan the signal.
  • the mode control signal can be sent to the mode switching circuit of the display panel as needed, and the resolution of the display panel can be reduced to 1/2 resolution or reduced to 1/4 resolution, thereby reducing the performance of the display panel. Consumption, extend standby time.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种显示面板及其驱动方法及显示装置，该显示面板包括4N条栅线（gate1、gate2、gate3、……gate4N），以及与各栅极驱动电路（GOA1、GOA2、GOA3、GOA4）连接的至少用于向各栅极驱动电路（GOA1、GOA2、GOA3、GOA4）输出一一对应的一组时序控制信号的驱动控制电路（1），该显示面板还包括：与驱动控制电路（1）连接的模式切换电路（2），该模式切换电路（2）可以在接收到第一模式控制信号时，控制驱动控制电路（1）驱动所有栅极驱动电路（GOA1、GOA2、GOA3、GOA4）沿扫描方向以相邻的两条栅线为一第一栅线组依次向各第一栅线组输出扫描信号；和/或模式切换电路（2）可以在接收到第二模式控制信号时，控制驱动控制电路（1）驱动所有栅极驱动电路（GOA1、GOA2、GOA3、GOA4）沿扫描方向以相邻的四条栅线为一第二栅线组依次向各第二栅线组输出扫描信号。因此，可以使显示面板降低功耗，延长待机时间。

Description

显示面板及其驱动方法及显示装置 技术领域
本公开涉及一种显示面板及其驱动方法及显示装置。
背景技术
在科技发展日新月异的现今时代中，液晶显示器已经广泛地应用在电子显示产品上，如电视机、计算机、手机及个人数字助理装置等。液晶显示器包括数据驱动装置(Source Driver)、栅极驱动装置(Gate Driver)及液晶显示面板等。其中，液晶显示面板中具有像素阵列，而栅极驱动装置用以依序开启像素阵列中对应的像素行，以将数据驱动器输出的像素数据传输至像素，进而显示待显示的图像。
目前，栅极驱动装置一般通过阵列工艺形成在液晶显示器的阵列基板上，即阵列基板行驱动(Gate Driver on Array,GOA)工艺。这种集成工艺不仅节省了成本，而且可以做到液晶面板(Panel)两边对称的美观设计，同时，也省去了栅极集成电路(IC，Integrated Circuit)的绑定(Bonding)区域以及扇出(Fan-out)区域的布线空间，从而可以实现窄边框的设计。并且，这种集成工艺还可以省去栅极扫描线方向的Bonding工艺，从而提高了产能和良率。栅极驱动装置通常由多个级联的移位寄存器构成，各级移位寄存器分别对应一条栅线，用于沿扫描方向依次向各栅线输出扫描信号。
但是，随着显示产品分辨率越来越高，显示面板上需要刷新的栅线的条数也越多，从而导致功耗也随着分辨率的增大而增大，因此待机时间大大减小。因此如何降低显示产品的功耗，以提高待机时间是本领域技术人员亟需解决的技术问题。
发明内容
有鉴于此，本公开实施例提供一种显示面板及其驱动方法及显示装置。该显示面板在特定情况下可以降低分辨率，从而降低显示面板的功耗。
本公开实施例提供的一种显示面板，包括4N条栅线，位于所述显示面板 一侧的与第4n+1条栅线连接的第一栅极驱动电路和与第4n+3条栅线连接的第三栅极驱动电路，位于所述显示面板另一侧的与第4n+2条栅线连接的第二栅极驱动电路和与第4n+4条栅线连接的第四栅极驱动电路，以及与各栅极驱动电路连接的至少用于向各栅极驱动电路输出一一对应的一组时序控制信号的驱动控制电路；其中，n为大于且等于0且小于N的整数，各组时序控制信号至少包括触发信号和时钟信号，且各组时序控制信号中触发信号的宽度相同，各所述栅极驱动电路用于在接收的对应组时序控制信号的控制下依次向对应的栅线输出扫描信号；还包括：与所述驱动控制电路连接的模式切换电路；其中，
所述模式切换电路用于在接收到第一模式控制信号时，控制所述驱动控制电路驱动所有栅极驱动电路沿扫描方向以相邻的两条栅线为一第一栅线组依次向各所述第一栅线组输出扫描信号；和/或
所述模式切换电路用于在接收到第二模式控制信号时，控制所述驱动控制电路驱动所有栅极驱动电路沿扫描方向以相邻的四条栅线为一第二栅线组依次向各所述第二栅线组输出扫描信号。
在一种可能的实施方式中，在本公开实施例提供的显示面板中，所述模式切换电路在接收到第一模式控制信号时，可以用于：
控制所述驱动控制电路向所述第一栅极驱动电路输出第一组时序控制信号的同时向所述第二栅极驱动电路输出的第二组时序控制信号，向所述第三栅极驱动电路输出第三组时序控制信号的同时向所述第四栅极驱动电路输出的第四组时序控制信号；其中，
所述第一组时序控制信号中各信号的时序与所述第二组时序控制信号中对应信号的时序相同，所述第三组时序控制信号中各信号的时序与所述第四组时序控制信号中对应信号的时序相同，所述第三组时序控制信号中各信号的时序比所述第一组时序控制信号中对应信号的时序延迟一个触发信号宽度。
在一种可能的实施方式中，在本公开实施例提供的显示面板中，所述模式切换电路在接收到第二模式控制信号时，可以用于：
控制所述驱动控制电路向所述第一栅极驱动电路输出第一组时序控制信号的同时向所述第二栅极驱动电路输出的第二组时序控制信号，向所述第三栅极驱动电路输出第三组时序控制信号，向所述第四栅极驱动电路输出的第四组 时序控制信号；其中，
所述第一组时序控制信号中各信号的时序与所述第二组时序控制信号中对应信号的时序、所述第三组时序控制信号中对应信号的时序、以及所述第四组时序控制信号中对应信号的时序均相同。
示例性地，在本公开实施例提供的显示面板中，所述模式切换电路还用于：
在接收到第三模式控制信号时，控制所述驱动控制电路驱动所有栅极驱动电路沿扫描方向依次向所述N条栅线输出扫描信号。
在一种可能的实施方式中，在本公开实施例提供的显示面板中，所述模式切换电路在接收到第三模式控制信号时，可以用于：
控制所述驱动控制电路依次向所述第一栅极驱动电路输出第一组时序控制信号，向所述第二栅极驱动电路输出的第二组时序控制信号，向所述第三栅极驱动电路输出第三组时序控制信号，向所述第四栅极驱动电路输出的第四组时序控制信号；其中，
所述第二组时序控制信号中各信号的时序比所述第一组时序控制信号中对应信号的时序延迟二分之一个触发信号宽度；所述第三组时序控制信号中各信号的时序比所述第二组时序控制信号中对应信号的时序延迟二分之一个触发信号宽度；所述第四组时序控制信号中各信号的时序比所述第三组时序控制信号中对应信号的时序延迟二分之一个触发信号宽度。
在具体实施时，本公开实施例提供的显示面板为液晶显示面板或有机电致发光显示面板。
相应地，本公开实施例还提供了一种本公开实施例提供的上述任一种显示面板的驱动方法，包括：
当所述模式切换电路接收到第一模式控制信号时，控制所述驱动控制电路驱动所有栅极驱动电路沿扫描方向以相邻的两条栅线为一第一栅线组依次向各所述第一栅线组输出扫描信号；
当所述模式切换电路接收到第二模式控制信号时，控制所述驱动控制电路驱动所有栅极驱动电路沿扫描方向以相邻的四条栅线为一第二栅线组依次向各所述第二栅线组输出扫描信号；
当所述模式切换电路在接收到第三模式控制信号时，控制所述驱动控制电路驱动所有栅极驱动电路沿扫描方向依次向所述N条栅线输出扫描信号。
示例性地，在本公开实施例提供的上述驱动方法中，所述模式切换电路控制所述驱动控制电路驱动所有栅极驱动电路沿扫描方向以相邻的两条栅线为一第一栅线组依次向各所述第一栅线组输出扫描信号，可以为：
所述模式切换电路控制所述驱动控制电路向所述第一栅极驱动电路输出第一组时序控制信号的同时向所述第二栅极驱动电路输出的第二组时序控制信号，向所述第三栅极驱动电路输出第三组时序控制信号的同时向所述第四栅极驱动电路输出的第四组时序控制信号；其中，
所述第一组时序控制信号中各信号的时序与所述第二组时序控制信号中对应信号的时序相同，所述第三组时序控制信号中各信号的时序与所述第四组时序控制信号中对应信号的时序相同，所述第三组时序控制信号中各信号的时序比所述第一组时序控制信号中对应信号的时序延迟一个触发信号宽度。
示例性地，在本公开实施例提供的上述驱动方法中，所述模式切换电路控制所述驱动控制电路驱动所有栅极驱动电路沿扫描方向以相邻的四条栅线为一第二栅线组依次向各所述第二栅线组输出扫描信号，可以为：
控制所述驱动控制电路向所述第一栅极驱动电路输出第一组时序控制信号的同时向所述第二栅极驱动电路输出的第二组时序控制信号，向所述第三栅极驱动电路输出第三组时序控制信号，向所述第四栅极驱动电路输出的第四组时序控制信号；其中，
所述第一组时序控制信号中各信号的时序与所述第二组时序控制信号中对应信号的时序、所述第三组时序控制信号中对应信号的时序、以及所述第四组时序控制信号中对应信号的时序均相同。
示例性地，在本公开实施例提供的上述驱动方法中，所述模式切换电路控制所述驱动控制电路驱动所有栅极驱动电路沿扫描方向依次向所述N条栅线输出扫描信号，可以为：
控制所述驱动控制电路向所述第一栅极驱动电路输出第一组时序控制信号的同时向所述第二栅极驱动电路输出的第二组时序控制信号；向所述第三栅极驱动电路输出第三组时序控制信号的同时向所述第四栅极驱动电路输出的第四组时序控制信号；其中，
所述第二组时序控制信号中各信号的时序比所述第一组时序控制信号中对应信号的时序延迟二分之一个触发信号宽度；所述第三组时序控制信号中各 信号的时序比所述第二组时序控制信号中对应信号的时序延迟二分之一个触发信号宽度；所述第四组时序控制信号中各信号的时序比所述第三组时序控制信号中对应信号的时序延迟二分之一个触发信号宽度。
相应地，本公开实施例还提供了一种显示装置，包括本公开实施例提供的上述任一种显示面板。
本公开实施例提供的一种显示面板的驱动方法、显示面板及显示装置，与现有的显示面板相比，还包括有与驱动控制电路连接的模式切换电路，模式切换电路用于在接收到第一模式控制信号时，控制驱动控制电路驱动所有栅极驱动电路沿扫描方向以相邻的两条栅线为一第一栅线组依次向各第一栅线组输出扫描信号；和/或模式切换电路用于在接收到第二模式控制信号时，控制驱动控制电路驱动所有栅极驱动电路沿扫描方向以相邻的四条栅线为一第二栅线组依次向各第二栅线组输出扫描信号。因此在实际应用中，可以根据需要向显示面板的模式切换电路发送模式控制信号，控制显示面板的分辨率降低为1/2分辨率或者降低为1/4分辨率，从而可以使显示面板降低功耗，延长待机时间。
附图说明
图1a为一种已知的显示面板的结构示意图；
图1b为图1a所示的显示面板所对应的输入输出时序图；
图2为本公开实施例提供的显示面板的结构示意图；
图3a为本公开实施例提供的显示面板中当模式切换电路接收到第一模式控制信号时控制驱动控制电路输出的四组时序控制信号的时序图；
图3b为当本公开实施例提供的显示面板中各组时序控制信号的时序图如图3a所示时所对应的栅线上的扫描信号时序图；
图4a为本公开实施例提供的显示面板中当模式切换电路接收到第二模式控制信号时控制驱动控制电路输出的四组时序控制信号的时序图；
图4b为当本公开实施例提供的显示面板中各组时序控制信号的时序图如图4a所示时所对应的栅线上的扫描信号时序图；
图5a为本公开实施例提供的栅极驱动电路的结构示意图；
图5b为当本公开实施例提供的第一栅极驱动电路的输入输出时序图；
图6为本公开实施例提供的显示面板的驱动方法的流程图。
具体实施方式
图1a示出一种已知的显示面板的结构示意图。如图1a所示，该显示面板包括4N条栅线，位于显示面板一侧的与第4n+1条栅线(gate1、gate5、gate9…)连接的第一栅极驱动电路GOA1和与第4n+3条栅线(gate3、gate7、gate11…)连接的第三栅极驱动电路GOA3，位于显示面板另一侧的与第4n+2条栅线(gate2、gate6、gate10…)连接的第二栅极驱动电路GOA2和与第4n+4条栅线(gate4、gate8、gate12…)连接的第四栅极驱动电路GOA4，以及与各栅极驱动电路(GOA1、GOA2、GOA3和GOA4)连接的至少用于向各栅极驱动电路输出一一对应的一组时序控制信号的驱动控制电路1，其中，n为大于且等于0且小于N的整数。各组时序控制信号至少包括触发信号和时钟信号，且各组时序控制信号中触发信号的宽度相同。各栅极驱动电路用于在接收的对应组时序控制信号的控制下依次向对应的栅线输出扫描信号。
驱动控制电路1依次向第一栅极驱动电路GOA1输出的第一组时序控制信号包括：第一触发信号STV1、第一时钟信号CK1和第二时钟信号CKB1；向第二栅极驱动电路GOA2输出的第二组时序控制信号包括：第二触发信号STV2、第三时钟信号CK2和第四时钟信号CKB2；向第三栅极驱动电路GOA3输出的第三组时序控制信号包括：第三触发信号STV3，第五时钟信号CK3和第六时钟信号CKB3；向第四栅极驱动电路GOA4输出的第四组时序控制信号包括：第四触发信号STV4、第七时钟信号CK4和第八时钟信号CKB4。驱动控制电路1为了实现驱动所有栅极驱动电路沿扫描方向依次向N条栅线输出扫描信号，使第二组时序控制信号中各信号的时序比第一组时序控制信号中对应信号的时序延迟二分之一个触发信号宽度；第三组时序控制信号中各信号的时序比第二组时序控制信号中对应信号的时序延迟二分之一个触发信号宽度；第四组时序控制信号中各信号的时序比第三组时序控制信号中对应信号的时序延迟二分之一个触发信号宽度；且各组时序控制信号中两个时钟信号在时序上相差一个触发信号宽度。具体地，各组时序控制信号以及栅线(gate1、gate2、gate3…)上的扫描信号的时序如图1b所示，其中图1b中仅示出前8条栅线上的扫描信号的时序，剩余栅线上的所描信号依次类推。
上述显示面板中，各栅极驱动电路在驱动控制电路1的控制下，只能实现逐行扫描栅线的功能。这样，当显示面板的分辨率比较高时，功耗会随着分辨率的增大而增大，从而导致待机时间大大减小。但是在实际应用中，在有些情况下，例如不方便充电的情况，我们既需要显示装置继续显示，又希望能够有较长待机时间的显示器，因此需要提供一种可以根据需求降低功耗的显示面板。
本公开正是基于上述连接方式的显示面板，提供了一种可以根据需求降低功耗的显示面板。
下面结合附图，对本公开实施例提供的显示面板及其驱动方法、显示装置的具体实施方式进行详细地说明。
图2示出本公开实施例提供的一种显示面板的结构示意图。如图1a和图2所示，该显示面板包括4N条栅线，位于显示面板一侧的与第4n+1条栅线(gate1、gate5、gate9…)连接的第一栅极驱动电路GOA1和与第4n+3条栅线(gate3、gate7、gate11…)连接的第三栅极驱动电路GOA3，位于显示面板另一侧的与第4n+2条栅线(gate2、gate6、gate10…)连接的第二栅极驱动电路GOA2和与第4n+4条栅线(gate4、gate8、gate12…)连接的第四栅极驱动电路GOA4，以及与各栅极驱动电路(GOA1、GOA2、GOA3和GOA4)连接的至少用于向各栅极驱动电路(GOA1、GOA2、GOA3和GOA4)输出一一对应的一组时序控制信号的驱动控制电路1，其中，n为大于且等于0且小于N的整数。各组时序控制信号至少包括触发信号和时钟信号，且各组时序控制信号中触发信号的宽度相同，各栅极驱动电路(GOA1、GOA2、GOA3和GOA4)用于在接收的对应组时序控制信号的控制下依次向对应的栅线输出扫描信号。如图2所示，该显示面板还包括：与驱动控制电路1连接的模式切换电路2。
在图2所示显示面板中，模式切换电路2可以用于在接收到第一模式控制信号时，控制驱动控制电路1驱动所有栅极驱动电路(GOA1、GOA2、GOA3和GOA4)沿扫描方向以相邻的两条栅线为一个第一栅线组依次向各个第一栅线组输出扫描信号，即显示面板是以两条栅线同时扫描的，显示面板的分辨率降低为1/2分辨率。
可替换地，模式切换电路2还可以用于在接收到第二模式控制信号时，控制驱动控制电路1驱动所有栅极驱动电路(GOA1、GOA2、GOA3和GOA4) 沿扫描方向以相邻的四条栅线为一个第二栅线组依次向各个第二栅线组输出扫描信号，即显示面板是以四条栅线同时扫描的，显示面板的分辨率降低为1/4分辨率。
可以注意到，图2所示的本公开实施例提供的上述显示面板，与图1所示的显示面板相比，还包括有与驱动控制电路1连接的模式切换电路2，模式切换电路2用于在接收到第一模式控制信号时，控制驱动控制电路1驱动所有栅极驱动电路沿扫描方向以相邻的两条栅线为一个第一栅线组依次向各个第一栅线组输出扫描信号；和/或模式切换电路2用于在接收到第二模式控制信号时，控制驱动控制电路1驱动所有栅极驱动电路沿扫描方向以相邻的四条栅线为一第二栅线组依次向各第二栅线组输出扫描信号。因此，在实际应用中，可以根据需要向显示面板的模式切换电路2发送模式控制信号，控制显示面板的分辨率降低为1/2分辨率或者降低为1/4分辨率，从而可以使显示面板的功耗降低，延长待机时间。
示例性地，在本公开实施例提供的上述显示面板中，模式切换电路2在接收到第一模式控制信号时，可以用于：
控制驱动控制电路1在向第一栅极驱动电路输出第一组时序控制信号的同时向第二栅极驱动电路输出的第二组时序控制信号，在向第三栅极驱动电路输出第三组时序控制信号的同时向第四栅极驱动电路输出的第四组时序控制信号。
图3a示出了本公开实施例提供的显示面板中当模式切换电路2接收到第一模式控制信号时控制驱动控制电路输出的四组时序控制信号的时序图。
如图3a所示，第一组时序控制信号(至少包括第一触发信号STV1、第一时钟信号CK1和第二时钟信号CKB1)中各信号的时序与第二组时序控制信号(至少包括第二触发信号STV2、第三时钟信号CK2和第四时钟信号CKB2)中对应信号的时序相同，第三组时序控制信号(至少包括第三触发信号STV3，第五时钟信号CK3和第六时钟信号CKB3)中各信号的时序与第四组时序控制信号(至少包括第四触发信号STV4、第七时钟信号CK4和第八时钟信号CKB4)中对应信号的时序相同，且第三组时序控制信号中各信号的时序比第一组时序控制信号中对应信号的时序延迟一个触发信号宽度。即相当于在已知的实现逐行驱动的四组时序控制信号时序的基础上，将第二组时序控制信号的 时序的改为与第一组时序控制信号的时序一致，将第四组时序控制信号的时序的改为与第三组时序控制信号的时序一致。
图3b示出当本公开实施例提供的显示面板中各组时序控制信号的时序图如图3a所示时对应的显示面板中栅线(gate1、gate2、gate3…)上的扫描信号的时序。
示例性地，在本公开实施例提供的上述显示面板中模式切换电路2在接收到第二模式控制信号时，可以用于：
控制驱动控制电路1在向第一栅极驱动电路输出第一组时序控制信号的同时向第二栅极驱动电路输出的第二组时序控制信号，向第三栅极驱动电路输出第三组时序控制信号，向第四栅极驱动电路输出的第四组时序控制信号。
图4a示出本公开实施例提供的显示面板中当模式切换电路2接收到第二模式控制信号时控制驱动控制电路1输出的四组时序控制信号的时序图。如图4a所示，第一组时序控制信号(至少包括第一触发信号STV1、第一时钟信号CK1和第二时钟信号CKB1)中各信号的时序与第二组时序控制信号(至少包括第二触发信号STV2、第三时钟信号CK2和第四时钟信号CKB2)中对应信号的时序、第三组时序控制信号(至少包括第三触发信号STV3，第五时钟信号CK3和第六时钟信号CKB3)中对应信号的时序、以及第四组时序控制信号(至少包括第四触发信号STV4、第七时钟信号CK4和第八时钟信号CKB4)中对应信号的时序均相同。即相当于在已知的实现逐行驱动的四组时序控制信号时序的基础上，将四组时序控制信号的时序均设置为一致。
图4b示出了当本公开实施例提供的显示面板中各组时序控制信号的时序图如图4a所示时对应的显示面板中栅线(gate1、gate2、gate3…)上的扫描信号的时序。
进一步地，在本公开实施例提供的上述显示面板中，模式切换电路2还可以用于：
在接收到第三模式控制信号时，控制驱动控制电路1驱动所有栅极驱动电路沿扫描方向依次向N条栅线输出扫描信号。这样，本公开实施例提供的上述显示面板不仅可以在需要省电的时候，设置为低分辨率显示，并且可以在不需要省电的时候实现高分辨率显示。
示例性地，在本公开实施例提供的上述显示面板中，模式切换电路2在接 收到第三模式控制信号时，可以用于：
控制驱动控制电路1依次向第一栅极驱动电路输出第一组时序控制信号，向第二栅极驱动电路输出的第二组时序控制信号，向第三栅极驱动电路输出第三组时序控制信号，向第四栅极驱动电路输出的第四组时序控制信号。
此时的时序图与已知的实现逐行驱动的四组时序控制信号的时序一致。如图1b所示，第二组时序控制信号(至少包括第二触发信号STV2、第三时钟信号CK2和第四时钟信号CKB2)中各信号的时序比第一组时序控制信号(至少包括第一触发信号STV1、第一时钟信号CK1和第二时钟信号CKB1)中对应信号的时序延迟二分之一个触发信号宽度；第三组时序控制信号(至少包括第三触发信号STV3，第五时钟信号CK3和第六时钟信号CKB3)中各信号的时序比第二组时序控制信号中对应信号的时序延迟二分之一个触发信号宽度；第四组时序控制信号(至少包括第四触发信号STV4、第七时钟信号CK4和第八时钟信号CKB4)中各信号的时序比第三组时序控制信号中对应信号的时序延迟二分之一个触发信号宽度。具体与参见图1b所进行的描述相同，在此不作详述。
在具体实施时，在本公开实施例提供的上述显示面板中，使用者可以根据实际需求通过该显示面板的操作界面向模式切换电路2发送模式控制信号，在此不作限定。
下面通过一个具体的实施例来举例说明一组时序控制信号对一个栅极驱动电路的控制。
图5a示出本公开实施例提供的栅极驱动电路的结构示意图。如图5a所示，该栅极驱动电路由级联的多个移位寄存器：SR(1)、SR(2)…SR(m)…SR(N-1)、SR(N)(共N个移位寄存器，1≤m≤N)构成。除最后一级移位寄存器SR(N)之外，其余每一级移位寄存器SR(m)的输出端Output_m(1≤m≤N)分别向与其相邻的下一级移位寄存器SR(m+1)提供输入信号Input。第一级移位寄存器SR(1)的输入信号Input为栅极驱动电路接收的触发信号；栅极驱动电路通过各级移位寄存器SR(m)的输出端Output_m顺序地向对应的栅线输出扫描信号。以第一栅极驱动电路GOA为例，驱动控制电路向第一级移位寄存器SR(1)输入第一触发信号STV1，分别向各级移位寄存器SR(m)输入第一时钟信号CK1和第二时钟信号CKB1。当第一级移位寄存器收到第一触发信号STV1后， 当开始接收第一时钟信号CK1的第一个有效脉冲信号时向第一条栅线gate1输出扫描信号；第一级移位寄存器SR(1)输出的扫描信号作为第二级移位寄存器SR(2)的输入信号Input，当第二级移位寄存器SR(2)收到第一级移位寄存器SR(1)输出的扫描信号后，当开始接收第二时钟信号CKB1的第一个有效脉冲信号时向第5条栅线gate5输出扫描信号；第二级移位寄存器SR(2)输出的扫描信号作为第三级移位寄存器SR(3)的输入信号Input，当第三级移位寄存器SR(3)收到第二级移位寄存器SR(2)输出的扫描信号后，当开始接收第一时钟信号CK1的第一个有效脉冲信号时向第9条栅线gate9输出扫描信号；第三级移位寄存器SR(3)输出的扫描信号作为第四级移位寄存器SR(4)的输入信号Input，当第四级移位寄存器SR(4)收到第三级移位寄存器SR(3)输出的扫描信号后，当开始接收第二时钟信号CKB2的第一个有效脉冲信号时向第13条栅线gate13输出扫描信号；依次类推，各级移位寄存器依次向对应的栅线输出扫描信号。
图5b示出了第一栅极驱动电路对应的输入输出时序图。需要说明的是，在本公开实施例提供的显示面板中，第一模式控制信号、第二模式控制信号以及第三模式控制信号中，各模式控制信号的维持时长是扫描4N条栅线所用的时长的整数倍，且任意两个模式控制信号之间的切换点与扫描栅线的起始点同步。
第二栅极驱动电路、第三栅极驱动电路和第四栅极驱动电路的工作原理与第一栅极驱动电路的工作原理相同，在此不作赘述。
进一步地，发明实施例提供的上述显示面板，既可以是液晶显示面板，也可以是有机电致发光显示面板，在此不作限定。
基于同一发明构思，本公开实施例还提供了一种显示装置，包括本公开实施例提供的上述任一种显示面板。该显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。该显示装置的实施可以参见上述显示面板的实施例，重复之处不再赘述。
基于同一发明构思，本公开实施例还提供了一种上述显示面板的驱动方法。
图6示出了本公开实施例提供的显示面板的驱动方法的流程图。
如图6所示，该显示面板的驱动方法包括下列工作过程：
在步骤S601中，当模式切换电路接收到第一模式控制信号时，控制驱动控制电路驱动所有栅极驱动电路沿扫描方向以相邻的两条栅线为一第一栅线组依次向各第一栅线组输出扫描信号；
在步骤S602中，当模式切换电路接收到第二模式控制信号时，控制驱动控制电路驱动所有栅极驱动电路沿扫描方向以相邻的四条栅线为一第二栅线组依次向各第二栅线组输出扫描信号；
在步骤S603中，当模式切换电路在接收到第三模式控制信号时，控制驱动控制电路驱动所有栅极驱动电路沿扫描方向依次向N条栅线输出扫描信号。
需要说明的是，在本公开实施例提供的上述驱动方法中，步骤S601、步骤S602和步骤S603是择一选择的关系，是根据模式切换电路接收到的模式控制信号决定执行哪一步骤。
示例性地，在本公开实施例提供的上述驱动方法中，模式切换电路控制驱动控制电路驱动所有栅极驱动电路沿扫描方向以相邻的两条栅线为一第一栅线组依次向各第一栅线组输出扫描信号，可以按照以下方式实施：
模式切换电路在控制驱动控制电路向第一栅极驱动电路输出第一组时序控制信号的同时向第二栅极驱动电路输出的第二组时序控制信号，在向第三栅极驱动电路输出第三组时序控制信号的同时向第四栅极驱动电路输出的第四组时序控制信号；其中，
第一组时序控制信号中各信号的时序与第二组时序控制信号中对应信号的时序相同，第三组时序控制信号中各信号的时序与第四组时序控制信号中对应信号的时序相同，第三组时序控制信号中各信号的时序比第一组时序控制信号中对应信号的时序延迟一个触发信号宽度。
示例性地，在本公开实施例提供的上述驱动方法中，模式切换电路控制驱动控制电路驱动所有栅极驱动电路沿扫描方向以相邻的四条栅线为一第二栅线组依次向各第二栅线组输出扫描信号，可以按照以下方式实施：
控制驱动控制电路在向第一栅极驱动电路输出第一组时序控制信号的同时向第二栅极驱动电路输出的第二组时序控制信号，向第三栅极驱动电路输出第三组时序控制信号，向第四栅极驱动电路输出的第四组时序控制信号；其中，
第一组时序控制信号中各信号的时序与第二组时序控制信号中对应信号的时序、第三组时序控制信号中对应信号的时序、以及第四组时序控制信号中 对应信号的时序均相同。
示例性地，在本公开实施例提供的上述驱动方法中，模式切换电路控制驱动控制电路驱动所有栅极驱动电路沿扫描方向依次向N条栅线输出扫描信号，可以按照以下方式实施：
控制驱动控制电路向第一栅极驱动电路输出第一组时序控制信号的同时向第二栅极驱动电路输出的第二组时序控制信号；向第三栅极驱动电路输出第三组时序控制信号的同时向第四栅极驱动电路输出的第四组时序控制信号；其中，
第二组时序控制信号中各信号的时序比第一组时序控制信号中对应信号的时序延迟二分之一个触发信号宽度；第三组时序控制信号中各信号的时序比第二组时序控制信号中对应信号的时序延迟二分之一个触发信号宽度；第四组时序控制信号中各信号的时序比第三组时序控制信号中对应信号的时序延迟二分之一个触发信号宽度。
本公开实施例提供的一种显示面板及其驱动方法、及显示装置，与已知的显示面板相比，还包括有与驱动控制电路连接的模式切换电路，模式切换电路用于在接收到第一模式控制信号时，控制驱动控制电路驱动所有栅极驱动电路沿扫描方向以相邻的两条栅线为一第一栅线组依次向各第一栅线组输出扫描信号；和/或模式切换电路用于在接收到第二模式控制信号时，控制驱动控制电路驱动所有栅极驱动电路沿扫描方向以相邻的四条栅线为一第二栅线组依次向各第二栅线组输出扫描信号。因此在实际应用中，可以根据需要向显示面板的模式切换电路发送模式控制信号，控制显示面板的分辨率降低为1/2分辨率或者降低为1/4分辨率，从而可以使显示面板降低功耗，延长待机时间。
显然，本领域的技术人员可以对本公开进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开所附权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。
本申请要求于2015年8月6日递交的中国专利申请第201510477633.6号的优先权，在此全文引用该中国专利申请公开的内容作为本申请的一部分。

Claims (12)

  1. 一种显示面板，包括4N条栅线；位于所述显示面板一侧的与第4n+1条栅线连接的第一栅极驱动电路和与第4n+3条栅线连接的第三栅极驱动电路；位于所述显示面板另一侧的与第4n+2条栅线连接的第二栅极驱动电路和与第4n+4条栅线连接的第四栅极驱动电路；以及与各栅极驱动电路连接的至少用于向各栅极驱动电路输出一一对应的一组时序控制信号的驱动控制电路，其中，n为大于且等于0且小于N的整数，该显示面板还包括：与所述驱动控制电路连接的模式切换电路，其中，
    所述模式切换电路用于在接收到第一模式控制信号时，控制所述驱动控制电路驱动所有栅极驱动电路沿扫描方向以相邻的两条栅线为一第一栅线组依次向各所述第一栅线组输出扫描信号；和/或
    所述模式切换电路用于在接收到第二模式控制信号时，控制所述驱动控制电路驱动所有栅极驱动电路沿扫描方向以相邻的四条栅线为一第二栅线组依次向各所述第二栅线组输出扫描信号。
  2. 如权利要求1所述的显示面板，其中，各组时序控制信号至少包括触发信号和时钟信号，且各组时序控制信号中触发信号的宽度相同，各所述栅极驱动电路用于在接收的对应组时序控制信号的控制下依次向对应的栅线输出扫描信号。
  3. 如权利要求2所述的显示面板，其中，所述模式切换电路在接收到第一模式控制信号时，控制所述驱动控制电路在向所述第一栅极驱动电路输出第一组时序控制信号的同时向所述第二栅极驱动电路输出第二组时序控制信号，在向所述第三栅极驱动电路输出第三组时序控制信号的同时向所述第四栅极驱动电路输出第四组时序控制信号；其中，
    所述第一组时序控制信号中各信号的时序与所述第二组时序控制信号中对应信号的时序相同，所述第三组时序控制信号中各信号的时序与所述第四组时序控制信号中对应信号的时序相同，所述第三组时序控制信号中各信号的时序比所述第一组时序控制信号中对应信号的时序延迟一个触发信号宽度。
  4. 如权利要求2所述的显示面板，其中，所述模式切换电路在接收到第二模式控制信号时，控制所述驱动控制电路在向所述第一栅极驱动电路输出第 一组时序控制信号的同时向所述第二栅极驱动电路输出的第二组时序控制信号，向所述第三栅极驱动电路输出第三组时序控制信号，向所述第四栅极驱动电路输出的第四组时序控制信号；其中，
    所述第一组时序控制信号中各信号的时序与所述第二组时序控制信号中对应信号的时序、所述第三组时序控制信号中对应信号的时序、以及所述第四组时序控制信号中对应信号的时序均相同。
  5. 如权利要求2所述的显示面板，其中，所述模式切换电路还用于：
    在接收到第三模式控制信号时，控制所述驱动控制电路驱动所有栅极驱动电路沿扫描方向依次向所述N条栅线输出扫描信号。
  6. 如权利要求5所述的显示面板，其中，所述模式切换电路在接收到第三模式控制信号时，控制所述驱动控制电路依次向所述第一栅极驱动电路输出第一组时序控制信号，向所述第二栅极驱动电路输出的第二组时序控制信号，向所述第三栅极驱动电路输出第三组时序控制信号，向所述第四栅极驱动电路输出的第四组时序控制信号；其中，
    所述第二组时序控制信号中各信号的时序比所述第一组时序控制信号中对应信号的时序延迟二分之一个触发信号宽度；所述第三组时序控制信号中各信号的时序比所述第二组时序控制信号中对应信号的时序延迟二分之一个触发信号宽度；所述第四组时序控制信号中各信号的时序比所述第三组时序控制信号中对应信号的时序延迟二分之一个触发信号宽度。
  7. 如权利要求1-6任一项所述的显示面板，其中，所述显示面板为液晶显示面板或有机电致发光显示面板。
  8. 一种如权利要求1-7任一项所述的显示面板的驱动方法，包括：
    当所述模式切换电路接收到第一模式控制信号时，控制所述驱动控制电路驱动所有栅极驱动电路沿扫描方向以相邻的两条栅线为一第一栅线组依次向各所述第一栅线组输出扫描信号；
    当所述模式切换电路接收到第二模式控制信号时，控制所述驱动控制电路驱动所有栅极驱动电路沿扫描方向以相邻的四条栅线为一第二栅线组依次向各所述第二栅线组输出扫描信号；
    当所述模式切换电路在接收到第三模式控制信号时，控制所述驱动控制电路驱动所有栅极驱动电路沿扫描方向依次向所述N条栅线输出扫描信号。
  9. 如权利要求8所述的驱动方法，其中，：
    当所述模式切换电路接收到第一模式控制信号时，所述模式切换电路控制所述驱动控制电路在向所述第一栅极驱动电路输出第一组时序控制信号的同时向所述第二栅极驱动电路输出的第二组时序控制信号，在向所述第三栅极驱动电路输出第三组时序控制信号的同时向所述第四栅极驱动电路输出第四组时序控制信号；其中，
    所述第一组时序控制信号中各信号的时序与所述第二组时序控制信号中对应信号的时序相同，所述第三组时序控制信号中各信号的时序与所述第四组时序控制信号中对应信号的时序相同，所述第三组时序控制信号中各信号的时序比所述第一组时序控制信号中对应信号的时序延迟一个触发信号宽度。
  10. 如权利要求8所述的驱动方法，其中，：
    当所述模式切换电路接收到第二模式控制信号时，所述模式切换电路在控制所述驱动控制电路向所述第一栅极驱动电路输出第一组时序控制信号的同时向所述第二栅极驱动电路输出的第二组时序控制信号，向所述第三栅极驱动电路输出第三组时序控制信号，向所述第四栅极驱动电路输出的第四组时序控制信号；其中，
    所述第一组时序控制信号中各信号的时序与所述第二组时序控制信号中对应信号的时序、所述第三组时序控制信号中对应信号的时序、以及所述第四组时序控制信号中对应信号的时序均相同。
  11. 如权利要求8所述的驱动方法，其中，
    当所述模式切换电路在接收到第三模式控制信号时，所述模式切换电路在控制所述驱动控制电路向所述第一栅极驱动电路输出第一组时序控制信号的同时向所述第二栅极驱动电路输出的第二组时序控制信号；向所述第三栅极驱动电路输出第三组时序控制信号的同时向所述第四栅极驱动电路输出的第四组时序控制信号；其中，
    所述第二组时序控制信号中各信号的时序比所述第一组时序控制信号中对应信号的时序延迟二分之一个触发信号宽度；所述第三组时序控制信号中各信号的时序比所述第二组时序控制信号中对应信号的时序延迟二分之一个触发信号宽度；所述第四组时序控制信号中各信号的时序比所述第三组时序控制信号中对应信号的时序延迟二分之一个触发信号宽度。
  12. 一种显示装置，其中，包括如权利要求1-7任一项所述的显示面板。
PCT/CN2015/100137 2015-08-06 2015-12-31 显示面板及其驱动方法及显示装置 WO2017020526A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/129,650 US10210789B2 (en) 2015-08-06 2015-12-31 Display panel and driving method thereof and display apparatus

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201510477633.6A CN104978944A (zh) 2015-08-06 2015-08-06 一种显示面板的驱动方法、显示面板及显示装置
CN201510477633.6 2015-08-06

Publications (1)

Publication Number Publication Date
WO2017020526A1 true WO2017020526A1 (zh) 2017-02-09

Family

ID=54275404

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2015/100137 WO2017020526A1 (zh) 2015-08-06 2015-12-31 显示面板及其驱动方法及显示装置

Country Status (3)

Country Link
US (1) US10210789B2 (zh)
CN (1) CN104978944A (zh)
WO (1) WO2017020526A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10891886B2 (en) 2017-02-17 2021-01-12 Boe Technology Group Co., Ltd. Shift register, gate line driving method, array substrate and display device for high and low resolution areas

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104916250B (zh) * 2015-06-26 2018-03-06 合肥鑫晟光电科技有限公司 一种数据传输方法及装置、显示装置
CN104978944A (zh) * 2015-08-06 2015-10-14 京东方科技集团股份有限公司 一种显示面板的驱动方法、显示面板及显示装置
KR102452523B1 (ko) 2015-08-27 2022-10-11 삼성디스플레이 주식회사 주사 구동부
CN105280153B (zh) * 2015-11-24 2017-11-28 深圳市华星光电技术有限公司 一种栅极驱动电路及其显示装置
CN105513556B (zh) * 2016-02-19 2019-03-22 武汉天马微电子有限公司 一种栅极驱动电路、显示面板及显示装置
CN106157873B (zh) * 2016-08-31 2019-02-26 昆山工研院新型平板显示技术中心有限公司 一种栅极驱动装置、驱动方法及显示面板
CN106531107B (zh) * 2016-12-27 2019-02-19 武汉华星光电技术有限公司 Goa电路
CN106531110B (zh) 2017-01-03 2022-01-18 京东方科技集团股份有限公司 驱动电路、驱动方法和显示装置
US10872565B2 (en) * 2017-01-16 2020-12-22 Semiconductor Energy Laboratory Co., Ltd. Display device
CN106548745A (zh) * 2017-01-19 2017-03-29 京东方科技集团股份有限公司 一种阵列基板、显示面板及显示装置
CN106710508B (zh) * 2017-02-17 2020-07-10 京东方科技集团股份有限公司 移位寄存器、栅线驱动方法、阵列基板和显示装置
CN106652878A (zh) * 2017-02-24 2017-05-10 厦门天马微电子有限公司 一种显示面板的驱动方法及显示面板
CN106847177B (zh) 2017-03-13 2019-11-22 武汉华星光电技术有限公司 显示装置及其寿命延长方法
CN107230447A (zh) * 2017-08-04 2017-10-03 京东方科技集团股份有限公司 一种驱动方法、驱动电路及显示面板
CN107393460B (zh) * 2017-08-08 2020-03-27 惠科股份有限公司 一种显示装置的驱动方法和驱动装置
CN107833550A (zh) * 2017-10-27 2018-03-23 友达光电（苏州）有限公司 显示装置及其时脉产生器
CN109064963A (zh) * 2018-09-05 2018-12-21 京东方科技集团股份有限公司 显示装置及驱动方法、移位寄存器、驱动电路
CN109410771B (zh) * 2018-10-31 2021-06-25 武汉天马微电子有限公司 显示面板和显示装置
CN112703550A (zh) * 2018-11-22 2021-04-23 深圳市柔宇科技股份有限公司 扫描驱动电路及显示面板
CN109920387A (zh) 2019-02-22 2019-06-21 合肥京东方卓印科技有限公司 移位寄存器单元及其驱动方法、栅极驱动电路及其驱动方法和显示装置
CN113096586B (zh) * 2019-12-20 2022-08-02 深圳蓝普科技有限公司 一种显示屏及其灰度调制方法、显示设备及存储介质
CN114420025A (zh) * 2020-10-28 2022-04-29 北京京东方显示技术有限公司 显示面板的驱动方法、驱动装置及显示装置
US11837133B2 (en) 2021-01-28 2023-12-05 Boe Technology Group Co., Ltd. Gate driving circuit, method of driving gate driving circuit, and display panel
CN115708151A (zh) * 2021-08-18 2023-02-21 北京京东方显示技术有限公司 显示装置及其驱动方法

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1758303A (zh) * 2004-10-07 2006-04-12 精工爱普生株式会社 电光装置及其驱动方法和电子设备
CN101359143A (zh) * 2008-09-27 2009-02-04 上海广电光电子有限公司 液晶显示装置及其驱动方法
CN102034448A (zh) * 2009-10-02 2011-04-27 索尼公司 图像显示装置和驱动图像显示装置的方法
US20140085347A1 (en) * 2012-09-21 2014-03-27 Seiko Epson Corporation Electro-optic apparatus, driving method therefor, and electronics device
CN104966506A (zh) * 2015-08-06 2015-10-07 京东方科技集团股份有限公司 一种移位寄存器、显示面板的驱动方法及相关装置
CN104978943A (zh) * 2015-08-06 2015-10-14 京东方科技集团股份有限公司 一种移位寄存器、显示面板的驱动方法及相关装置
CN104978944A (zh) * 2015-08-06 2015-10-14 京东方科技集团股份有限公司 一种显示面板的驱动方法、显示面板及显示装置

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104157249B (zh) * 2014-07-16 2016-05-11 京东方科技集团股份有限公司 一种显示面板的栅极驱动装置及显示装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1758303A (zh) * 2004-10-07 2006-04-12 精工爱普生株式会社 电光装置及其驱动方法和电子设备
CN101359143A (zh) * 2008-09-27 2009-02-04 上海广电光电子有限公司 液晶显示装置及其驱动方法
CN102034448A (zh) * 2009-10-02 2011-04-27 索尼公司 图像显示装置和驱动图像显示装置的方法
US20140085347A1 (en) * 2012-09-21 2014-03-27 Seiko Epson Corporation Electro-optic apparatus, driving method therefor, and electronics device
CN104966506A (zh) * 2015-08-06 2015-10-07 京东方科技集团股份有限公司 一种移位寄存器、显示面板的驱动方法及相关装置
CN104978943A (zh) * 2015-08-06 2015-10-14 京东方科技集团股份有限公司 一种移位寄存器、显示面板的驱动方法及相关装置
CN104978944A (zh) * 2015-08-06 2015-10-14 京东方科技集团股份有限公司 一种显示面板的驱动方法、显示面板及显示装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10891886B2 (en) 2017-02-17 2021-01-12 Boe Technology Group Co., Ltd. Shift register, gate line driving method, array substrate and display device for high and low resolution areas

Also Published As

Publication number Publication date
CN104978944A (zh) 2015-10-14
US20170178557A1 (en) 2017-06-22
US10210789B2 (en) 2019-02-19

Similar Documents

Publication Publication Date Title
WO2017020526A1 (zh) 显示面板及其驱动方法及显示装置
WO2017020549A1 (zh) 移位寄存器、栅极驱动电路、显示面板的驱动方法、显示装置
EP3333842A1 (en) Shift register, gate driving circuit, display panel and driving method therefor, and display device
US10127875B2 (en) Shift register unit, related gate driver and display apparatus, and method for driving the same
US10891886B2 (en) Shift register, gate line driving method, array substrate and display device for high and low resolution areas
EP3159885B1 (en) Gate driving circuit, array substrate, display device, and driving method
TWI397882B (zh) 用於顯示器的驅動裝置及其相關方法
KR102277072B1 (ko) Goa 회로 구동 아키텍처
CN104157249B (zh) 一种显示面板的栅极驱动装置及显示装置
WO2016155052A1 (zh) Cmos栅极驱动电路
CN105489189A (zh) 栅极驱动单元、栅极驱动电路及其驱动方法和显示装置
CN104217690B (zh) 栅极驱动电路、阵列基板、显示装置
US8237650B2 (en) Double-gate liquid crystal display device
WO2016000369A1 (zh) 发射电极扫描电路、阵列基板和显示装置
US10657864B2 (en) Drive circuit of display device and driving method for display device having single-ended to differential modules
WO2017067407A1 (zh) 用于触摸屏的驱动电路、内嵌式触摸屏及显示装置
CN107016953A (zh) 显示面板的驱动方法、显示面板及显示装置
WO2017211282A1 (zh) 一种栅极驱动电路、其驱动方法、显示面板及显示装置
WO2019007085A1 (zh) 扫描驱动电路及驱动方法、阵列基板和显示装置
WO2018161806A1 (zh) 移位寄存器、其驱动方法、栅线集成驱动电路及显示装置
WO2018129786A1 (zh) Cmos goa电路
WO2020192340A1 (zh) 移位寄存器、栅极驱动电路及其驱动方法、显示装置
CN104050946A (zh) 多相栅极驱动器及其显示面板
CN204029332U (zh) 发射电极扫描电路、阵列基板和显示装置
CN104700802A (zh) 一种液晶面板的驱动电路

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 15129650

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15900289

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 15900289

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 15900289

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 22/08/18)

122 Ep: pct application non-entry in european phase

Ref document number: 15900289

Country of ref document: EP

Kind code of ref document: A1