WO2021253457A1 - 用于直流电压转换的装置和电子设备 - Google Patents

用于直流电压转换的装置和电子设备 Download PDF

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Publication number
WO2021253457A1
WO2021253457A1 PCT/CN2020/097283 CN2020097283W WO2021253457A1 WO 2021253457 A1 WO2021253457 A1 WO 2021253457A1 CN 2020097283 W CN2020097283 W CN 2020097283W WO 2021253457 A1 WO2021253457 A1 WO 2021253457A1
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Prior art keywords
frequency
signal
voltage
selection signal
event
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PCT/CN2020/097283
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English (en)
French (fr)
Inventor
胡章荣
吴琨
周卓敏
产竹标
衡草飞
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华为技术有限公司
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Priority to PCT/CN2020/097283 priority Critical patent/WO2021253457A1/zh
Priority to CN202080006186.5A priority patent/CN114080749A/zh
Publication of WO2021253457A1 publication Critical patent/WO2021253457A1/zh

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators

Definitions

  • the embodiments of the present application generally relate to the field of circuit technology, and more specifically, to a device and electronic equipment for DC voltage conversion.
  • DVS Dynamic Voltage Scaling
  • a processor such as a system-on-a-chip (SOC) sends instructions to the PMIC according to the voltage required by the load.
  • the PMIC adjusts the output voltage according to instructions from the processor, and the output voltage is provided to the load, such as the SOC or the processor.
  • the processor When the output voltage is adjusted to the target value, the processor as the load starts to execute the corresponding service.
  • the output voltage close to the voltage required by the load is the best state. Restricted by the speed of voltage regulation, it is difficult for the output voltage to accurately track the voltage required by the load in practice. This causes a waste of energy efficiency.
  • the device for DC voltage conversion usually has at least a pulse width modulation (Pulse Width Modulation, PWM) mode.
  • PWM pulse width modulation
  • one development direction is to adopt higher switching frequency in PWM mode. That is, always working at a relatively high switching frequency can bring several benefits in terms of voltage conversion performance, for example, it can increase the startup speed of the device, increase the voltage regulation speed, and improve the transient response performance of the device.
  • operating at the preset high switching frequency also reduces the power utilization efficiency.
  • the embodiments of the present disclosure provide a device and electronic equipment for DC voltage conversion to improve the voltage conversion performance and alleviate the reduction in power utilization efficiency.
  • an embodiment of the present disclosure provides a device for DC voltage conversion.
  • the device includes: a frequency converter configured to increase the frequency of the periodic signal from a first frequency to a second frequency based on the first selection signal; and a voltage regulator, coupled to the frequency converter, and configured to pulse In the width modulation mode, the first DC voltage is converted into the second DC voltage based on the periodic signal of the second frequency.
  • the first DC voltage is also called the input voltage
  • the second DC voltage is also called the output voltage.
  • the switching frequency in the pulse width modulation mode can be increased according to the trigger of the event, that is, the switching frequency is no longer fixed, but can be changed.
  • the performance of the voltage conversion can be improved, for example, the speed of the voltage conversion can be increased, and the reduction of the power utilization efficiency caused by the operation at the preset high switching frequency can be alleviated, and the system requirements can be better adapted. Therefore, the embodiments of the present disclosure can balance voltage conversion performance and power utilization efficiency.
  • the frequency converter is further configured to: reduce the frequency of the periodic signal from the second frequency to the first frequency based on a second selection signal different from the first selection signal; and the voltage regulator is further configured to : In the pulse width modulation mode, the first DC voltage is converted into the second DC voltage based on the periodic signal of the first frequency. In this way, it automatically returns to the lower switching frequency at the end of the event, realizing the dynamic conversion of the switching frequency. This further facilitates the balance between voltage conversion performance and power utilization efficiency.
  • the frequency converter is further configured to: based on a second selection signal different from the first selection signal, reduce the frequency of the periodic signal from the second frequency to a third frequency different from the first frequency; and the voltage The regulator is further configured to: in the pulse width modulation mode, convert the first direct current voltage into a second direct current voltage based on the periodic signal of the third frequency. In this way, it automatically returns to the lower switching frequency at the end of the event, realizing the dynamic conversion of the switching frequency. This further facilitates the balance between voltage conversion performance and power utilization efficiency.
  • the first selection signal and the second selection signal are different indication states of the same indication signal, the first selection signal is used to indicate the occurrence of at least one event, and the second selection signal is used to indicate the end of the at least one event . In this way, a simple circuit configuration can be used to realize the conversion of a periodic signal between high frequency and low frequency.
  • the device further includes a selection signal determination circuit, coupled to the frequency converter, and configured to determine the first selection signal based on the at least one event signal. In this way, multiple event signals can be configured to consider switching frequency changes in multiple scenarios.
  • the at least one event signal includes at least one of the following: a first event signal indicating that the voltage regulator is activated, a second event signal indicating that the target value of the second DC voltage has been adjusted, or a second event signal indicating the second DC voltage The third event signal whose actual value exceeds the predetermined range.
  • the selection signal determination circuit includes an OR gate, the input of the OR gate is at least one event signal, and the output of the OR gate is the first selection signal.
  • the frequency converter includes: a first multiplexer configured to select, based on the first selection signal, from a first candidate periodic signal with a first frequency and a second candidate periodic signal with a second frequency The second candidate periodic signal is selected as the periodic signal.
  • the first candidate periodic signal and the second candidate periodic signal may be ramp signals.
  • the first candidate periodic signal and the second candidate periodic signal may be PWM signals.
  • the frequency converter further includes: a second multiplexer, coupled to the first multiplexer, and configured to be based on a third selection signal representing a specification constraint condition of the load, from having a fourth frequency
  • One candidate periodic signal is selected as the first candidate periodic signal from the third candidate periodic signal with the fifth frequency and the fourth candidate periodic signal with the fifth frequency.
  • the switching frequency in the pulse width modulation mode can be configured according to the power supply requirements of the load (for example, requirements for ripple voltage, requirements for transient response speed, etc.), so as to better adapt to system requirements. This further facilitates the balance between voltage conversion performance and power utilization efficiency.
  • the voltage regulator includes: an error amplifier configured to generate an error signal based on a reference signal and a feedback signal indicative of the second DC voltage; a comparator, coupled to the error amplifier and the frequency converter, and configured to generate an error signal based on The periodic signal and the error signal generate a pulse width modulation signal; a switch drive circuit, coupled to the comparator, and configured to generate a switch drive signal based on the pulse width modulation signal; and a switch circuit, coupled to the switch drive circuit, and configured to be based on the switch The driving signal converts the first direct current voltage into a second direct current voltage.
  • the voltage regulator further includes a loop compensator, coupled to the error amplifier and the output terminal of the voltage regulator, and configured to adjust the pole-zero configuration of the loop formed by the voltage regulator.
  • the loop compensator includes: a first loop compensation circuit configured to adjust the pole-zero configuration in response to a second selection signal different from the first selection signal; and a second loop compensation circuit configured The pole-zero configuration is adjusted in response to the first selection signal. In this way, accurate compensation can be performed for pulse width modulation modes of different frequencies. This helps the device to operate stably at different frequencies.
  • an embodiment of the present disclosure provides an electronic device.
  • the electronic device includes: a processor configured to generate a first frequency conversion signal in response to the occurrence of at least one event; and a device for DC voltage conversion, coupled to the processor, and configured to: in response to receiving The first frequency conversion signal raises the frequency of the periodic signal from the first frequency to the second frequency, and in the pulse width modulation mode, based on the periodic signal of the second frequency, the first direct current voltage is transformed into the second direct current voltage.
  • the first DC voltage is also called the input voltage
  • the second DC voltage is also called the output voltage.
  • the device may enable the first selection signal based on the first frequency conversion signal, and increase the frequency of the periodic signal from the first frequency to the second frequency based on the first selection signal.
  • the switching frequency in the pulse width modulation mode can be changed according to the trigger of the event.
  • the performance of voltage conversion can be improved, for example, the speed of voltage conversion can be increased, and the reduction in power utilization efficiency caused by operation at a preset high switching frequency can be alleviated, and the power supply requirements of electronic devices can be better adapted. This helps to realize electronic equipment with optimized power efficiency.
  • the at least one event includes at least one of the following: the device is activated, or the target value of the second DC voltage is adjusted.
  • the device is further configured to: in response to determining the end of at least one event, reduce the frequency of the periodic signal from the second frequency to the first frequency; and in the pulse width modulation mode, based on the period of the first frequency Signal to convert the first direct current voltage into a second direct current voltage.
  • the device enables the second selection signal in response to determining the end of at least one event, and the second selection signal is used to reduce the frequency of the periodic signal from the second frequency to the first frequency.
  • the processor is further configured to: determine a specification constraint condition of the load; and generate a second frequency conversion signal based on the specification constraint condition.
  • the device is also configured to: in response to receiving the second frequency conversion signal, set the first frequency of the periodic signal to one of a plurality of preset frequencies.
  • the device may enable the third selection signal based on the second frequency conversion signal, and set the first frequency of the periodic signal to one of a plurality of preset frequencies based on the third selection signal.
  • the device may select a periodic signal from a plurality of candidate periodic signals based on the third selection signal.
  • Each of the plurality of candidate periodic signals has a corresponding frequency among a plurality of preset frequencies.
  • the device for DC voltage conversion may further include: an enabling component that enables the first selection signal based on the first frequency conversion signal. Additionally, in some embodiments, the enabling component that enables the first selection signal may also be configured to enable the first selection signal in response to the actual value of the second direct current voltage exceeding a predetermined range. Alternatively or additionally, the device for DC voltage conversion may further include: an enabling component that enables the third selection signal based on the second frequency conversion signal. The enabling component that enables the first selection signal and the enabling component that enables the third selection signal may be the same or different components.
  • the device for DC voltage conversion may further include: a frequency converter, coupled to an enabling component that enables the first selection signal, and configured to change the frequency of the periodic signal from the first selection signal based on the first selection signal The first frequency is raised to the second frequency; and a voltage regulator, coupled to the frequency converter, and configured to convert the first direct current voltage to a second direct current based on a periodic signal of the second frequency in a pulse width modulation mode Voltage.
  • the device for DC voltage conversion may further include: a detection component for determining the end of at least one event.
  • the detection component may determine the end of at least one event by detecting electrical parameters. Such electrical parameters may include the output voltage of the device for DC voltage conversion.
  • the detection component may be coupled to an enabling component that enables the first selection signal. If it is determined that at least one event is over, the detection component may send an event end signal to the enabling component that enables the first selection signal.
  • the enabling component that enables the first selection signal may enable a second selection signal different from the first selection signal based on the event end signal, and invalidate the first selection signal.
  • the frequency converter may be further configured to: reduce the frequency of the periodic signal from the second frequency to the first frequency based on the second selection signal; and the voltage regulator may be further configured to: in the pulse width modulation mode, The first direct current voltage is converted into a second direct current voltage based on the periodic signal of the first frequency.
  • the frequency converter is further configured to: reduce the frequency of the periodic signal from the second frequency to a third frequency different from the first frequency based on the second selection signal; and the voltage regulator is further configured to: In the pulse width modulation mode, the first DC voltage is converted into the second DC voltage based on the periodic signal of the third frequency.
  • the first selection signal and the second selection signal are different indication states of the same indication signal, wherein the first selection signal is used to indicate the occurrence of at least one event, and the second selection signal is used to indicate the end of the at least one event.
  • the frequency converter may include: a first multiplexer configured to select from a first candidate periodic signal with a first frequency and a second candidate periodic signal with a second frequency based on the first selection signal
  • the second candidate periodic signal serves as the periodic signal.
  • the first candidate periodic signal and the second candidate periodic signal may be ramp signals.
  • the first candidate periodic signal and the second candidate periodic signal may be PWM signals.
  • the frequency converter may further include: a second multiplexer, the control end of the second multiplexer is coupled to the enabling component that enables the third selection signal, and the output end is coupled to the first multiplexer And is configured to select one candidate periodic signal as the first candidate periodic signal from the third candidate periodic signal with the fourth frequency and the fourth candidate periodic signal with the fifth frequency based on the third selection signal.
  • a second multiplexer the control end of the second multiplexer is coupled to the enabling component that enables the third selection signal
  • the output end is coupled to the first multiplexer And is configured to select one candidate periodic signal as the first candidate periodic signal from the third candidate periodic signal with the fourth frequency and the fourth candidate periodic signal with the fifth frequency based on the third selection signal.
  • the voltage regulator may include: an error amplifier configured to generate an error signal based on the reference signal and a feedback signal indicating the second DC voltage; a comparator, coupled to the error amplifier and the frequency converter, and configured to be based on the period The signal and the error signal generate a pulse width modulation signal; a switch drive circuit, coupled to the comparator, and configured to generate a switch drive signal based on the pulse width modulation signal; and a switch circuit, coupled to the switch drive circuit, and configured to drive based on the switch The signal converts the first direct current voltage into a second direct current voltage.
  • the voltage regulator may further include a loop compensator, coupled to the error amplifier and the output terminal of the voltage regulator, and configured to adjust the pole-zero configuration of the loop formed by the voltage regulator.
  • a loop compensator coupled to the error amplifier and the output terminal of the voltage regulator, and configured to adjust the pole-zero configuration of the loop formed by the voltage regulator.
  • the loop compensator may include: a first loop compensation circuit configured to adjust the pole-zero configuration in response to the second selection signal; and a second loop compensation circuit configured to adjust the pole-zero configuration in response to the first selection signal Zero and pole configuration.
  • a first loop compensation circuit configured to adjust the pole-zero configuration in response to the second selection signal
  • a second loop compensation circuit configured to adjust the pole-zero configuration in response to the first selection signal Zero and pole configuration.
  • the embodiments of the present disclosure provide a device for DC voltage conversion.
  • the device includes: a frequency converter configured to convert the frequency of the periodic signal based on the selection signal; and a voltage regulator, coupled to the frequency converter, and configured to convert the first signal based on the periodic signal in a pulse width modulation mode
  • the direct current voltage is converted into a second direct current voltage.
  • the first DC voltage is also called the input voltage
  • the second DC voltage is also called the output voltage.
  • the switching frequency in the pulse width modulation mode can be changed, that is, the switching frequency is no longer fixed, but can be changed. In this way, the system requirements can be better adapted.
  • the frequency converter may also be configured to increase the frequency of the periodic signal from the first frequency to the second frequency based on the first selection signal.
  • the frequency converter may be further configured to reduce the frequency of the periodic signal from the second frequency to the first frequency based on a second selection signal different from the first selection signal. In some embodiments, the frequency converter may be further configured to reduce the frequency of the periodic signal from the second frequency to a third frequency different from the first frequency based on a second selection signal different from the first selection signal.
  • the embodiments described herein regarding the device of the first aspect can be applied to the device of the third aspect, and have the same beneficial effects.
  • an embodiment of the present disclosure provides an electronic system including the electronic device according to the second aspect and a memory, the memory is used to store computer program instructions, and the processor in the electronic device is used to execute the computer program instructions to generate The first frequency conversion signal.
  • embodiments of the present disclosure provide a chip system including a first chip and a second chip.
  • the first chip includes a processor in the electronic device according to the second aspect
  • the second chip includes a device for DC voltage conversion in the electronic device according to the second aspect.
  • an embodiment of the present disclosure provides a chip, including the device for DC voltage conversion of the first aspect, and an interface for receiving the The first frequency conversion signal.
  • FIG. 1 shows a schematic block diagram of an electronic device to which an embodiment of the present disclosure can be applied
  • Figure 2 shows a schematic block diagram of an electronic device according to some embodiments of the present disclosure
  • Fig. 3 shows a schematic block diagram of an apparatus for DC voltage conversion according to some embodiments of the present disclosure
  • FIG. 4 shows a graph of switching frequency and load current according to some embodiments of the present disclosure
  • Fig. 5 shows a schematic block diagram of an apparatus for DC voltage conversion according to some embodiments of the present disclosure
  • Fig. 6 shows a schematic structural diagram of a device for DC voltage conversion according to some embodiments of the present disclosure
  • FIG. 7 shows a schematic structural diagram of a device for DC voltage conversion according to other embodiments of the present disclosure.
  • FIG. 8 shows a schematic structural diagram of a device for DC voltage conversion according to still other embodiments of the present disclosure.
  • Fig. 9 shows a schematic structural diagram of a frequency converter according to some embodiments of the present disclosure.
  • FIG. 10 shows a graph of switching frequency and load current according to some embodiments of the present disclosure
  • FIG. 11 shows a schematic structural diagram of a device for DC voltage conversion according to some embodiments of the present disclosure
  • FIG. 12 shows an example process of frequency conversion according to some embodiments of the present disclosure.
  • FIG. 13 shows a schematic block diagram of an electronic device according to some embodiments of the present disclosure.
  • one solution is to set the switching frequency of the device for DC voltage conversion (hereinafter also referred to as the conversion device) in the PWM mode to a high frequency.
  • the peak-to-peak value of the current flowing through the same inductor is lower.
  • OCP Over Current Protection
  • the high switching frequency significantly reduces the loop hardware delay of the switching device.
  • the high switching frequency can bring several benefits in terms of the performance of the voltage conversion, for example, it can increase the startup speed of the conversion device, increase the voltage regulation speed, and reduce the drop or overshoot amplitude of the output voltage.
  • the use of a fixed high switching frequency also reduces the power conversion efficiency. Therefore, it is difficult to achieve high-efficiency power supply efficiency only by using a fixed high switching frequency to achieve fast DVS.
  • the embodiments of the present disclosure provide a solution for DC voltage conversion.
  • the device for DC voltage conversion increases the switching frequency by increasing the frequency of the periodic signal in the PWM mode when an event occurs.
  • the event that causes the device to increase the frequency of the periodic signal may also be referred to as a "trigger event" in the following.
  • the switching frequency in the PWM mode can be dynamically changed according to the event, that is, the switching frequency is changeable. In this way, the voltage conversion performance can be improved, and the loss of power utilization efficiency caused by the operation at the preset high switching frequency can be alleviated.
  • the embodiments of the present disclosure can achieve a balance between voltage conversion performance and power utilization efficiency.
  • FIG. 1 shows a schematic block diagram of an electronic device 100 to which an embodiment of the present disclosure can be applied.
  • the electronic device 100 includes a processor 101.
  • the processor 101 may be any suitable type of processing unit, including but not limited to Central Processing Unit (CPU), Graphics Processing Unit (GPU), Digital Signal Processor (DSP) based on Artificial Intelligence (AI) processing unit, etc.
  • CPU Central Processing Unit
  • GPU Graphics Processing Unit
  • DSP Digital Signal Processor
  • AI Artificial Intelligence
  • the processor 101 may execute according to computer program instructions stored in a read-only memory (Read-Only Memory, ROM) 102 or computer program instructions loaded from the storage unit 108 to a random access memory (Random Access Memory, RAM) 103 Various appropriate actions and processing.
  • ROM Read-Only Memory
  • RAM Random Access Memory
  • various programs and data required for the operation of the electronic device 100 can also be stored.
  • the processor 101, the read only memory 102, and the random access memory 103 are connected to each other through a bus 104.
  • An input/output (Input/Output, I/O) interface 105 is also connected to the bus 104.
  • the electronic device 100 further includes a power supply unit 110.
  • the power supply unit 110 may provide electrical energy required for operation of components in the electronic device 100.
  • the power supply unit 110 may include a PMIC.
  • the I/O interface 105 includes: an input unit 106, such as a keyboard, a mouse, etc.; an output unit 107, such as various types of displays, speakers, etc.; and a storage unit 108, such as a magnetic disk or an optical disk. And the like; and the communication unit 109, such as a network card, a modem, a wireless communication transceiver, etc.
  • the communication unit 109 allows the electronic device 100 to exchange information or data with other devices through a computer network such as the Internet or various telecommunication networks.
  • the processor 101 can perform methods and processing.
  • the methods and processing may be implemented as a computer software program or a computer program product, which is tangibly contained in a machine-readable medium, such as the storage unit 108.
  • part or all of the computer program may be loaded and/or installed on the electronic device 100 via the read-only memory 102 and/or the communication unit 109.
  • multiple components in the electronic device 100 may be integrated on the same chip.
  • components including but not limited to the processor 101, the bus 104, the read-only memory 102, and the random access memory 103 may be integrated on the SoC.
  • the processor 101, the bus 104, and the communication unit 109 may be integrated on an SoC, which is defined as the first chip.
  • the electronic device 100 may include a smart phone.
  • the electronic device 100 may include at least one of the following: a set-top box, an entertainment unit, a navigation device, a communication device, a fixed location data unit, a mobile location data unit, a mobile phone, a cellular phone, a tablet computer, a tablet phone, a computer , Portable computer, desktop computer, personal digital assistant (PDA), monitor, computer monitor, TV, tuner, radio, satellite radio, music player, digital music player, portable music player, digital Video players, video players, Digital Versatile Disc (DVD) players, portable digital video players, etc.
  • PDA personal digital assistant
  • FIG. 2 shows a schematic block diagram of an electronic device 200 according to some embodiments of the present disclosure.
  • the electronic device 200 may be implemented in the electronic device 100.
  • the electronic device 200 includes a processor 101.
  • the processor 101 is configured to generate a frequency conversion signal in response to the occurrence of an event.
  • the specific operation of the processor 101 will be described with reference to FIG. 11.
  • the processor 101 may be integrated on the SoC.
  • the electronic device 200 also includes a device 210 for DC voltage conversion that communicates with the processor 101, which may also be referred to as a conversion device 210 for short hereinafter.
  • the conversion device 210 is configured to convert the DC voltage Vin into the DC voltage Vout. In other words, the conversion device 210 can convert the input voltage into an output voltage to provide to the load.
  • the load may include the processor 101. Alternatively or additionally, the load may include one or more other components of the electronic device 100, such as a read-only memory 102, a random access memory 103, a storage unit 108, a communication unit 109, and so on.
  • the input voltage can come from a battery or a charging adapter of the electronic device 100, or can come from the output of the power supply unit 110 or other circuits in the PMIC.
  • the device 210 for DC voltage conversion may be located inside the power supply unit 110, for example, inside the PMIC. Alternatively, the device 210 for DC voltage conversion may be another chip independent of the PMIC, which is not limited in this embodiment.
  • the device 210 for DC voltage conversion is generally on a different chip from the SoC where the processor 101 is located, that is, the device 210 can be located on a second chip and is coupled to the processor 101 in the SoC through an interface.
  • the device 210 can interact with the processor 101 through an interface as shown in FIG. 2 with various information or instructions. For details, refer to various signals described later.
  • the conversion device 210 may operate in the PWM mode.
  • the conversion device 210 may be configured with multiple PWM modes with different switching frequencies. For example, if a trigger event occurs, the conversion device 210 may increase the frequency of the periodic signal in the PWM mode, thereby switching to the high-frequency PWM mode. If the trigger event ends, the conversion device 210 can reduce the frequency of the periodic signal in the PWM mode, thereby switching back to the low-frequency PWM mode. In other words, the conversion device 210 can selectively adjust the frequency of the periodic signal to better adapt to the system requirements.
  • the conversion device 210 may also be configured with a pulse frequency modulation (Pulse-Frequency Modulation, PFM) mode to improve the efficiency of the conversion device 210 under light load conditions. For example, if the load current is less than a predetermined value, the conversion device 210 may switch to the PFM mode. That is, the conversion device 210 can dynamically reduce the switching frequency according to the load current, so as to improve the power supply efficiency under light load conditions.
  • PFM pulse frequency modulation
  • the conversion device 210 may be implemented as a part of the power supply unit 110 shown in FIG. 1. In some embodiments, the conversion device 210 may be at least a part of the PMIC.
  • the conversion device 210 may include any suitable DC-DC type circuit with a PWM mode, including but not limited to a buck (BUCK) circuit, a boost (BOOST) circuit, a buck-boost (BUCK-BOOST) circuit, Switched-Capacitor (SC) circuits, charge pumps, switched-type low dropout regulators (LDO), etc.
  • the conversion device 210 may also be independent of the power supply unit 110 or the PMIC.
  • FIG. 3 shows a schematic block diagram of an apparatus 210 for DC voltage conversion according to some embodiments of the present disclosure.
  • the conversion device 210 in order to perform frequency conversion, includes a frequency converter 310.
  • the frequency converter 310 is configured to increase the frequency of the periodic signal Vp from the first frequency to the second frequency based on the selection signal S1.
  • the selection signal S1 may indicate the occurrence of a trigger event.
  • the conversion device 210 also includes a voltage regulator 350 coupled to the frequency converter 310.
  • the voltage regulator 350 is configured to convert the DC voltage Vin into the DC voltage Vout based on the periodic signal Vp of the second frequency in the PWM mode.
  • the DC voltage Vin is also called the first DC voltage in the embodiment, and is the input voltage of the voltage regulator 350.
  • the DC voltage Vout is also called the second DC voltage in the embodiment, and is the output voltage of the voltage regulator 350.
  • the frequency converter 310 may also be configured to reduce the frequency of the periodic signal Vp from the second frequency based on a selection signal S2 (not shown in FIG. 3) different from the selection signal S1.
  • the selection signal S2 may indicate the end of the trigger event.
  • the voltage regulator 350 may also be configured to convert the DC voltage Vin into the DC voltage Vout based on the periodic signal Vp having a frequency lower than the second frequency in the PWM mode.
  • the frequency converter 310 may reduce the frequency of the periodic signal Vp from the second frequency back to the first frequency based on the selection signal S2.
  • the frequency converter 310 may reduce the frequency of the periodic signal Vp from the second frequency to a third frequency different from the first frequency based on the selection signal S2. For example, this may be the case in the embodiment described below with reference to FIG. 9.
  • the periodic signal Vp may be a ramp signal, which is also called a triangular wave signal.
  • the periodic signal Vp may be a ramp signal, such as the embodiments described below with reference to FIGS. 5 to 8.
  • the periodic signal Vp may be a PWM signal.
  • the periodic signal Vp may be a PWM signal, such as the embodiment described below with reference to FIG. 11.
  • the selection signal S1 and the selection signal S2 may be two different indication values or indication states of the same indication signal received by the frequency converter 310.
  • the indicator signal is at a high level to indicate the occurrence of the trigger event, that is, the indicator signal is embodied as the selection signal S1; the indicator signal is at a low level to indicate the trigger event End, that is, the instruction signal is embodied as the selection signal S2.
  • the selection signal S1 and the selection signal S2 may be two independent indication signals.
  • the subsequent embodiments use two different indication values or indication states of the same indication signal to represent the selection signal S1 and the selection signal S2, it should be understood that the embodiments of the present disclosure are not limited in this respect.
  • the switching frequency of the conversion device 210 in the PWM mode depends on the frequency of the periodic signal Vp. Therefore, the frequency of the periodic signal Vp is converted between a low frequency (for example, the first frequency or the third frequency) and a high frequency (for example, the second frequency), so that the switching frequency of the conversion device 210 in the PWM mode is between the high frequency and the high frequency. Change between low frequencies.
  • the following describes the conversion of the frequency of the periodic signal Vp between the first frequency and the second frequency as an example.
  • the PWM mode corresponding to the first frequency is referred to as "first PWM mode”
  • the PWM mode corresponding to the second frequency is referred to as "second PWM mode”.
  • FIG. 4 shows a graph 400 of switching frequency and load current according to some embodiments of the present disclosure.
  • Curves 451 and 452 show the relationship between the switching frequency and the load current in the first PWM mode and the second PWM mode, respectively.
  • the conversion device 210 can switch between the first PWM mode and the second PWM mode.
  • the dashed line 453 in some embodiments, if the load current is less than a predetermined value, the conversion device 210 may operate in the PFM mode.
  • the basic PWM mode refers to the PWM mode in which the conversion device 210 is located when no trigger event occurs.
  • the high-frequency PWM mode refers to the PWM mode in which the conversion device 210 is located during the occurrence of a trigger event. It is understandable that, compared to the basic PWM mode, the high-frequency PWM mode is a transient mode.
  • the first PWM mode can be regarded as the basic PWM mode, and the second PWM mode can be regarded as the high frequency PWM mode.
  • the trigger event may be that the voltage regulator 350 is activated.
  • the conversion device 210 may switch to the second PWM mode to achieve a quick start. After the slow start is completed, the conversion device 210 can switch back to the first PWM mode.
  • the trigger event may be that the target value of the DC voltage Vout is adjusted, indicating that the voltage regulator 350 has entered or is about to enter the voltage adjustment phase, and the specific DC voltage Vout may be adjusted by the reference signal Vref .
  • the conversion device 210 may switch to the second PWM mode to achieve rapid voltage adjustment. After the voltage regulation is completed, the conversion device 210 can switch back to the first PWM mode. In this solution, during the voltage adjustment phase, the output voltage switching of the voltage regulator 350 occurs. In order to speed up the output voltage switching or adjustment, the conversion device 210 enters the second PWM mode, and switches back to the first PWM mode after the voltage switching or adjustment is over. A PWM mode.
  • the trigger event may be that the actual value of the DC voltage Vout exceeds a predetermined range.
  • the conversion device 210 can monitor the DC voltage Vout. For example, if the actual value of the DC voltage Vout falls below the threshold, the conversion device 210 may switch to the second PWM mode. The high switching frequency in the second PWM mode can reduce the drop range of the DC voltage Vout. When the actual value of the DC voltage Vout is restored to the predetermined range, the conversion device 210 can switch back to the first PWM mode. Likewise, if the actual value of the DC voltage Vout rises above the threshold, the conversion device 210 can operate similarly. This can reduce the overshoot amplitude of the DC voltage Vout. Alternatively or additionally, the conversion device 210 may also determine the change in the actual value of the DC voltage Vout by monitoring the output current.
  • trigger events described above are only exemplary and are not intended to limit the scope of the present disclosure. In the embodiments of the present disclosure, one or more of the trigger events described above and any other suitable events may be considered.
  • the conversion device uses a single switching frequency in the PWM mode. If the switching frequency is low, the voltage conversion performance is poor, such as slow device startup speed, slow voltage regulation, and large overshoot or drop of the output voltage. If the switching frequency is high, although the voltage conversion performance is improved, the electric energy utilization efficiency is reduced, resulting in a waste of energy efficiency. Therefore, the use of a preset fixed switching frequency has drawbacks.
  • the switching frequency in the PWM mode is dynamically changed according to the trigger event, that is, the switching frequency is no longer fixed, but can be switched. Thus, during the occurrence of the trigger event, the increase of the switching frequency can improve the voltage conversion performance. During the period when the triggering event does not occur, the lower switching frequency can alleviate the decrease in power utilization efficiency. In this way, it is possible to achieve a balance between voltage conversion performance and electric energy utilization efficiency.
  • FIG. 5 shows a schematic block diagram of an apparatus 210-1 for DC voltage conversion according to some embodiments of the present disclosure.
  • the conversion device 210-1 can be regarded as a specific implementation of the conversion device 210, where the frequency converter 310-1 is a specific implementation of the frequency converter 310, and the closed-loop mode voltage regulator 350-1 is a specific implementation of the voltage regulator 350. Specific implementation, and the periodic signal Vramp in the form of a ramp is a specific implementation of the periodic signal Vp.
  • the conversion device 210-1 may further include a selection signal determination circuit 520.
  • the selection signal determination circuit 520 is coupled to the frequency converter 310-1, and is configured to determine the selection signal S1 or the selection signal S2 based on at least one event signal, and output the selection signal S1 or the selection signal S2. For example, the selection signal determination circuit 520 may receive one or more event signals, and output the selection signal S1 or the selection signal S2 based on whether the one or more event signals are valid.
  • the one or more event signals may include, but are not limited to, an event signal indicating that the voltage regulator 350-1 is activated, an event signal indicating that the target value of the DC voltage Vout is adjusted, and an event signal indicating that the actual value of the DC voltage Vout exceeds a predetermined range. .
  • the conversion device 210-1 may not include the selection signal determination circuit 520.
  • the event signal may be directly provided to the frequency converter 310-1 as a selection signal.
  • the frequency converter 310-1 may include a multiplexer 512.
  • the multiplexer 512 may be configured to select one ramp signal as the periodic signal Vramp from the ramp signal F1_Vramp with the first frequency and the ramp signal F2_Vramp with the second frequency based on the selection signal.
  • the periodic signal Vramp is implemented as a ramp signal.
  • the multiplexer 512 is configured to select the ramp signal F2_Vramp from the ramp signal F1_Vramp and the ramp signal F2_Vramp based on the selection signal S1 indicating the occurrence of the trigger event, and use it as the periodic signal Vramp. .
  • the multiplexer 512 is also configured to select the ramp signal F1_Vramp as the periodic signal Vramp from the ramp signal F1_Vramp and the ramp signal F2_Vramp based on the selection signal S2 indicating the end of the trigger event.
  • the frequency of the periodic signal Vramp can be changed in response to the occurrence and end of the trigger event, so that the conversion device 210-1 can switch between the first PWM mode and the second PWM mode.
  • the switching frequency is no longer fixed, but can be changed. Therefore, during the occurrence of the trigger event, the benefits of the high-frequency PWM mode can be obtained and the voltage conversion performance can be improved. After the trigger event is over, switching back to the low-frequency PWM mode can avoid the loss of power utilization efficiency at high frequencies.
  • the embodiments according to the present disclosure can balance voltage conversion performance and power utilization efficiency.
  • the selection signal S1 and the selection signal S2 are represented as two different indication values or indication states of the same indication signal.
  • the selection signal S1 and the selection signal S2 can also be two independent indication signals.
  • the enabling of the selection signal S1 may provide the ramp signal F2_Vramp to the input terminal of the comparator 556 as a periodic signal
  • the enabling of the selection signal S2 may provide the ramp signal F1_Vramp to the input terminal of the comparator 556 as a periodic signal.
  • the voltage regulator 350-1 may include a comparator 556, a switch driving circuit 558, a switch circuit 560, an error amplifier 554, and a loop compensator 530.
  • the comparator 556 is coupled to the frequency converter 310-1.
  • the comparator 556 may be coupled to the output terminal of the multiplexer 512 to receive the periodic signal Vramp.
  • the comparator 556 is configured to generate a PWM signal based on the periodic signal Vramp and the error signal from the error amplifier 554.
  • the frequency of the PWM signal generated by the comparator 556 is the same as the frequency of the periodic signal Vramp.
  • the switch drive circuit 558 is coupled to the comparator 556 to receive the PWM signal, and is configured to generate the switch drive signal based on the PWM signal.
  • the switch circuit 560 is coupled to the switch drive circuit 558, and is configured to convert the DC voltage Vin into the DC voltage Vout based on the switch drive signal.
  • the switching circuit 560 may include multiple transistors, for example, a metal-oxide-semiconductor field-effect transistor (MOSFET).
  • MOSFET metal-oxide-semiconductor field-effect transistor
  • the error amplifier 554 is coupled to the comparator 556 and is configured to generate an error signal provided to the comparator 556 based on the reference signal Vref and the feedback signal Vfb indicating the direct current voltage Vout.
  • the magnitude of the DC voltage Vout output by the conversion device 210-1 in the steady state will depend on the setting of the reference signal Vref, that is, the reference signal Vref can determine the value of the output voltage Vout.
  • the loop compensator 530 is coupled to the output terminals of the error amplifier 554 and the voltage regulator 350-1.
  • the loop compensator 530 is configured to adjust the pole-zero configuration of the loop in which it is located. Thus, a negative feedback mechanism is formed in the voltage regulator 350-1.
  • Using the loop compensator 530 to adjust the pole-zero configuration can ensure the stable operation of the voltage regulator 350-1 within a certain bandwidth.
  • the specific circuit of the loop compensator is not shown in FIG. 5. It can be understood that the loop compensator 530 may include one or more components connected in parallel with the error amplifier 554, and one or more components between the input terminal of the error amplifier receiving the feedback signal Vfb and the output terminal of the voltage regulator 350-1. Multiple components.
  • the configuration of loop compensation may also be different.
  • the loop compensator 530 may include multiple loop compensation circuits for PWM modes of different switching frequencies. As shown in FIG. 5, the first loop compensation circuit 531 can be used in the first PWM mode, and the second loop compensation circuit 532 can be used in the second PWM mode.
  • the loop compensator 530 may receive the selection signal S1 or the selection signal S2. In response to the selection signal S2, the first loop compensation circuit 531 is connected to the loop to adjust the pole-zero configuration. Or in response to the selection signal S1, the second loop compensation circuit 532 is connected to the loop to adjust the pole-zero configuration.
  • the corresponding loop compensation circuit is selected. In this way, accurate loop compensation can be performed for the PWM modes of different switching frequencies, so that the voltage regulator 350 can operate stably under different switching frequencies.
  • FIG. 6 shows a schematic structural diagram of a device 210-1-1 for DC voltage conversion according to some embodiments of the present disclosure.
  • the conversion device 210-1-1 can be regarded as a specific implementation of the conversion device 210-1, where the "OR" gate 520-1 is a specific implementation of the selection signal determination circuit 520, and the voltage regulator 350-1-1 is a voltage A specific implementation of the regulator 350-1, and the switch circuit 560-1 is a specific implementation of the switch circuit 560.
  • FIG. 6 shows the event signals Vsoft_going, Vset_going, and Vdrop_going.
  • the voltage regulator 350-1-1 When the voltage regulator 350-1-1 is in a startup process (for example, a slow startup process), the event signal Vsoft_going is valid; after the startup ends, the event signal Vsoft_going returns to zero.
  • the voltage regulator 350-1-1 When the voltage regulator 350-1-1 is in the process of adjusting the DC voltage Vout (for example, because the target value of the DC voltage Vout is adjusted), the event signal Vset_going is valid; after the adjustment is completed, the event signal Vset_going returns to zero.
  • the OR gate 520-1 When the actual value of the DC voltage Vout exceeds the predetermined range, the event signal Vdrop_going is valid; after the actual value of the DC voltage Vout returns to the predetermined range, the event signal Vdrop_going returns to zero. Therefore, as long as any one or more of the event signals Vsoft_going, Vset_going, and Vdrop_going are valid, the OR gate 520-1 will output the selection signal S1 at a high level. When the event signals Vsoft_going, Vset_going, and Vdrop_going are all reset to zero, the OR gate 520-1 will output the selection signal S2 at “0”.
  • the validity of the event signals Vsoft_going and Vset_going may depend on instructions or signals from the processor 101.
  • the validity of the event signal Vdrop_going may depend on the internal detection of the device 210, for example, the detection of the DC voltage Vout.
  • the resetting of the event signals Vsoft_going, Vset_going, and Vdrop_going may all depend on the internal detection of the device 210. This will be described below with reference to multiple drawings.
  • the control terminal of the multiplexer 512 is coupled to the output terminal of the OR gate 520-1 to receive the selection signal S1 or the selection signal S2.
  • the two input ends of the multiplexer 512 respectively receive the ramp signal F1_Vramp with the first frequency and the ramp signal F2_Vramp with the second frequency. If the control terminal receives the selection signal S1, the multiplexer 512 selects the ramp signal F2_Vramp and uses it as the periodic signal Vramp. If the control terminal receives the selection signal S2, the multiplexer 512 selects the ramp signal F1_Vramp and uses it as the periodic signal Vramp.
  • the multiplexer 512 when any event signal is valid, the multiplexer 512 will select the ramp signal F2_Vramp with the higher second frequency as the periodic signal Vramp. After the event signals are all reset to zero, the multiplexer 512 will select the ramp signal F1_Vramp with the lower first frequency as the periodic signal Vramp.
  • the comparator 556 is coupled to the output terminal of the multiplexer 512 to receive the periodic signal Vramp.
  • the comparator 556 generates a PWM signal having the same frequency as the periodic signal Vramp based on the periodic signal Vramp and the error signal from the error amplifier 554.
  • the switch drive circuit 558 is coupled to the comparator 556 to receive the PWM signal, and generates a switch drive signal based on the PWM signal.
  • the switch circuit 560-1 is coupled to the switch drive circuit 558 to receive the switch drive signal.
  • the switch drive signal controls the alternate conduction of the upper transistor 661 and the lower transistor 662, thereby converting the input voltage from the power supply PVDD into a direct current voltage Vout.
  • the upper transistor 661 is a P-type metal-oxide-semiconductor (PMOS) transistor, and the lower transistor 662 is an N-type metal-oxide-semiconductor (NMOS). ) Transistor.
  • PMOS P-type metal-oxide-semiconductor
  • NMOS N-type metal-oxide-semiconductor
  • the loop compensator 530 is coupled to the output terminals of the error amplifier 554 and the voltage regulator 550 to adjust the pole-zero configuration of the loop.
  • the loop compensator 530 may include both a first loop compensation circuit 531 for the first PWM mode and a loop compensation circuit 532 for the second PWM mode.
  • the loop compensator 530 may be further coupled to the output terminal of the OR gate 520-1 to receive the selection signal S1 or the selection signal S2.
  • the two input terminals of the error amplifier 554 receive the feedback signal Vfb and the reference signal Vref, respectively.
  • the output terminal of the error amplifier 554 is coupled to the comparator 556 to provide the comparator 556 with an error signal generated based on the feedback signal Vfb and the reference signal Vref.
  • the feedback signal Vfb can be used to reflect the magnitude of the DC voltage Vout, and it can be selectively equal to the DC voltage Vout or the divided voltage of the DC voltage Vout, which is not limited in this embodiment.
  • the magnitude of the DC voltage Vout output by the voltage regulator 350-1 can be achieved by changing the setting of the reference signal Vref. For example, during the startup process of the voltage regulator 350-1, by slowly adjusting the voltage of the reference signal Vref, the voltage of the DC voltage Vout can be slowly increased.
  • the control end of the multiplexer 652 receives the event signal Vsoft_going. The validity of the event signal Vsoft_going indicates that the voltage regulator 350-1-1 is in the process of starting. At this time, the multiplexer 652 selects Vsoft and uses it as the reference signal Vref; after the start, the event signal Vsoft_going returns to zero, and the multiplexer selects Vsoft.
  • the device 652 selects Vset and uses it as the reference signal Vref.
  • Vsoft represents the reference soft start signal, and Vset corresponds to the target value of the direct current voltage Vout, and can be configured by, for example, the processor 101.
  • the frequency converter 310-1 is configured to transform the frequency of the periodic signal based on the selection signal S1/S2.
  • the periodic signal is converted based on the selection signal S1.
  • the frequency of Vp is increased from the first frequency to the second frequency; when all at least one event ends, based on the selection signal S2, the frequency of the periodic signal Vp is decreased from the second frequency, thereby adjusting the voltage in the pulse width modulation mode
  • the switching frequency of the device 350-1 that is, the frequency of the periodic signal Vramp, is variable, resulting in that the switching frequency of the switching circuit 560 is no longer fixed, but can be changed. In this way, the system requirements can be better adapted.
  • FIG. 7 shows a schematic structural diagram of a device 210-1-2 for DC voltage conversion according to other embodiments of the present disclosure.
  • the conversion device 210-1-2 can be regarded as another specific implementation of the conversion device 210-1, in which the "OR" gate 520-1 is a specific implementation of the selection signal determination circuit 520, and the voltage regulator 350-1-2 is A specific implementation of the voltage regulator 350-1, and the switch circuit 560-2 is a specific implementation of the switch circuit 560.
  • FIG. 8 shows a schematic structural diagram of a device 210-1-3 for DC voltage conversion according to other embodiments of the present disclosure.
  • the conversion device 210-1-3 can be regarded as another specific implementation of the conversion device 210-1, in which the "OR" gate 520-1 is a specific implementation of the selection signal determination circuit 520, and the voltage regulator 350-1-3 is A specific implementation of the voltage regulator 350-1, and the switch circuit 560-3 is a specific implementation of the switch circuit 560.
  • the description of the same parts of the conversion devices 210-1-2, 210-1-3 and the conversion device 210-1-1 will not be repeated here.
  • the difference between the conversion devices 210-1-2 and 210-1-3 and the conversion device 210-1-1 lies in the type of voltage regulator.
  • the voltage regulator 350-1-1 of the conversion device 210-1-1 is a BUCK type, and includes a BUCK type switching circuit 560-1.
  • the voltage regulator 350-1-2 of the conversion device 210-1-2 is of the BOOST type, and includes a BOOST type of switching circuit 560-2.
  • the voltage regulator 350-1-3 of the conversion device 210-1-3 is a BUCK-BOOST type, and includes a BUCK-BOOST type switch circuit 560-3.
  • the voltage regulator described above with reference to FIGS. 6 to 8 is a closed-loop mode voltage regulator. It should be understood that, in addition to the types of voltage regulators shown in FIGS. 6 to 8, the embodiments of the present disclosure can also be applied to other types of DC-DC circuits with PWM modes, including but not limited to switched capacitor circuits, charge pumps, Switch type LDO, etc.
  • Fig. 9 shows a schematic structural diagram of a frequency converter 310-1-1 according to some embodiments of the present disclosure.
  • the frequency converter 310-1-1 can be regarded as a specific implementation of the frequency converter 310-1.
  • the frequency converter 310-1-1 may further include a multiplexer 914.
  • the multiplexer 914 is coupled to the multiplexer 512.
  • the multiplexer 914 may be configured to select a ramp signal from the ramp signal F4_Vramp with the fourth frequency and the ramp signal F5_Vramp with the fifth frequency as the ramp signal F1_Vramp based on the selection signal S3 representing the specification constraint condition of the load.
  • the control end of the multiplexer 914 receives the selection signal S3.
  • the two input ends of the multiplexer 914 respectively receive the ramp signal F4_Vramp with the fourth frequency and the ramp signal F5_Vramp with the fifth frequency.
  • the multiplexer 914 may be configured to select one of the ramp signal F4_Vramp and the ramp signal F5_Vramp as the ramp signal F1_Vramp based on the selection signal S3.
  • the selection signal S3 represents the specification constraint condition of the load.
  • the load has requirements for the voltage provided by the device for DC voltage conversion based on its own specifications.
  • the specification constraints include: requirements for ripple voltage contained in the voltage, or requirements for transient response speed Request etc.
  • the specification constraint condition of the load may be determined by the processor 101 according to the power supply requirements of the currently activated load or the load to be activated.
  • the ripple voltage constraint condition of the load may be determined by the processor 101 according to the ripple voltage requirements of the currently activated load or the load to be activated (described in detail below).
  • the load's requirement for ripple voltage refers to the maximum ripple voltage that the load can withstand.
  • Different loads have different levels of requirements for the ripple voltage, and the switching frequency in the PWM mode affects the ripple voltage in the DC voltage Vout. The higher the switching frequency, the smaller the ripple voltage. It is assumed here that the fourth frequency is higher than the fifth frequency.
  • the selection signal S3 causes the ramp signal F4_Vramp to be selected as the ramp signal F1_Vramp. If the ripple voltage constraint condition of the load indicates that the load can withstand a relatively large ripple voltage, the selection signal S3 causes the ramp signal F5_Vramp to be selected as the ramp signal F1_Vramp.
  • the frequency of the ramp signal F1_Vramp may be the fourth frequency or the fifth frequency. Since the frequency of the ramp signal F1_Vramp corresponds to the switching frequency of the conversion device 210 in the basic PWM mode, the switching frequency in the basic PWM mode may be the fourth frequency or the fifth frequency.
  • the PWM mode corresponding to the fourth frequency is referred to as "fourth PWM mode”.
  • the ramp signal F4_Vramp is selected as the periodic signal Vramp.
  • the PWM mode corresponding to the fifth frequency is called "fifth PWM mode”.
  • the ramp signal F5_Vramp is selected as the periodic signal Vramp.
  • FIG. 10 shows a graph 1000 of switching frequency and load current according to some embodiments of the present disclosure, which is a graph of a further optimized embodiment based on the embodiment of FIG. 4.
  • Curves 452, 1053, and 1054 respectively show the relationship between the switching frequency and the load current in the second PWM mode, the fourth PWM mode, and the fifth PWM mode.
  • the second PWM mode is the high-frequency PWM mode described above. It can be understood that both the fourth PWM mode and the fifth PWM mode are basic PWM modes.
  • the conversion device 210 may be operated in the fourth PWM mode or the fifth PWM mode. During the occurrence of the trigger event, the conversion device 210 will switch to the second PWM mode, that is, the high-frequency PWM mode.
  • the frequency converter Since in the basic PWM mode, the frequency converter will select the ramp signal F1_Vramp as the periodic signal Vramp, therefore, the switching frequency in the basic PWM mode is the same as the frequency of the ramp signal F1_Vramp. That is, in this embodiment, the switching frequency in the basic PWM mode may be different depending on the specification voltage constraint condition of the load.
  • the switching frequency in the basic PWM mode in addition to realizing the dynamic switching of the switching frequency based on the trigger event, can also be configured based on the load's requirement for the supply voltage (for example, the requirement for the ripple voltage) . For example, when the load can withstand a large ripple voltage, the switching frequency in the basic PWM mode can be reduced. In this way, the power utilization efficiency can be improved without reducing the voltage conversion performance.
  • FIG. 11 shows a schematic structural diagram of a device 210-2 for DC voltage conversion according to some embodiments of the present disclosure.
  • the conversion device 210-2 can be regarded as a specific implementation of the conversion device 210, in which the frequency converter 310-2 is a specific implementation of the frequency converter 310, and the voltage regulator 350-2 in the open loop mode is a specific implementation of the voltage regulator 350.
  • a concrete realization, and the periodic signal Vpwm in the form of PWM is a concrete realization of the periodic signal Vp.
  • the voltage regulator 350-2 in the open loop mode does not have a feedback loop, so there is no circuit for implementing the feedback loop such as a comparator, so that the switch drive circuit 1158 directly receives the cycle in the form of PWM output from the multiplexer 1112 Signal Vpwm.
  • the magnitude of the DC voltage Vout output by the voltage regulator 350-2 in the open loop mode is proportional to the magnitude of the input DC voltage Vin. This ratio is determined by the topology of the power stage circuit. Therefore, the DC voltage Vout will change as the DC voltage Vin changes.
  • the conversion device 210-2 may further include a selection signal determination circuit 1120.
  • the selection signal determination circuit 1120 is shown as an OR gate.
  • the selection signal determination circuit 1120 is coupled to the frequency converter 310-2, and is configured to determine the selection signal S1 or the selection signal S2 based on at least one event signal.
  • the selection signal determination circuit 520 may receive one or more event signals, and output the selection signal S1 or the selection signal S2 based on whether the one or more event signals are valid.
  • FIG. 11 shows event signals Vsoft_going and Vdrop_going. These event signals are similar to those described with reference to FIG. 6, and the description of these event signals will not be repeated here. Since there is no reference signal Vref in FIG. 11, the DC voltage Vout is not adjusted by the reference signal Vref, so the event signal does not include Vset_going.
  • the conversion device 210-2 may not include the selection signal determination circuit 1120.
  • the event signal may be directly provided to the frequency converter 310-2 as a selection signal.
  • the frequency converter 310-2 may include a multiplexer 1112.
  • the multiplexer 1112 may be configured to select one PWM signal as the periodic signal Vpwm from the PWM signal F1_Vpwm having the first frequency and the PWM signal F2_Vpwm having the second frequency based on the selection signal.
  • the periodic signal Vp is implemented as a PWM signal.
  • control terminal of the multiplexer 1112 is coupled to the output terminal of the selection signal determination circuit 1120 to receive the selection signal S1 or the selection signal S2.
  • the two input ends of the multiplexer 1112 respectively receive the PWM signal F1_Vpwm with the first frequency and the PWM signal F2_Vpwm with the second frequency. If the control terminal receives the selection signal S1, the multiplexer 1112 selects the ramp signal PWM signal F2_Vpwm and uses it as the periodic signal Vpwm. If the control terminal receives the selection signal S2, the multiplexer 512 selects the PWM signal F1_Vpwm and uses it as the periodic signal Vpwm.
  • the frequency converter 310-2 may further include a multiplexer 1114.
  • the multiplexer 1114 is coupled to the multiplexer 1112.
  • the multiplexer 1114 may be configured to select one PWM signal as the PWM signal F1_Vpwm from the PWM signal F4_Vpwm having the fourth frequency and the PWM signal F5_Vpwm having the fifth frequency based on the selection signal S3 representing the specification constraint condition of the load.
  • the control end of the multiplexer 1114 receives the selection signal S3.
  • the two input ends of the multiplexer 1114 respectively receive the PWM signal F4_Vpwm with the fourth frequency and the PWM signal F5_Vpwm with the fifth frequency.
  • the multiplexer 1114 may be configured to select one of the PWM signal F4_Vpwm and the PWM signal F5_Vpwm as the PWM signal F1_Vpwm based on the selection signal S3.
  • the selection signal S3 is similar to that described above with reference to FIG. 9, and the description of the selection signal S3 will not be repeated here.
  • the voltage regulator 350-2 may include a switch driving circuit 1158 and a switch circuit 1160.
  • the switch driving circuit 1158 is coupled to the frequency converter 310-2 to receive the periodic signal Vpwm.
  • the switch driving circuit 1158 may be configured to generate a switch driving signal based on the periodic signal Vpwm.
  • the switch circuit 1160 is coupled to the switch drive circuit 1158 and is configured to convert the DC voltage Vin into the DC voltage Vout based on the switch drive signal.
  • the switch circuit 1160 includes an SC type circuit, and the DC voltage Vout can be selectively one-half of the DC voltage Vin.
  • the conversion device 210-2 includes an open-loop mode voltage regulator 350-2. Therefore, the event-based frequency conversion scheme according to an embodiment of the present disclosure can be applied to various types of voltage regulators, regardless of whether they are in an open-loop mode or a closed-loop mode.
  • the device 210 for DC voltage conversion is described above with reference to FIGS. 3 to 11. Refer back to Figure 2.
  • the processor 101 and the conversion device 210 can communicate.
  • the following describes an example in which the processor 101 and the conversion device 210 cooperate to perform frequency conversion in conjunction with FIG. 2 and FIG. 12.
  • Figure 12 illustrates an example process 1200 of frequency transformation according to some embodiments of the present disclosure.
  • the processor 101 determines in 1205 whether a trigger event has occurred. If a trigger event occurs, the processor 101 generates a first frequency conversion signal in 1210, and sends the first frequency conversion signal to the conversion device 210 in 1215. In response to receiving the first frequency conversion signal in 1220, the conversion device 210 increases the frequency of the periodic signal from the first frequency to the second frequency, and in the PWM mode, converts the DC voltage Vin into DC voltage Vout.
  • the first frequency conversion signal can enable the selection signal S1, thereby increasing the frequency of the periodic signal Vp from the first frequency to the second frequency.
  • the conversion device 210 may include other components not shown in the figure.
  • Such a component may be a conversion component or an enabling component, which enables the selection signal S1 based on the first frequency conversion signal, that is, generates the selection signal S1.
  • a component may generate the event signal Vsoft_going or Vset_going shown in FIGS. 6 to 8 and FIG. 11 based on the first frequency conversion signal, or set the state of the event signal Vsoft_going or Vset_going.
  • the device 210 may determine the end of the trigger event, and enable the selection signal S2 based on the end of the trigger event.
  • the device 210 may include a detection component for determining the end of the trigger event. Such a detection component can determine whether the trigger event is over by detecting electrical parameters (for example, voltage, current, and power) inside the device 210. In the case of determining that the trigger event ends, the detection component may enable the selection signal S2, for example, reset the event signal Vsoft_going or Vset_going to zero.
  • the detection component may be coupled to the aforementioned enabling component. When it is determined that the trigger event ends, the detection component may send a signal to the enabling component, and the enabling component may invalidate the selection signal S1 and enable the selection signal S2 based on the signal from the detection component.
  • the trigger event may include the conversion device 210 being activated. If the processor 101 determines that the conversion device 210 is activated, the first frequency conversion signal may be generated. Correspondingly, the conversion device 210 increases the frequency of the periodic signal Vp from the first frequency to the second frequency in response to receiving the first frequency conversion signal. Additionally, in some embodiments, the conversion device 210 may also detect whether the activation is complete, and the operation of detecting whether the activation is complete may be performed by a detection component inside the conversion device 210. The detection component can determine whether the start-up is over by detecting electrical parameters inside the device 210. For example, if it is detected that the DC voltage Vout changes from zero to a preset value, it can be determined that the start-up is over. If the end of the start is detected, the conversion device 210 may reduce the frequency of the periodic signal Vp from the second frequency back to the first frequency.
  • the first frequency conversion signal from the processor 101 may make the event signal Vsoft_going shown in FIGS. 6 to 8 valid.
  • the multiplexer 512 can select the ramp signal F2_Vramp as the periodic signal Vramp based on the selection signal S1. If the end of the start is detected, the event signal Vsoft_going can be reset to zero. For example, if it is detected that the DC voltage Vout reaches a preset value, the above-mentioned detecting component or enabling component may reset the event signal Vsoft_going to zero. In the case where the other event signals also return to zero, the multiplexer 512 may select the ramp signal F1_Vramp as the periodic signal Vramp based on the selection signal S2.
  • the trigger event may include that the target value of the DC voltage Vout is adjusted. If the processor 201 determines that the target value of the DC voltage Vout is adjusted, the first frequency conversion signal may be generated. Correspondingly, the conversion device 210 increases the frequency of the periodic signal Vp from the first frequency to the second frequency in response to receiving the first frequency conversion signal. Additionally, in some embodiments, the conversion device 210 can also detect the DC voltage Vout. For example, the above-mentioned detection component can be used to detect the DC voltage Vout. If it is detected that the DC voltage Vout reaches the target value, the conversion device 210 may reduce the frequency of the periodic signal Vp from the second frequency back to the first frequency.
  • the first frequency conversion signal from the processor 101 may make the event signal Vset_going shown in FIGS. 6 to 8 valid.
  • the multiplexer 512 can select the ramp signal F2_Vramp as the periodic signal Vramp based on the selection signal S1. If it is detected that the DC voltage Vout reaches the target value, the event signal Vset_going can be reset to zero. For example, if the DC voltage Vout reaches the target value, the above-mentioned detecting component or enabling component may reset the event signal Vset_going to zero. In the case where the other event signals also return to zero, the multiplexer 512 may select the ramp signal F1_Vramp as the periodic signal Vramp based on the selection signal S2.
  • the conversion device 210 may also convert the frequency of the periodic signal in the PWM mode based on the internally detected trigger event.
  • the conversion device 210 can detect electrical parameters, which represent the current of the load coupled to the conversion device 210 (hereinafter also referred to as load current), and this process can be executed by a detection component in the conversion device 210 (not shown in the figure) .
  • load current represents the current of the load coupled to the conversion device 210
  • the conversion device 210 can detect the output voltage, output current, or output power.
  • the conversion device 210 may increase the frequency of the periodic signal Vp from the first frequency to the second frequency. If it is detected that the electrical parameter returns to the predetermined range, the conversion device 210 can reduce the frequency of the periodic signal Vp from the second frequency back to the first frequency.
  • the operation of detecting whether the electrical parameter exceeds a predetermined range may also be performed by the detecting component. Therefore, the event that triggers the frequency converter to increase the frequency of the periodic signal can come from the processor 101 or from the detection component inside the conversion device 210, which is not limited in this embodiment.
  • the conversion device 210 may enable the event signal Vdrop_going shown in FIGS. 6 to 8 to be valid.
  • the multiplexer 512 can select the ramp signal F2_Vramp as the periodic signal Vramp based on the selection signal S1. If it is detected that the electrical parameters return to the predetermined range, the event signal Vdrop_going can be reset to zero. For example, if it is detected that the electrical parameter returns to a predetermined range, the above-mentioned detecting component or enabling component may reset the event signal Vdrop_going to zero. In the case where the other event signals also return to zero, the multiplexer 512 may select the ramp signal F1_Vramp as the periodic signal Vramp based on the selection signal S2.
  • FIG. 13 shows a schematic block diagram of an electronic device 200 according to some embodiments of the present disclosure.
  • the electronic device 200 may also include loads 1321-1 and 1321-2 powered by the conversion device 210.
  • loads 1321-1 and 1321-2 are also collectively referred to as loads 1321.
  • the load 1321 may communicate with the processor 101, and the processor 101 may control the enabling and disabling of the load 1321.
  • the load 1321 may be any component in the electronic device 200, such as a camera, a memory, and other processors.
  • the processor 101 itself can also be used as a load.
  • the processor 101 is also powered by the conversion device 210.
  • one or more of the loads 1321-1 and 1321-2 may be located on the same chip as the processor 101, for example on the same SoC.
  • the number of loads shown in FIG. 13 is only illustrative, and is not intended to limit the scope of the present disclosure.
  • the switching frequency in the PWM mode affects the magnitude of the ripple voltage in the DC voltage Vout.
  • the processor 1001 may determine the ripple voltage constraint condition for the direct current voltage Vout. For example, the ripple voltage constraint condition can be determined based on the highest requirements of the ripple voltage of the load that has been activated and the load to be activated. Likewise, if one or more loads are disabled, the processor 101 may determine the ripple voltage constraint based on the ripple voltage requirements of the loads that are still enabled. In either case, the processor 101 can configure the switching frequency of the conversion device 210 in the basic PWM mode to a frequency that matches the ripple voltage constraint.
  • the processor 101 determines the ripple voltage constraint condition of the load, and generates the second frequency conversion signal based on the ripple voltage constraint condition.
  • the processor 101 sends the second frequency conversion signal to the conversion device 210.
  • the conversion device 210 may set the above-mentioned first frequency of the periodic signal to one of a plurality of preset frequencies, and the frequency matches the ripple voltage constraint condition of the load.
  • the device 210 may include a conversion component or an enabling component, which determines or enables the selection signal S3 based on the second frequency conversion signal, that is, sets the state of the selection signal S3.
  • the enabling component for determining or enabling the third selection signal S3 and the enabling component for enabling the first selection signal S1 may be the same or different components, which is not limited in this embodiment.
  • the conversion component or the enabling component may set the state of the selection signal S3 as shown in FIGS. 9 and 11 based on the second frequency conversion signal from the processor 101.
  • the selection signal S3 may have a plurality of states (such as a plurality of levels) corresponding to a plurality of preset frequencies, respectively. For example, in the case of having two preset frequencies, the selection signal S3 may have a valid state and a return-to-zero state.
  • the state of the selection signal S3 (for example, the selection signal S3 is valid) will cause the ramp signal F4_Vramp to be selected as Ramp signal F1_Vramp.
  • the switching frequency of the conversion device 210 in the PWM mode is the frequency of the ramp signal F4_Vramp.
  • the conversion device 210 operates in the fourth PWM mode shown in FIG. 10. During the occurrence of the trigger event, the conversion device 210 can switch to the second PWM mode, that is, the high-frequency PWM mode.
  • the state of the selection signal S3 (for example, the selection signal S3 is zeroed) will cause the ramp signal F5_Vramp to be selected as the ramp signal F1_Vramp.
  • the switching frequency of the conversion device 210 in the PWM mode is the frequency of the ramp signal F5_Vramp.
  • the conversion device 210 operates in the fifth PWM mode shown in FIG. 10.
  • the conversion device 210 can switch to the second PWM mode, that is, the high-frequency PWM mode.
  • the switching frequency of the conversion device 310 in the basic PWM mode can also be adjusted based on other power supply requirements of the load (for example, requirements for transient response speed, requirements for starting speed of the conversion device, etc.).
  • the switching frequency in the basic PWM mode can be configured based on the power supply requirements of the load. In the case that the power supply requirement of the load is high, the switching frequency of the conversion device can be appropriately increased, so that the voltage conversion performance can be improved. When the power supply requirement of the load is low, the switching frequency of the conversion device can be appropriately reduced, so that the power supply efficiency of the conversion device can be further improved.
  • the processor 101 may include any suitable type of processing unit, including but not limited to CPU, GPU, artificial intelligence-based processing unit, microprocessor, controller, microcontroller, etc.
  • the processor 101 can execute various processes and actions described above according to a computer software program.
  • the computer software program can be tangibly contained in a computer-readable medium.
  • the computer-readable medium may be a computer-readable signal medium or a computer-readable storage medium.
  • the computer-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or device, or any suitable combination thereof. More detailed examples of computer-readable storage media include electrical connections with one or more wires, portable computer disks, hard drives, RAM, ROM, erasable programmable read-only memory (EPROM), Flash memory, optical fiber, CD-ROM (Compact Disc Read-Only Memory), optical storage device, magnetic storage device, or any suitable combination thereof.

Abstract

一种用于直流电压转换的装置和电子设备。用于直流电压转换的装置（210）包括：频率变换器（310），被配置为基于第一选择信号，将周期信号的频率从第一频率升高到第二频率；以及电压调节器（350），耦合至频率变换器（310），并且被配置为在脉冲宽度调制模式下，基于第二频率的周期信号，将第一直流电压转换为第二直流电压。上述装置和电子设备可以根据事件来动态地改变脉冲宽度调制模式下的开关频率，即实现了可变换的开关频率。以此方式，可以提高电压转换的性能，并缓解单纯提高开关频率带来的电能利用效率的降低。

Description

用于直流电压转换的装置和电子设备 技术领域
本申请实施例总体涉及电路技术领域，更具体地，涉及一种用于直流电压转换的装置和电子设备。
背景技术
随着电子技术的发展，诸如智能电话、平板计算机等电子设备的性能得到了日益提升，可以为用户提供多样化的功能应用。相应地，电子设备内各种部件(例如，处理单元)的运行速率越来越高。处理单元等部件运行速率的提高导致电子设备的功耗也越来越大。为此，在此类电子设备的供电中，通常采用动态电压调节(Dynamic Voltage Scaling，DVS)技术。例如，电源管理集成电路(Power Management Integrated Circuit，PMIC)根据负载的耗电情况对PMIC的输出电压进行实时、动态的调节。这种负载可以包括处理单元等部件。
在基于DVS技术的典型供电架构中，诸如系统级芯片(System-on-a-chip，SOC)上的处理器根据负载所需电压，向PMIC发送指令。PMIC根据来自处理器的指令调节输出电压，该输出电压被提供给上述负载，例如上述SOC或处理器。当输出电压调整到目标值时，作为负载的处理器开始执行相应业务。在这种架构中，输出电压贴近负载所需电压为最佳状态。受制于电压调节速度的影响，在实际中输出电压难以精确跟踪负载所需电压。这造成了能效浪费。
用于直流电压转换的装置通常至少具有脉冲宽度调制(Pulse Width Modulation，PWM)模式。为了实现快速DVS技术，一个发展方向是在PWM模式下采用更高的开关频率。即，始终以比较高的开关频率工作可以在电压转换的性能方面带来若干益处，例如可以提高装置的启动速度、提高电压调节速度、提高装置的瞬态响应性能等。然而，以预设的高开关频率工作也降低了电能利用效率。
发明内容
本公开的实施例提供了一种用于直流电压转换的装置和电子设备，以提高电压转换性能，并缓解电能利用效率的降低。
在第一方面，本公开的实施例提供了一种用于直流电压转换的装置。该装置包括：频率变换器，被配置为基于第一选择信号，将周期信号的频率从第一频率升高到第二频率；以及电压调节器，耦合至频率变换器，并且被配置为在脉冲宽度调制模式下，基于第二频率的周期信号，将第一直流电压转换为第二直流电压。其中，第一直流电压也叫输入电压，第二直流电压也叫输出电压。
在所提供的装置中，可以根据事件的触发提高脉冲宽度调制模式下的开关频率，即开关频率不再固定，而是可变换的。以此方式，可以提高电压转换的性能，例如可以提高电 压转换的速度，并缓解以预设的高开关频率工作带来的电能利用效率的降低，更好的适配系统需求。因此，本公开的实施例可以平衡电压转换性能和电能利用效率。
在一些实施例中，频率变换器还被配置为：基于不同于第一选择信号的第二选择信号，将周期信号的频率从第二频率降低至第一频率；以及电压调节器还被配置为：在脉冲宽度调制模式下，基于第一频率的周期信号将第一直流电压转换为第二直流电压。以此方式，在事件结束时自动返回到较低的开关频率，实现了开关频率的动态变换。这进一步有利于电压转换性能和电能利用效率之间的平衡。
在一些实施例中，频率变换器还被配置为：基于不同于第一选择信号的第二选择信号，将周期信号的频率从第二频率降低至不同于第一频率的第三频率；以及电压调节器还被配置为：在脉冲宽度调制模式下，基于第三频率的周期信号将第一直流电压转换为第二直流电压。以此方式，在事件结束时自动返回到较低的开关频率，实现了开关频率的动态变换。这进一步有利于电压转换性能和电能利用效率之间的平衡。
在一些实施例中，第一选择信号和第二选择信号是同一指示信号的不同指示状态，第一选择信号用于表示至少一个事件的发生，第二选择信号用于表示该至少一个事件的结束。以此方式，可以利用简单的电路配置实现周期信号在高频与低频之间的变换。
在一些实施例中，装置还包括：选择信号确定电路，耦合至频率变换器，并且被配置为基于至少一个事件信号确定第一选择信号。以此方式，可以配置多个事件信号，从而考虑多种场景下的开关频率变换。
在一些实施例中，至少一个事件信号包括如下至少一项：指示电压调节器被启动的第一事件信号，指示第二直流电压的目标值被调整的第二事件信号，或指示第二直流电压的实际值超出预定范围的第三事件信号。
在一些实施例中，选择信号确定电路包括“或”门，“或”门的输入是至少一个事件信号，“或”门的输出是第一选择信号。
在一些实施例中，频率变换器包括：第一多路选择器，被配置为基于第一选择信号，从具有第一频率的第一候选周期信号和具有第二频率的第二候选周期信号中选择第二候选周期信号作为周期信号。在一些实施例中，第一候选周期信号和第二候选周期信号可以是斜坡信号。在一些实施例中，第一候选周期信号和第二候选周期信号可以是PWM信号。
在一些实施例中，频率变换器还包括：第二多路选择器，耦合至第一多路选择器，并且被配置为基于表示负载的规格约束条件的第三选择信号，从具有第四频率的第三候选周期信号和具有第五频率的第四候选周期信号中选择一个候选周期信号作为第一候选周期信号。以此方式，可以根据负载的供电要求(例如，对纹波电压的要求、对瞬态响应速度的要求等)来配置脉冲宽度调制模式下的开关频率，从而更好地适配系统需求。这进一步有利于电压转换性能和电能利用效率之间的平衡。
在一些实施例中，电压调节器包括：误差放大器，被配置为基于参考信号和指示第二直流电压的反馈信号生成误差信号；比较器，耦合至误差放大器和频率变换器，并且被配置为基于周期信号和误差信号生成脉冲宽度调制信号；开关驱动电路，耦合至比较器，并且被配置为基于脉冲宽度调制信号生成开关驱动信号；以及开关电路，耦合至开关驱动电路，并且被配置为基于开关驱动信号将第一直流电压转换为第二直流电压。
在一些实施例中，电压调节器还包括：环路补偿器，耦合至误差放大器和电压调节器 的输出端，并且被配置为调节所述电压调节器形成的环路的零极点配置。
在一些实施例中，环路补偿器包括：第一环路补偿电路，被配置为响应于不同于第一选择信号的第二选择信号调节零极点配置；以及第二环路补偿电路，被配置为响应于第一选择信号调节零极点配置。以此方式，可以针对不同频率的脉冲宽度调制模式，进行精确的补偿。这有助于装置在不同频率下稳定地操作。
在第二方面，本公开的实施例提供了一种电子设备。该电子设备，包括：处理器，被配置为响应于至少一个事件的发生来生成第一频率变换信号；以及用于直流电压转换的装置，耦合至处理器，并且被配置为：响应于接收到第一频率变换信号，将周期信号的频率从第一频率升高到第二频率，以及在脉冲宽度调制模式下，基于第二频率的周期信号，将第一直流电压转换为第二直流电压。其中，第一直流电压也叫输入电压，第二直流电压也叫输出电压。可选地，所述装置可以基于第一频率变换信号使能第一选择信号，并基于所述第一选择信号，将周期信号的频率从第一频率升高到第二频率。
在所提供的电子设备中，可以根据事件的触发变换脉冲宽度调制模式下的开关频率。以此方式，可以提高电压转换的性能，例如可以提高电压转换的速度，并缓解以预设的高开关频率工作带来的电能利用效率的降低，更好地适配电子设备的供电需求。这有助于实现供电能效优化的电子设备。
在一些实施例中，至少一个事件包括如下至少一项：装置被启动，或第二直流电压的目标值被调整。
在一些实施例中，装置还被配置为：响应于确定至少一个事件的结束，将周期信号的频率从第二频率降低至第一频率；以及在脉冲宽度调制模式下，基于第一频率的周期信号，将第一直流电压转换为第二直流电压。具体地，装置响应于确定至少一个事件的结束而使能第二选择信号，该第二选择信号用于将周期信号的频率从第二频率降低至第一频率。
在一些实施例中，处理器还被配置为：确定负载的规格约束条件；以及基于所述规格约束条件，生成第二频率变换信号。该装置还被配置为：响应于接收到第二频率变换信号，将周期信号的第一频率设置为多个预设频率中的一个频率。可选地，所述装置可以基于第二频率变换信号使能第三选择信号，并且基于第三选择信号，将周期信号的第一频率设置为多个预设频率中的一个频率。例如，该装置可以基于第三选择信号，从多个候选周期信号中选择周期信号。所述多个候选周期信号中的每一个具有多个预设频率中的相应频率。以此方式，可以根据负载的供电要求来配置脉冲宽度调制模式下的开关频率，从而更好地适配电子设备内部的供电需求。这进一步有利于电压转换性能和电能利用效率之间的平衡。
可选地，所述用于直流电压转换的装置还可以包括：基于第一频率变换信号使能第一选择信号的使能部件。附加地，在一些实施例中，使能第一选择信号的使能部件还可以被配置为：响应于第二直流电压的实际值超出预定范围而使能第一选择信号。备选地或附加地，所述用于直流电压转换的装置还可以包括：基于第二频率变换信号使能第三选择信号的使能部件。使能第一选择信号的使能部件和使能第三选择信号的使能部件可以是相同或不同的部件。
可选地，所述用于直流电压转换的装置还可以包括：频率变换器，耦合至使能第一选择信号的使能部件，并且被配置为基于第一选择信号，将周期信号的频率从第一频率升高 到第二频率；以及电压调节器，耦合至频率变换器，并且被配置为在脉冲宽度调制模式下，基于第二频率的周期信号，将第一直流电压转换为第二直流电压。可选地，所述用于直流电压转换的装置还可以包括：用于确定至少一个事件的结束的检测部件。可选地，所述检测部件可以通过检测电学参数来确定至少一个事件的结束。这样的电学参数可以包括所述用于直流电压转换的装置的输出电压。
可选地，检测部件可以耦合至使能第一选择信号的使能部件。如果确定至少一个事件结束，检测部件可以向使能第一选择信号的使能部件发送事件结束信号。使能第一选择信号的使能部件可以基于事件结束信号，使能不同于第一选择信号的第二选择信号，并且使第一选择信号无效。
可选地，频率变换器还可以被配置为：基于第二选择信号，将周期信号的频率从第二频率降低至第一频率；以及电压调节器还被配置为：在脉冲宽度调制模式下，基于第一频率的周期信号将第一直流电压转换为第二直流电压。在一些实施例中，频率变换器还被配置为：基于第二选择信号，将周期信号的频率从第二频率降低至不同于第一频率的第三频率；以及电压调节器还被配置为：在脉冲宽度调制模式下，基于第三频率的周期信号将第一直流电压转换为第二直流电压。
可选地，第一选择信号和第二选择信号是同一指示信号的不同指示状态，其中第一选择信号用于表示至少一个事件的发生，第二选择信号用于表示该至少一个事件的结束。
可选地，频率变换器可以包括：第一多路选择器，被配置为基于第一选择信号，从具有第一频率的第一候选周期信号和具有第二频率的第二候选周期信号中选择第二候选周期信号作为周期信号。在一些实施例中，第一候选周期信号和第二候选周期信号可以是斜坡信号。在一些实施例中，第一候选周期信号和第二候选周期信号可以是PWM信号。
可选地，频率变换器还可以包括：第二多路选择器，第二多路选择器的控制端耦合至使能第三选择信号的使能部件，输出端耦合至第一多路选择器，并且被配置为基于第三选择信号，从具有第四频率的第三候选周期信号和具有第五频率的第四候选周期信号中选择一个候选周期信号作为第一候选周期信号。
可选地，电压调节器可以包括：误差放大器，被配置为基于参考信号和指示第二直流电压的反馈信号生成误差信号；比较器，耦合至误差放大器和频率变换器，并且被配置为基于周期信号和误差信号生成脉冲宽度调制信号；开关驱动电路，耦合至比较器，并且被配置为基于脉冲宽度调制信号生成开关驱动信号；以及开关电路，耦合至开关驱动电路，并且被配置为基于开关驱动信号将第一直流电压转换为第二直流电压。
可选地，电压调节器还可以包括：环路补偿器，耦合至误差放大器和电压调节器的输出端，并且被配置为调节所述电压调节器形成的环路的零极点配置。
可选地，环路补偿器可以包括：第一环路补偿电路，被配置为响应于第二选择信号调节零极点配置；以及第二环路补偿电路，被配置为响应于第一选择信号调节零极点配置。以此方式，可以针对不同频率的脉冲宽度调制模式，进行精确的补偿。这有助于装置在不同频率下稳定地操作。
在第三方面，本公开的实施例提供了一种用于直流电压转换的装置。该装置包括：频率变换器，被配置为基于选择信号，变换周期信号的频率；以及电压调节器，耦合至频率变换器，并且被配置为在脉冲宽度调制模式下，基于周期信号，将第一直流电压转换为第 二直流电压。其中，第一直流电压也叫输入电压，第二直流电压也叫输出电压。
在所提供的装置中，可以变换脉冲宽度调制模式下的开关频率，即开关频率不再固定，而是可变换的。以此方式，可以更好的适配系统需求。
在一些实施例中，频率变换器还可以被配置为：基于第一选择信号，将周期信号的频率从第一频率升高到第二频率。
在一些实施例中，频率变换器还可以被配置为：基于不同于第一选择信号的第二选择信号，将周期信号的频率从第二频率降低至第一频率。在一些实施例中，频率变换器还可以被配置为：基于不同于第一选择信号的第二选择信号，将周期信号的频率从第二频率降低至不同于第一频率的第三频率。
此外，本文中关于第一方面的装置所描述的实施例可以应用于第三方面的装置，并且具有同样的有益效果。
第四方面，本公开的实施例提供了一种电子系统，包括根据第二方面的电子设备以及存储器，存储器用于存储计算机程序指令，电子设备中的处理器用于执行所述计算机程序指令以生成第一频率变换信号。
第五方面，本公开的实施例提供了一种芯片系统，包括第一芯片和第二芯片。所述第一芯片包括根据第二方面的电子设备中的处理器，所述第二芯片包括根据第二方面的电子设备中的用于直流电压转换的装置。
第六方面，本公开的实施例提供了一种芯片，包括第一方面的用于直流电压转换的装置，以及接口，所述接口用于从第二方面的电子设备中的处理器接收所述第一频率变换信号。
应当理解，发明内容部分中所描述的内容并非旨在限定本公开的实施例的关键或重要特征，亦非用于限制本公开的范围。本公开的其它特征将通过以下的描述变得容易理解。
附图说明
结合附图并参考以下详细说明，本公开各实施例的上述和其他特征、优点及方面将变得更加明显。在附图中，相同或相似的附图标记表示相同或相似的元素，其中：
图1示出了本公开的实施例能够应用于其中的电子设备的示意性框图；
图2示出了根据本公开一些实施例的电子设备的示意性框图；
图3示出了根据本公开一些实施例的用于直流电压转换的装置的示意性框图；
图4示出了根据本公开一些实施例的开关频率与负载电流的曲线图；
图5示出了根据本公开一些实施例的用于直流电压转换的装置的示意性框图；
图6示出了根据本公开一些实施例的用于直流电压转换的装置的结构示意图；
图7示出了根据本公开另一些实施例的用于直流电压转换的装置的结构示意图；
图8示出了根据本公开又一些实施例的用于直流电压转换的装置的结构示意图；
图9示出了根据本公开一些实施例的频率变换器的结构示意图；
图10示出了根据本公开一些实施例的开关频率与负载电流的曲线图；
图11示出了根据本公开一些实施例的用于直流电压转换的装置的结构示意图；
图12示出了根据本公开一些实施例的频率变换的示例过程；以及
图13示出了根据本公开一些实施例的电子设备的示意性框图。
具体实施方式
下面将参照附图更详细地描述本公开的实施例。虽然附图中显示了本公开的某些实施例，然而应当理解的是，本公开可以通过各种形式来实现，而且不应该被解释为限于这里阐述的实施例，相反提供这些实施例是为了更加透彻和完整地理解本公开。应当理解的是，本公开的附图及实施例仅用于示例性作用，并非用于限制本公开的保护范围。
在本公开的实施例的描述中，术语“包括”及其类似用语应当理解为开放性包含，即“包括但不限于”。术语“基于”应当理解为“至少部分地基于”。术语“一个实施例”或“该实施例”应当理解为“至少一个实施例”。术语“第一”、“第二”等等可以指代不同的或相同的对象。下文还可能包括其他明确的和隐含的定义。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的，等同于广义上的耦合或电性联通。
如上文简述，为了实现快速DVS技术，一种解决方案是将用于直流电压转换的装置(以下也可以称为转换装置)在PWM模式下的开关频率设置为高频率。与低开关频率相比，在高开关频率情况下，流过相同电感的电流的峰峰值较低。在每个周期中电流限制保护(Over Current Protection，OCP)配置相同的情况下，流过电感的电流Iout增加。在转换装置的缓启动、电压调节、输出电压跌落响应等过程中，本质上是对转换装置的输出电容充电。这使得Iout增加，从而缩短了缓启动、电压调节、输出电压跌落响应的时间。另一方面，与低开关频率相比，高开关频率显著减小了转换装置的环路硬件延迟。在负载发生瞬态改变时，可以减小输出电压的瞬态跌落或瞬态上冲。开关频率高诚然可以在电压转换的性能方面带来若干益处，例如可以提高转换装置的启动速度、提高电压调节速度、降低输出电压的跌落或上冲幅度等。然而，采用固定的高开关频率也降低了电能转换效率。因此，仅通过采用固定高开关频率来实现快速DVS难以实现高效的供电效能。
为了至少部分地解决上述问题以及其他潜在问题，本公开的实施例提供了一种用于直流电压转换的方案。总体而言，根据在此描述的各种实施例，用于直流电压转换的装置在事件发生时，通过提高PWM模式下周期信号的频率来提高开关频率。引起装置提高周期信号的频率的事件在下文中也可以被称为“触发事件”。由此，能够有益地根据事件来动态地改变PWM模式下的开关频率，即开关频率是可变换的。以此方式，可以提高电压转换性能，并缓解以预设的高开关频率工作带来的电能利用效率的损失。本公开的实施例可以实现电压转换性能和电能利用效率之间的平衡。
下面将结合附图描述本公开的各种示例实施例。图1示出了本公开的实施例能够应用于其中的电子设备100的示意性框图。如图所示，电子设备100包括处理器101。处理器101可以是任何合适类型的处理单元，包括但不限于中央处理单元(Central Processing Unit，CPU)、图形处理单元(Graphics Processing Unit，GPU)、数字信号处理器(Digital Signal Processor，DSP)基于人工智能(Artificial Intelligence，AI)的处理单元等。
处理器101可以根据存储在只读存储器(Read-Only Memory，ROM)102中的计算机程序指令或者从存储单元108加载到随机访问存储器(Random Access Memory，RAM)103中的计算机程序指令，来执行各种适当的动作和处理。在随机访问存储器103中，还可存储电子设备100操作所需的各种程序和数据。处理器101、只读存储器102以及随机访问 存储器103通过总线104彼此相连。输入/输出(Input/Output，I/O)接口105也连接至总线104。
电子设备100还包括供电单元110。供电单元110可以为电子设备100内的部件提供运行所需要的电能。在一些实施例中，供电单元110可以包括PMIC。
电子设备100中的多个部件连接至I/O接口105，包括：输入单元106，例如键盘、鼠标等；输出单元107，例如各种类型的显示器、扬声器等；存储单元108，例如磁盘、光盘等；以及通信单元109，例如网卡、调制解调器、无线通信收发机等。通信单元109允许电子设备100通过诸如因特网的计算机网络或各种电信网络与其他设备交换信息或数据。
处理器101可以执行方法和处理。例如，在一些实施例中，方法和处理可以被实现为计算机软件程序或计算机程序产品，其被有形地包含于机器可读介质，例如存储单元108。在一些实施例中，计算机程序的部分或者全部可以经由只读存储器102和/或通信单元109而被载入和/或安装到电子设备100上。
在一些实施例中，电子设备100中的多个部件可以被集成在同一芯片。例如，包括但不限于处理器101、总线104、只读存储器102、随机访问存储器103的部件可以被集成在SoC上。再例如，处理器101、总线104和通信单元109可以被集成在SoC上，该SoC被定义为第一芯片。
在一些实施例中，电子设备100可以包括智能电话。在一些实施例中，电子设备100可以包括以下至少一项：机顶盒、娱乐单元、导航设备、通信设备、固定位置数据单元、移动位置数据单元、移动电话、蜂窝电话、平板电脑、平板手机、计算机、便携式计算机、台式计算机、个人数字助理(Personal Digital Assistant，PDA)、监视器、计算机监视器、电视、调谐器、收音机、卫星收音机、音乐播放器、数字音乐播放器、便携式音乐播放器、数字视频播放器、视频播放器、数字视频光盘(Digital Versatile Disc，DVD)播放器、便携式数字视频播放器等。
图2示出了根据本公开一些实施例的电子设备200的示意性框图。电子设备200可以被实现在电子设备100中。如图2所示，电子设备200包括处理器101。处理器101被配置为响应于事件的发生来生成频率变换信号。下文将参考图11描述处理器101的具体操作。在一些实施例中，处理器101可以被集成在SoC上。
电子设备200还包括与处理器101通信的、用于直流电压转换的装置210，其在下文中也可以简称为转换装置210。转换装置210被配置为将直流电压Vin转换为直流电压Vout。换言之，转换装置210可以将输入电压转换为输出电压，以提供给负载。该负载可以包括处理器101。备选地或附加地，负载可以包括电子设备100的一个或多个其他部件，例如只读存储器102、随机访问存储器103、存储单元108、通信单元109等。输入电压可以来自电池或者电子设备100的充电适配器，或者可以来自供电单元110或PMIC内的其他电路的输出。用于直流电压转换的装置210可位于供电单元110内部，例如位于PMIC内部。备选地，用于直流电压转换的装置210可以是独立于PMIC的其他芯片，本实施例对此不做限定。用于直流电压转换的装置210一般来说与处理器101所在SoC处于不同芯片上，即装置210可位于第二芯片，并通过接口与SoC内的处理器101耦合。装置210可以如图2所示，通过接口与处理器101交互各种信息或指令，具体可参照后续介绍的各类 信号。
转换装置210可以在PWM模式下操作。转换装置210可以被配置有不同开关频率的多个PWM模式。例如，如果触发事件发生，转换装置210可以将PWM模式下周期信号的频率升高，从而切换到高频PWM模式。如果触发事件结束，转换装置210可以将PWM模式下周期信号的频率降低，从而切换回低频PWM模式。也即是说，转换装置210可以选择性调周期信号的频率，以更好的适配系统需求。
在一些实施例中，转换装置210还可以被配置有脉冲频率调制(Pulse-Frequency Modulation，PFM)模式，以改善转换装置210在轻负载情况下的效率。例如，如果负载电流小于预定值，转换装置210可以切换到PFM模式。即，转换装置210可以根据负载电流动态降低开关频率，以此提升轻负载情况下的供电效率。
转换装置210可以被实现为图1中所示的供电单元110的一部分。在一些实施例中，转换装置210可以是PMIC的至少一部分。转换装置210可以包括任何合适的具有PWM模式的直流-直流类型电路，包括但不限于降压式(BUCK)电路、升压式(BOOST)电路、降压升压式(BUCK-BOOST)电路、开关电容器(Switched-Capacitor，SC)电路、电荷泵、开关型低压差线性稳压器(Low Dropout regulator，LDO)等。可选地，转换装置210也可独立于供电单元110或PMIC。
图3示出了根据本公开一些实施例的用于直流电压转换的装置210的示意性框图。如图所示，为了进行频率变换，转换装置210包括频率变换器310。频率变换器310被配置为基于选择信号S1，将周期信号Vp的频率从第一频率升高到第二频率。选择信号S1可以表示触发事件的发生。转换装置210还包括耦合至频率变换器310的电压调节器350。电压调节器350被配置为在PWM模式下，基于第二频率的周期信号Vp，将直流电压Vin转换为直流电压Vout。直流电压Vin在实施例中也叫第一直流电压，是电压调节器350的输入电压。直流电压Vout在实施例中也叫第二直流电压，是电压调节器350的输出电压。
在一些实施例中，频率变换器310还可以被配置为基于与选择信号S1不同的选择信号S2(图3中未示出)，使周期信号Vp的频率从第二频率降低。选择信号S2可以表示触发事件的结束。相应地，电压调节器350还可以被配置为在PWM模式下，基于频率低于第二频率的周期信号Vp将直流电压Vin转换为直流电压Vout。频率变换器310可以基于选择信号S2，将周期信号Vp的频率从第二频率降低回第一频率。可选地，频率变换器310可以基于选择信号S2，将周期信号Vp的频率从第二频率降低至不同于第一频率的第三频率。例如，在下文参考图9所描述的实施例中，可以是这种情况。
在一些实施例中，周期信号Vp可以是斜坡信号，其也称为三角波信号。例如，在电压调节器350为闭环模式的电压调节器的情况下，周期信号Vp可以是斜坡信号，例如下文参考图5至图8所描述的实施例。在一些实施例中，周期信号Vp可以是PWM信号。又例如，在电压调节器350为开环模式的电压调节器的情况下，周期信号Vp可以是PWM信号，例如下文参考图11所描述的实施例。
在某些实施例中，选择信号S1和选择信号S2可以是频率变换器310接收的同一指示信号的两种不同指示值或指示状态。例如，以该指示信号是1比特(bit)信号为例，该指示信号处于高电平表示触发事件的发生，即该指示信号体现为选择信号S1；该指示信 号处于低电平表示触发事件的结束，即该指示信号体现为选择信号S2。可选地，选择信号S1和选择信号S2可以是两个独立的指示信号。尽管后续实施例以同一指示信号的两种不同指示值或指示状态来表示选择信号S1和选择信号S2进行介绍，但是应当理解本公开的实施例在此方面不限定。
转换装置210在PWM模式下的开关频率取决于周期信号Vp的频率。因此，周期信号Vp的频率在低频率(例如，第一频率或第三频率)与高频率(例如，第二频率)之间的变换使得转换装置210在PWM模式下的开关频率在高频率与低频率之间变换。下面以周期信号Vp的频率在第一频率与第二频率之间的变换为例进行描述。在本文中，与第一频率相对应的PWM模式被称为“第一PWM模式”，并且与第二频率相对应的PWM模式被称为“第二PWM模式”。
图4示出了根据本公开的一些实施例的开关频率与负载电流的曲线图400。曲线451和452分别示出了第一PWM模式和第二PWM模式下开关频率与负载电流的关系。如图所示，转换装置210可以在第一PWM模式与第二PWM模式之间切换。如虚线453所示，在一些实施例中，如果负载电流小于预定值，转换装置210可以在PFM模式下操作。
在本文中，基础PWM模式是指在未发生触发事件时转换装置210所在的PWM模式。高频PWM模式是指在发生触发事件期间转换装置210所在的PWM模式。可以理解的是，相比于基础PWM模式，高频PWM模式是一种暂态模式。在图4中，第一PWM模式可以被视为基础PWM模式，第二PWM模式可以被视为高频PWM模式。
作为示例，触发事件可以是电压调节器350被启动。例如，在电压调节器350处于缓启动阶段时，转换装置210可以切换到第二PWM模式，以实现快速启动。在缓启动完成后，转换装置210可以切换回第一PWM模式。
备选地或者附加地，在其他实施例中，触发事件可以是直流电压Vout的目标值被调整，指示电压调节器350已经或即将进入电压调整阶段，具体直流电压Vout可以被参考信号Vref所调整。例如，在电压调节器350处于电压调整阶段时，转换装置210可以切换到第二PWM模式，以实现快速调压。在调压完成后，转换装置210可以切换回第一PWM模式。在本方案中，在电压调整阶段，发生电压调节器350的输出电压切换，为了加快输出电压切换或调整的速度，转换装置210进入第二PWM模式，并在电压切换或调整结束后切换回第一PWM模式。
再如，在某些示例中，触发事件可以是直流电压Vout的实际值超出预定范围。转换装置210可以监测直流电压Vout。例如，如果直流电压Vout的实际值跌落至阈值以下，转换装置210可以切换到第二PWM模式。第二PWM模式下的高开关频率可以降低直流电压Vout的跌落幅度。当直流电压Vout的实际值恢复至预定范围后，转换装置210可以切换回第一PWM模式。同样地，如果直流电压Vout的实际值升高至阈值以上，转换装置210可以类似地操作。这可以降低直流电压Vout的上冲幅度。备选地或附加地，转换装置210还可以通过监测输出电流来判断直流电压Vout的实际值的变化。
应当理解，以上描述的触发事件仅是示例性而无意限制本公开的范围。在本公开的实施例中，可以考虑以上描述的触发事件中的一个或多个以及任何其他合适的事件。
在常规方案中，转换装置在PWM模式下采用单一开关频率。如果该开关频率较低，则电压转换性能不佳，例如装置启动速度慢、电压调节慢、输出电压的上冲或跌落幅度大。 如果该开关频率较高，尽管提高了电压转换性能，但降低了电能利用效率，造成能效浪费。因此采用预设的固定开关频率具有缺陷。在本公开的实施例中，根据触发事件来动态地改变PWM模式下的开关频率，即开关频率不再固定，而是可以被切换。由此，在触发事件发生期间，开关频率的升高可以提高电压转换性能。在未发生触发事件期间，较低的开关频率可以缓解电能利用效率的降低。以此方式，能够实现电压转换性能与电能利用效率之间的平衡。
图5示出了根据本公开一些实施例的用于直流电压转换的装置210-1的示意性框图。转换装置210-1可以被视为转换装置210的一个具体实现，其中频率变换器310-1是频率变换器310的一个具体实现，闭环模式的电压调节器350-1是电压调节器350的一个具体实现，并且斜坡形式的周期信号Vramp是周期信号Vp的一个具体实现。如图所示，在一些实施例中，转换装置210-1还可以包括选择信号确定电路520。选择信号确定电路520耦合至频率变换器310-1，并且被配置为基于至少一个事件信号确定选择信号S1或选择信号S2，并输出选择信号S1或选择信号S2。例如，选择信号确定电路520可以接收一个或多个事件信号，并且基于该一个或多个事件信号是否有效来输出选择信号S1或选择信号S2。一个或多个事件信号可以包括但不限于指示电压调节器350-1被启动的事件信号、指示直流电压Vout的目标值被调整的事件信号、指示直流电压Vout的实际值超出预定范围的事件信号。
应当理解，在仅存在一个事件信号的实施例中，转换装置210-1可以不包括选择信号确定电路520。在这种实施例中，该事件信号可以被直接提供给频率变换器310-1作为选择信号。
频率变换器310-1可以包括多路选择器512。多路选择器512可以被配置为基于选择信号从具有第一频率的斜坡信号F1_Vramp和具有第二频率的斜坡信号F2_Vramp中选择一个斜坡信号作为周期信号Vramp。在图5的实施例中，周期信号Vramp被实现为斜坡信号。
具体而言，在这样的实施例中，多路选择器512被配置为基于表示触发事件发生的选择信号S1，而从斜坡信号F1_Vramp和斜坡信号F2_Vramp中选择斜坡信号F2_Vramp，将其作为周期信号Vramp。多路选择器512还被配置为：基于表示触发事件结束的选择信号S2，而从斜坡信号F1_Vramp和斜坡信号F2_Vramp中选择斜坡信号F1_Vramp作为周期信号Vramp。
通过这样来配置多路选择器512，可以响应于触发事件的发生和结束而变换周期信号Vramp的频率，从而使转换装置210-1在第一PWM模式与第二PWM模式之间切换。换言之，开关频率不再固定，而是可变换的。由此，在触发事件发生期间，可以获得高频PWM模式的益处，提高电压转换性能。在触发事件结束后，切换回低频PWM模式可以避免高频下的电能利用效率的损失。根据本公开的实施例可以平衡电压转换性能和电能利用效率。
如图5所示，选择信号S1和选择信号S2被表示为同一指示信号的两种不同指示值或指示状态。如上文简述的，选择信号S1和选择信号S2也可以是两个独立的指示信号。例如，选择信号S1的使能可以将斜坡信号F2_Vramp提供到比较器556的输入端作为周期信号，而选择信号S2的使能可以将斜坡信号F1_Vramp提供到比较器556的输入端作为周期信号。
在图5所示的实施例中，电压调节器350-1可以包括比较器556、开关驱动电路558、 开关电路560、误差放大器554和环路补偿器530。比较器556耦合至频率变换器310-1。例如，比较器556可以耦合至多路选择器512的输出端以接收周期信号Vramp。比较器556被配置为基于周期信号Vramp和来自误差放大器554的误差信号生成PWM信号。由比较器556生成的PWM信号的频率与周期信号Vramp的频率相同。
开关驱动电路558耦合至比较器556以接收PWM信号，并且被配置为基于PWM信号生成开关驱动信号。开关电路560耦合至开关驱动电路558，并且被配置为基于开关驱动信号将直流电压Vin转换为直流电压Vout。具体地，取决于电压调节器350-1的具体类型，开关电路560可以包括多个晶体管，例如，金属氧化物半导体场效应晶体管(metal–oxide–semiconductor field-effect transistor，MOSFET)。开关驱动信号可以控制多个晶体管的交替导通，从而将直流电压Vin转换为直流电压Vout。
误差放大器554耦合至比较器556，并且被配置为基于参考信号Vref和指示直流电压Vout的反馈信号Vfb生成提供给比较器556的误差信号。转换装置210-1在稳态下输出的直流电压Vout的大小将取决于参考信号Vref的设置，即参考信号Vref可以确定该输出电压Vout的值。
环路补偿器530耦合至误差放大器554和电压调节器350-1的输出端。环路补偿器530被配置为调节所在环路的零极点配置。由此，在电压调节器350-1内形成负反馈机制。利用环路补偿器530来调整零极点配置，可以保证在一定带宽内电压调节器350-1稳定操作。图5中未示出环路补偿器的具体电路。可以理解的是，环路补偿器530可以包括与误差放大器554并联的一个或多个元件，以及在误差放大器接收反馈信号Vfb的输入端与电压调节器350-1的输出端之间的一个或多个元件。
在不同开关频率的PWM模式下，环路补偿的配置也可能不同。在一些实施例中，环路补偿器530可以包括用于不同开关频率的PWM模式的多个环路补偿电路。如图5所示，第一环路补偿电路531可以用于第一PWM模式，并且第二环路补偿电路532可以用于第二PWM模式。环路补偿器530可以接收选择信号S1或选择信号S2。响应于选择信号S2，第一环路补偿电路531被连接至环路以调节零极点配置。或响应于选择信号S1，第二环路补偿电路532被连接至环路以调节零极点配置。
在这种实施例中，在不同开关频率的PWM模式下，相应的环路补偿电路被选择。以此方式，可以针对不同开关频率的PWM模式进行准确的环路补偿，从而使得电压调节器350可以在不同开关频率下均稳定操作。
下面参考图6至图8来描述根据本公开一些实施例的用于直流电压转换的装置的一些示例。图6示出了根据本公开一些实施例的用于直流电压转换的装置210-1-1的结构示意图。转换装置210-1-1可以被视为转换装置210-1的一个具体实现，其中“或”门520-1是选择信号确定电路520的一个具体实现，电压调节器350-1-1是电压调节器350-1的一个具体实现，开关电路560-1是开关电路560的一个具体实现。
作为示例，图6示出了事件信号Vsoft_going、Vset_going和Vdrop_going。在电压调节器350-1-1处于启动过程(例如，缓启动过程)中，事件信号Vsoft_going有效；在启动结束后，事件信号Vsoft_going归零。在电压调节器350-1-1处于直流电压Vout调整(例如，由于直流电压Vout的目标值被调整)过程中，事件信号Vset_going有效；在调整结束后，事件信号Vset_going归零。在直流电压Vout的实际值超出预定范围期间， 事件信号Vdrop_going有效；在直流电压Vout的实际值恢复至预定范围后，事件信号Vdrop_going归零。因此，事件信号Vsoft_going、Vset_going和Vdrop_going中只要有任何一个或多个事件信号有效，“或”门520-1将输出处于高电平的选择信号S1。当事件信号Vsoft_going、Vset_going和Vdrop_going均归零后，“或”门520-1将输出处于“0”的选择信号S2。
事件信号Vsoft_going、Vset_going的有效可以取决于来自处理器101的指令或信号。事件信号Vdrop_going的有效可以取决于装置210的内部检测，例如对直流电压Vout的检测。事件信号Vsoft_going、Vset_going和Vdrop_going的归零可以均取决于装置210的内部检测。下文将参考多个附图对此进行描述。
多路选择器512的控制端耦合至“或”门520-1的输出端，以接收选择信号S1或选择信号S2。多路选择器512的两个输入端分别接收具有第一频率的斜坡信号F1_Vramp和具有第二频率的斜坡信号F2_Vramp。如果控制端接收到选择信号S1，则多路选择器512选择斜坡信号F2_Vramp，将其作为周期信号Vramp。如果控制端接收到选择信号S2，则多路选择器512选择斜坡信号F1_Vramp，将其作为周期信号Vramp。
以此方式，在任一事件信号有效的情况下，多路选择器512将选择具有较高的第二频率的斜坡信号F2_Vramp作为周期信号Vramp。在事件信号均归零后，多路选择器512将选择具有较低的第一频率的斜坡信号F1_Vramp作为周期信号Vramp。
比较器556耦合至多路选择器512的输出端以接收周期信号Vramp。比较器556基于周期信号Vramp和来自误差放大器554的误差信号，生成与周期信号Vramp频率相同的PWM信号。开关驱动电路558耦合至比较器556以接收PWM信号，并且基于PWM信号生成开关驱动信号。开关电路560-1耦合至开关驱动电路558以接收开关驱动信号。开关驱动信号控制上晶体管661和下晶体管662的交替导通，从而将来自功率电源PVDD的输入电压转换为直流电压Vout。在图6中，上晶体管661是P型金属氧化物半导体(P-type metal-oxide-semiconductor，PMOS)晶体管，下晶体管662是N型金属氧化物半导体(N-type metal-oxide-semiconductor，NMOS)晶体管，后续其他附图中类似画法的晶体管可参照此处的定义。
环路补偿器530耦合至误差放大器554和电压调节器550的输出端，以调节所在环路的零极点配置。在一些实施例中，环路补偿器530可以包括用于第一PWM模式的第一环路补偿电路531和用于第二PWM模式的环路补偿电路532两者。在这种实施例中，环路补偿器530可以进一步耦合至“或”门520-1的输出端，以接收选择信号S1或选择信号S2。
误差放大器554的两个输入端分别接收反馈信号Vfb和参考信号Vref。误差放大器554的输出端耦合至比较器556，以向比较器556提供基于反馈信号Vfb和参考信号Vref而生成的误差信号。反馈信号Vfb可以用于反映直流电压Vout的大小，其可以选择性等于直流电压Vout或直流电压Vout的分压电压，本实施例对此不限定。
一般而言，电压调节器350-1所输出的直流电压Vout的大小可以通过改变参考信号Vref的设置而实现。例如，在电压调节器350-1的启动过程中，通过缓慢调整参考信号Vref的电压，即可以实现直流电压Vout电压的缓慢上升。如图6所示，多路选择器652的控制端接收事件信号Vsoft_going。事件信号Vsoft_going的有效指示电压调节器350-1-1处于启动过程中，此时多路选择器652选择Vsoft，将其作为参考信号Vref；在 启动结束后，事件信号Vsoft_going归零，多路选择器652选择Vset，将其作为参考信号Vref。Vsoft表示基准缓启动信号，而Vset与直流电压Vout的目标值相对应，并且可以由例如处理器101配置。
基于图6，在本发明实施例中，频率变换器310-1，被配置为基于选择信号S1/S2，变换周期信号的频率，当至少一个事件发生的时候，基于选择信号S1，将周期信号Vp的频率从第一频率升高到第二频率；当全部至少一个事件结束的时候，基于选择信号S2，将周期信号Vp的频率从第二频率降低，从而在脉冲宽度调制模式下对电压调节器350-1的开关频率，即周期信号Vramp的频率可变，导致开关电路560的开关频率不再固定，而是可变换的。以此方式，可以更好的适配系统需求。
图7示出了根据本公开另一些实施例的用于直流电压转换的装置210-1-2的结构示意图。转换装置210-1-2可以被视为转换装置210-1的另一具体实现，其中“或”门520-1是选择信号确定电路520的一个具体实现，电压调节器350-1-2是电压调节器350-1的一个具体实现，开关电路560-2是开关电路560的一个具体实现。
图8示出了根据本公开又一些实施例的用于直流电压转换的装置210-1-3的结构示意图。转换装置210-1-3可以被视为转换装置210-1的又一具体实现，其中“或”门520-1是选择信号确定电路520的一个具体实现，电压调节器350-1-3是电压调节器350-1的一个具体实现，开关电路560-3是开关电路560的一个具体实现。
在此将不重复描述转换装置210-1-2、210-1-3与转换装置210-1-1的相同部分。转换装置210-1-2、210-1-3与转换装置210-1-1的不同在于电压调节器的类型。转换装置210-1-1的电压调节器350-1-1为BUCK类型，并且包括BUCK类型的开关电路560-1。与之相比，转换装置210-1-2的电压调节器350-1-2为BOOST类型，并且包括BOOST类型的开关电路560-2。转换装置210-1-3的电压调节器350-1-3为BUCK-BOOST类型，并且包括BUCK-BOOST类型的开关电路560-3。
以上参考图6至图8所描述的电压调节器是闭环模式的电压调节器。应当理解，除了图6至图8所示的电压调节器的类型，本公开的实施例还可以应用于具有PWM模式的其他类型的直流-直流电路，包括但不限于开关电容器电路、电荷泵、开关型LDO等。
图9示出了根据本公开一些实施例的频率变换器310-1-1的结构示意图。频率变换器310-1-1可以被视为频率变换器310-1的一个具体实现。在图9的实施例中，除了多路选择器512，频率变换器310-1-1还可以包括多路选择器914。多路选择器914耦合至多路选择器512。多路选择器914可以被配置为基于表示负载的规格约束条件的选择信号S3，从具有第四频率的斜坡信号F4_Vramp和具有第五频率的斜坡信号中F5_Vramp选择一个斜坡信号作为斜坡信号F1_Vramp。
具体而言，多路选择器914的控制端接收选择信号S3。多路选择器914的两个输入端分别接收具有第四频率的斜坡信号F4_Vramp和具有第五频率的斜坡信号F5_Vramp。多路选择器914可以被配置为基于选择信号S3，从斜坡信号F4_Vramp和斜坡信号F5_Vramp中选择一个作为斜坡信号F1_Vramp。
选择信号S3表示负载的规格约束条件。一般而言，负载基于自身的规格而对由用于直流电压转换的装置提供的电压具有要求，例如规格约束条件包括：对该电压中包含的纹波电压的要求、或对瞬态响应速度的要求等。负载的规格约束条件可以是由处理器101根 据当前被启用的负载或即将被启用的负载的供电要求来确定的。
下面以纹波电压约束条件作为示例来进行描述。负载的纹波电压约束条件可以是由处理器101根据当前被启用的负载或即将被启用的负载对纹波电压的要求来确定的(下文将具体描述)。在本文中，负载对纹波电压的要求是指负载能够承受的最大纹波电压。不同负载对纹波电压有不同级别的要求，而PWM模式下开关频率的高低影响直流电压Vout中的纹波电压的大小。开关频率越高，波纹电压越小。在此假设第四频率高于第五频率。如果负载的纹波电压约束条件指示负载要求相对小的纹波电压，则选择信号S3使得斜坡信号F4_Vramp被选择作为斜坡信号F1_Vramp。如果负载的纹波电压约束条件指示负载可以承受相对大的纹波电压，则选择信号S3使得斜坡信号F5_Vramp被选择作为斜坡信号F1_Vramp。
在这种实施例中，取决于选择信号S3，斜坡信号F1_Vramp的频率可以为第四频率或第五频率。由于斜坡信号F1_Vramp的频率对应于转换装置210在基础PWM模式下的开关频率，因此基础PWM模式下的开关频率可以为第四频率或第五频率。在本文中，与第四频率相对应的PWM模式被称为“第四PWM模式”。在第四PWM模式下，斜坡信号F4_Vramp被选择作为周期信号Vramp。与第五频率相对应的PWM模式被称为“第五PWM模式”。在第五PWM模式下，斜坡信号F5_Vramp被选择作为周期信号Vramp。
图10示出了根据本公开一些实施例的开关频率与负载电流的曲线图1000，其是在图4的实施例基础上的进一步优化的实施例的曲线图。曲线452、1053、1054分别示出了第二PWM模式、第四PWM模式、第五PWM模式下的开关频率与负载电流的关系。第二PWM模式即为上文所描述的高频PWM模式。可以理解的是，第四PWM模式和第五PWM模式均是基础PWM模式。
如图10所示，在未发生触发事件期间，取决于表示负载的规格电压约束条件的选择信号S3，转换装置210可以操作于第四PWM模式或第五PWM模式。在触发事件发生期间，转换装置210将切换到第二PWM模式，即高频PWM模式。
由于在基础PWM模式下，频率变换器将选择斜坡信号F1_Vramp作为周期信号Vramp，因此，基础PWM模式下的开关频率与斜坡信号F1_Vramp的频率相同。也就是说，在这种实施例中，基础PWM模式下的开关频率可以取决于负载的规格电压约束条件而不同。
因此，在这种实施例中，在实现基于触发事件的开关频率动态切换之外，还可以基于负载对供电电压的要求(例如，对纹波电压的要求)来配置基础PWM模式下的开关频率。例如，在负载能够承受较大的纹波电压的情况下，可以降低基础PWM模式下的开关频率。这样，可以在不降低电压转换性能的情况下，提高电能利用效率。
图11示出了根据本公开一些实施例的用于直流电压转换的装置210-2的结构示意图。转换装置210-2可以被视为转换装置210的一个具体实现，其中频率变换器310-2是频率变换器310的一个具体实现，开环模式的电压调节器350-2是电压调节器350的一个具体实现，并且PWM形式的周期信号Vpwm是周期信号Vp的一个具体实现。开环模式的电压调节器350-2不存在反馈环路，因此不存在比较器等用于实现反馈环路的电路，从而开关驱动电路1158直接接收来自多路选择器1112输出的PWM形式的周期信号Vpwm。开环模式的电压调节器350-2所输出的直流电压Vout的大小与输入的直流电压Vin的大小成比例。该比例由功率级电路的拓扑决定。因此，直流电压Vout将随着直流电压Vin的改变而发 生变化。
如图11所示，在一些实施例中，转换装置210-2还可以包括选择信号确定电路1120。在图11中，选择信号确定电路1120被示出为“或”门。选择信号确定电路1120耦合至频率变换器310-2，并且被配置为基于至少一个事件信号确定选择信号S1或选择信号S2。例如，选择信号确定电路520可以接收一个或多个事件信号，并且基于该一个或多个事件信号是否有效来输出选择信号S1或选择信号S2。作为示例，图11示出了事件信号Vsoft_going和Vdrop_going。这些事件信号与参考图6所描述的类似，在此不重复对这些事件信号的描述。由于图11中不存在参考信号Vref，直流电压Vout不被参考信号Vref所调整，因此事件信号不包括Vset_going。
应当理解，在仅存在一个事件信号的实施例中，转换装置210-2可以不包括选择信号确定电路1120。在这种实施例中，该事件信号可以被直接提供给频率变换器310-2作为选择信号。
频率变换器310-2可以包括多路选择器1112。多路选择器1112可以被配置为基于选择信号从具有第一频率的PWM信号F1_Vpwm和具有第二频率的PWM信号F2_Vpwm中选择一个PWM信号作为周期信号Vpwm。在图11的实施例中，周期信号Vp被实现为PWM信号。
具体而言，多路选择器1112的控制端耦合至选择信号确定电路1120的输出端，以接收选择信号S1或选择信号S2。多路选择器1112的两个输入端分别接收具有第一频率的PWM信号F1_Vpwm和具有第二频率的PWM信号F2_Vpwm。如果控制端接收到选择信号S1，则多路选择器1112选择斜坡信号PWM信号F2_Vpwm，将其作为周期信号Vpwm。如果控制端接收到选择信号S2，则多路选择器512选择PWM信号F1_Vpwm，将其作为周期信号Vpwm。
在一些实施例中，频率变换器310-2还可以包括多路选择器1114。多路选择器1114耦合至多路选择器1112。多路选择器1114可以被配置为基于表示负载的规格约束条件的选择信号S3，从具有第四频率的PWM信号F4_Vpwm和具有第五频率的PWM信号F5_Vpwm中选择一个PWM信号作为PWM信号F1_Vpwm。
具体而言，多路选择器1114的控制端接收选择信号S3。多路选择器1114的两个输入端分别接收具有第四频率的PWM信号F4_Vpwm和具有第五频率的PWM信号F5_Vpwm。多路选择器1114可以被配置为基于选择信号S3，从PWM信号F4_Vpwm和PWM信号F5_Vpwm中选择一个作为PWM信号F1_Vpwm。选择信号S3与上文参考图9描述的类似，在此不再重复对选择信号S3的描述。
在图11所示的实施例中，电压调节器350-2可以包括开关驱动电路1158和开关电路1160。开关驱动电路1158耦合至频率变换器310-2，以接收周期信号Vpwm。开关驱动电路1158可以被配置为基于周期信号Vpwm生成开关驱动信号。开关电路1160耦合至开关驱动电路1158，并且被配置为基于开关驱动信号将直流电压Vin转换为直流电压Vout。在图11的实施例中，开关电路1160包括SC类型的电路，并且可选择性地直流电压Vout是直流电压Vin的二分之一。
与图6至图8所示的实施例不同，在图11所示的实施例中，转换装置210-2包括开环模式的电压调节器350-2。因此，根据本公开实施例的基于事件变换频率的方案可以应用于各种类型的电压调节器，不管其为开环模式还是闭环模式。
以上参考图3至图11描述了根据本公开一些实施例的用于直流电压转换的装置210。 回到参考图2。如上文所提及的，处理器101和转换装置210可以通信。下面结合图2和图12来描述处理器101和转换装置210协作来进行频率变换的示例。图12示出了根据本公开一些实施例的频率变换的示例过程1200。
如图11所示，处理器101在1205中确定触发事件是否发生。如果触发事件发生，则处理器101在1210中生成第一频率变换信号，并且在1215中向转换装置210发送该第一频率变换信号。转换装置210在1220中响应于接收到第一频率变换信号，将周期信号的频率从第一频率升高到第二频率，并且在PWM模式下基于第二频率的周期信号将直流电压Vin转换为直流电压Vout。
该第一频率变换信号可以使能选择信号S1，从而将周期信号Vp的频率从第一频率升高到第二频率。应当理解，除图3所示的频率变换器310和电压调节器350之外，转换装置210可以包括图中未示出的其他部件。这样的部件可以是一转换部件或使能部件，其基于第一频率变换信号来使能选择信号S1，即产生选择信号S1。例如，这样的部件可以基于第一频率变换信号来生成图6至图8以及图11中所示的事件信号Vsoft_going或Vset_going，或者设置事件信号Vsoft_going或Vset_going的状态。
可选地，装置210可以确定触发事件的结束，并且基于触发事件的结束来使能选择信号S2。装置210可以包括用于确定触发事件的结束的检测部件。这样的检测部件可以通过检测装置210内部的电学参数(例如，电压、电流、功率)来确定触发事件是否结束。在确定触发事件结束的情况下，该检测部件可以使能选择信号S2，例如，将事件信号Vsoft_going或Vset_going归零。可选地，该检测部件可以耦合至上述使能部件。在确定触发事件结束的情况下，检测部件可以向使能部件发送信号，使能部件可以基于来自检测部件的信号，使选择信号S1无效同时使能选择信号S2。
在一些实施例中，触发事件可以包括转换装置210被启动。如果处理器101确定转换装置210被启动，则可以生成第一频率变换信号。相应地，转换装置210响应于接收到第一频率变换信号，将周期信号Vp的频率从第一频率升高到第二频率。附加地，在一些实施例中，转换装置210还可以检测启动是否结束，检测启动是否结束的操作可以由转换装置210内部的检测部件执行。该检测部件可以通过检测装置210内部的电学参数来确定启动是否结束。例如，如果检测到直流电压Vout从零变化到预设值，则可以确定启动结束。如果检测到启动结束，则转换装置210可以将周期信号Vp的频率从第二频率降低回第一频率。
例如，来自处理器101的第一频率变换信号可以使得图6至图8中所示的事件信号Vsoft_going有效。由此，多路选择器512可以基于选择信号S1，选择斜坡信号F2_Vramp作为周期信号Vramp。如果检测到启动结束，事件信号Vsoft_going可以被归零。例如，如果检测到直流电压Vout达到预设值，则上述检测部件或使能部件可以使事件信号Vsoft_going归零。在其他事件信号也归零的情况下，多路选择器512可以基于选择信号S2，选择斜坡信号F1_Vramp作为周期信号Vramp。
备选地或附加地，在一些实施例中，触发事件可以包括直流电压Vout的目标值被调整。如果处理器201确定直流电压Vout的目标值被调整，则可以生成第一频率变换信号。相应地，转换装置210响应于接收到第一频率变换信号，将周期信号Vp的频率从第一频率升高到第二频率。附加地，在一些实施例中，转换装置210还可以检测直流电压Vout。 例如，上述检测部件可以用于检测直流电压Vout。如果检测到直流电压Vout达到目标值，则转换装置210可以将周期信号Vp的频率从第二频率降低回第一频率。
例如，来自处理器101的第一频率变换信号可以使得图6至图8中所示的事件信号Vset_going有效。由此，多路选择器512可以基于选择信号S1，选择斜坡信号F2_Vramp作为周期信号Vramp。如果检测到直流电压Vout达到目标值，事件信号Vset_going可以被归零。例如，如果直流电压Vout达到目标值，则上述检测部件或使能部件可以使事件信号Vset_going归零。在其他事件信号也归零的情况下，多路选择器512可以基于选择信号S2，选择斜坡信号F1_Vramp作为周期信号Vramp。
附加地，在一些实施例中，转换装置210还可以基于内部检测到的触发事件来变换PWM模式下的周期信号的频率。转换装置210可以检测电学参数，该电学参数表示耦合至转换装置210的负载的电流(以下也可以称为负载电流)，该过程可被转换装置210内一检测部件执行(图中未示出)。在负载电流增大的情况下，转换装置210的输出电压将下降，输出电流将增大；在负载电流减小的情况下，转换装置210的输出电压将增大，输出电流将减小。因此，转换装置210可以检测输出电压、输出电流或输出功率。如果检测到该电学参数超出预定范围，转换装置210可以将周期信号Vp的频率从第一频率升高到第二频率。如果检测到该电学参数返回预定范围，转换装置210可以将周期信号Vp的频率从第二频率降低回第一频率。检测该电学参数是否超出预定范围的操作也可以由所述检测部件执行。因此，触发频率变换器提升周期信号的频率的事件可以来自处理器101，也可以来自转换装置210内部的检测部件，本实施例不做限定。
例如，如果检测到电学参数超出预定范围，转换装置210可以使得图6至图8中所示的事件信号Vdrop_going有效。由此，多路选择器512可以基于选择信号S1，选择斜坡信号F2_Vramp作为周期信号Vramp。如果检测到电学参数返回预定范围，事件信号Vdrop_going可以被归零。例如，如果检测到电学参数返回预定范围，则上述检测部件或使能部件可以使事件信号Vdrop_going归零。在其他事件信号也归零的情况下，多路选择器512可以基于选择信号S2，选择斜坡信号F1_Vramp作为周期信号Vramp。
如上文所提及的，在一些实施例中，可以基于负载的供电要求来调整转换装置210在基础PWM模式下的开关频率。图13示出了根据本公开一些实施例的电子设备200的示意性框图。如图13所示，除了处理器101和转换装置210之外，电子设备200还可以包括由转换装置210供电的负载1321-1、1321-2。在下文中，负载1321-1、1321-2也被统称为负载1321。负载1321可以与处理器101通信，并且处理器101可以控制负载1321的启用和禁用。负载1321可以是电子设备200中的任何部件，例如相机、存储器、其他处理器等。可选地，处理器101本身也可以被作为一个负载。在图13的实施例中，处理器101也由转换装置210供电。在一些实施例中，负载1321-1、1321-2中的一个或多个可以与处理器101位于同一芯片上，例如位于同一SoC上。此外，图13中所示的负载的数目仅是示意性，而无意限制本公开的范围。
以纹波电压为例，不同负载对纹波电压有不同级别的要求，而PWM模式下开关频率的高低影响直流电压Vout中的纹波电压的大小。开关频率越高，波纹电压越小。
如果处理器101确定耦合至转换装置210的负载(例如，负载1321-2)将要被启用，则处理器1001可以确定针对直流电压Vout的纹波电压约束条件。例如，该纹波电压约束 条件可以基于已经被启用的负载和将要被启用的负载对纹波电压的最高要求来确定。同样地，如果一个或多个负载被禁用，则处理器101可以基于仍被启用的负载对纹波电压的要求，来确定纹波电压约束条件。无论哪种情况，处理器101都可以将转换装置210在基础PWM模式下的开关频率配置为与该纹波电压约束条件相匹配的频率。
例如，如果处理器101确定负载的纹波电压约束条件，并且基于该纹波电压约束条件生成第二频率变换信号。处理器101将该第二频率变换信号发送给转换装置210。响应于接收到第二频率变换信号，转换装置210可以将周期信号的上述第一频率设置与多个预设频率中的一个频率，该频率与负载的纹波电压约束条件相匹配。可选地，装置210可以包括转换部件或使能部件，其基于第二频率变换信号来确定或使能选择信号S3，即设置选择信号S3的状态。确定或使能第三选择信号S3的使能部件和使能第一选择信号S1的使能部件可以是相同或不同的部件，本实施例对此不进行限定。例如，该转换部件或使能部件可以基于来自处理器101的第二频率变换信号来设置如图9和图11中所示的选择信号S3的状态。选择信号S3可以具有分别与多个预设频率相对应的多个状态(诸如多个电平)。例如，在具有两个预设频率的情况下，选择信号S3可以具有有效状态和归零状态。
作为示例，假设负载1321-2对纹波电压的要求高于负载1321-1，并且斜坡信号F4_Vramp的频率高于斜坡信号F5_Vramp。在负载1321-1和负载1321-2均被启用的情况下，或在负载1321-2被启用的情况下，选择信号S3的状态(例如，选择信号S3有效)将使得斜坡信号F4_Vramp被选择作为斜坡信号F1_Vramp。在未发生触发事件期间，转换装置210在PWM模式下的开关频率为斜坡信号F4_Vramp的频率。例如，转换装置210操作于图10所示的第四PWM模式下。在触发事件发生期间，转换装置210可以切换到第二PWM模式，即高频PWM模式。
在负载1321-1被启用而负载1321-2未被启用的情况下，选择信号S3的状态(例如，选择信号S3归零)将使得斜坡信号F5_Vramp被选择作为斜坡信号F1_Vramp。在未发生触发事件期间，转换装置210在PWM模式下的开关频率为斜坡信号F5_Vramp的频率。例如，转换装置210操作于图10所示的第五PWM模式下。在触发事件发生期间，转换装置210可以切换到第二PWM模式，即高频PWM模式。
应当理解，也可以基于负载的其他供电要求(例如，对瞬态响应速度的要求、对转换装置启动速度的要求等)来调整转换装置310在基础PWM模式下的开关频率。在这种实施例中，可以基于负载的供电要求来配置基础PWM模式下的开关频率。在负载的供电要求高的情况下，可以适当增大转换装置的开关频率，从而能够提高电压转换性能。在负载的供电要求低的情况下，可以适当降低转换装置的开关频率，从而能够进一步提高转换装置的供电效率。
处理器101可以包括任何合适类型的处理单元，包括但不限于CPU、GPU、基于人工智能的处理单元、微处理器、控制器、微控制器等。处理器101可以根据计算机软件程序来执行上文所描述的各种处理和动作。计算机软件程序可以被有形地包含于计算机可读介质。
计算机可读介质可以是计算机可读信号介质或计算机可读存储介质。计算机可读介质可以包括但不限于电子的、磁的、光学的、电磁的、红外的或半导体系统、装置或设备，或其任意合适的组合。计算机可读存储介质的更详细示例包括带有一根或多根导线的电气 连接、便携式计算机磁盘、硬盘、RAM、ROM、可擦除可编程只读存储器(erasable programmable read-only memory，EPROM)、闪存、光纤、便携式光盘只读存储器(Compact Disc Read-Only Memory，CD-ROM)、光存储设备、磁存储设备，或其任意合适的组合。
最后应说明的是：以上各实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述各实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (16)

  1. 一种用于直流电压转换的装置，包括：
    频率变换器，被配置为基于第一选择信号，将周期信号的频率从第一频率升高到第二频率；以及
    电压调节器，耦合至所述频率变换器，并且被配置为在脉冲宽度调制模式下，基于所述第二频率的所述周期信号，将第一直流电压转换为第二直流电压。
  2. 根据权利要求1所述的装置，其中所述频率变换器还被配置为：基于不同于所述第一选择信号的第二选择信号，将所述周期信号的频率从所述第二频率降低至所述第一频率；以及
    所述电压调节器还被配置为：在所述脉冲宽度调制模式下，基于所述第一频率的所述周期信号，将所述第一直流电压转换为所述第二直流电压。
  3. 根据权利要求1所述的装置，其中所述频率变换器还被配置为：基于不同于所述第一选择信号的第二选择信号，将所述周期信号的频率从所述第二频率降低至不同于所述第一频率的第三频率；以及
    所述电压调节器还被配置为：在所述脉冲宽度调制模式下，基于所述第三频率的所述周期信号，将所述第一直流电压转换为所述第二直流电压。
  4. 根据权利要求2或3所述的装置，其中所述第一选择信号和所述第二选择信号是同一指示信号的不同指示状态，所述第一选择信号用于表示至少一个事件的发生，所述第二选择信号用于表示所述至少一个事件的结束。
  5. 根据权利要求1所述的装置，还包括：
    选择信号确定电路，耦合至所述频率变换器，并且被配置为基于至少一个事件信号确定所述第一选择信号。
  6. 根据权利要求5所述的装置，其中所述至少一个事件信号包括如下至少一项：
    指示所述电压调节器被启动的第一事件信号，
    指示所述第二直流电压的目标值被调整的第二事件信号，或
    指示所述第二直流电压的实际值超出预定范围的第三事件信号。
  7. 根据权利要求5或6所述的装置，其中所述选择信号确定电路包括“或”门，所述“或”门的输入是所述至少一个事件信号，所述“或”门的输出是所述第一选择信号。
  8. 根据权利要求1至7中任一项所述的装置，其中所述频率变换器包括：
    第一多路选择器，被配置为基于所述第一选择信号，从具有所述第一频率的第一候选周期信号和具有所述第二频率的第二候选周期信号中选择所述第二候选周期信号作为所述周期信号。
  9. 根据权利要求8所述的装置，其中所述频率变换器还包括：
    第二多路选择器，耦合至所述第一多路选择器，并且被配置为基于表示负载的规格约束条件的第三选择信号，从具有第四频率的第三候选周期信号和具有第五频率的第四候选周期信号中选择一个候选周期信号作为所述第一候选周期信号，所述负载使用所述第二直流电压。
  10. 根据权利要求1所述的装置，其中所述电压调节器包括：
    误差放大器，被配置为基于参考信号和指示所述第二直流电压的反馈信号生成误差信号；
    比较器，耦合至所述误差放大器和所述频率变换器，并且被配置为基于所述周期信号和所述误差信号生成脉冲宽度调制信号；
    开关驱动电路，耦合至所述比较器，并且被配置为基于所述脉冲宽度调制信号生成开关驱动信号；以及
    开关电路，耦合至所述开关驱动电路，并且被配置为基于所述开关驱动信号将所述第一直流电压转换为所述第二直流电压。
  11. 根据权利要求10所述的装置，其中所述电压调节器还包括：
    环路补偿器，耦合至所述误差放大器和所述电压调节器的输出端，并且被配置为调节所述电压调节器形成的环路的零极点配置。
  12. 根据权利要求11所述的装置，其中所述环路补偿器包括：
    第一环路补偿电路，被配置为响应于不同于所述第一选择信号的第二选择信号调节所述零极点配置；以及
    第二环路补偿电路，被配置为响应于所述第一选择信号调节所述零极点配置。
  13. 一种电子设备，包括：
    处理器，被配置为响应于至少一个事件的发生来生成第一频率变换信号；以及
    用于直流电压转换的装置，耦合至所述处理器，并且被配置为：
    响应于接收到所述第一频率变换信号，将周期信号的频率从第一频率升高到第二频率，以及
    在脉冲宽度调制模式下，基于所述第二频率的所述周期信号，将第一直流电压转换为第二直流电压。
  14. 根据权利要求13所述的电子设备，其中所述至少一个事件包括如下至少一项：
    所述装置被启动，或
    所述第二直流电压的目标值被调整。
  15. 根据权利要求13或14所述的电子设备，其中所述装置还被配置为：
    响应于确定所述至少一个事件的结束，将所述周期信号的频率从所述第二频率降低至所述第一频率；以及
    在所述脉冲宽度调制模式下，基于所述第一频率的所述周期信号，将所述第一直流电压转换为所述第二直流电压。
  16. 根据权利要求13所述的电子设备，其中所述处理器还被配置为：
    确定负载的规格约束条件；以及
    基于所述规格约束条件，生成第二频率变换信号；并且
    所述装置还被配置为：响应于接收到所述第二频率变换信号，将所述周期信号的所述第一频率设置为多个预设频率中的一个频率。
PCT/CN2020/097283 2020-06-20 2020-06-20 用于直流电压转换的装置和电子设备 WO2021253457A1 (zh)

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