WO2021250063A3 - Leiterplatte mit einem eingebetteten halbleiterbauelement, verfahren zum herstellen einer leiterplatte - Google Patents

Leiterplatte mit einem eingebetteten halbleiterbauelement, verfahren zum herstellen einer leiterplatte Download PDF

Info

Publication number
WO2021250063A3
WO2021250063A3 PCT/EP2021/065398 EP2021065398W WO2021250063A3 WO 2021250063 A3 WO2021250063 A3 WO 2021250063A3 EP 2021065398 W EP2021065398 W EP 2021065398W WO 2021250063 A3 WO2021250063 A3 WO 2021250063A3
Authority
WO
WIPO (PCT)
Prior art keywords
circuit board
semiconductor component
contact region
contact
lead frame
Prior art date
Application number
PCT/EP2021/065398
Other languages
English (en)
French (fr)
Other versions
WO2021250063A2 (de
Inventor
Thomas Paesler
Original Assignee
Vitesco Technologies Germany Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Vitesco Technologies Germany Gmbh filed Critical Vitesco Technologies Germany Gmbh
Publication of WO2021250063A2 publication Critical patent/WO2021250063A2/de
Publication of WO2021250063A3 publication Critical patent/WO2021250063A3/de

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/145—Organic substrates, e.g. plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09118—Moulded substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10742—Details of leads
    • H05K2201/10886—Other details
    • H05K2201/10924—Leads formed from a punched metal foil
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0014—Shaping of the substrate, e.g. by moulding

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

Offenbart wird eine (gedruckte) Leiterplatte (LP) mit einem eingebetteten Halbleiterbauelement (HB), aufweisend: - einen Leadframe (LF), der auf einer ersten Oberfläche (OF1) einen Kontaktbereich (KB) aufweist; - das Halbleiterbauelement (HB), das auf dem Kontaktbereich (KB) aufliegt und mit dem Leadframe (LF) körperlich und elektrisch verbunden ist; - ein elektrisch isolierendes Leiterplattenträgermaterial; - wobei das Leiterplattenträgermaterial direkt auf dem Halbleiterbauelement (HB) und dem Leadframe (LF) aufliegt und somit eine elektrische Isolierschicht (IS) für das Halbleiterbauelement (HB) und den Leadframe (LF) bildet; - wobei der Kontaktbereich (KB) in der gleichen Ebene liegt wie der Restbereich (RB) der ersten Oberfläche (OF1), der sich seitlich des Kontaktbereichs (KB) befindet, sodass das Halbleiterbauelement (HB) gegenüber der ersten Oberfläche (OF1) vorstehend auf dem Kontaktbereich (KB) aufliegt. Ferner wird ein Verfahren zum Herstellen einer (gedruckten) Leiterplatte mit einem eingebetteten Halbleiterbauelement bereitgestellt.
PCT/EP2021/065398 2020-06-10 2021-06-09 Leiterplatte mit einem eingebetteten halbleiterbauelement, verfahren zum herstellen einer leiterplatte WO2021250063A2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102020207279.5 2020-06-10
DE102020207279.5A DE102020207279A1 (de) 2020-06-10 2020-06-10 Leiterplatte mit einem eingebetteten Halbleiterbauelement, Verfahren zum Herstellen einer Leiterplatte

Publications (2)

Publication Number Publication Date
WO2021250063A2 WO2021250063A2 (de) 2021-12-16
WO2021250063A3 true WO2021250063A3 (de) 2022-02-17

Family

ID=76444400

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2021/065398 WO2021250063A2 (de) 2020-06-10 2021-06-09 Leiterplatte mit einem eingebetteten halbleiterbauelement, verfahren zum herstellen einer leiterplatte

Country Status (2)

Country Link
DE (1) DE102020207279A1 (de)
WO (1) WO2021250063A2 (de)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0920058A2 (de) * 1997-11-25 1999-06-02 Matsushita Electric Industrial Co., Ltd. Modul mit Einbaukomponente und seine Herstellung
US20110127675A1 (en) * 2009-12-01 2011-06-02 Infineon Technologies Ag Laminate electronic device

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10320646A1 (de) 2003-05-07 2004-09-16 Infineon Technologies Ag Elektronisches Bauteil, sowie Systemträger und Nutzen zur Herstellung desselben
DE102013200652B4 (de) 2013-01-17 2014-07-24 Continental Automotive Gmbh Vorrichtung zum Schalten hoher Ströme
WO2014202282A1 (de) 2013-06-20 2014-12-24 Conti Temic Microelectronic Gmbh Leiterplatte

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0920058A2 (de) * 1997-11-25 1999-06-02 Matsushita Electric Industrial Co., Ltd. Modul mit Einbaukomponente und seine Herstellung
US20110127675A1 (en) * 2009-12-01 2011-06-02 Infineon Technologies Ag Laminate electronic device

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
SHARMA ANKIT BHUSHAN ET AL: "PCB embedded power package with reinforced top-side chip contacts", 2016 6TH ELECTRONIC SYSTEM-INTEGRATION TECHNOLOGY CONFERENCE (ESTC), IEEE, 13 September 2016 (2016-09-13), pages 1 - 5, XP033015868, DOI: 10.1109/ESTC.2016.7764706 *

Also Published As

Publication number Publication date
DE102020207279A1 (de) 2021-12-16
WO2021250063A2 (de) 2021-12-16

Similar Documents

Publication Publication Date Title
US9966327B2 (en) Lead frame, semiconductor device, method for manufacturing lead frame, and method for manufacturing semiconductor device
US10681801B2 (en) Mounting assembly with a heatsink
TW200509331A (en) Semiconductor chip package and method for making the same
TW200507218A (en) Layout circuit substrate, manufacturing method of layout circuit substrate, and circuit module
JP2013197209A (ja) 半導体装置及びその製造方法
US11310904B2 (en) Chip package and power module
US9362142B2 (en) Flip-chip electronic device and production method thereof
JP5974642B2 (ja) 電子部品モジュール及び製造方法
US11749589B2 (en) Module
US10166747B2 (en) Resin multilayer substrate and method of manufacturing the same
WO2021250063A3 (de) Leiterplatte mit einem eingebetteten halbleiterbauelement, verfahren zum herstellen einer leiterplatte
US10847473B2 (en) Printed circuit boards with anti-warping molding portions and related semiconductor packages and methods of fabricating
US12074100B2 (en) Flat no-lead package with surface mounted structure
US20180145397A1 (en) High-frequency module
TW200735315A (en) Package substrate and the manufacturing method making the same
JPH10117018A (ja) チップ型発光ダイオード
US20110228487A1 (en) Integrated Circuit Card
US12052821B2 (en) Stacked-layer board, electronic component module, and method of manufacturing stacked-layer board
US9141902B2 (en) Smart card module for a smart card
US20200329565A1 (en) Package carrier and package structure
US20140085845A1 (en) Thick-film hybrid circuit structure and method of manufacture the same
CN102024771A (zh) 封装结构以及封装方法
US20060175694A1 (en) Stacked structure of integrated circuits and method for manufacturing the same
JPH06244056A (ja) 半導体素子収納用パッケージ
JP2743524B2 (ja) 混成集積回路装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21732241

Country of ref document: EP

Kind code of ref document: A2

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21732241

Country of ref document: EP

Kind code of ref document: A2