WO2021249130A1 - 复用电路、方法、复用模组和显示装置 - Google Patents

复用电路、方法、复用模组和显示装置 Download PDF

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Publication number
WO2021249130A1
WO2021249130A1 PCT/CN2021/094234 CN2021094234W WO2021249130A1 WO 2021249130 A1 WO2021249130 A1 WO 2021249130A1 CN 2021094234 W CN2021094234 W CN 2021094234W WO 2021249130 A1 WO2021249130 A1 WO 2021249130A1
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Prior art keywords
control
multiplexing
nth
unit circuit
voltage
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PCT/CN2021/094234
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English (en)
French (fr)
Inventor
袁志东
李永谦
袁粲
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京东方科技集团股份有限公司
合肥京东方卓印科技有限公司
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Priority to US17/641,991 priority Critical patent/US11929022B2/en
Publication of WO2021249130A1 publication Critical patent/WO2021249130A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present disclosure relates to the field of multiplexing technology, and in particular to a multiplexing circuit, method, multiplexing module, and display device.
  • the current more mature technologies include liquid crystal display technology and active matrix OLED (organic light emitting diode) display technology.
  • OLED organic light emitting diode
  • the general technology of OLED display products is to excite spectra of various wavelengths through the direct recombination of electrons and holes to form patterns.
  • the display device formed by the OLED display technology has a fast response speed and can maximize the contrast. Therefore, the OLED display device is expected to become the mainstream display product of the next generation.
  • an OLED display device includes a display panel, a gate driving device, a data driver, and a timing controller.
  • the display panel includes data lines, gate lines, and pixels controlled by them.
  • the usual working mode is that when a gate drive signal is provided to the gate line, a row of pixels is provided with the data voltage of the data line. The pixels are based on the data voltage. The size emits light of different brightness.
  • the gate driving device is used to provide gate signals to the gate lines, and the gate driving device includes a separate gate driving integrated circuit or a panel gate driving circuit.
  • an embodiment of the present disclosure provides a multiplexing circuit, including N multiplexing unit circuits, N energy storage unit circuits, and N control unit circuits; N is an integer greater than 1;
  • the control terminal of the n-th multiplexing unit circuit is electrically connected to the n-th control terminal, the first terminal of the n-th multiplexing unit circuit is electrically connected to the n-th output data line, and the second terminal of the n-th multiplexing unit circuit is Electrically connected to the input data line, the n-th multiplexing unit circuit is used to turn on or disconnect the n-th output data line and the input data line under the control of the potential of the n-th control terminal connect;
  • the first end of the nth energy storage unit circuit is electrically connected to the nth clock signal end, the second end of the nth energy storage unit circuit is electrically connected to the nth control end, and the nth energy storage unit circuit is used for Controlling the potential of the n-th control terminal according to the n-th clock signal; the n-th clock signal terminal is used to provide the n-th clock signal;
  • the n-th control unit circuit is electrically connected to the control voltage terminal, the n-th control terminal, and the n-th switch control line, and is configured to turn on or off the n-th control terminal according to the control voltage signal and the n-th switch control signal Connection with the nth switch control line; the control voltage terminal is used to provide the control voltage signal; the nth switch control line is used to provide the nth switch control signal;
  • n is a positive integer less than or equal to N.
  • the nth energy storage unit circuit includes an nth storage capacitor
  • the first end of the nth storage capacitor is electrically connected to the nth clock signal end, and the second end of the nth storage capacitor is electrically connected to the nth control end.
  • the nth control unit circuit includes an nth control transistor
  • the control electrode of the nth control transistor is electrically connected to the control voltage terminal, the first electrode of the nth control transistor is electrically connected to the nth switch control line, and the second electrode of the nth control transistor is electrically connected to the The nth control terminal is electrically connected.
  • the nth control transistor is an n-type transistor, and the control voltage signal is a high voltage signal; or,
  • the nth control transistor is a p-type transistor, and the control voltage signal is a low voltage signal.
  • the n-th multiplexing unit circuit includes an n-th multiplexing transistor
  • the control electrode of the n-th multiplexing transistor is electrically connected to the n-th control terminal, the first electrode of the n-th multiplexing transistor is electrically connected to the n-th output data line, and the second electrode of the n-th multiplexing transistor is electrically connected to The input data line is electrically connected.
  • an embodiment of the present invention also provides a multiplexing method, which is applied to the above multiplexing circuit, and the multiplexing method includes:
  • the n-th multiplexing unit circuit conducts or disconnects the connection between the n-th output data line and the input data line under the control of the potential of the n-th control terminal;
  • the n-th energy storage unit circuit controls the potential of the n-th control terminal according to the n-th clock signal
  • the nth control unit circuit conducts or disconnects the connection between the nth control terminal and the nth switch control line according to the control voltage signal and the nth switch control signal;
  • N is an integer greater than 1, and n is a positive integer less than or equal to N.
  • the multiplexing method described in at least one embodiment of the present invention specifically includes:
  • the n-th switch control line provides the first voltage signal, the potential of the n-th clock signal changes from the second voltage to the first voltage, the n-th energy storage unit circuit changes the potential of the n-th control terminal accordingly, and the n-th multiplexing unit circuit is in the n-th Under the control of the potential of the control terminal, the connection between the nth output data line and the input data line is turned on; the nth control unit circuit disconnects the nth control terminal from the nth switch control signal according to the control voltage signal and the nth switch control signal. Connection between the nth switch control lines;
  • the potential of the n-th clock signal changes from the first voltage to the second voltage
  • the n-th switch control line provides the second voltage signal
  • the n-th energy storage unit circuit changes the potential of the n-th control terminal accordingly
  • the n-th control unit circuit is based on the control voltage signal
  • the n-th switch control signal to turn on the connection between the n-th control terminal and the n-th switch control line to control the discharge of the n-th control terminal, and the potential of the n-th multiplexing unit circuit at the n-th control terminal Under the control of, disconnect the connection between the nth output data line and the input data line.
  • the n-th control transistor included in the n-th control unit circuit is an n-type transistor
  • the n-th multiplexing transistor included in the n-th multiplexing unit circuit is an n-type transistor
  • the first voltage is a high voltage
  • the second voltage Is low voltage
  • the n-th control transistor is a p-type transistor
  • the n-th multiplexing transistor is a p-type transistor
  • the first voltage is a low voltage
  • the second voltage is a high voltage.
  • the embodiments of the present disclosure also provide a multiplexing module, including a plurality of the above multiplexing circuits.
  • an embodiment of the present disclosure also provides a display device, including the aforementioned multiplexing module.
  • FIG. 1 is a structural diagram of an n-th multiplexing unit circuit included in a multiplexing circuit according to at least one embodiment of the present disclosure
  • FIG. 2 is a circuit diagram of at least one embodiment of the nth multiplexing unit
  • FIG. 3 is a working sequence diagram of at least one embodiment of the nth multiplexing unit
  • FIG. 5 is a circuit diagram of a multiplexing circuit according to at least one embodiment of the present disclosure.
  • FIG. 6 is a working sequence diagram of the multiplexing circuit according to at least one embodiment of the present disclosure.
  • FIG. 7 is a circuit diagram of the multiplexing module according to at least one embodiment of the present disclosure.
  • the transistors used in all the embodiments of the present disclosure may be triodes, thin film transistors or field effect transistors or other devices with the same characteristics.
  • one of the poles is called the first pole, and the other pole is called the second pole.
  • the control electrode when the transistor is a triode, can be a base electrode, the first electrode can be a collector, and the second electrode can be an emitter; or, the control electrode can be a base.
  • the first electrode may be an emitter electrode, and the second electrode may be a collector electrode.
  • the control electrode when the transistor is a thin film transistor or a field effect transistor, the control electrode may be a gate, the first electrode may be a drain, and the second electrode may be a source; or The control electrode may be a gate, the first electrode may be a source, and the second electrode may be a drain.
  • the multiplexing circuit described in the embodiment of the present disclosure includes N multiplexing unit circuits, N energy storage unit circuits, and N control unit circuits; N is an integer greater than 1;
  • the control terminal of the n-th multiplexing unit circuit 11 is electrically connected to the n-th control terminal Qn, and the first terminal of the n-th multiplexing unit circuit 11 is electrically connected to the n-th output data line D1n.
  • the second terminal of the n-th multiplexing unit circuit 11 is electrically connected to the input data line D2, and the n-th multiplexing unit circuit 11 is used to turn on or off the n-th control terminal Qn under the control of the potential of the n-th control terminal Qn.
  • the first terminal of the n-th energy storage unit circuit 12 is electrically connected to the n-th clock signal terminal Kn, the second terminal of the n-th energy storage unit circuit 12 is electrically connected to the n-th control terminal Qn, and the n-th energy storage unit circuit 12 is electrically connected to the n-th control terminal Qn.
  • the energy unit circuit 12 is used to control the potential of the n-th control terminal Qn according to the n-th clock signal; the n-th clock signal terminal Kn is used to provide the n-th clock signal;
  • the n-th control unit circuit 13 is electrically connected to the control voltage terminal V0, the n-th control terminal Qn, and the n-th switch control line Sn, respectively, for turning on or off the control voltage signal and the n-th switch control signal.
  • the connection between the nth control terminal Qn and the nth switch control line Sn; the control voltage terminal V0 is used to provide the control voltage signal; the nth switch control line Sn is used to provide the nth switch control signal;
  • n is a positive integer less than or equal to N.
  • the input data line is used to provide an n-th input data voltage.
  • the multiplexing circuit can further increase or decrease according to the nth clock signal through the nth energy storage unit circuit and the nth control unit circuit when the nth switch control line provides the first voltage signal.
  • the potential of the nth control terminal improves the output capability of the nth multiplexing unit circuit.
  • the multiplexing circuit when the transistor included in the n-th multiplexing unit circuit is an n-type transistor, the multiplexing circuit can further increase the potential of the n-th control terminal to increase the n-th multiplexing unit circuit. Output capacity;
  • the multiplexing circuit can further reduce the potential of the n-th control terminal to improve the output capability of the n-th multiplexing unit circuit.
  • the first voltage signal when the transistor included in the n-th multiplexing unit circuit is an n-type transistor, the first voltage signal may be a high voltage signal, but is not limited to this;
  • the first voltage signal when the transistor included in the n-th multiplexing unit circuit is a p-type transistor, the first voltage signal may be a low voltage signal, but is not limited to this.
  • the n-th switch control line Sn provides the first voltage signal
  • the potential of the n-th clock signal changes from the second voltage to the first voltage
  • the n-th energy storage unit circuit 12 changes the potential of the n-th control terminal Qn accordingly
  • the n-th multiplexing unit Under the control of the potential of the n-th control terminal Qn, the circuit 11 turns on the connection between the n-th output data line D1n and the input data line D2; the n-th control unit circuit 13 turns off according to the control voltage signal and the n-th switch control signal. Open the connection between the nth control terminal Qn and the nth switch control line Sn;
  • the potential of the nth clock signal changes from the first voltage to the second voltage
  • the nth switch control line Sn provides the second voltage signal
  • the nth energy storage unit circuit 12 changes the potential of the nth control terminal Qn accordingly
  • the nth control unit circuit 13 According to the control voltage signal and the n-th switch control signal, the connection between the n-th control terminal Qn and the n-th switch control line Sn is turned on to control the discharge of the n-th control terminal Qn, and the n-th multiplexing
  • the unit circuit 11 disconnects the connection between the n-th output data line D1n and the input data line D2 under the control of the potential of the n-th control terminal Qn.
  • the second voltage signal when the transistor included in the n-th multiplexing unit circuit is an n-type transistor, the second voltage signal may be a low voltage, but is not limited to this;
  • the second voltage when the transistor included in the n-th multiplexing unit circuit is a p-type transistor, the second voltage may be a high voltage, but it is not limited thereto.
  • the n-th energy storage unit circuit may include an n-th storage capacitor
  • the first end of the nth storage capacitor is electrically connected to the nth clock signal end, and the second end of the nth storage capacitor is electrically connected to the nth control end.
  • the nth control unit circuit includes an nth control transistor
  • the control electrode of the nth control transistor is electrically connected to the control voltage terminal, the first electrode of the nth control transistor is electrically connected to the nth switch control line, and the second electrode of the nth control transistor is electrically connected to the The nth control terminal is electrically connected.
  • the nth control transistor is an n-type transistor, and the control voltage signal is a high voltage signal; or,
  • the nth control transistor is a p-type transistor, and the control voltage signal is a low voltage signal.
  • the n-th multiplexing unit circuit includes an n-th multiplexing transistor
  • the control electrode of the n-th multiplexing transistor is electrically connected to the n-th control terminal, the first electrode of the n-th multiplexing transistor is electrically connected to the n-th output data line, and the second electrode of the n-th multiplexing transistor is electrically connected to The input data line is electrically connected.
  • the n-th energy storage unit circuit 12 includes an n-th storage capacitor Cn;
  • the first terminal of the n-th storage capacitor Cn is electrically connected to the n-th clock signal terminal Kn, and the second terminal of the n-th storage capacitor Cn is electrically connected to the n-th control terminal Qn;
  • the nth control unit circuit 13 includes an nth control transistor Tdn;
  • the control electrode of the nth control transistor Tdn is electrically connected to the control voltage terminal V0, the source electrode of the nth control transistor Tdn is electrically connected to the nth switch control line Sn, and the drain electrode of the nth control transistor Tdn Electrically connected to the nth control terminal Qn;
  • the n-th multiplexing unit circuit 11 includes an n-th multiplexing transistor Twn;
  • the gate of the n-th multiplexing transistor Twn is electrically connected to the n-th control terminal Qn, the source of the n-th multiplexing transistor Twn is electrically connected to the n-th output data line D1n, and the n-th multiplexing transistor Twn The drain is electrically connected to the input data line D2.
  • control voltage provided by the control voltage terminal V0 may be a high DC voltage, but it is not limited thereto. In actual operation, the voltage value of the DC high voltage should not be higher than the high voltage value of the nth switch control signal on the nth switch control line.
  • the high voltage value of the nth switch control signal refers to the voltage value of the nth switch control signal when the nth switch control signal is a high voltage signal.
  • all the transistors are n-type thin film transistors, but not limited to this.
  • the transistor may be an n-type transistor or a p-type transistor.
  • Sn provides a high voltage
  • the potential of the nth clock signal provided by Kn changes from a low voltage to a high voltage. Due to the existence of Cn, the potential of Qn is coupled to a higher voltage.
  • the gate voltage of Tdn is consistent with the high voltage provided by Sn.
  • Tdn is in the off state, and the higher potential of Qn can be maintained to increase the driving ability of Twn.
  • Twn is on, and D2 provides the nth input data voltage to D1n.
  • the rising edge time of the output data voltage on D1n is reduced, that is, the nth input data voltage can be transmitted to D1n faster;
  • the potential of the nth clock signal provided by Kn changes from a high voltage to a low voltage, Sn provides a low voltage signal, and Cn pulls down the potential of Qn accordingly to control Tdn to turn on and discharge the potential of Qn, and Twn to turn off to disconnect D1n The connection with D2.
  • FIG. 4 is a simulation diagram of the working sequence of at least one embodiment of the multiplexing circuit shown in FIG. 2 of the present disclosure. After simulation, it can be seen that the rise time of the output data voltage on D1n is 0.056us, while the output of the existing multiplexing circuit The rise time of the data voltage is 0.77us.
  • N is equal to 2.
  • the multiplexing circuit described in at least one embodiment of the present disclosure includes a first multiplexing unit circuit, a first energy storage unit circuit, a first control unit circuit, a second multiplexing unit circuit, A second energy storage unit circuit and a second control unit circuit;
  • the first energy storage unit circuit includes a first storage capacitor C1;
  • the first terminal of the first storage capacitor C1 is electrically connected to the first clock signal terminal K1, and the second terminal of the first storage capacitor C1 is electrically connected to the first control terminal Q1;
  • the first control unit circuit includes a first control transistor Td1;
  • the gate of the first control transistor Td1 is electrically connected to the control voltage terminal V0, the source of the first control transistor Td1 is electrically connected to the first switch control line S1, and the drain of the first control transistor Td1 Electrically connected to the first control terminal Q1;
  • the first multiplexing unit circuit includes a first multiplexing transistor Tw1;
  • the gate of the first multiplexing transistor Tw1 is electrically connected to the first control terminal Q1, the source of the first multiplexing transistor Tw1 is electrically connected to the first output data line D11, and the first multiplexing transistor Tw1 The drain is electrically connected to the input data line D2;
  • the second energy storage unit circuit includes a second storage capacitor C2;
  • the first terminal of the second storage capacitor C2 is electrically connected to the second clock signal terminal K2, and the second terminal of the second storage capacitor C2 is electrically connected to the second control terminal Q2;
  • the second control unit circuit includes a second control transistor Td2;
  • the gate of the second control transistor Td2 is electrically connected to the high voltage terminal, the source of the second control transistor Td2 is electrically connected to the second switch control line S2, and the drain of the second control transistor Td2 is electrically connected to the The second control terminal Q2 is electrically connected;
  • the second multiplexing unit circuit includes a second multiplexing transistor Tw2;
  • the gate of the second multiplexing transistor Tw2 is electrically connected to the second control terminal Q2, the source of the second multiplexing transistor Tw2 is electrically connected to the second output data line D12, and the second multiplexing transistor Tw2 The drain is electrically connected to the input data line D2.
  • all the transistors are n-type thin film transistors, but not limited to this.
  • the first switch control line S1 is used to provide a first switch control signal
  • the second switch control line S2 is used to provide a second switch control signal
  • control voltage provided by the control voltage terminal V0 may be a high DC voltage, but is not limited to this.
  • the voltage value of the direct current high voltage should not be higher than the high voltage value of the first switch control signal, and the voltage value of the direct current high voltage should not be higher than the high voltage value of the second switch control signal.
  • S1 provides a high voltage
  • the potential of the first clock signal provided by K1 changes from a low voltage to a high voltage. Due to the existence of C1, the potential of Q1 is coupled to a higher voltage, and the gate voltage of Td1 is The high voltage provided by S1 is the same.
  • the gate-source voltage of Td1 is close to 0V, Td1 is in the off state, and the higher potential of Q1 can be maintained to improve the driving ability of Tw1.
  • Tw1 is turned on, and D2 provides the first input data voltage to D11;
  • S2 provides a low voltage
  • K2 provides a low voltage
  • Td2 is turned on
  • Q2 is a low voltage
  • Tw2 is turned off to disconnect the connection between D12 and D2;
  • S2 provides a high voltage
  • the potential of the second clock signal provided by K2 changes from a low voltage to a high voltage. Due to the presence of C2, the potential of Q2 is coupled to a higher voltage, and the gate voltage of Td2 is The high voltage provided by S2 is the same. At this time, the gate-source voltage of Td2 is close to 0V, Td2 is in the off state, and the higher potential of Q2 can be maintained to improve the driving ability of Tw2.
  • Tw2 is turned on, and D2 provides the second input data voltage to D12;
  • S1 provides a low voltage
  • K1 provides a low voltage
  • Td1 is turned on
  • the potential of Q1 is a low voltage
  • Tw1 is turned off to disconnect the connection between D11 and D2.
  • the multiplexing method described in the embodiment of the present disclosure is applied to the aforementioned multiplexing circuit, and the multiplexing method includes:
  • the n-th multiplexing unit circuit conducts or disconnects the connection between the n-th output data line and the input data line under the control of the potential of the n-th control terminal;
  • the n-th energy storage unit circuit controls the potential of the n-th control terminal according to the n-th clock signal
  • the nth control unit circuit conducts or disconnects the connection between the nth control terminal and the nth switch control line according to the control voltage signal and the nth switch control signal;
  • N is an integer greater than 1, and n is a positive integer less than or equal to N.
  • the nth energy storage unit circuit and the nth control unit can be used to further increase or decrease according to the nth clock signal.
  • the potential of the nth control terminal improves the output capability of the nth multiplexing unit circuit.
  • the multiplexing method may specifically include:
  • the n-th switch control line provides the first voltage signal, the potential of the n-th clock signal changes from the second voltage to the first voltage, the n-th energy storage unit circuit changes the potential of the n-th control terminal accordingly, and the n-th multiplexing unit circuit is in the n-th Under the control of the potential of the control terminal, the connection between the nth output data line and the input data line is turned on; the nth control unit circuit disconnects the nth control terminal from the nth switch control signal according to the control voltage signal and the nth switch control signal. Connection between the nth switch control lines;
  • the potential of the n-th clock signal changes from the first voltage to the second voltage
  • the n-th switch control line provides the second voltage signal
  • the n-th energy storage unit circuit changes the potential of the n-th control terminal accordingly
  • the n-th control unit circuit is based on the control voltage signal
  • the n-th switch control signal to turn on the connection between the n-th control terminal and the n-th switch control line to control the discharge of the n-th control terminal, and the potential of the n-th multiplexing unit circuit at the n-th control terminal Under the control of, disconnect the connection between the nth output data line and the input data line.
  • the n-th control transistor included in the n-th control unit circuit is an n-type transistor
  • the n-th multiplexing transistor included in the n-th multiplexing unit circuit is an n-type transistor
  • the first voltage is a high voltage
  • the second voltage Is low voltage
  • the n-th control transistor is a p-type transistor
  • the n-th multiplexing transistor is a p-type transistor
  • the first voltage is a low voltage
  • the second voltage is a high voltage.
  • the multiplexing module in the embodiment of the present disclosure includes a plurality of the aforementioned multiplexing circuits.
  • the multiplexing module described in at least one embodiment of the present disclosure includes two multiplexing circuits described in at least one embodiment of the present disclosure as an example;
  • the multiplexing module includes a first multiplexing circuit and a second multiplexing circuit
  • the first multiplexing circuit includes a first multiplexing unit circuit, a first energy storage unit circuit, a first control unit circuit, a second multiplexing unit circuit, a second energy storage unit circuit, and a second control unit circuit;
  • the first energy storage unit circuit includes a first first storage capacitor C11;
  • the first terminal of C11 is electrically connected to the first clock signal terminal K1, and the second terminal of C11 is electrically connected to the first first control terminal Q11;
  • the first control unit circuit includes a first first control transistor Td11;
  • the gate of Td11 is electrically connected to the control voltage terminal V0, the source of Td1 is electrically connected to the first switch control line S1, and the drain of Td1 is electrically connected to Q11;
  • the first multiplexing unit circuit includes a first first multiplexing transistor Tw11;
  • the gate of Tw11 is electrically connected to Q11, the source of Tw11 is electrically connected to the first first output data line D111, and the drain of Tw11 is electrically connected to the first input data line D21;
  • the second energy storage unit circuit includes a first second storage capacitor C12;
  • the first terminal of C12 is electrically connected to the second clock signal terminal K2, and the second terminal of C12 is electrically connected to the first second control terminal Q12;
  • the second control unit circuit includes a first and second control transistor Td12;
  • Td12 The gate of Td12 is electrically connected to the high voltage terminal, the source of Td12 is electrically connected to the second switch control line S2, and the drain of Td12 is electrically connected to Q12;
  • the second multiplexing unit circuit includes a first second multiplexing transistor Tw12;
  • the gate of Tw12 is electrically connected to Q12, the source of Tw12 is electrically connected to the first second output data line D112, and the drain of Tw12 is electrically connected to the first input data line D21;
  • the second multiplexing circuit includes a third multiplexing unit circuit, a third energy storage unit circuit, a third control unit circuit, a fourth multiplexing unit circuit, a fourth energy storage unit circuit, and a fourth control unit circuit;
  • the third energy storage unit circuit includes a second first storage capacitor C21;
  • the first terminal of C21 is electrically connected to the first clock signal terminal K1, and the second terminal of C21 is electrically connected to the second first control terminal Q21;
  • the third control unit circuit includes a second first control transistor Td21;
  • Td21 is electrically connected to the control voltage terminal V0, the source of Td2 is electrically connected to the first switch control line S1, and the drain of Td21 is electrically connected to Q21;
  • the third multiplexing unit circuit includes a second first multiplexing transistor Tw21;
  • the gate of Tw21 is electrically connected to Q21, the source of Tw21 is electrically connected to the second first output data line D121, and the drain of Tw21 is electrically connected to the second input data line D22;
  • the fourth energy storage unit circuit includes a second second storage capacitor C22;
  • the first terminal of C22 is electrically connected to the second clock signal terminal K2, and the second terminal of C22 is electrically connected to the second second control terminal Q22;
  • the second control unit circuit includes a second second control transistor Td22;
  • the gate of Td22 is electrically connected to the high voltage terminal, the source of Td22 is electrically connected to the second switch control line S2, and the drain of Td22 is electrically connected to Q22;
  • the fourth multiplexing unit circuit includes a second second multiplexing transistor Tw22;
  • the gate of Tw22 is electrically connected to Q22, the source of Tw22 is electrically connected to the second second output data line D122, and the drain of Tw22 is electrically connected to the second input data line D22.
  • all the transistors are n-type thin film transistors, but not limited to this.
  • the first switch control line S1 is used to provide a first switch control signal
  • the second switch control line S2 is used to provide a second switch control signal
  • control voltage provided by the control voltage terminal V0 may be a high DC voltage, but is not limited to this.
  • the voltage value of the direct current high voltage should not be higher than the high voltage value of the first switch control signal, and the voltage value of the direct current high voltage should not be higher than the high voltage value of the second switch control signal.
  • the display device described in the embodiment of the present disclosure includes the multiplexing module described in the embodiment of the present disclosure.
  • the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator.
  • a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator.

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Abstract

一种复用电路、方法、复用模组和显示装置，复用电路包括N个复用单元电路、N个储能单元电路和N个控制单元电路；N为大于1的整数；第n复用单元电路(11)在第n控制端的电位的控制下，导通或断开第n输出数据线与输入数据线之间的连接；第n储能单元电路(12)根据第n时钟信号，控制第n控制端的电位；第n控制单元电路(13)根据控制电压信号和第n开关控制信号，导通或断开第n控制端与第n开关控制线之间的连接；n为小于或等于N的正整数。复用方法与复用电路对应，复用模组包括多个复用电路，显示装置包括复用模组。复用电路能够提高复用电路的输出能力。

Description

复用电路、方法、复用模组和显示装置
相关申请的交叉引用
本申请主张在2020年6月10日在中国提交的中国专利申请号No.202010523269.3的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及复用技术领域，尤其涉及一种复用电路、方法、复用模组和显示装置。
背景技术
在显示领域，目前较成熟的技术有液晶显示技术及主动矩阵式OLED(有机发光二极管)显示技术。在整套显示系统中，OLED显示产品一般技术为通过借助电子与空穴直接的复合，激发出各种波长的光谱，从而形成图形。通过OLED显示技术形成的显示装置具有快速的响应速度，同时可以达到对比度最大化，因此OLED显示装置有望成为下一代显示主流产品。
一般地，OLED显示装置包括：显示面板、栅极驱动装置、数据驱动器和时序控制器。其中显示面板包括：数据线、栅线以及通过它们控制的像素，通常工作方式为当栅极驱动信号被提供至栅线时某一行像素则被提供给数据线的数据电压，像素根据数据电压的大小发出不同亮度的光。栅极驱动装置用于向栅极线提供栅极信号，栅极驱动装置包括单独的栅极驱动集成电路或者面板栅极驱动电路。
在高PPI(Pixels Per Inch，像素密度)显示时，由于像素个数变多，信号线数量随着增多，由于模组绑定工艺能力的上限存在，故COF(Chip On Film，覆晶薄膜)上的Bonding PAD Pitch(绑定焊盘间距)不可能无限制缩小用以满足高PPI显示。由于复用电路可以有效减少COF上信号数量，因此在高PPI显示时，采用复用电路也变得频繁。但是，随着像素数量的增加，显示面板内信号线之间的cross(交叉)也变得密集，信号线的RC Loading(RC负载)也随之增大，复用电路本身又具有限流缺点存在，现有的复用电路的输出能 力低。
发明内容
在一个方面中，本公开实施例提供了一种复用电路，包括N个复用单元电路、N个储能单元电路和N个控制单元电路；N为大于1的整数；
第n复用单元电路的控制端与第n控制端电连接，所述第n复用单元电路的第一端与第n输出数据线电连接，所述第n复用单元电路的第二端与输入数据线电连接，所述第n复用单元电路用于在所述第n控制端的电位的控制下，导通或断开所述第n输出数据线与所述输入数据线之间的连接；
第n储能单元电路的第一端与第n时钟信号端电连接，所述第n储能单元电路的第二端与所述第n控制端电连接，所述第n储能单元电路用于根据第n时钟信号，控制第n控制端的电位；所述第n时钟信号端用于提供所述第n时钟信号；
第n控制单元电路分别与控制电压端、所述第n控制端和第n开关控制线电连接，用于根据控制电压信号和第n开关控制信号，导通或断开所述第n控制端与所述第n开关控制线之间的连接；所述控制电压端用于提供所述控制电压信号；所述第n开关控制线用于提供所述第n开关控制信号；
n为小于或等于N的正整数。
可选的，所述第n储能单元电路包括第n存储电容；
第n存储电容的第一端与第n时钟信号端电连接，所述第n存储电容的第二端与所述第n控制端电连接。
可选的，所述第n控制单元电路包括第n控制晶体管；
所述第n控制晶体管的控制极与所述控制电压端电连接，所述第n控制晶体管的第一极与所述第n开关控制线电连接，所述第n控制晶体管的第二极与所述第n控制端电连接。
可选的，所述第n控制晶体管为n型晶体管，所述控制电压信号为高电压信号；或者，
所述第n控制晶体管为p型晶体管，所述控制电压信号为低电压信号。
可选的，第n复用单元电路包括第n复用晶体管；
所述第n复用晶体管的控制极与第n控制端电连接，所述第n复用晶体管的第一极与第n输出数据线电连接，所述第n复用晶体管的第二极与输入数据线电连接。
在第二个方面中，本发明实施例还提供了一种复用方法，应用于上述的复用电路，所述复用方法包括：
第n复用单元电路在第n控制端的电位的控制下，导通或断开第n输出数据线与输入数据线之间的连接；
第n储能单元电路根据第n时钟信号，控制第n控制端的电位；
第n控制单元电路根据控制电压信号和第n开关控制信号，导通或断开所述第n控制端与所述第n开关控制线之间的连接；
N为大于1的整数，n为小于或等于N的正整数。
可选的，本发明至少一实施例所述的复用方法具体包括：
第n开关控制线提供第一电压信号，第n时钟信号的电位由第二电压变为第一电压，第n储能单元电路相应改变第n控制端的电位，第n复用单元电路在第n控制端的电位的控制下，导通第n输出数据线与输入数据线之间的连接；第n控制单元电路根据控制电压信号和第n开关控制信号，断开所述第n控制端与所述第n开关控制线之间的连接；
第n时钟信号的电位由第一电压变为第二电压，第n开关控制线提供第二电压信号，第n储能单元电路相应改变第n控制端的电位，第n控制单元电路根据控制电压信号和第n开关控制信号，导通所述第n控制端与所述第n开关控制线之间的连接，以控制对第n控制端进行放电，第n复用单元电路在第n控制端的电位的控制下，断开第n输出数据线与输入数据线之间的连接。
可选的，所述第n控制单元电路包括的第n控制晶体管为n型晶体管，第n复用单元电路包括的第n复用晶体管为n型晶体管，第一电压为高电压，第二电压为低电压；或者，
所述第n控制晶体管为p型晶体管，所述第n复用晶体管为p型晶体管，第一电压为低电压，第二电压为高电压。
在第三个方面中，本公开实施例还提供了一种复用模组，包括多个上述 的复用电路。
在第四个方面中，本公开实施例还提供了一种显示装置，包括上述的复用模组。
附图说明
图1是本发明公开至少一实施例所述的复用电路包括的第n复用单元电路的结构图；
图2是所述第n复用单元的至少一实施例的电路图；
图3是所述第n复用单元的至少一实施例的工作时序图；
图4是所述第n复用单元的至少一实施例的仿真工作时序图；
图5是本公开至少一实施例所述的复用电路的电路图；
图6是本公开至少一实施例所述的复用电路的工作时序图；
图7是本公开至少一实施例所述的复用模组的电路图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开所有实施例中采用的晶体管均可以为三极管、薄膜晶体管或场效应管或其他特性相同的器件。在本公开实施例中，为区分晶体管除控制极之外的两极，将其中一极称为第一极，另一极称为第二极。
在实际操作时，当所述晶体管为三极管时，所述控制极可以为基极，所述第一极可以为集电极，所述第二极可以发射极；或者，所述控制极可以为基极，所述第一极可以为发射极，所述第二极可以集电极。
在实际操作时，当所述晶体管为薄膜晶体管或场效应管时，所述控制极可以为栅极，所述第一极可以为漏极，所述第二极可以为源极；或者，所述控制极可以为栅极，所述第一极可以为源极，所述第二极可以为漏极。
本公开实施例所述的复用电路包括N个复用单元电路、N个储能单元电 路和N个控制单元电路；N为大于1的整数；
如图1所示，第n复用单元电路11的控制端与第n控制端Qn电连接，所述第n复用单元电路11的第一端与第n输出数据线D1n电连接，所述第n复用单元电路11的第二端与输入数据线D2电连接，所述第n复用单元电路11用于在所述第n控制端Qn的电位的控制下，导通或断开所述第n输出数据线D1n与所述输入数据线D2之间的连接；
第n储能单元电路12的第一端与第n时钟信号端Kn电连接，所述第n储能单元电路12的第二端与所述第n控制端Qn电连接，所述第n储能单元电路12用于根据第n时钟信号，控制第n控制端Qn的电位；所述第n时钟信号端Kn用于提供所述第n时钟信号；
第n控制单元电路13分别与控制电压端V0、所述第n控制端Qn和第n开关控制线Sn电连接，用于根据控制电压信号和第n开关控制信号，导通或断开所述第n控制端Qn与所述第n开关控制线Sn之间的连接；所述控制电压端V0用于提供所述控制电压信号；所述第n开关控制线Sn用于提供所述第n开关控制信号；
n为小于或等于N的正整数。
在本公开至少一实施例中，所述输入数据线用于提供第n输入数据电压。
本公开至少一实施例所述的复用电路能够在第n开关控制线提供第一电压信号时，通过第n储能单元电路和第n控制单元电路，根据第n时钟信号，进一步提升或降低第n控制端的电位，提高第n复用单元电路的输出能力。
在本公开至少一实施例中，当所述第n复用单元电路包括的晶体管为n型晶体管时，所述复用电路能够进一步拉升第n控制端的电位，以提高第n复用单元电路的输出能力；
当所述第n复用单元电路包括的晶体管为p型晶体管时，所述复用电路能够进一步降低第n控制端的电位，以提高第n复用单元电路的输出能力。
在本公开至少一实施例中，当所述第n复用单元电路包括的晶体管为n型晶体管时，所述第一电压信号可以为高电压信号，但不以此为限；
在本公开至少一实施例中，当所述第n复用单元电路包括的晶体管为p型晶体管时，所述第一电压信号可以为低电压信号，但不以此为限。
本公开至少一实施例所述的复用电路在工作时，
第n开关控制线Sn提供第一电压信号，第n时钟信号的电位由第二电压变为第一电压，第n储能单元电路12相应改变第n控制端Qn的电位，第n复用单元电路11在第n控制端Qn的电位的控制下，导通第n输出数据线D1n与输入数据线D2之间的连接；第n控制单元电路13根据控制电压信号和第n开关控制信号，断开所述第n控制端Qn与所述第n开关控制线Sn之间的连接；
第n时钟信号的电位由第一电压变为第二电压，第n开关控制线Sn提供第二电压信号，第n储能单元电路12相应改变第n控制端Qn的电位，第n控制单元电路13根据控制电压信号和第n开关控制信号，导通所述第n控制端Qn与所述第n开关控制线Sn之间的连接，以控制对第n控制端Qn进行放电，第n复用单元电路11在第n控制端Qn的电位的控制下，断开第n输出数据线D1n与输入数据线D2之间的连接。
在本公开至少一实施例中，当所述第n复用单元电路包括的晶体管为n型晶体管时，所述第二电压信号可以为低电压，但不以此为限；
在本公开至少一实施例中，当所述第n复用单元电路包括的晶体管为p型晶体管时，所述第二电压可以为高电压，但不以此为限。
在具体实施时，所述第n储能单元电路可以包括第n存储电容；
第n存储电容的第一端与第n时钟信号端电连接，所述第n存储电容的第二端与所述第n控制端电连接。
可选的，所述第n控制单元电路包括第n控制晶体管；
所述第n控制晶体管的控制极与所述控制电压端电连接，所述第n控制晶体管的第一极与所述第n开关控制线电连接，所述第n控制晶体管的第二极与所述第n控制端电连接。
在本公开至少一实施例中，所述第n控制晶体管为n型晶体管，所述控制电压信号为高电压信号；或者，
所述第n控制晶体管为p型晶体管，所述控制电压信号为低电压信号。
可选的，第n复用单元电路包括第n复用晶体管；
所述第n复用晶体管的控制极与第n控制端电连接，所述第n复用晶体 管的第一极与第n输出数据线电连接，所述第n复用晶体管的第二极与输入数据线电连接。
如图2所示，在图1所示的复用电路的至少一实施例的基础上，
所述第n储能单元电路12包括第n存储电容Cn；
第n存储电容Cn的第一端与第n时钟信号端Kn电连接，所述第n存储电容Cn的第二端与所述第n控制端Qn电连接；
所述第n控制单元电路13包括第n控制晶体管Tdn；
所述第n控制晶体管Tdn的控制极与控制电压端V0电连接，所述第n控制晶体管Tdn的源极与所述第n开关控制线Sn电连接，所述第n控制晶体管Tdn的漏极与所述第n控制端Qn电连接；
第n复用单元电路11包括第n复用晶体管Twn；
所述第n复用晶体管Twn的栅极与第n控制端Qn电连接，所述第n复用晶体管Twn的源极与第n输出数据线D1n电连接，所述第n复用晶体管Twn的漏极与输入数据线D2电连接。
在图2所示的至少一实施例中，所述控制电压端V0提供的控制电压可以为直流高电压，但不以此为限。在实际操作时，所述直流高电压的电压值应不高于第n开关控制线上的第n开关控制信号的高电压值。
在本公开至少一实施例中，所述第n开关控制信号的高电压值指的是：当第n开关控制信号为高电压信号时，所述第n开关控制信号的电压值。
在图2所示的复用电路的至少一实施例中，所有的晶体管都为n型薄膜晶体管，但不以此为限。在实际操作时，所述晶体管可以为n型晶体管，也可以为p型晶体管。
如图3所示，本公开如图2所示的复用电路的至少一实施例在工作时，
Sn提供高电压，Kn提供的第n时钟信号的电位由低电压变为高电压，由于Cn的存在，Qn的电位耦合至更高电压，Tdn的栅极电压与Sn提供的高电压一致，此时Tdn的栅源电压接近于0V，Tdn处于关闭状态，Qn的更高电位能够保持，以能够提升Twn的驱动能力，Twn打开，D2提供第n输入数据电压至D1n，当所述第n输入数据电压为高电压时，D1n上的输出数据电压的上升沿时间降低，也即，所述第n输入数据电压能够更快的传送至D1n；
Kn提供的第n时钟信号的电位由高电压变为低电压，Sn提供低电压信号，Cn相应拉低Qn的电位，以控制Tdn打开，对Qn的电位进行放电，Twn关闭，以断开D1n与D2之间的连接。
图4是本公开如图2所示的复用电路的至少一实施例工作时序仿真图，经过仿真可知，D1n上的输出数据电压的上升时间为0.056us，而现有的复用电路的输出数据电压的上升时间为0.77us。
如图5所示，N等于2，本公开至少一实施例所述的复用电路包括第一复用单元电路、第一储能单元电路、第一控制单元电路、第二复用单元电路、第二储能单元电路和第二控制单元电路；
所述第一储能单元电路包括第一存储电容C1；
第一存储电容C1的第一端与第一时钟信号端K1电连接，所述第一存储电容C1的第二端与第一控制端Q1电连接；
所述第一控制单元电路包括第一控制晶体管Td1；
所述第一控制晶体管Td1的栅极与控制电压端V0电连接，所述第一控制晶体管Td1的源极与所述第一开关控制线S1电连接，所述第一控制晶体管Td1的漏极与所述第一控制端Q1电连接；
第一复用单元电路包括第一复用晶体管Tw1；
所述第一复用晶体管Tw1的栅极与第一控制端Q1电连接，所述第一复用晶体管Tw1的源极与第一输出数据线D11电连接，所述第一复用晶体管Tw1的漏极与输入数据线D2电连接；
所述第二储能单元电路包括第二存储电容C2；
第二存储电容C2的第一端与第二时钟信号端K2电连接，所述第二存储电容C2的第二端与第二控制端Q2电连接；
所述第二控制单元电路包括第二控制晶体管Td2；
所述第二控制晶体管Td2的栅极与高电压端电连接，所述第二控制晶体管Td2的源极与所述第二开关控制线S2电连接，所述第二控制晶体管Td2的漏极与所述第二控制端Q2电连接；
第二复用单元电路包括第二复用晶体管Tw2；
所述第二复用晶体管Tw2的栅极与第二控制端Q2电连接，所述第二复 用晶体管Tw2的源极与第二输出数据线D12电连接，所述第二复用晶体管Tw2的漏极与输入数据线D2电连接。
在图5所示的复用电路的至少一实施例中，所有的晶体管都为n型薄膜晶体管，但不以此为限。
在本公开至少一实施例中，所述第一开关控制线S1用于提供第一开关控制信号，所述第二开关控制线S2用于提供第二开关控制信号。
在图5所示的至少一实施例中，所述控制电压端V0提供的控制电压可以为直流高电压，但不以此为限。在实际操作时，所述直流高电压的电压值应不高于第一开关控制信号的高电压值，所述直流高电压的电压值应不高于第二开关控制信号的高电压值。
如图6所示，本公开如图5所示的复用电路的至少一实施例在工作时，
在第一复用阶段t1，S1提供高电压，K1提供的第一时钟信号的电位由低电压变为高电压，由于C1的存在，Q1的电位耦合至更高电压，Td1的栅极电压与S1提供的高电压一致，此时Td1的栅源电压接近于0V，Td1处于关闭状态，Q1的更高电位能够保持，以能够提升Tw1的驱动能力，Tw1打开，D2提供第一输入数据电压至D11；
在第一复用阶段t1，S2提供低电压，K2提供低电压，Td2开启，Q2的电位为低电压，Tw2关断，以断开D12与D2之间的连接；
在第二复用阶段t2，S2提供高电压，K2提供的第二时钟信号的电位由低电压变为高电压，由于C2的存在，Q2的电位耦合至更高电压，Td2的栅极电压与S2提供的高电压一致，此时Td2的栅源电压接近于0V，Td2处于关闭状态，Q2的更高电位能够保持，以能够提升Tw2的驱动能力，Tw2打开，D2提供第二输入数据电压至D12；
在第二复用阶段t2，S1提供低电压，K1提供低电压，Td1开启，Q1的电位为低电压，Tw1关断，以断开D11与D2之间的连接。
本公开实施例所述的复用方法，应用于上述的复用电路，所述复用方法包括：
第n复用单元电路在第n控制端的电位的控制下，导通或断开第n输出数据线与输入数据线之间的连接；
第n储能单元电路根据第n时钟信号，控制第n控制端的电位；
第n控制单元电路根据控制电压信号和第n开关控制信号，导通或断开所述第n控制端与所述第n开关控制线之间的连接；
N为大于1的整数，n为小于或等于N的正整数。
在本公开实施例所述的复用方法中，在第n开关控制线提供第一电压信号时，能够通过第n储能单元电路和第n控制单元，根据第n时钟信号，进一步提升或降低第n控制端的电位，提高第n复用单元电路的输出能力。
在具体实施时，所述复用方法可以具体包括：
第n开关控制线提供第一电压信号，第n时钟信号的电位由第二电压变为第一电压，第n储能单元电路相应改变第n控制端的电位，第n复用单元电路在第n控制端的电位的控制下，导通第n输出数据线与输入数据线之间的连接；第n控制单元电路根据控制电压信号和第n开关控制信号，断开所述第n控制端与所述第n开关控制线之间的连接；
第n时钟信号的电位由第一电压变为第二电压，第n开关控制线提供第二电压信号，第n储能单元电路相应改变第n控制端的电位，第n控制单元电路根据控制电压信号和第n开关控制信号，导通所述第n控制端与所述第n开关控制线之间的连接，以控制对第n控制端进行放电，第n复用单元电路在第n控制端的电位的控制下，断开第n输出数据线与输入数据线之间的连接。
可选的，所述第n控制单元电路包括的第n控制晶体管为n型晶体管，第n复用单元电路包括的第n复用晶体管为n型晶体管，第一电压为高电压，第二电压为低电压；或者，
所述第n控制晶体管为p型晶体管，所述第n复用晶体管为p型晶体管，第一电压为低电压，第二电压为高电压。
本公开实施例所述的复用模组包括多个上述的复用电路。
如图7所示，以N等于2，本公开至少一实施例所述的复用模组包括两个本公开至少一实施例所述的复用电路为例说明；
如图7所示，本公开至少一实施例所述的复用模组包括第一复用电路和第二复用电路；
所述第一复用电路包括第一复用单元电路、第一储能单元电路、第一控制单元电路、第二复用单元电路、第二储能单元电路和第二控制单元电路；
所述第一储能单元电路包括第一个第一存储电容C11；
C11的第一端与第一时钟信号端K1电连接，C11的第二端与第一个第一控制端Q11电连接；
所述第一控制单元电路包括第一个第一控制晶体管Td11；
Td11的栅极与控制电压端V0电连接，Td1的源极与所述第一开关控制线S1电连接，Td1的漏极与Q11电连接；
第一复用单元电路包括第一个第一复用晶体管Tw11；
Tw11的栅极与Q11电连接，Tw11的源极与第一个第一输出数据线D111电连接，Tw11的漏极与第一输入数据线D21电连接；
所述第二储能单元电路包括第一个第二存储电容C12；
C12的第一端与第二时钟信号端K2电连接，C12的第二端与第一个第二控制端Q12电连接；
所述第二控制单元电路包括第一第二控制晶体管Td12；
Td12的栅极与高电压端电连接，Td12的源极与所述第二开关控制线S2电连接，Td12的漏极与Q12电连接；
第二复用单元电路包括第一个第二复用晶体管Tw12；
Tw12的栅极与Q12电连接，Tw12的源极与第一个第二输出数据线D112电连接，Tw12的漏极与第一输入数据线D21电连接；
所述第二复用电路包括第三复用单元电路、第三储能单元电路、第三控制单元电路、第四复用单元电路、第四储能单元电路和第四控制单元电路；
所述第三储能单元电路包括第二个第一存储电容C21；
C21的第一端与第一时钟信号端K1电连接，C21的第二端与第二个第一控制端Q21电连接；
所述第三控制单元电路包括第二个第一控制晶体管Td21；
Td21的栅极与控制电压端V0电连接，Td2的源极与所述第一开关控制线S1电连接，Td21的漏极与Q21电连接；
第三复用单元电路包括第二个第一复用晶体管Tw21；
Tw21的栅极与Q21电连接，Tw21的源极与第二个第一输出数据线D121电连接，Tw21的漏极与第二输入数据线D22电连接；
所述第四储能单元电路包括第二个第二存储电容C22；
C22的第一端与第二时钟信号端K2电连接，C22的第二端与第二个第二控制端Q22电连接；
所述第二控制单元电路包括第二个第二控制晶体管Td22；
Td22的栅极与高电压端电连接，Td22的源极与所述第二开关控制线S2电连接，Td22的漏极与Q22电连接；
第四复用单元电路包括第二个第二复用晶体管Tw22；
Tw22的栅极与Q22电连接，Tw22的源极与第二个第二输出数据线D122电连接，Tw22的漏极与第二输入数据线D22电连接。
在图7所示的至少一实施例中，所有的晶体管都为n型薄膜晶体管，但不以此为限。
在本公开至少一实施例中，所述第一开关控制线S1用于提供第一开关控制信号，所述第二开关控制线S2用于提供第二开关控制信号。
在图7所示的至少一实施例中，所述控制电压端V0提供的控制电压可以为直流高电压，但不以此为限。在实际操作时，所述直流高电压的电压值应不高于第一开关控制信号的高电压值，所述直流高电压的电压值应不高于第二开关控制信号的高电压值。
本公开实施例所述的显示装置包括本公开实施例所述的复用模组。
本公开实施例所提供的显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上所述是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (10)

  1. 一种复用电路，包括N个复用单元电路、N个储能单元电路和N个控制单元电路；N为大于1的整数；
    第n复用单元电路的控制端与第n控制端电连接，所述第n复用单元电路的第一端与第n输出数据线电连接，所述第n复用单元电路的第二端与输入数据线电连接，所述第n复用单元电路用于在所述第n控制端的电位的控制下，导通或断开所述第n输出数据线与所述输入数据线之间的连接；
    第n储能单元电路的第一端与第n时钟信号端电连接，所述第n储能单元电路的第二端与所述第n控制端电连接，所述第n储能单元电路用于根据第n时钟信号，控制第n控制端的电位；所述第n时钟信号端用于提供所述第n时钟信号；
    第n控制单元电路分别与控制电压端、所述第n控制端和第n开关控制线电连接，用于根据控制电压信号和第n开关控制信号，导通或断开所述第n控制端与所述第n开关控制线之间的连接；所述控制电压端用于提供所述控制电压信号；所述第n开关控制线用于提供所述第n开关控制信号；
    n为小于或等于N的正整数。
  2. 如权利要求1所述的复用电路，其中，所述第n储能单元电路包括第n存储电容；
    第n存储电容的第一端与第n时钟信号端电连接，所述第n存储电容的第二端与所述第n控制端电连接。
  3. 如权利要求1所述的复用电路，其中，所述第n控制单元电路包括第n控制晶体管；
    所述第n控制晶体管的控制极与所述控制电压端电连接，所述第n控制晶体管的第一极与所述第n开关控制线电连接，所述第n控制晶体管的第二极与所述第n控制端电连接。
  4. 如权利要求3所述的复用电路，其中，所述第n控制晶体管为n型晶体管，所述控制电压信号为高电压信号；或者，
    所述第n控制晶体管为p型晶体管，所述控制电压信号为低电压信号。
  5. 如权利要求1所述的复用电路，其中，第n复用单元电路包括第n复用晶体管；
    所述第n复用晶体管的控制极与第n控制端电连接，所述第n复用晶体管的第一极与第n输出数据线电连接，所述第n复用晶体管的第二极与输入数据线电连接。
  6. 一种复用方法，应用于如权利要求1至5中任一权利要求所述的复用电路，所述复用方法包括：
    第n复用单元电路在第n控制端的电位的控制下，导通或断开第n输出数据线与输入数据线之间的连接；
    第n储能单元电路根据第n时钟信号，控制第n控制端的电位；
    第n控制单元电路根据控制电压信号和第n开关控制信号，导通或断开所述第n控制端与所述第n开关控制线之间的连接；
    N为大于1的整数，n为小于或等于N的正整数。
  7. 如权利要求6所述的复用方法，其中，所述复用方法具体包括：
    第n开关控制线提供第一电压信号，第n时钟信号的电位由第二电压变为第一电压，第n储能单元电路相应改变第n控制端的电位，第n复用单元电路在第n控制端的电位的控制下，导通第n输出数据线与输入数据线之间的连接；第n控制单元电路根据控制电压信号和第n开关控制信号，断开所述第n控制端与所述第n开关控制线之间的连接；
    第n时钟信号的电位由第一电压变为第二电压，第n开关控制线提供第二电压信号，第n储能单元电路相应改变第n控制端的电位，第n控制单元电路根据控制电压信号和第n开关控制信号，导通所述第n控制端与所述第n开关控制线之间的连接，以控制对第n控制端进行放电，第n复用单元电路在第n控制端的电位的控制下，断开第n输出数据线与输入数据线之间的连接。
  8. 如权利要求7所述的复用方法，其中，所述第n控制单元电路包括的第n控制晶体管为n型晶体管，第n复用单元电路包括的第n复用晶体管为n型晶体管，第一电压为高电压，第二电压为低电压；或者，
    所述第n控制晶体管为p型晶体管，所述第n复用晶体管为p型晶体管， 第一电压为低电压，第二电压为高电压。
  9. 一种复用模组，包括多个如权利要求1至5中任一权利要求所述的复用电路。
  10. 一种显示装置，包括如权利要求9所述的复用模组。
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