WO2021243880A1 - 显示基板以及显示装置 - Google Patents

显示基板以及显示装置 Download PDF

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Publication number
WO2021243880A1
WO2021243880A1 PCT/CN2020/114734 CN2020114734W WO2021243880A1 WO 2021243880 A1 WO2021243880 A1 WO 2021243880A1 CN 2020114734 W CN2020114734 W CN 2020114734W WO 2021243880 A1 WO2021243880 A1 WO 2021243880A1
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WIPO (PCT)
Prior art keywords
signal line
display
area
opening
pixel
Prior art date
Application number
PCT/CN2020/114734
Other languages
English (en)
French (fr)
Inventor
杨慧娟
刘庭良
姜晓峰
周洋
于鹏飞
和玉鹏
李�根
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/419,754 priority Critical patent/US20220320232A1/en
Priority to DE112020005601.5T priority patent/DE112020005601T5/de
Publication of WO2021243880A1 publication Critical patent/WO2021243880A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/88—Dummy elements, i.e. elements having non-functional features
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0413—Details of dummy pixels or dummy lines in flat panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes

Definitions

  • the embodiment of the present disclosure relates to a display substrate and a display device.
  • the display screen of the display device is developing in the direction of large-screen and full-screen.
  • a display device such as a mobile phone, a tablet computer, etc.
  • the camera device is usually arranged on a side outside the display area of the display screen.
  • the camera device can be combined and overlapped with the display area of the display screen to reserve a place for the camera device in the display area to maximize the display area of the display screen.
  • At least one embodiment of the present disclosure provides a display substrate, which includes a base substrate, a first signal line, and a second signal line.
  • the base substrate includes a first opening area and a display area; the first opening area includes a first opening and a first opening peripheral area surrounding the first opening; the display area at least partially surrounds the first opening area and includes a first opening area. Display area and second display area.
  • the first display area is located on the first side of the first opening area; the second display area is located on the second side of the first opening area, and the first side and the second side are opposite to each other in the first direction ,
  • the first display area and the second display area include a first pixel array; a first signal line is configured to provide a first display signal to the first pixel array, and sequentially pass through the
  • the first display area, the first opening peripheral area, and the second display area include a first lead part and a first winding part located in the first opening peripheral area; the first winding part partially surrounds The first opening is provided, and the first lead part is connected to the first winding part; the second signal line is configured to provide a second display signal to the first pixel array, and crosses the first direction.
  • the second direction passes through the peripheral area of the first opening, and includes a second winding part located in the peripheral area of the first opening, wherein the second winding part is partially disposed around the first opening;
  • the orthographic projection of the first lead part on the base substrate and the orthographic projection of the second signal line on the base substrate have a first overlapping area, and the first winding part is on the substrate.
  • the orthographic projection on the substrate and the orthographic projection of the second winding portion on the base substrate have a second overlapping area, and the area of the first overlapping area is smaller than the area of the second overlapping area.
  • the first winding portion extends from the first side of the first opening to surround the first opening to the second side of the first opening, so The first side of the first opening and the second side of the first opening are opposite to each other in the first direction; the second winding part surrounds the first side from the third side of the first opening.
  • the opening extends to a fourth side of the first opening, and the third side and the fourth side are opposite to each other in the second direction.
  • the first pixel array includes a first pixel row and a second pixel row respectively extending along the first direction, the first pixel row and the second pixel row
  • the pixel rows are all disconnected by the first opening area
  • the display substrate includes a plurality of the first signal lines, and the plurality of first signal lines include: configured to provide the first pixel rows with the first signal lines The first signal line for a display signal, and the first signal line configured to provide the first display signal to the second pixel row; to provide the first display signal to the first pixel row
  • the first winding portion of the first signal line partially surrounds the first opening on the third side of the first opening; the second pixel row provides the first display signal to the second pixel row
  • a first winding portion of a signal line partially surrounds the first opening on the fourth side of the first opening.
  • the first pixel array includes a first pixel column and a second pixel column respectively extending along the second direction;
  • the display substrate includes a plurality of second pixel columns.
  • Signal line, the plurality of second signal lines include: the second signal line configured to provide the second display signal to the first pixel column, and the second signal line configured to provide the second pixel column
  • the second winding portion of the second signal line that provides the second display signal to the first pixel column is convex toward the first side of the first opening And partially surround the first opening on the first side of the first opening;
  • the second winding portion of the second signal line that provides the second display signal to the second pixel column faces toward the The second side of the first opening protrudes and partially surrounds the first opening on the second side of the first opening.
  • the first winding portion of the first signal line that provides the first display signal to the first pixel row is different from that to the second pixel row.
  • the first winding portion of the first signal line that provides the first display signal is substantially symmetrical with respect to the axis of symmetry along the first direction; the second display is provided to the first pixel column
  • the second winding part of the second signal line of the signal and the second winding part of the second signal line providing the second display signal to the second pixel column are opposite to the edge
  • the axis of symmetry in the second direction is substantially symmetrical.
  • the planar shape of the first winding portion and the planar shape of the second winding portion respectively constitute a part of the concentric ring of the planar shape of the first opening.
  • the planar shape of the first winding portion and the planar shape of the second winding portion respectively include arc shapes, or include arc shapes and linear segments, respectively.
  • the first signal line is a gate scan signal line
  • the first display signal is a gate scan signal
  • the display area includes a plurality of pixels, each of the pixels includes a plurality of sub-pixels, each of the sub-pixels includes a pixel circuit, and the pixel circuit includes: a transistor, Light-emitting elements and storage capacitors.
  • the transistor includes an active layer, a gate, and a source and drain; a light-emitting element is connected to one of the source and drain of the transistor; the storage capacitor includes a first plate and a second plate, the gate and the first signal The line and the first plate of the storage capacitor are arranged in the same layer.
  • a display substrate provided by the present disclosure further includes a third display area and a plurality of third signal lines.
  • the third display area is located on at least one side of the first display area and the second display area in the second direction, and is connected to the first display area and the second display area, and
  • the second pixel array includes a second pixel array; the second pixel array includes multiple rows and multiple columns of pixels; and a plurality of third signal lines are configured to respectively provide third scanning signals to the multiple rows of pixels included in the second pixel array and extend along the Extending in the first direction, wherein the second signal line is further configured to provide the second display signal to a plurality of columns of pixels of the second pixel array.
  • the number of pixels included in each row of pixels of the second pixel array is greater than the number of pixels included in the first pixel row of the first pixel array, and The number of pixels included in the second pixel row of the first pixel array.
  • the second signal line includes a data line
  • the data line is configured to provide the sub-pixel with a data signal for controlling the light-emitting gray level of the sub-pixel.
  • a display substrate provided in the present disclosure further includes a first power line.
  • the first power line is connected to the first voltage terminal and is configured to provide a first power voltage to the pixel circuit, and is connected to the second plate of the storage capacitor, and includes a plurality of first sub-lines extending along the first direction.
  • a plurality of second sub-wiring lines extending along the second direction; a first part of the first sub-wiring of the plurality of first sub-wiring lines is disconnected in the first opening area, and the plurality of The second part of the first sub-wiring in the first sub-wiring runs through the third display area; the first part of the second sub-wiring in the plurality of second sub-wiring is broken in the first opening area Open, the second part of the second sub-wiring of the plurality of second sub-wiring runs sequentially through the first display area and the third display region or sequentially runs through the second display region and the third display area; the first part of the first sub-wiring A sub-wiring is electrically connected to at least one second sub-wiring in the second portion of the second sub-wiring in the first display area and the second display area, and the first portion of the second sub-wiring The wire is electrically connected to at least one first sub-wiring in the second part of the first sub-wiring in the third display area.
  • the first sub-wiring and the second plate of the storage capacitor are provided in the same layer; the second sub-wiring and the data line are provided in the same layer.
  • a display substrate provided in the present disclosure further includes a first power line.
  • the first power line is connected to the first voltage terminal and is configured to provide a first power voltage to the pixel circuit, and is connected to the second plate of the storage capacitor, and includes a plurality of first sub-lines extending along the first direction.
  • a display substrate provided by the present disclosure further includes a second opening area and an inter-opening area; the second opening area is adjacent to the first opening area, and includes a second opening and a second opening surrounding the second opening. The area around the opening; the area between the openings is located between the first opening area and the second opening area.
  • the second opening area and the first opening area are arranged along the first direction; the first display area is located far away from the first opening area.
  • the second display area is located on the side of the second opening area away from the inter-opening area; the first signal line passes through the first signal line sequentially along the first direction A display area, a peripheral area of the first opening, an area between the openings, a peripheral area of the second opening, and the second display area.
  • the second opening area and the first opening area are arranged along the second direction; the second signal line sequentially passes through all along the second direction.
  • the first opening peripheral area, the inter-opening area, the second opening peripheral area, and the third display area are arranged along the second direction; the second signal line sequentially passes through all along the second direction.
  • At least one of the inter-opening area, the first opening peripheral area, and the second opening peripheral area includes a first dummy sub-pixel, and
  • the first dummy sub-pixel includes a first dummy pixel circuit, and the first dummy pixel circuit includes a first compensation capacitor;
  • the first compensation capacitor includes a first electrode plate and a second electrode plate.
  • the first electrode plate is arranged in the same layer as the first signal line and is electrically connected to the first signal line; the second electrode plate is arranged in a different layer and insulated from the first electrode plate of the first compensation capacitor;
  • the orthographic projection of the first plate of a compensation capacitor on the base substrate and the orthographic projection of the second plate of the first compensation capacitor on the base substrate at least partially overlap.
  • the second plate of the first compensation capacitor and the second plate of the storage capacitor are arranged in the same layer.
  • the first plate of the first compensation capacitor is disconnected from other parts of the first dummy pixel circuit except for the first signal line.
  • the area between the openings includes a second dummy sub-pixel, the second dummy sub-pixel includes a second dummy pixel circuit, and the second dummy pixel circuit includes a second compensation circuit.
  • Capacitor; the first plate of the second compensation capacitor is arranged on the same layer as the first signal line and is electrically connected to the first signal line; the orthographic projection of the first signal line on the base substrate At least partially overlaps with the orthographic projection of the second electrode plate of the second compensation capacitor on the base substrate.
  • the second plate of the second compensation capacitor includes a first body portion and a first extension portion.
  • the first body portion is located on the first side of the first signal line in the second direction; the first extension portion extends from the first body portion toward the first signal line in the second direction ,
  • the orthographic projection of the first signal line on the base substrate and the orthographic projection of the first extension portion on the base substrate at least partially overlap.
  • the second electrode plate of the second compensation capacitor and the second electrode plate of the first compensation capacitor are arranged in the same layer.
  • the first plate of the second compensation capacitor includes a second body portion, a second extension portion, and a third extension portion.
  • the second body portion is located on the first side of the first signal line in the second direction; the second extension portion extends from the second body portion toward the first signal line in the second direction , Located between the second body part and the first signal line; the second body part is electrically connected to the first signal line through the second extension part; the third extension part is from the first signal line
  • a signal line extends in the second direction away from the second body portion, is located on the second side of the first signal line in the second direction and is electrically connected to the first signal line. Connected, the second side of the first signal line is opposite to the first side of the first signal line.
  • the orthographic projection of the first plate of the second compensation capacitor on the base substrate is located on the second plate of the second compensation capacitor on the substrate. In the orthographic projection on the base substrate.
  • the first body part and the first extension part are integrally formed; the second body part, the second extension part, the first signal line, and the The third extension part is integrally formed.
  • the second dummy sub-pixel includes a first dummy semiconductor layer.
  • the first dummy semiconductor layer is located on the side of the first plate of the second compensation capacitor close to the base substrate, and includes a first part and a second part spaced apart so as not to be connected to each other; the first part is located on the On the first side of the first signal line, the second part is located on the second side of the first signal line; the orthographic projection of the first signal line on the base substrate and the first signal line
  • the orthographic projection of a virtual semiconductor layer on the base substrate does not overlap.
  • the first part and the second part of the first dummy semiconductor layer are both configured to be sent electrical signals through the second dummy pixel circuit; the first dummy semiconductor layer
  • the first part has a first end and a second end opposite to each other in the first direction, the second end is configured to be sent to the electrical signal through the second dummy pixel circuit, and the first end is connected to The second end is connected.
  • the area between the openings further includes third dummy sub-pixels, each of the third dummy sub-pixels includes a third dummy pixel circuit, and the third dummy pixel circuit includes The second virtual semiconductor layer.
  • the second dummy semiconductor layer includes a first portion and a second portion spaced apart so as not to be connected to each other, the first portion of the second dummy semiconductor layer is located on the first side of the first signal line, and the second The first part of the dummy semiconductor layer is located on the second side of the first signal line; the orthographic projection of the first signal line on the base substrate and the second dummy semiconductor layer on the base substrate The orthographic projections on do not overlap.
  • the third dummy pixel circuit and the pixel circuit have the same circuit design, except that the second dummy semiconductor layer is disconnected.
  • the display substrate includes a base substrate, a first signal line, and a second signal line.
  • the base substrate includes: a first opening area, a second opening area, an inter-opening area, and a display area.
  • the first opening area includes a first opening and a first opening peripheral area surrounding the first opening;
  • a second opening area is disposed adjacent to the first opening area, and includes a second opening and a peripheral area surrounding the second opening.
  • the second opening peripheral area; the inter-opening area is located between the first opening area and the second opening area, and the inter-opening area, the first opening peripheral area and the second opening peripheral area are in three At least one of includes a first dummy sub-pixel; a display area at least partially surrounds the first opening area, the second opening area, and the inter-opening area, and includes a pixel array; the first signal line extends through the The area between the openings is configured to provide a first display signal to the pixel array and pass through the first dummy sub-pixel.
  • the first dummy sub-pixel includes a first dummy pixel circuit, and the first dummy pixel circuit includes a first dummy pixel circuit.
  • One compensation capacitor is configured to provide a first display signal to the pixel array and pass through the first dummy sub-pixel.
  • the first compensation capacitor includes: a first electrode plate and a second electrode plate.
  • the first electrode plate is arranged on the same layer as the first signal line and is electrically connected to the first signal line; the second electrode plate is arranged on a different layer from the first electrode plate and is insulated, wherein the first compensation capacitor
  • the orthographic projection of the second electrode plate on the base substrate and the orthographic projection of the first electrode plate of the first compensation capacitor on the base substrate at least partially overlap.
  • the first signal line extends in a first direction, and the first opening area and the second opening area are arranged adjacent to each other in the first direction;
  • the first direction is vertical;
  • the first electrode plate of the first compensation capacitor includes a first body portion and a first extension portion.
  • the first body part is on the first side of the first signal line in the second direction;
  • the first extension part, the first body part extends toward the first signal line, and is located at the first
  • the signal line is on the first side in the second direction and is located between the first body part and the first signal line, wherein the first body part passes through the first extension part and the first signal line.
  • the first signal line is electrically connected.
  • the first plate of the first compensation capacitor further includes a second extension.
  • the second extension portion extends from the first signal line toward a direction away from the first body portion, and is located on the second side of the first signal line in the second direction and is connected to the first signal line. Electrically connected, the second side is opposite to the first side.
  • the first body portion, the first extension portion, the first signal line, and the second extension portion are integrally formed.
  • the width of the first extension in the first direction, the width of the second extension in the first direction and the first body are substantially equal.
  • the display area includes a first display area and a second display area.
  • the first display area is located on the side of the first opening area away from the inter-opening area;
  • the second display area is located on the side of the second opening area away from the inter-opening area, wherein the first The display area and the second display area include a first pixel array, and the first pixel array includes a first pixel row and a second pixel row respectively extending along the first direction, the first pixel row and the The second pixel rows are all disconnected by the whole composed of the first opening area, the inter-opening area, and the second opening area;
  • the first signal line sequentially passes through the A first display area, a peripheral area of the first opening, an area between the openings, a peripheral area of the second opening, and the second display area;
  • the display substrate includes: configured to provide the first pixel row The first signal line of the first display signal, and the first signal line configured to provide the first display signal to the second pixel row.
  • the inter-opening area includes a first virtual sub-pixel row corresponding to the first pixel row and a second virtual sub-pixel row corresponding to the second pixel row
  • the first signal line configured to provide the first display signal to the first pixel row passes through the first pixel row and the first dummy pixel row, and the configuration is to provide the
  • the first signal line for providing the first display signal in the second pixel row passes through the second pixel row and the second dummy pixel row; the number of pixels in the first pixel row is the same as the second pixel row.
  • the number of pixels in the pixel row is different, and the number of the first compensation capacitors in the first virtual pixel row is different from the number of the first compensation capacitors in the second virtual pixel row.
  • the first signal line is a gate scan signal line
  • the first display signal is a gate scan signal
  • the display area includes a plurality of pixels, each of the pixels includes a plurality of sub-pixels, and each of the sub-pixels includes a pixel circuit;
  • the pixel circuit includes a transistor, a light emitting Components and storage capacitors.
  • the transistor includes an active layer, a gate, and a source and drain; a light-emitting element is connected to one of the source and drain of the transistor;
  • a storage capacitor includes a first plate and a second plate; the gate and the first signal
  • the wire, the first plate of the storage capacitor and the first plate of the first compensation capacitor are arranged in the same layer.
  • the first electrode plate of the storage capacitor and the first signal line are spaced apart from each other, and spaced apart from the gate electrode.
  • the second plate of the first compensation capacitor and the second plate of the storage capacitor are arranged in the same layer.
  • the first plate of the first compensation capacitor is disconnected from other parts of the first dummy pixel circuit except for the first signal line.
  • the first dummy pixel circuit further includes a first switching electrode.
  • the first switching electrode is electrically connected to the first plate of the first compensation capacitor, and is disconnected from other parts of the first dummy pixel circuit except the first signal line.
  • the first dummy pixel circuit includes a first dummy semiconductor layer, and the first dummy semiconductor layer is located near the substrate plate of the first signal line.
  • the display substrate further includes a disconnection electrode; the disconnection electrode is electrically connected to the first dummy semiconductor layer, is disposed on the same layer as the first transfer electrode, and is spaced apart from the first transfer electrode so as to be different from each other. connect.
  • the first dummy pixel circuit and the pixel circuit have the same circuit design, except for the first plate of the first compensation capacitor and the first compensation The first plate of the capacitor is disconnected from other parts of the first dummy pixel circuit.
  • the area between the openings further includes a second virtual sub-pixel; the second virtual sub-pixel includes a second virtual pixel circuit.
  • the second virtual pixel circuit includes a second compensation capacitor; the first plate of the second compensation capacitor is arranged in the same layer as the first signal line and is electrically connected to the first signal line; the first signal
  • the orthographic projection of the line on the base substrate and the orthographic projection of the second electrode plate of the second compensation capacitor on the base substrate at least partially overlap.
  • the second plate of the second compensation capacitor includes a second body portion and a third extension portion.
  • the second body portion is located on the first side of the first signal line in the second direction; the third extension portion extends from the second body portion toward the first signal line in the second direction ,
  • the orthographic projection of the first signal line on the base substrate and the orthographic projection of the third extension portion on the base substrate at least partially overlap.
  • the second electrode plate of the second compensation capacitor and the second electrode plate of the first compensation capacitor are arranged in the same layer.
  • the first plate of the second compensation capacitor includes a third body portion and a fourth extension portion.
  • the third body portion is located on the first side of the first signal line in the second direction; the fourth extension portion extends from the third body portion toward the first signal line in the second direction , Located between the third body part and the first signal line; the third body part is electrically connected to the first signal line through the fourth extension part.
  • the orthographic projection of the first plate of the second compensation capacitor on the base substrate is located on the second plate of the second compensation capacitor on the substrate. In the orthographic projection on the base substrate.
  • the second dummy sub-pixel circuit includes a second switching electrode, and the second switching electrode is provided in the same layer as the first switching electrode and is arranged in the same layer as the first switching electrode.
  • the second plate of the second compensation capacitor is electrically connected.
  • the second dummy sub-pixel includes a first dummy semiconductor layer.
  • the first dummy semiconductor layer includes a first portion and a second portion spaced apart so as not to be connected to each other; the first portion is located on the first side of the first signal line, and the second portion is located on the first signal line The second side; the orthographic projection of the first signal line on the base substrate and the orthographic projection of the first dummy semiconductor layer on the base substrate do not overlap.
  • the second part of the first dummy semiconductor layer is configured to be sent an electrical signal through the second dummy pixel circuit; the first part of the first dummy semiconductor layer There is a first end and a second end opposite to each other in the first direction, the second end is configured to be sent to the electrical signal through the second dummy pixel circuit, and the first end and the second end are Two-terminal connection.
  • the area between the openings further includes a third dummy sub-pixel, the third dummy sub-pixel includes a third dummy pixel circuit, and the third dummy pixel circuit includes a second dummy pixel circuit.
  • the second dummy semiconductor layer includes a first portion and a second portion spaced apart so as not to be connected to each other, the first portion of the second dummy semiconductor layer is located on the first side of the first signal line, and the second The first part of the dummy semiconductor layer is located on the second side of the first signal line; the orthographic projection of the first signal line on the base substrate and the third dummy semiconductor layer on the base substrate The orthographic projections on do not overlap.
  • the third dummy sub-pixel and the pixel circuit have the same circuit design, except that the second dummy semiconductor layer is disconnected.
  • the display area further includes a third display area. It is located on at least one side of the first display area and the second display area in the second direction, and is connected to the first display area and the second display area at the same time, and includes a second pixel array
  • the second pixel array includes multiple rows and multiple columns of pixels
  • the third display area includes multiple rows and multiple columns of pixels that respectively provide scanning signals for each row of pixels and extend along the first direction.
  • Three signal lines; the number of pixels included in each row of pixels of the second pixel array is more than the number of pixels included in the first pixel row of the first pixel array and the number of pixels in the first pixel array The number of pixels included in the second pixel row.
  • At least one embodiment of the present disclosure provides a display device including any of the above-mentioned display substrates.
  • Figure 1 is a schematic plan view of a display substrate
  • FIG. 2A is a schematic plan view of a display substrate provided by an embodiment of the present disclosure.
  • FIG. 2B is a partial enlarged schematic diagram of the first opening area in FIG. 2A;
  • Fig. 2C is a schematic cross-sectional view taken along the line I-I' in Fig. 2B;
  • 2D is a schematic plan view of another display substrate according to an embodiment of the disclosure.
  • 2E is a schematic plan view of still another display substrate according to an embodiment of the disclosure.
  • 2F is a schematic plan view of a pixel arrangement near a first opening area of a display substrate according to an embodiment of the present disclosure
  • 3A is a schematic cross-sectional view of the display area of the display substrate in FIG. 2A along the line A-A';
  • 3B is another schematic cross-sectional view of the display area of the display substrate in FIG. 2A along the line A-A';
  • 3C is another schematic cross-sectional view of the display area of the display substrate in FIG. 2A along the line A-A';
  • FIG. 4 is an equivalent circuit diagram of a pixel circuit in a display substrate provided by an embodiment of the present disclosure
  • 5A is a schematic diagram of a planar layout of a pixel circuit in a display substrate according to an embodiment of the present disclosure
  • Fig. 5B is a schematic cross-sectional view taken along line A1-B1 in Fig. 5A;
  • 5C-5F are schematic diagrams of various layers of a pixel circuit of a display substrate provided by an embodiment of the present disclosure.
  • FIG. 6 is a signal timing diagram of the working process of the pixel circuit shown in FIG. 4;
  • FIG. 7A is a partial enlarged schematic diagram of the first opening area in FIG. 2A;
  • Fig. 7B is a schematic cross-sectional view taken along the line H-H' in Fig. 7A;
  • FIG. 8A is a schematic plan view of still another display substrate provided by an embodiment of the present disclosure.
  • FIG. 8B is a partial enlarged schematic view of the first opening area and the second opening area in FIG. 8A;
  • FIG. 8C is a partially enlarged schematic diagram of a first opening area and a second opening area of another display substrate provided by an embodiment of the present disclosure.
  • FIG. 9 is an equivalent circuit diagram of a first dummy pixel circuit in a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 10A is a schematic diagram of a planar layout of a first dummy pixel circuit in a display substrate according to an embodiment of the present disclosure
  • Fig. 10B is a schematic cross-sectional view taken along line A2-B2 in Fig. 10A;
  • 10C-10G are schematic diagrams of each layer of a first dummy pixel circuit of a display substrate provided by an embodiment of the present disclosure
  • FIG. 11 is a schematic plan view of a pixel arrangement near a first opening area or a second opening area of a display substrate according to an embodiment of the present disclosure
  • FIG. 12A is a schematic diagram of a planar layout of a second virtual pixel circuit in a display substrate according to an embodiment of the present disclosure
  • Fig. 12B is a schematic cross-sectional view taken along line A3-B3 in Fig. 12A;
  • 12C-12F are schematic diagrams of various layers of a second dummy pixel circuit of a display substrate provided by an embodiment of the present disclosure.
  • FIG. 13A is a schematic plan view of still another display substrate according to an embodiment of the disclosure.
  • Fig. 13B is an enlarged schematic diagram of a part L1 of the racetrack-shaped opening of Fig. 13A including arc-shaped routing;
  • Fig. 13C is an enlarged schematic diagram of a part L2 of the racetrack-shaped opening of Fig. 13A including a straight line.
  • Fig. 1 is a schematic plan view of a display substrate.
  • the display substrate 10 includes a display area 101 and a peripheral area 102 surrounding the display area 101.
  • the display area 101 is designed, for example, in an irregular shape with a notch 103 on at least one side.
  • Devices such as cameras, distance sensors, etc. are arranged in the area of the notch 103, thereby contributing to the realization of the narrow frame design of the display substrate 10.
  • the display area 101 includes a first display area 1011 and a second display area 1012 located on the left and right sides of the notch 103.
  • the first display area 1011 and the second display area 1012 are opposite to the bottom of the display area 101.
  • the sides are at the same horizontal position, and are driven by one or more scanning signal lines (gate lines) that extend horizontally from the left and right in the figure, for example.
  • the first display area and the second display area may also be in different horizontal positions.
  • the first display area and the second display area are arranged along the curved edge of the display screen, and the first display area and the second display area may not be in the same horizontal position.
  • the number of pixels in the same row of pixels in the first display area 1011 and the second display area 1012 is greater than that in the display area 101 except for the first display area 1011 and the second display area 1012.
  • the number of pixels in a row of pixels in a part is small.
  • the number of pixels connected to the horizontally extending signal lines used to provide display signals (such as scanning signals) for pixels in the same row of the first display area 1011 and the second display area 1012 It is different from the number of pixels connected to the signal lines used to provide electrical signals (such as scanning signals) for a row of pixels in other parts of the display area 101 except for the first display area 1011 and the second display area 1012, and the number of pixels connected in the notch
  • the number of pixels in different rows of pixels in the first display area 1011 and the second display area 1012 may also be different.
  • the display substrate 10 because the number of pixels in different rows of pixels is different, the load of the signal lines connecting the pixels of different rows is different, and the signal transmission speeds of these signal lines are different. The difference between the actual display signal and the design value is The deviation is different, which will affect the display effect of the display substrate.
  • load compensation can be performed on these signal lines with different loads, so that the loads of these signal lines are basically the same, thereby reducing the adverse effect of the notch 103 on the display quality.
  • At least one embodiment of the present disclosure provides a display substrate, which includes a base substrate, a first signal line, and a second signal line.
  • the base substrate includes a first opening area and a display area; the first opening area includes a first opening and a first opening peripheral area surrounding the first opening; the display area at least partially surrounds the first opening area and includes a first opening area. Display area and second display area.
  • the first display area is located on the first side of the first opening area; the second display area is located on the second side of the first opening area, and the first side and the second side are opposite to each other in the first direction ,
  • the first display area and the second display area include a first pixel array; a first signal line is configured to provide a first display signal to the first pixel array, and sequentially pass through the
  • the first display area, the first opening peripheral area, and the second display area include a first lead part and a first winding part located in the first opening peripheral area; the first winding part partially surrounds The first opening is provided, and the first lead part is connected to the first winding part; the second signal line is configured to provide a second display signal to the first pixel array, and crosses the first direction.
  • the second direction passes through the peripheral area of the first opening, and includes a second winding part located in the peripheral area of the first opening, wherein the second winding part is partially disposed around the first opening;
  • the orthographic projection of the first lead part on the base substrate and the orthographic projection of the second signal line on the base substrate have a first overlapping area, and the first winding part is on the substrate.
  • the orthographic projection on the substrate and the orthographic projection of the second winding portion on the base substrate have a second overlapping area, and the area of the first overlapping area is smaller than the area of the second overlapping area.
  • At least one embodiment of the present disclosure further provides a display substrate.
  • the display substrate includes a base substrate, a first signal line, and a second signal line.
  • the base substrate includes: a first opening area, a second opening area, an inter-opening area, and a display area.
  • the first opening area includes a first opening and a first opening peripheral area surrounding the first opening;
  • a second opening area is disposed adjacent to the first opening area, and includes a second opening and a peripheral area surrounding the second opening.
  • the second opening peripheral area; the inter-opening area is located between the first opening area and the second opening area, and the inter-opening area, the first opening peripheral area and the second opening peripheral area are in three At least one of includes a first dummy sub-pixel; a display area at least partially surrounds the first opening area, the second opening area, and the inter-opening area, and includes a pixel array; the first signal line extends through the The area between the openings is configured to provide a first display signal to the pixel array and pass through the first dummy sub-pixel.
  • the first dummy sub-pixel includes a first dummy pixel circuit, and the first dummy pixel circuit includes a first dummy pixel circuit.
  • One compensation capacitor is configured to provide a first display signal to the pixel array and pass through the first dummy sub-pixel.
  • the first compensation capacitor includes: a first electrode plate and a second electrode plate.
  • the first electrode plate is arranged on the same layer as the first signal line and is electrically connected to the first signal line; the second electrode plate is arranged on a different layer from the first electrode plate and is insulated, wherein the first compensation capacitor
  • the orthographic projection of the second electrode plate on the base substrate and the orthographic projection of the first electrode plate of the first compensation capacitor on the base substrate at least partially overlap.
  • FIG. 2A is a schematic plan view of a display substrate according to an embodiment of the disclosure
  • FIG. 2B is a partial enlarged schematic view of the first opening area in FIG. 2A.
  • the display substrate 20 includes a base substrate, a first signal line 23, and a second signal line 24.
  • the base substrate includes a first opening area 202A, a display area 201 and a frame area 204.
  • the first opening area 202A includes a first opening 201A and a first opening peripheral area 203A surrounding the first opening 201A; the display area 201 surrounds the first opening area 202A, and the frame area 204 surrounds the display area 201.
  • the display area 201 includes pixels arranged in an array, and each pixel includes one or more sub-pixels, and also includes various signal lines for transmitting various electrical signals to the sub-pixels to realize the display function; the frame area 204 includes various sub-pixels.
  • a driving circuit, signal lines that electrically connect the sub-pixels, contact pads, etc., and the signal lines of the frame area 204 are electrically connected (or integrally formed) with the signal lines (such as gate lines, data lines, etc.) in the display area 201 to provide the sub-pixels. Electrical signals (such as scan signals, data signals, etc.).
  • the first opening 201A is set to allow light from the display side of the display substrate to pass through to reach the camera and the distance sensor to realize light sensing, thereby realizing functions such as image shooting and distance sensing; for example, in the area corresponding to the first opening 201A
  • a camera, a distance sensor, and other devices can be arranged on the back side of the display substrate (that is, the side opposite to the display side), and the camera, the distance sensor, etc. are at least partially exposed through the first opening 201A.
  • various signal lines from the frame area 204 extend through the display area 201.
  • these signal lines pass through the first opening peripheral area 203A and bypass the first opening 201A, and then enter the display area.
  • electrical signals such as scanning signals, data signals, etc.
  • these signal lines may not be provided in the first opening 201A to increase the light transmittance of the first opening 201A .
  • the display area 201 includes a first display area 2011 and a second display area 2012.
  • the first display area 2011 is located on the first side of the first opening area 202A
  • the second display area 2012 is located on the second side of the first opening area 202A.
  • the first side and the second side are in the first direction R1 (in the figure) In the horizontal direction) are opposite to each other.
  • the first display area 2011, the first opening peripheral area 203A, and the second display area 2012 are sequentially arranged along the first direction R1.
  • the whole formed by the first display area 2011 and the second display area 2012 includes a first pixel array.
  • the first pixel array includes a plurality of pixels arranged in an array, each pixel includes a plurality of sub-pixels, and each sub-pixel includes a pixel circuit.
  • the display substrate includes a plurality of first signal lines 2301/2302/2303/2304/2305/2306, and the first signal line 2301 is configured to provide a first pixel array with a Display signals, and sequentially pass through the first display area 2011, the first opening peripheral area 203A, and the second display area 2012 along the first direction R1, thereby electrically connecting the first display area 2011 and the first display area 2011 on opposite sides of the first opening 201A.
  • the sub-pixels in the second display area 2012 for example, provide the first display signal for the sub-pixels of the plurality of pixels in the first display area 2011 and the second display area 2012 that are at the same horizontal position as the first opening peripheral area 203A.
  • the first display signal may be, for example, a gate scan signal, a light emission control signal, or a reset voltage signal in any form of electrical signal.
  • a plurality of first signal lines 2301/2302/2303/2304/2305/2306 can provide scan signals, light emission control signals, reset voltage signals, etc. for the pixel circuits in the first display area 2011 and the second display area 2012 of the display area.
  • Fig. 2C is a schematic cross-sectional view taken along the line I-I' in Fig. 2B. 2B and 2C
  • the first signal line 2301 includes a first lead portion E1A1/E2A2 located in the peripheral area of the first opening 203A (that is, taking a first signal line as an example, for example, the first lead portion is the one in FIG. 2B
  • the straight line segment E1A1 and the straight line segment E2A2 and the first winding part A1A2 located in the first opening peripheral area 203A that is, the first winding part is the curved segment A1A2 in FIG. 2B
  • the first winding part A1A2 partially surrounds the first
  • the opening 201A is provided.
  • the second signal line 24 is configured to provide a second display signal to the first pixel array, and passes through the first opening peripheral area 203A in a second direction R2 that intersects the first direction R1, and includes a second opening peripheral area 203A located in the first opening peripheral area 203A.
  • the winding part C1C2, that is, the second winding part is the curved section C1C2 in FIG. 2B; the second winding part C1C2 is partially arranged around the first opening 201A.
  • the orthographic projection of the first lead portion E1A1/E2A2 on the base substrate and the orthographic projection of the second signal line 24 on the base substrate respectively have a first overlap area S1/S2, that is, the area where the two intersect.
  • the orthographic projection of the first winding portion A1A2 on the base substrate and the orthographic projection of the second winding portion C1C2 on the base substrate have a second overlap area, for example, the two overlap in the A1C1 section and the D1A2 section, and the second overlap The area is the area represented by A1C1 and D1A2.
  • a compensation capacitor is formed between the first signal line 2301 and the second signal line 24 that overlap each other in the direction perpendicular to the base substrate, thereby compensating for the first signal.
  • the above wiring method can also reduce the arrangement space of the first signal line and the second signal line, and reduce the area occupied by the peripheral area 203A of the first opening as much as possible.
  • the influence of the first opening area 202A on the display effect of the area is reduced, or, in other embodiments, when the first opening peripheral area 203A is located in the frame area 204 In the middle, the width of the frame area 204 can also be reduced, thereby helping to achieve a narrow frame and large-screen design of the display substrate 20.
  • the orthographic projection of the lead portion E1A1 of the first signal line 2301 on the base substrate and the orthographic projection of the second winding portion of the second signal line 24 on the base substrate have a first overlap. Area.
  • the lead portion E1A1 of the same first signal line 2301 and the plurality of second signal lines 24 may form a first overlapping area, that is, the lead portion E1A1 of the same first signal line 2301 may be connected to the plurality of second signal lines 24.
  • Crossing so as to increase the compensation capacitance formed by the first overlap area to a greater extent, and to increase the load of the first signal line 2301 to a greater extent.
  • the present disclosure implements For example, the space in the peripheral area of the first opening surrounding the first opening can be fully utilized to meet the requirements of a larger range of compensation capacitors, and the amplitude of the compensation capacitor formed by the second overlapping area can be enlarged.
  • the first winding portion A1A2 extends from the first side of the first opening 201A around the first opening 201A to the second side of the first opening 201A, and the first side of the first opening 201A is connected to the second side of the first opening 201A.
  • the sides are opposite to each other in the first direction R1;
  • the second winding portion C1C2 extends from the third side of the first opening 201A around the first opening 201A to the fourth side of the first opening 201A, and the third side of the first opening 201A
  • the fourth sides of the first opening 201A are opposed to each other in the second direction R2.
  • the planar shape of the first winding portion A1A2 and the planar shape of the second winding portion C1C2 each constitute a part of the concentric ring of the planar shape of the first opening 201A.
  • the planar shape of the first opening 201A is circular, and the planar shape of the first winding portion A1A2 and the planar shape of the second winding portion C1C2 each constitute a part of the circular concentric ring.
  • the planar shape of the first winding portion A1A2 and the planar shape of the second winding portion C1C2 are both circular arcs, that is, the planar shape of the first winding portion and the planar shape of the second winding portion include circular arcs.
  • the first winding portion A1A2 and the second winding portion C1C2 match the shapes of the first opening 201A and the first opening peripheral area 203A.
  • This design makes full use of the area of the first opening peripheral area 203A to facilitate reduction
  • the area occupied by the peripheral area 203A of the first opening is reduced, and the area of the display area occupied by the first opening area 202A is reduced.
  • the first display area 2011 and the second display area 2012 include multiple rows of pixels separated by the first opening area 202A, and the multiple rows of pixels of the first display area 2011 and the second display area 2012
  • the rows of pixels correspond to each other one-to-one.
  • the pixels of the nth row (n is a positive integer) of the first display area 2011 correspond to the pixels of the nth row of the second display area 2012, and they are located in the same row from the perspective of the display effect, so they are regarded as in the display area 201 in this article.
  • the first pixel array includes a first pixel row and a second pixel row respectively extending in a first direction R1, the first pixel row and the second pixel row are arranged in the second direction R2, and the first pixel row and the second pixel row are arranged in the second direction R2.
  • the rows are all broken by the first opening area 202A.
  • FIG. 2F shows a schematic plan view of the pixel arrangement near the first opening area 2011.
  • the first and sixth rows are full of pixel rows
  • the second to fifth rows are pixel rows on both sides of the first opening area 2011 in FIG. 2B. Full row of pixels.
  • FIG. 2F shows a schematic plan view of the pixel arrangement near the first opening area 2011.
  • the display substrate 20 includes a plurality of first signal lines 23.
  • the plurality of first signal lines 23 include a first signal line 2301 configured to provide a first display signal to a first pixel row and a first signal line 2301 configured to provide a second pixel row.
  • the pixel row provides the first signal line 2302 of the first display signal.
  • the first pixel row and the second pixel row may be two adjacent pixel rows, such as the second row and the third row shown in FIG. 2F, respectively; for another example, the first pixel row and the second pixel row It may be two non-adjacent pixel rows, for example, the second row and the fourth row shown in FIG. 2F, respectively.
  • the first signal line 2301 and the first signal line 2302 are provided in the same layer.
  • the first winding portion A1A2 of the first signal line 2301 protrudes toward the third side of the first opening 201A and partially surrounds the first opening 201A on the third side of the first opening 201A.
  • the first winding portion B1B2 of the first signal line 2302 protrudes toward the fourth side of the first opening 201A and partially surrounds the first opening 201A on the fourth side of the first opening 201A.
  • the first signal line 2301 provides the first display signal for the first pixel rows arranged along the first direction R1 in the first display area 2011 and the second display area 2012.
  • the first signal line 2302 provides a first display signal for the second pixel rows arranged along the first direction R1 in the first display area 2011 and the second display area 2012.
  • the first signal line 2301 and the first signal line 2302 are gate scan signal lines, and correspondingly, the first display signal is a gate scan signal.
  • the first signal line 2301 and the first signal line 2302 are gate scan signal lines (also referred to as gate lines) that provide gate scan signals to different pixel rows in the first display area 2011 and the second display area 2012. .
  • one second signal line 24 and two different first signal lines at least partially overlap in the direction perpendicular to the base substrate, and the two first signal lines give two different signals to the first pixel array.
  • the pixel row provides the first display signal.
  • the orthographic projections of the first winding portion B1B2 of the first signal line 2302 and the second winding portion C1C2 of the second signal line 24 on the base substrate partially overlap, for example, the two overlap in the A1C1 section and the B1C2 section.
  • a compensation capacitor is formed between the first signal line 2302 and the second signal line 24 that overlap each other in the direction perpendicular to the base substrate, and the load on the first signal line 2302 is compensated.
  • the first pixel array includes a first pixel column and a second pixel column respectively extending along the second direction R2, and the first pixel column and the second pixel column are arranged in the first direction R1.
  • the display substrate 20 includes a plurality of second signal lines 24, and the plurality of second signal lines 24 include a second signal line 241 configured to provide a second display signal to a first pixel column and a second signal line 241 configured to provide a second pixel column with the second signal line. 2.
  • the second signal line 242 for displaying signals.
  • the first pixel column and the second pixel column may be two adjacent pixel columns, such as the seventh column and the eighth row shown in FIG.
  • first pixel column and the second pixel column may also be two non-adjacent pixel columns, such as the seventh column and the ninth column shown in FIG. 2F, respectively.
  • the second winding portion C1C2 of the second signal line 241 protrudes toward the first side of the first opening 201A and partially surrounds the first opening 201A on the first side of the first opening 201A; the second winding portion of the second signal line 242
  • the line portion D1D2 protrudes toward the second side of the first opening 201A and partially surrounds the first opening 201A on the second side of the first opening 201A to avoid affecting the light transmittance of the first opening 201A.
  • FIG. 2F is only exemplary, and the number of pixel rows and pixel columns in the embodiment of the present disclosure is not limited to the number shown in FIG. 2F.
  • first winding portion A1A2 of the first signal line 2301 and the first winding portion B1B2 of the first signal line 2302 are substantially symmetrical with respect to the symmetry axis along the first direction R1.
  • the second winding portion C1C2 of the second signal line 241 and the second winding portion D1D2 of the second signal line 242 are substantially symmetrical with respect to the symmetry axis along the second direction R2.
  • the first winding portion A1A2 and the second winding portion C1C2 match the shapes of the first opening 201A and the first opening peripheral area 203A.
  • This design makes full use of the area of the first opening peripheral area 203A to facilitate reduction
  • the area occupied by the peripheral area 203A of the first opening is reduced, and the area of the display area occupied by the first opening area 202A is reduced.
  • the adverse effect of the area display effect is reduced.
  • first winding portion A1A2 of the first signal line 2301 and the first winding portion B1B2 of the first signal line 2302 may not be symmetrical with respect to the symmetry axis along the first direction R1;
  • the second winding portion C1C2 of the second signal line 241 and the second winding portion D1D2 of the second signal line 242 may not be substantially symmetrical with respect to the symmetry axis along the second direction R2.
  • first signal line 2301 and the first signal line 2302 Similar to the first signal line 2301 and the first signal line 2302, the same is true for the first signal line 2303 and the first signal line 2304. It should be understood that this embodiment only takes the first signal line and the second signal line shown as an example, and is not limited to only the first signal line and the second signal line shown in FIG. 2B.
  • the display substrate 20 further includes a third display area 2013.
  • the third display area 2013 includes a first portion 2013C located on the first side of the first display area 2011 and the second display area 2012 in the second direction R2, and a first portion 2013C located on the first side of the first display area 2011 and the second display area 2012 in the second direction R2.
  • the second portion 2013D of the second side of the display area 2012, the first side of the first display area 2011 and the second display area 2012 and the second side of the first display area 2011 and the second display area 2012 are in the second direction R2 Opposite each other; the first part 2013C and the second part 2013D are both connected to the first display area 2011 and the second display area 2012.
  • the two edges 2013A and 2013B of the first portion 2013C of the third display area 2013 that are opposite to each other in the second direction R2 are respectively aligned with the edges of the first display area 2011 that extend along the second direction R2 and are away from the first opening 201A.
  • 2011A and the edge 2012A of the second display area 201 extending along the second direction R2 and away from the first opening 201A are aligned.
  • the third display area 2013 includes a second pixel array, and the second pixel array includes multiple rows and multiple columns of pixels.
  • the display substrate 20 further includes a plurality of third signal lines 2307, and the plurality of third signal lines 2307 are located in the first portion 2013C and the second portion 2013D of the third display area 2013.
  • the third signal lines 2307 are configured to respectively provide third scan signals to the pixels in the second pixel array and extend along the first direction R1; for example, in this embodiment, the second signal lines 24 are sequentially along the second direction R2. It passes through the second portion 2013D of the third display area 2013, the first opening peripheral area 203A, and the first portion 2013C of the third display area 2013, and is configured to provide second display signals to multiple columns of pixels in the second pixel array.
  • the third display area 2013 also includes a plurality of pixels, each pixel includes a plurality of sub-pixels, and each sub-pixel includes a pixel circuit.
  • Each pixel of the third display area 2013 may have the same structure as each pixel of the first display area and the second display area.
  • the number of pixels included in each row of pixels in multiple rows and multiple columns of sub-pixels in the third display area 2013 is substantially the same.
  • the number of pixels electrically connected to the plurality of third signal lines 2037 is substantially the same, so the plurality of third signal lines 2037 have substantially the same load.
  • each row of pixels in multiple rows and multiple columns includes more pixels than the first pixel row of the first pixel array and more pixels than the second pixel row of the first pixel array.
  • the load of each first signal line 2301/2302/2303/2304 after load compensation is basically the same as the load of the multiple third signal lines 2037, and each first signal line 2301/2302/2303/2304 is
  • the signal transmission speed of each third signal line 2037 is basically the same, and the deviation between the actual display signal transmitted to the pixel circuit of the sub-pixel and the design value is basically the same, so that the display consistency of the display area 201 can be maintained, and the display substrate can be improved. 20 display effect.
  • the second signal line 24 is a data line and is configured to provide the sub-pixel with a data signal for controlling the light-emitting gray level of the sub-pixel.
  • the display substrate 20 further includes a first power supply line VDD, the first power supply line VDD is connected to the first voltage terminal and is configured to provide a first power supply voltage to the pixel circuits of one or more sub-pixels.
  • the first power supply line VDD includes a plurality of first sub-wiring lines 2421/2422 extending in the first direction R1 and a plurality of second sub-wiring lines 2423/2424 extending in the second direction R2.
  • the first part of the first sub-wiring 2421 among the plurality of first sub-wiring 2421/2422 is disconnected in the first opening area 202A, and the second part of the first sub-wiring 2422 among the plurality of first sub-wiring 2421/2422 Through the third display area.
  • the first sub-wiring 2422 penetrates the first portion 2013C of the third display area 2013 along the first direction R1.
  • the first part of the second sub-wiring 2423 of the multiple second sub-wiring 2423/2424 is disconnected in the first opening area 202A, and the second part of the second sub-wiring 2424 of the multiple second sub-wiring 2423/2424
  • the first display area 2011 and the third display area 2013 are sequentially passed through, for example, in this embodiment, the second portion 2013D of the third display area 2013, the first display area 2011, and the first portion 2013C of the third display area 2013 are sequentially passed through.
  • the second sub-wiring 2424 sequentially passes through the second display area 2012 and the third display area 2013, for example, in this embodiment, passes through the second portion 2013D, the second display area 2012, and the third display area of the third display area 2013 in order.
  • the first part of area 2013 is 2013C.
  • At least one of the first sub-wiring 2421 of the first part and the second sub-wiring 2424 of the second part 2424 is electrically connected in the first display area 2011 and the second display area 2012, and the second sub-travel of the first part
  • the line 2423 is electrically connected to at least one of the first sub-wiring 2422 in the second part of the first sub-wiring 2422 in the third display area 2013, so as to provide uniformity for the sub-pixels in each row and column of the first pixel array and the second pixel array.
  • the planar shape of the first opening area of the display substrate provided by at least one embodiment of the present disclosure is not limited to a circular shape, for example, it may also be a regular pattern such as a rectangle and an ellipse, or an irregular pattern such as a racetrack shape and a drop shape. In these cases, the arrangement principles and technical effects of the first signal line and the second signal line are the same as or similar to those of the circular example described above.
  • FIG. 2D is a schematic plan view of another display substrate according to an embodiment of the disclosure.
  • the first opening area 202A is a rectangular groove.
  • the first opening area 202A is located at one end of the display area 201, there is no display area on the upper side of the first opening area 202A, and the display area 201 partially surrounds the first opening area 202A.
  • FIG. 2D is a schematic plan view of another display substrate according to an embodiment of the disclosure.
  • the first opening area 202A is a rectangular groove.
  • the first opening area 202A is located at one end of the display area 201, there is no display area on the upper side of the first opening area 202A, and the display area 201 partially surrounds the first opening area 202A.
  • FIG. 2D is a schematic plan view of another display substrate according to an embodiment of the disclosure.
  • the first opening area 202A is a rectangular groove.
  • the first opening area 202A is located at one end of the display area 201, there is no display area on
  • the first opening region 202A is located at a position lower than the middle of the entire display substrate, for example, a photoelectric conversion device is provided in the first opening 201A for fingerprint recognition; and
  • the planar shape of the opening region 202A and the planar shape of the first opening 201A are both rectangular, and the planar shape of the first opening peripheral region 203A is a rectangular ring surrounding the rectangle.
  • the planar shape distribution of the bent portion of the first signal line and the bent portion of the second signal line constitutes a part of a rectangular ring surrounding the rectangle, for example, the rectangular ring is the rectangular ring.
  • concentric rings are concentric rings.
  • FIG. 3A is a schematic cross-sectional view of the display area of the display substrate in FIG. 2A along the line A-A'
  • FIG. 3B is another schematic cross-sectional view of the display area of the display substrate in FIG. 2A along the line A-A'.
  • the pixel circuit of each sub-pixel in the display area 201 of the display substrate 20 includes a transistor, which is described by taking a thin film transistor (TFT) as an example, a light-emitting element 180, and a storage capacitor Cst.
  • the thin film transistor includes an active layer 120, a gate 121, and source and drain electrodes 122/123; the storage capacitor Cst includes a first plate CE1 and a second capacitor plate CE2.
  • the light emitting element 180 includes a cathode 183, an anode 181, and a light emitting layer 182 between the cathode 183 and the anode 181.
  • the anode 181 is electrically connected to one of the source and drain electrodes 122/123 of the thin film transistor TFT, such as the drain electrode 123.
  • the light-emitting element may be, for example, an organic light-emitting diode (OLED) or a quantum dot light-emitting diode (QLED), and correspondingly, the light-emitting layer 182 is an organic light-emitting layer or a quantum dot light-emitting layer.
  • the gate 121, the entire first signal line 2301 and the first electrode plate CE1 of the storage capacitor Cst are arranged in the same layer.
  • the part of the first signal line 2301/2032 shown in FIG. Part of 2011 and the second display area 2012 are arranged in different layers (that is, arranged in different layers from the gate 121 and the first electrode plate CE1 of the storage capacitor Cst).
  • the portion of the first signal line 2301/2032 located in the first opening peripheral area 203A is electrically connected to the portion of the first signal line 2301/2032 located in the first display area 2011 and the second display area 2012 through the via hole. .
  • the gate 121 and the part of the first signal line 2301/2032 located in the first display area 2011 and the second display area 2012 and the first electrode plate CE1 of the storage capacitor Cst are arranged in the same layer; the first signal line 2301/ The portion of 2032 located in the peripheral area 203A of the first opening is arranged on the same layer as the second plate CE2 of the storage capacitor Cst.
  • the structure arranged in the same layer can be formed by a patterning process, thereby simplifying the manufacturing process of the display substrate 20.
  • the other structures of the embodiment shown in FIG. 3B are the same as those in FIG. 3A, please refer to the description of FIG. 3A.
  • the display area 201 further includes a first gate insulating layer 151 located between the active layer 120 and the gate electrode 121, a second gate insulating layer 152 located above the gate electrode 121, and an interlayer insulating layer 160.
  • the second gate insulating layer 152 is located between the first electrode plate CE1 and the second capacitor electrode plate CE2, so that the first electrode plate CE1, the second gate insulating layer 152 and the second capacitor electrode plate CE2 constitute a storage capacitor Cst.
  • the interlayer insulating layer 160 covers the second capacitor plate CE2.
  • the display area 201 further includes an insulating layer 113 (for example, a passivation layer) covering the pixel circuit and a first planarization layer 112.
  • the display area 201 further includes a pixel defining layer 170 for defining a plurality of sub-pixels, and spacers (not shown) on the pixel defining layer 170 and other structures. As shown in FIG. 3A, the display area 201 further includes an insulating layer 113 (for example, a passivation layer) covering the pixel circuit and a first planarization layer 112.
  • the display area 201 further includes a pixel defining layer 170 for defining a plurality of sub-pixels, and spacers (not shown) on the pixel defining layer 170 and other structures. As shown in FIG.
  • the insulating layer 113 is located above the source and drain electrodes 122/123 (for example, the passivation layer is formed of silicon oxide, silicon nitride, or silicon oxynitride), and the insulating layer 113 is located above There is a first planarization layer 112, and the anode 181 is electrically connected to the drain 123 through a via hole penetrating the first planarization layer 112 and the insulating layer 113.
  • the first opening peripheral area 203A of the display substrate 20 further includes encapsulation layers 291, 292, and 293.
  • the display area 201 further includes an encapsulation layer 190, and the encapsulation layer 190 includes a plurality of encapsulation sublayers 191/192/193.
  • the encapsulation layer 190 is not limited to three layers, and may also be two layers, or four, five or more layers.
  • the first encapsulation layer 291 and the first encapsulation sublayer 191 in the encapsulation layer 190 are provided on the same layer
  • the second encapsulation layer 292 is provided on the same layer as the second encapsulation sublayer 192 in the encapsulation layer 190
  • the third encapsulation layer 293 is provided on the same layer as the first encapsulation sublayer 191 in the encapsulation layer 190.
  • the third encapsulation sublayer 193 in the encapsulation layer 190 is arranged in the same layer.
  • both the first encapsulation layer 291 and the third encapsulation layer 293 may include inorganic encapsulation materials, such as silicon oxide, silicon nitride, or silicon oxynitride.
  • the second encapsulation layer 292 may include organic materials, such as resin materials.
  • the multi-layer packaging structure of the display area 201 and the first opening peripheral area 203A can achieve a better packaging effect to prevent impurities such as water vapor or oxygen from penetrating into the display substrate 20.
  • the display substrate further includes a buffer layer 111 on the base substrate 210.
  • the buffer layer 111 serves as a transition layer to prevent harmful substances in the base substrate 210 from intruding into the interior of the display substrate 20. , It can increase the adhesion of the film in the display substrate 20 on the base substrate 210.
  • the material of the buffer layer 111 may include a single-layer or multi-layer structure formed of insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride.
  • FIG. 3C is another schematic cross-sectional view of the display area of the display substrate in FIG. 2A along the line A-A', and FIG. 3C only shows a partial cross-sectional view of the display area.
  • the difference from the display area shown in FIG. 3A is that in the display area shown in FIG.
  • the transfer electrode 171 is covered with the second planarization layer 114, for example, the second planarization layer 114 is covered on the first planarization layer 112.
  • the second planarization layer 114 in the cross-sectional view of the display area 201 on the left in FIG. 3C extends into the first opening peripheral area 203A, thereby forming the cross-sectional view of the first opening peripheral area 203A on the right in FIG. 3C Structure.
  • the display area of the display substrate may not have the insulating layer 113 and the second planarization layer 114.
  • the base substrate 210 may be a glass substrate, a quartz substrate, a metal substrate, a resin substrate, or the like.
  • the material of the base substrate 210 may include an organic material.
  • the organic material may be polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, and polyethylene terephthalate. Resin materials such as esters and polyethylene naphthalate.
  • the base substrate 210 may be a flexible substrate or a non-flexible substrate, which is not limited in the embodiment of the present disclosure.
  • the material of any one of the first gate insulating layer 151, the second gate insulating layer 152, the interlayer insulating layer 160, the first planarization layer 112, the pixel defining layer 170, and the spacers may include silicon oxide, silicon nitride , Inorganic insulating materials such as silicon oxynitride, or may include organic insulating materials such as polyimide, polyphthalimide, polyphthalamide, acrylic resin, benzocyclobutene, or phenolic resin.
  • the embodiments of the present disclosure do not specifically limit the materials of the first gate insulating layer 151, the second gate insulating layer 152, the interlayer insulating layer 160, the first planarization layer 112, the pixel defining layer 170, and the spacers.
  • the materials of the first gate insulating layer 151, the second gate insulating layer 152, the interlayer insulating layer 160, the first planarization layer 112, the second planarization layer 114, the pixel defining layer 170, and the spacers may be the same or the same as each other.
  • the parts are the same, and may also be different from each other, which is not limited in the embodiments of the present disclosure.
  • the display substrate 20 may further include a barrier wall 28 located in the peripheral area 203A of the first opening and at least partially surrounding the first opening 201A.
  • the barrier wall 28 at least partially overlaps the first signal line and the second signal line.
  • the barrier wall 28 can provide barrier and support in the peripheral area 203A of the first opening, maintain the stability of the first opening 201A, protect the photoelectric sensor components such as the camera in the first opening 201A, and block harmful impurities such as water vapor and oxygen from passing through the first opening.
  • 201A diffuses into the display area, thereby preventing harmful impurities from deteriorating the pixel circuit in the display area.
  • FIGS. 5A-5E are schematic diagrams of various layers of a pixel circuit in a display substrate provided by some embodiments of the present disclosure.
  • the pixel circuit includes a plurality of thin film transistors: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and The seventh transistor T7, the multiple signal lines connected to the multiple thin film transistors T1, T2, T3, T4, T5, T6, and T7, and the storage capacitor Cst, that is, the pixel circuit in this embodiment has a 7T1C structure.
  • the plurality of signal lines include gate lines GLn/GLn-1 (ie, scan signal lines), light emission control lines EM, initialization lines RL, data lines DATA, and first power supply lines VDD.
  • the gate line GLn/GLn-1 may include a first gate line GLn and a second gate line GLn-1.
  • the first gate line GLn is used to transmit a gate scan signal
  • the second gate line GLn-1 is used to transmit a reset voltage signal.
  • the so-called first emission control line EM1 refers to a signal line connected to the first emission control terminal EM1 and configured to provide the first emission control signal to the first emission control terminal EM1) and the second emission control terminal EM2 (hereinafter referred to as
  • the second light-emitting control line EM2 refers to a signal line connected to the second light-emitting control terminal EM2 and configured to provide a second light-emitting control signal to the second light-emitting control terminal EM2).
  • the gate of the fifth transistor T5 is connected to the first light emission control terminal EM1, or used as the first light emission control terminal EM1 to receive the first light emission control signal; the gate of the sixth transistor T6 is connected to the second light emission control terminal EM2, or As the second light emission control terminal EM2, to receive the second light emission control signal.
  • the above-mentioned first signal line is a gate line GLn/GLn-1 (that is, a gate scan signal line), and correspondingly, the first display signal is a gate scan signal.
  • the first signal line 23 may further include a light-emitting control line connected to the light-emitting control terminal.
  • the first signal line 2305/2306 shown in FIG. 2B can be connected to the first emission control terminal EM1 or the second emission control terminal EM2, and the first emission control terminal EM1 or the The two light-emitting control terminals EM2 and the second signal line at least partially overlap to compensate the load of the first light-emitting control terminal EM1 or the second light-emitting control terminal EM2, and improve the display uniformity of the entire display area 201.
  • the embodiments of the present disclosure include, but are not limited to, the above-mentioned 7T1C structure pixel circuit.
  • the pixel circuit may also adopt other types of circuit structures, such as 7T2C structure or 9T2C structure, which is not limited by the embodiment of the present disclosure.
  • the first gate of the first thin film transistor T1 is electrically connected to the third drain D3 of the third thin film transistor T3 and the fourth drain D4 of the fourth thin film transistor T4.
  • the first source S1 of the first thin film transistor T1 is electrically connected to the second drain D2 of the second thin film transistor T2 and the fifth drain D5 of the fifth thin film transistor T5.
  • the first drain electrode D1 of the first thin film transistor T1 is electrically connected to the third source electrode S3 of the third thin film transistor T3 and the sixth source electrode S6 of the sixth thin film transistor T6.
  • the second gate of the second thin film transistor T2 is configured to be electrically connected to the first gate line GLn to receive the gate scan signal;
  • the second source S2 of the second thin film transistor T2 is configured To be electrically connected to the data line DATA to receive data signals;
  • the second drain electrode D2 of the second thin film transistor T2 is electrically connected to the first source electrode S1 of the first thin film transistor T1.
  • the third gate electrode of the third thin film transistor T3 is configured to be electrically connected to the first gate line GLn, and the third source electrode S3 of the third thin film transistor T3 is connected to the first gate line GLn of the first thin film transistor T1.
  • the drain electrode D1 is electrically connected, and the third drain electrode D3 of the third thin film transistor T3 is electrically connected to the first gate electrode of the first thin film transistor T1.
  • the fourth gate of the fourth thin film transistor T4 is configured to be electrically connected to the second gate line GLn-1 to receive the reset voltage signal
  • the fourth source S4 of the fourth thin film transistor T4 is configured
  • the fourth drain electrode D4 of the fourth thin film transistor T4 is electrically connected to the first gate electrode of the first thin film transistor T1.
  • the fifth gate electrode of the fifth thin film transistor T5 is configured to be electrically connected to the light emission control line EM to receive the light emission control signal
  • the fifth source electrode S5 of the fifth thin film transistor T5 is configured to be connected to the light emission control line EM.
  • a power line VDD is electrically connected to receive the first power signal
  • the fifth drain electrode D5 of the fifth thin film transistor T5 is electrically connected to the first source electrode S1 of the first thin film transistor T1.
  • the sixth gate of the sixth thin film transistor T6 is configured to be electrically connected to the emission control line EM to receive the emission control signal, and the sixth source S6 of the sixth thin film transistor T6 is connected to the first thin film transistor.
  • the first drain D1 of T1 is electrically connected, and the sixth drain D6 of the sixth thin film transistor T6 is electrically connected to the first display electrode (for example, the anode) of the light-emitting element 180.
  • the thin film transistor TFT in FIGS. 3A-3C is the sixth thin film transistor T6.
  • the seventh gate of the seventh thin film transistor T7 is configured to be electrically connected to the second gate line GLn-1 to receive the reset voltage signal
  • the seventh source S7 of the seventh thin film transistor T7 is The first display electrode (for example, the anode 181) of the element 180 is electrically connected
  • the seventh drain D7 of the seventh thin film transistor T7 is configured to be electrically connected to the initialization line RL to receive the initialization voltage signal.
  • the seventh drain electrode D7 of the seventh thin film transistor T7 may be electrically connected to the initialization line RL by being connected to the fourth source electrode S4 of the fourth thin film transistor T4.
  • the storage capacitor Cst includes a first electrode plate CE1 and a second electrode plate CE2.
  • the second electrode plate CE2 is electrically connected to the first power line VDD
  • the first electrode plate CE1 is electrically connected to the first gate electrode of the first thin film transistor T1 and the third drain electrode D3 of the third thin film transistor T3.
  • the first power supply line VDD includes a first sub-wiring 2422 and a second sub-wiring 2424.
  • the first power line VDD is connected to the first voltage terminal; for example, the second sub-wiring 2424 is connected to the second plate CE2 of the storage capacitor through a third via VH3; for example, the second sub-wiring 2424 is connected to the second electrode of the storage capacitor.
  • the board CE2 is integrally formed, and the second sub-line 2422 and the first sub-line 2422 are connected through the ninth via VH9.
  • the second display electrode (for example, the cathode 183) of the light-emitting element 180 is electrically connected to the second power line VSS.
  • the first power line VDD provides a high voltage power line for the pixel circuit
  • the second power line VSS is connected to the second voltage terminal and the second power line VSS provides a low voltage (lower than the aforementioned high voltage) power line for the pixel circuit.
  • the first power supply line VDD provides a constant first power supply voltage, and the first power supply voltage is a positive voltage
  • the second power supply line VSS provides a constant second power supply voltage
  • the second power supply voltage can be It is negative voltage and so on.
  • the second power supply voltage may be a ground voltage.
  • the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other switching devices with the same characteristics.
  • the thin film transistors may include oxide semiconductor thin film transistors, amorphous silicon thin film transistors, or polysilicon thin film transistors.
  • the source and drain of the transistor can be symmetrical in structure, so the source and drain can be indistinguishable in physical structure. In the embodiments of the present disclosure, all or part of the source and drain of the transistor are as required Are interchangeable.
  • the pixel circuit includes the aforementioned thin film transistors T1, T2, T3, T4, T5, T6, and T7, a storage capacitor Cst, and a plurality of thin film transistors T1, T2, T3, and T4. , T5, T6, and T7 of the first gate line GLn, the second gate line GLn-1, the light emission control line EM, the initialization line RL, the data line DATA, and the first power supply line VDD.
  • FIG. 5A is a schematic layout diagram of the stacked position relationship of the semiconductor layer, the first conductive layer, the second conductive layer, and the third conductive layer of the pixel circuit.
  • FIG. 5C shows the semiconductor layer of the pixel circuit.
  • the semiconductor layer shown in FIG. 5C includes the active layer 120 shown in FIG. 3A, and the active layer 120 is, for example, the active layer of the sixth thin film transistor T6.
  • the semiconductor layer can be formed by a patterning process using a semiconductor material layer.
  • the semiconductor layer can be used to make the aforementioned first thin film transistor T1, second thin film transistor T2, third thin film transistor T3, fourth thin film transistor T4, fifth thin film transistor T5, sixth thin film transistor T6, and seventh thin film transistor T7.
  • the source layer, each active layer may include a source region, a drain region, and a channel region between the source region and the drain region.
  • the semiconductor layer can be made of amorphous silicon, polysilicon, oxide semiconductor materials (for example, indium gallium tin oxide (IGZO)), or the like.
  • oxide semiconductor materials for example, indium gallium tin oxide (IGZO)
  • the aforementioned source region and drain region may be regions doped with n-type impurities or p-type impurities.
  • the semiconductor layer of the pixel circuit can be formed in the same layer as the semiconductor pattern in the first opening peripheral area 203A (when the first opening peripheral area 203A includes the first dummy pixel, the semiconductor pattern is the semiconductor layer of the first dummy pixel, This will be described in detail below), that is, the semiconductor layer of the pixel circuit and the semiconductor pattern in the first opening peripheral region 203A can be formed using the same semiconductor material layer through the same patterning process.
  • an insulating layer is formed on the aforementioned semiconductor layer; for clarity, the insulating layer is not shown in FIGS. 5A and 5C-5F.
  • FIG. 5D shows the first conductive layer of the pixel circuit.
  • the first conductive layer of the pixel circuit is provided on the above-mentioned insulating layer so as to be insulated from the semiconductor layer shown in FIG. 5D.
  • the first conductive layer may include the first plate CE1 of the storage capacitor Cst, the first gate line GLn, the second gate line GLn-1, the light emission control line EM, and the first thin film transistor T1, the second thin film transistor T2, and the third The gates of the thin film transistor T3, the fourth thin film transistor T4, the fifth thin film transistor T5, the sixth thin film transistor T6, and the seventh thin film transistor T7. As shown in FIG.
  • the gates of the second thin film transistor T2, the fourth thin film transistor T4, the fifth thin film transistor T5, the sixth thin film transistor T6, and the seventh thin film transistor T7 are the first gate line GLn and the second gate line GLn- 1 The part that overlaps the semiconductor layer.
  • the third thin film transistor T3 may be a thin film transistor with a double-gate structure, one gate of the third thin film transistor T3 may be the part where the first gate line GLn overlaps the semiconductor layer, and the other gate of the third thin film transistor T3 may be A protrusion protruding from the first gate line GLn; the gate of the first thin film transistor T1 may be the first electrode plate CE1.
  • the fourth thin film transistor T4 may be a thin film transistor with a double-gate structure, and the two gates are respectively the overlapping portions of the second gate line GLn-1 and the semiconductor layer.
  • the gates of the above-mentioned thin film transistors are respectively integrally formed with the corresponding first gate line GLn or the second gate line GLn-1.
  • the first signal line 2301/2302/2303/2304 shown in FIG. 2B is the first gate line GLn or the second gate line GLn-1, that is, the gate of each thin film transistor, the first signal line, and the storage capacitor Cst.
  • the first electrode plate CE1 is arranged in the same layer and can be formed at the same time through the same patterning process.
  • the above-mentioned first signal line 2301 is a first gate line GLn; for example, in some embodiments, the first signal line 2301 may further include a second gate line GLn-1.
  • the above-mentioned first signal line 2301 is taken as the first gate line GLn as an example.
  • the first gate line 5D extends from the first display area 2011 into the first opening peripheral area 203A, and then extends from the first opening peripheral area 203A to the second display area 2012, the first gate line
  • the portion of the GLn located in the first opening peripheral area 203A is arranged in the same layer as the portion of the first gate line GLn located in the first display area 2011 and the second display area 2012.
  • the gates and gate lines of multiple thin film transistors are arranged in the same layer, for example, integrally formed, this situation is the situation shown in FIG. 3A, and the entire first gate line GLn (that is, the first signal line 2301/2302)
  • the gate electrode 121 and the first electrode plate CE1 of the storage capacitor Cst are arranged in the same layer.
  • the second gate line GLn-1 may also be provided in the same layer as the first gate line GLn.
  • the first electrode plate CE1 of the storage capacitor Cst and the first gate line GLn that is, the first signal line 2301 are spaced apart from each other, so that the two are not electrically connected, nor are there between them.
  • the gate and the first gate line GLn are integrally formed, and the first plate CE1 of the storage capacitor Cst and the gate are also spaced apart from each other, so that the two are not electrically connected.
  • the part of the first signal line 2301 located in the first opening peripheral area 203A and the part of the first signal line 2301 located in the first display area 2011 and the second display area 2012 are arranged in different layers (that is, different from the gate 121).
  • Layer arrangement that is, the first gate line GLn in FIG. 5D extends from the first display area 2011 into the first opening peripheral area 203A, and then extends from the first opening peripheral area 203A to the second display area 2012, the first gate line GLn
  • the portion of the first gate line GLn located in the first opening peripheral area 203A and the portion of the first gate line GLn located in the first display area 2011 and the second display area 2012 are arranged in different layers.
  • the portion of the first gate line GLn located in the first opening peripheral area 203A is electrically connected to the portion of the first gate line GLn located in the first display area 2011 and the second display area 2012 through the via hole.
  • the gates and gate lines of multiple thin film transistors are arranged in the same layer, for example, integrally formed, this situation is the situation shown in FIG. 3B.
  • the portion located in the peripheral region 203A of the first opening is arranged in the same layer as the gate 121.
  • the portion of the first gate line GLn located in the first opening peripheral area 203A passes through the via hole passing through the second gate insulating layer 152 shown in FIG. 3B and the portion of the first gate line GLn located in the first display area 2011 and the second The second part of the display area 2012.
  • another insulating layer is formed on the above-mentioned first conductive layer, and the insulating layer includes the second gate insulating layer 152 shown in FIG. 5B. It is also not shown in -5F.
  • FIG. 5E shows the second conductive layer of the pixel circuit.
  • the second conductive layer of the pixel circuit includes the second plate CE2 of the storage capacitor Cst, the initialization line RL and the second sub-wiring 2422, that is, the second sub-wiring 2422 and the storage capacitor Cst
  • the second plate CE2 is arranged on the same layer.
  • the second electrode plate CE2 and the first electrode plate CE1 at least partially overlap to form a storage capacitor Cst.
  • the second electrode plate CE2 shown in FIG. 5E has a gap K0.
  • the second electrode plate CE2 may not have the gap.
  • the embodiment of the present disclosure does not limit the specific structure of the second electrode plate CE2.
  • the first signal line 2301 in the first opening peripheral area 203A and the second conductive layer of the pixel circuit are formed in the same layer, that is, the first signal line 2301 in the first opening peripheral area 203A and the second conductive layer of the pixel circuit pass through
  • the same conductive material layer is formed by the same patterning process, that is, the first signal line 2301, the second electrode plate CE2 and the initialization line RL are formed by the same conductive material layer and the same patterning process.
  • the second conductive layer may further include a first light shielding portion 791 and a second light shielding portion 792.
  • the orthographic projection of the first light shielding portion 791 on the base substrate 210 covers the active layer between the active layer of the second thin film transistor T2, the drain of the third thin film transistor T3, and the drain of the fourth thin film transistor T4, thereby Prevent external light from affecting the active layers of the second thin film transistor T2, the third thin film transistor T3, and the fourth thin film transistor T4.
  • the orthographic projection of the second light shielding portion 792 on the base substrate 210 covers the active layer between the two gates of the third thin film transistor T3, thereby preventing external light from affecting the active layer of the third thin film transistor T3.
  • the first light shielding portion 791 may be an integral structure with the second light shielding portion 792 of the adjacent pixel circuit, and is electrically connected to the first power line VDD through the tenth via VH9' in the insulating layer, as shown in FIG. 5A.
  • another insulating layer is formed on the above-mentioned second conductive layer, and the insulating layer includes the interlayer insulating layer 160 shown in FIG. 3A, as shown in FIGS. 5A and 5C-5F. Not shown in.
  • FIG. 5F shows the third conductive layer of the pixel circuit.
  • the third conductive layer of the pixel circuit includes a data line DATA (for example, the second signal line 241/242 in FIG. 2A) and a second sub-wiring 2424 of the first power line VDD, that is, the The second sub-wiring 2424 is arranged on the same layer as the data line DATA.
  • the data line DATA passes through at least one via hole (for example, via hole VH1) in the first gate insulating layer, the second gate insulating layer, and the interlayer insulating layer, and the first gate in the semiconductor layer.
  • the source regions of the two thin film transistors T2 are connected.
  • the first power line VDD is connected to the source region of the semiconductor layer corresponding to the fifth thin film transistor T5 through at least one via hole (for example, via hole VH2) in the first gate insulating layer, the second gate insulating layer, and the interlayer insulating layer .
  • the first power line VDD is connected to the second electrode plate CE2 in the second conductive layer through at least one via hole (for example, via hole VH3) in the interlayer insulating layer.
  • the third conductive layer further includes a first connection portion CP1, a second connection portion CP2, and a third connection portion CP3.
  • One end of the first connection portion CP1 passes through at least one via hole (for example, via hole VH4) in the first gate insulating layer, the second gate insulating layer, and the interlayer insulating layer and is connected to the drain electrode of the third thin film transistor T3 in the semiconductor layer.
  • the regions are connected, and the other end of the first connecting portion CP1 is connected to the gate of the first thin film transistor T1 in the first conductive layer through at least one via (for example, via VH5) in the second gate insulating layer and the interlayer insulating layer .
  • One end of the second connecting portion CP2 is connected to the initialization line RL through a via hole (for example, via VH6) in the interlayer insulating layer, and the other end of the second connecting portion CP2 is connected to the first gate insulating layer and the second gate insulating layer.
  • At least one via hole (for example, via hole VH7) in the interlayer insulating layer is connected to the source region of the seventh thin film transistor T7 and the source region of the fourth thin film transistor T4 in the semiconductor layer.
  • the third connection portion CP3 is connected to the drain region of the sixth thin film transistor T6 in the semiconductor layer through at least one via hole (for example, via hole VH8) in the first gate insulating layer, the second gate insulating layer, and the interlayer insulating layer .
  • a protective layer is formed on the above-mentioned third conductive layer, and the protective layer includes the first planarization layer 112 shown in FIG. 5B, as shown in FIGS. 5A and 5C-5F.
  • the protective layer includes the first planarization layer 112 shown in FIG. 5B, as shown in FIGS. 5A and 5C-5F.
  • a sub-layer of the barrier wall 28 in the first opening peripheral area 203A is formed in the same layer as the protective layer, that is, a sub-layer of the barrier wall 28 in the first opening peripheral area 203A and the protective layer are made of the same insulating material Layers are formed through the same patterning process.
  • Fig. 6 is a signal timing diagram of the pixel circuit shown in Fig. 4.
  • the working principle of the pixel circuit shown in FIG. 4 will be described below in conjunction with the signal timing diagram shown in FIG. 6.
  • the first light-emitting control line EM1 and the second light-emitting control line EM2 in FIG. 4 are the same common light-emitting control line as an example.
  • the first light-emitting control line EM1 and the second light-emitting control line EM2 may also be different signal lines, respectively, which provide different first light-emitting control signals and second light-emitting control signals.
  • the transistors shown in FIG. 6 are all P-type transistors.
  • the gate of each P-type transistor is turned on when it is connected to a low level, and is turned off when it is connected to a high level.
  • the following embodiments are the same as this, and will not be repeated here.
  • the working process of the pixel circuit includes three stages, which are an initialization stage P1, a data writing and compensation stage P2, and a light-emitting stage P3.
  • the figure shows the timing waveform of each signal in each stage.
  • the second gate line Gn-1 provides a reset signal Rst
  • the fourth transistor T4 and the seventh transistor T7 are turned on by the low level of the reset signal
  • the initialization signal low level signal, for example, can be grounded or Other low-level signals
  • the initialization signal is applied to the N4 node, that is, the light-emitting element 180 is reset, so that the light-emitting element 180 can be displayed in a black state and not emit light before the light-emitting stage P3 , Improve the display effect such as the contrast of the display device using the pixel circuit.
  • the second transistor T2, the third transistor T3, the fifth transistor T5, and the sixth transistor T6 are turned off by the high-level signals respectively connected to them.
  • the first gate line GLn provides the scan signal Gn-1
  • the data line DATA provides the data signal Data
  • the second transistor T2 and the third transistor T3 are turned on.
  • the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are turned off by the high-level signals respectively connected to them.
  • the first transistor T1, and the third transistor T3 the first node N1 is charged (that is, the storage capacitor Cst is charged), that is, the potential of the first node N1 gradually increases. It is easy to understand that since the second transistor T2 is turned on, the potential of the second node N2 remains at Vdata.
  • Vdata represents the voltage value of the data signal Data
  • Vth represents the threshold voltage of the first transistor T1.
  • the first transistor T1 is described as a P-type transistor, so the threshold here The voltage Vth may be a negative value.
  • the potentials of the first node N1 and the third node N3 are both Vdata+Vth, that is to say, the voltage information with the data signal Data and the threshold voltage Vth is stored in the storage capacitor Cst , To provide gray scale display data and compensate the threshold voltage of the first transistor T1 during the subsequent light-emitting stage.
  • the light emitting control line provides the light emitting control signal EM, and the fifth transistor T5 and the sixth transistor T6 are turned on by the low level of the light emitting control signal EM.
  • the second transistor T2, the third transistor T3, the fourth transistor T4, and the seventh transistor T7 are turned off when the high level is connected to each of them.
  • the potential of the first node N1 is Vdata+Vth, and the potential of the second node N2 is VDD, so the first transistor T1 is also kept on at this stage.
  • the anode and cathode of the light-emitting element 180 are respectively connected to the first power supply voltage (high voltage) and the second voltage VSS (low voltage) provided by the first power line VDD, so that the light-emitting element 180 flows through the first transistor T1 Light is emitted under the action of driving current.
  • Fig. 7A is another partial enlarged schematic view of the first opening area in Fig. 2A
  • Fig. 7B is a schematic cross-sectional view taken along the line H-H' in Fig. 7A.
  • the embodiment shown in FIGS. 7A and 7B has the following differences from the embodiment shown in FIGS. 2B and 2C.
  • the second signal line 241/242 is the second sub-wiring of the first power line VDD, and the second sub-wiring 241/242 sequentially passes through the first opening peripheral area 203A and the second sub-wiring.
  • the second sub-wiring 241/242 sequentially passes through the second portion 2013D of the third display area 2013, the first opening peripheral area 203A, and the third display area along the second direction R2
  • the first part of 2013 2013C is located on the side of the first signal line 2301/2302 and the light emission control line 2305/2306 away from the base substrate 210.
  • the display substrate provided in this embodiment can achieve the same or similar technical effects as the above-mentioned embodiments, which will not be repeated here.
  • Other features and corresponding technical effects of the display substrate provided in this embodiment are the same as those in the previous embodiment, please refer to the previous description.
  • FIG. 8A is a schematic plan view of another display substrate according to an embodiment of the disclosure
  • FIG. 8B is a partial enlarged schematic view of the first opening area and the second opening area in FIG. 8A.
  • the display substrate 20 includes an opening area 200 that includes a first opening area 202A, a second opening area 202B adjacent to the first opening area 202A, and an inter-opening area 2014.
  • the first opening area 202A includes a first opening 201A and a first opening peripheral area 203A surrounding the first opening 201A;
  • the second opening area 202B includes a second opening 201B and a second opening peripheral area 203B surrounding the second opening 201B.
  • the inter-opening area 2014 is located between the first opening area 202A and the second opening area 202B.
  • the second opening region 202B and the first opening region 202A are arranged along the first direction R1, and thus, the inter-opening region 2014 is located in the first opening in the first direction R1.
  • the first display area 2011 is located on the side of the first opening area 202A away from the inter-opening area 2014
  • the second display area 2012 is located on the side of the second opening area 202B away from the inter-opening area 2014.
  • the first display area 2011 is located on the first side of the first opening area 202A
  • the second display area 2012 is located on the second side of the second opening area 201B.
  • the first display area, the first opening area, the inter-opening area, the second opening area, and the second display area are sequentially arranged along the first direction.
  • the first opening area 202A and the second opening area 201B respectively, it is still satisfied that the first display area 2011 is located on the first side of the first opening area 202A, and the second display area 2012 is located on the second side of the first opening area 202A, The first side and the second side are opposite to each other in the first direction R1.
  • the first signal line 23 sequentially passes through the first display area 2011, the first opening peripheral area 203A, the inter-opening area 2014, the second opening peripheral area 203B, and the second display area 2012 along the first direction R1.
  • the arrangement of the first signal line 23 and the second signal line 24 in the second opening area 202B is the same as the arrangement in the first opening area 202A in the above embodiment.
  • I will not repeat it here.
  • the second opening area 202B and the first opening area 202A are arranged along the second direction R2, so the inter-opening area 2014 is located between the first opening area 202A and the first opening area 202A in the second direction R2.
  • the second signal line 24 sequentially passes through the first opening peripheral area 203A, the inter-opening area 2014, the second opening peripheral area 203B, and the third display area 2013 along the second direction R2.
  • the second winding portion C1C2 extends from the third side of the first opening 201A around the first opening 201A to the fourth side of the first opening 201A.
  • the third side and the fourth side of the first opening 201A are opposite to each other in the second direction R2;
  • the second winding portion C1C2 located in the second opening peripheral area 203B of the second opening area 202B is It extends from the third side of the second opening 201B around the second opening 201B to the fourth side of the second opening 201B, and the third side of the second opening 201B and the fourth side of the second opening 201B are in the second direction R2 Opposite each other.
  • the inter-opening area 2014, the first opening peripheral area 203A, and the second opening peripheral area 203B includes one or more first virtual sub-pixels.
  • the first dummy sub-pixel has at least a partial or substantially complete pixel circuit structure, it does not emit light during operation, and therefore does not participate in the display operation.
  • the first dummy sub-pixel includes a first dummy pixel circuit, and the first dummy pixel circuit includes a first compensation capacitor for providing load compensation for the signal line.
  • FIG. 9 is an equivalent circuit diagram of a first dummy pixel circuit in a display substrate provided by at least one embodiment of the present disclosure
  • FIG. 10A is a plan view of a first dummy pixel circuit in a display substrate provided by an embodiment of the present disclosure Layout schematic diagram
  • FIG. 10B is a schematic cross-sectional view taken along the line A2-B2 in FIG. 10A
  • FIGS. 10C-10F are schematic diagrams of various layers of a pixel circuit of a display substrate provided by an embodiment of the present disclosure.
  • the pixel circuit structure of the first dummy sub-pixel is at least partially or substantially the same as the pixel circuit of the sub-pixel in the display area, and therefore can be understood in conjunction with the schematic diagrams shown in FIGS. 4 and 5A-5F.
  • the difference between the pixel circuit of the first dummy sub-pixel and the pixel circuit of the sub-pixel of the display area includes the connection mode of the storage capacitor.
  • the storage capacitor includes a first electrode plate CE1 and a second electrode plate CE2.
  • the second electrode plate CE2 is electrically connected to the first power line VDD, and the first electrode plate CE1 is connected to the first thin film transistor T1.
  • the first gate electrode and the third drain electrode D3 of the third thin film transistor T3 are electrically connected.
  • the storage capacitor is converted to a compensation capacitor and has a changed connection relationship. One of the plates is connected to the gate line GLn and is connected to the third drain electrode D3 of the third thin film transistor T3. disconnect.
  • the first compensation capacitor COM1 includes a first electrode plate CE1 and a second electrode plate CE2.
  • the first electrode plate CE1 of the first compensation capacitor COM1 is arranged on the same layer as the first signal line 2301 and is electrically connected to the first signal line 2301.
  • the first electrode plate CE1 of a compensation capacitor COM1 is connected to the first signal line 2301.
  • the signal line 2301 is integrally formed.
  • the second electrode plate CE2 of the first compensation capacitor COM1 and the first electrode plate COM1 of the first compensation capacitor COM1 are arranged in different layers and insulated; for example, the first electrode plate CE1 of the first compensation capacitor COM1 is on the base substrate 210.
  • the projection and the orthographic projection of the second plate CE2 of the first compensation capacitor COM1 on the base substrate 210 at least partially overlap.
  • the first compensation capacitor COM1 provides load compensation for the first signal line 2301 connected to it.
  • the first dummy pixel circuit includes a first dummy semiconductor layer, and the first dummy semiconductor layer is located on a side of the first signal line close to the substrate plate.
  • FIG. 10C shows the pattern of the first dummy semiconductor layer of the first dummy pixel circuit, for example, the pattern of the first dummy semiconductor layer is the same as the pattern of the semiconductor layer of the pixel circuit of the sub-pixels of the display area to maintain the display substrate The etching is uniform, and the manufacturing process of the first dummy pixel circuit is simplified, and the manufacturing cost is reduced.
  • FIG. 10D shows a structure of the first dummy pixel circuit in the first conductive layer
  • FIG. 10E shows the structure of the first dummy pixel circuit in the second conductive layer.
  • the first electrode plate CE1 of the first compensation capacitor COM1 includes a first body portion CE10 and a first extension portion CE11.
  • the first plate CE1 of the first compensation capacitor COM1 is located on the first conductive layer, that is, the gate of each thin film transistor of the pixel circuit and the first plate of the storage capacitor CST and the first plate of the first compensation capacitor COM1 are arranged on the same layer .
  • the first electrode plate CE1 of the first compensation capacitor COM1 is located on the first side of the first signal line 2301 (for example, the first signal line 2301 is the first gate line GLn) in the second direction R2; the first extension portion CE11 It extends from the first body portion toward the first signal line, is located on the first side of the first signal line 2301 in the second direction, and is located between the first body portion CE10 and the first signal line 2301.
  • the first body portion CE10 is electrically connected to the first signal line 2301 through the first extension portion CE11.
  • the first body portion CE10 and the first extension portion CE11 have substantially the same width in the first direction; for another example, in the first direction, the width of the first body portion CE10 is larger than the width of the first extension portion CE11 , That is, the first body portion CE10 and the first signal line 2301 are electrically connected through the narrowed first extension portion CE11 between the two; for another example, in the first direction, the width of the first body portion CE10 is greater than
  • the width of the first extension portion CE11 is small, that is, the first body portion CE10 and the first signal line 2301 are electrically connected by the enlarged first extension portion CE11 therebetween.
  • the second electrode plate CE2 of the first compensation capacitor COM1 is located on the second conductive layer, that is, the second electrode plate of the first compensation capacitor COM1 and the second electrode plate of the storage capacitor CST are arranged in the same layer. Moreover, the second plate CE2 of the first compensation capacitor COM1 and the first plate CE1 of the first compensation capacitor COM1 at least partially overlap in a direction perpendicular to the base substrate 210, as shown in FIG. 10B, thereby forming a first compensation Capacitor COM1.
  • the pattern of the first body portion CE10 may be the same as the pattern of the first plate of the storage capacitor of the pixel circuit in the sub-pixel of the display area.
  • the first compensation capacitor COM1 is The area of the electrode plate CE1 is increased, so that the overlap area of the first electrode plate CE1 of the first compensation capacitor COM1 and the second electrode plate CE2 of the first compensation capacitor COM1 can be increased to increase the area of the first compensation capacitor COM1. Capacitance, thereby further increasing the load of the first signal line 2301.
  • the first body portion CE10, the first extension portion CE11, and the first signal line 2301 are integrally formed.
  • FIG. 10G shows another structure of the first dummy pixel circuit located on the first conductive layer.
  • the first plate CE1 of the first compensation capacitor COM1 further includes a second extension portion CE12.
  • the second extension portion CE12 extends from the first signal line 2301 in a direction away from the first body portion 2301, is located on the second side of the first signal line 2301 in the second direction R2 and is electrically connected to the first signal line 2301.
  • the second side of a signal line 2301 is opposite to the first side of the first signal line 2301, thereby further increasing the area of the first electrode plate CE1 of the first compensation capacitor COM1. Therefore, if the area of the second plate of the first compensation capacitor COM1 is increased at the same time, the first compensation capacitor COM1 can be further increased to meet the requirements for a greater degree of compensation of the first signal line.
  • the first body portion CE10, the first extension portion CE11, the first signal line 2301, and the second extension portion CE12 are integrally formed.
  • the width of the first extension portion CE11 in the first direction R1, the width of the second extension portion CE12 in the first direction R1, and the width of the first body portion CE10 in the first direction R1 Basically equal, in order to make full use of the limited space to achieve a greater degree of compensation requirements.
  • the first pixel row and the second pixel row of the first pixel array in the first display area 2011 and the second display area 2012 are all interrupted by the first opening area 202A, the inter-opening area 2014, and the second opening area 202B. open.
  • the inter-opening area 2014 includes a first virtual sub-pixel row corresponding to the first pixel row and a second virtual sub-pixel row corresponding to the second pixel row.
  • the first signal line configured to provide the first display signal to the first pixel row passes through the first pixel row and the first dummy pixel row
  • the first signal line configured to provide the first display signal to the second pixel row passes through the first pixel row.
  • Two pixel rows and a second virtual pixel row The number of pixels in the first pixel row is different from the number of pixels in the second pixel row. Therefore, the load of the first signal line configured to provide the first display signal to the first pixel row is different from the load of the first signal line configured to provide the first display signal to the second pixel row.
  • the first dummy pixel row The number of the first compensation capacitor COM1 in the second virtual pixel row is different from the number of the first compensation capacitor COM1 in the second virtual pixel row, so as to perform load compensation on the first signal lines with different loads, so that the load of these first signal lines is It is basically the same, thereby reducing the adverse effect on the display quality due to the provision of the first opening area.
  • FIG. 11 shows six rows of pixels near the first opening area or the second opening area.
  • the sixth row of sub-pixels is a full row of pixels
  • the total load of the first signal line passing through the full row of pixels is M.
  • the first to fifth rows of pixels are pixels on both sides of the first opening area, which are pixel rows that are not full rows, and the number of pixels gradually increases from the first row to the fifth row.
  • the first compensation capacitor COM1 is provided for the sub-pixels in the first row to the fifth row of pixels, so that the load of the first signal line of each row of pixels approaches or is substantially equal to M.
  • the total number of first compensation capacitors COM1 provided for the sub-pixels in the pixels in the first row to the fifth row is gradually reduced.
  • the number of second compensation capacitors described below can also be similarly designed according to needs.
  • FIG. 10F shows the structure of the first dummy pixel circuit in the third conductive layer.
  • the first dummy pixel circuit further includes a first transfer electrode CP1
  • the first transfer electrode CP1 is electrically connected to the first plate CE1 of the first compensation capacitor COM1, and is connected to the first dummy
  • the other parts of the pixel circuit except for the first signal line 2301 are disconnected by the interval K1.
  • the display substrate further includes a disconnection electrode CP4, and the disconnection electrode CP4 is electrically connected to the first virtual semiconductor through the via hole VH4.
  • the first virtual semiconductor includes a part A1 and a part A3, and the disconnection electrode CP4 is electrically connected to the part A1 through a via VH4.
  • the disconnection electrode CP4 and the first transfer electrode CP1 are arranged in the same layer, for example, both are located on the third conductive layer shown in FIG.
  • the first plate CE1 of a compensation capacitor COM1 is disconnected from the other parts of the first dummy pixel circuit except for the first signal line 2301, so that the first dummy pixel circuit is disconnected.
  • the first dummy sub-pixel does not perform the display function and does not Affect the two substrates of the first compensation capacitor COM1.
  • the patterns of the data line DATA, the first power line VDD, the second connection portion CP2, and the third connection portion CP3 in the two figures are all the same.
  • the CP1 in FIG. 5F is disconnected to obtain the data shown in FIG. 10F.
  • the first transition electrode CP1 and the disconnect electrode CP4 are shown.
  • the first virtual pixel circuit and the pixel circuit of the display area have the same circuit design, except for the shape of the first plate CE1 of the first compensation capacitor COM1, and the first plate CE1 of the first compensation capacitor COM1 and the first virtual pixel circuit The other parts are disconnected outside.
  • the difference includes the shape of the first electrode plate CE1 of the first compensation capacitor COM1 and the difference between
  • the pixel circuit shown in FIG. 9 may further include more differences. These differences include, but are not limited to: the transistor T2 is disconnected from the data line (that is, it is not Then receive the data line signal), the transistor T2 is disconnected from the node N2, and the transistor T6 is disconnected from the OLED.
  • the embodiments of the present disclosure do not limit these differences, and at least enable the first virtual sub-pixel to provide a compensation capacitor without substantially affecting the display operation of the display area.
  • FIG. 12A is a schematic plan view of a second virtual pixel circuit in a second virtual sub-pixel (the virtual sub-pixel on the right side of the figure) in a display substrate provided by an embodiment of the present disclosure
  • FIG. 12B is an along view A schematic cross-sectional view of line A3-B3 in 12A
  • FIGS. 12C to 12F are schematic views of various layers of a second dummy pixel circuit of a display substrate provided by an embodiment of the present disclosure.
  • the inter-opening area 2014 further includes a second dummy sub-pixel, and the second dummy sub-pixel includes a second dummy pixel circuit, as shown in FIG. 12A.
  • the second virtual pixel circuit includes a second compensation capacitor COM10, and the second compensation capacitor COM10 includes a first electrode plate CE10 and a second electrode plate CE20.
  • FIG. 12D shows a structure of the second dummy pixel circuit in the first conductive layer
  • FIG. 12E shows the structure of the second dummy pixel circuit in the second conductive layer.
  • the first electrode plate CE10 of the second compensation capacitor COM10 and the first signal line 2301 are arranged in the same layer, for example, are located on the first conductive layer, and the second compensation capacitor COM10
  • the first electrode plate CE10 is electrically connected to the first signal line 2301.
  • the orthographic projection of the first signal line 2301 on the base substrate 210 and the orthographic projection of the second electrode plate CE20 of the second compensation capacitor COM10 on the base substrate 210 at least partially overlap.
  • the first pole CE10 board of the second compensation capacitor COM10 includes: a second body portion CE100 and a third extension portion CE101.
  • the second body portion CE100 is located on the first side of the first signal line 2301 in the second direction R2; the third extension portion CE101 extends from the second body portion CE100 in the second direction R2 toward the first signal line 2301, and is located in the second direction R2.
  • a signal line 2301 is on the first side in the second direction and is located between the second body part CE100 and the first signal line 2301, and the second body part CE100 is electrically connected to the first signal line 2301 through the third extension part CE101 .
  • the first pole CE20 board of the second compensation capacitor COM10 includes a fourth extension portion CE102, which extends from the first signal line 2301 toward a direction away from the second body portion CE100, and is located on the first signal line 2301.
  • the second side in the second direction R2 is electrically connected to the first signal line 2301, and the second side of the first signal line 2301 is opposite to the first side of the first signal line 2301, thereby further increasing the second compensation capacitor COM10 If the area of the first electrode plate CE10 is increased at the same time as the area of the second electrode plate of the second compensation capacitor COM10, the second compensation capacitor COM10 can be further increased to meet the requirements of different compensation levels for the first signal line.
  • the second body portion CE100, the third extension portion CE101, the first signal line 2301, and the fourth extension portion CE102 are integrally formed, so that these structures can be formed by the same patterning process, simplifying the manufacturing process of the display substrate.
  • the second electrode plate CE20 of the second compensation capacitor COM10 includes a third body portion CE200 and a fifth extension portion CE201.
  • the third body portion CE200 is located on the first side of the first signal line 2301 in the second direction R2; the fifth extension portion CE201 extends from the third body portion CE200 in the second direction R2 toward the first signal line 2301, the first The orthographic projection of the signal line 2301 on the base substrate 210 and the orthographic projection of the fifth extension portion CE201 on the base substrate 210 at least partially overlap.
  • the orthographic projection of the first plate CE10 of the second compensation capacitor COM10 on the base substrate 210 is located on the front of the second plate CE20 of the second compensation capacitor COM10 on the base substrate 210.
  • the limited space is used to form the required size of the second compensation capacitor.
  • a portion 7921 of the second electrode plate CE20 of the second compensation capacitor COM10 may be the same position and pattern as the light shielding portion in the pixel circuit of the display area to maintain uniformity of etching.
  • the second dummy sub-pixel includes a second dummy semiconductor layer, and the second dummy semiconductor layer is located on a side of the first plate of the second compensation capacitor close to the base substrate.
  • FIG. 12C shows the pattern of the second virtual sub-pixel, and the second virtual sub-pixel is the virtual sub-pixel A02 on the right side in FIG. 12C. As shown in conjunction with FIGS.
  • the second virtual semiconductor layer includes a first portion AP21 and a second portion AP22 spaced apart so as not to be connected to each other; the first portion AP21 is located on the first side of the first signal line 2301, and the second portion AP22 is located The second side of the first signal line 2301; the orthographic projection of the first signal line 2301 on the base substrate 210 and the orthographic projection of the first dummy semiconductor layer on the base substrate 210 do not overlap, so that the second dummy pixel circuit is not There are real thin film transistors that do not realize the display function. For example, the orthographic projection of the second compensation capacitor COM10 on the base substrate 210 and the orthographic projection of the first virtual semiconductor layer on the base substrate do not overlap.
  • FIG. 12F shows the structure of the second dummy pixel circuit on the third conductive layer.
  • the second dummy pixel circuit includes a second transfer electrode CP10, the second transfer electrode CP10 and the first transfer electrode of the first dummy pixel circuit, and pixels in the display area
  • the first connection part CP1 of the circuit is arranged in the same layer, for example, they are all located on the third conductive layer, and are electrically connected to the second plate CE20 of the second compensation capacitor COM10, for example, the second transfer electrode CP10 passes through the via hole VH40 and the via hole
  • the VH50 is electrically connected to the second electrode plate CE20 of the second compensation capacitor COM10, so as to maintain the etching uniformity between this and other positions such as the display area of the display substrate.
  • the second plate CE20 of the second compensation capacitor COM10 is connected to the first power line VDD through the via hole VH40 and the via hole VH50, for example, the first power line VDD
  • the line 2424 is connected to provide the first power voltage to the second plate CE20 of the second compensation capacitor COM10 to form the second compensation capacitor COM10.
  • the second part AP22 of the second dummy semiconductor layer is configured to be sent an electrical signal through the second dummy pixel circuit;
  • the first part AP21 of the first dummy semiconductor layer has a first end P21 and a
  • the second terminal P22 and the second terminal P22 are configured to be sent the electrical signal through the second dummy pixel circuit.
  • the first terminal P21 is connected to the second terminal P22, so that the electrical signal from the second terminal P2 can be transmitted to the first terminal P2.
  • the terminal P21 prevents signal drift caused by no signal input at the first terminal P21. For example, as shown in FIG.
  • the second terminal P22 is electrically connected to the second sub-wiring 2424 of the first power line VDD, for example, electrically connected through the via hole VH20, thereby connecting the second sub-wiring from the first power line VDD
  • the first power supply voltage of 2424 is transmitted to the second terminal P22 and the first terminal P21.
  • the inter-opening area 2014 further includes a third dummy sub-pixel (the dummy sub-pixel A01 on the left in FIG. 12C), and each third dummy sub-pixel includes a third dummy pixel circuit.
  • the third virtual pixel circuit includes a third virtual semiconductor layer, and the third virtual semiconductor layer is provided in the same layer as the second virtual semiconductor layer and the first virtual semiconductor layer.
  • the third dummy semiconductor layer includes a first part AP11 and a second part AP12 spaced apart so as not to be connected to each other, the first part AP11 of the third dummy semiconductor layer is located on the first side of the first signal line 2301, and the first part of the third dummy semiconductor layer AP11 is located on the second side of the first signal line 2301; the orthographic projection of the first signal line 2301 on the base substrate 210 and the orthographic projection of the third dummy semiconductor layer on the base substrate do not overlap, so that the third dummy sub-pixel No real thin film transistors are formed in, and the third dummy sub-pixel does not perform a display function.
  • the second dummy semiconductor layer is not provided in the outer region 2015 of the inter-opening region 2014 close to the display region, but the third dummy pixel circuit is provided to maintain the outer region 2015 and the display region. Etching uniformity to avoid affecting display uniformity.
  • the third dummy pixel circuit has the same circuit design as the pixel circuit of the sub-pixel in the display area.
  • the connection structure CP11/CP21/CP31 of the third virtual pixel circuit in FIG. 12F may have the same pattern as the connection structure of the corresponding position in the pixel circuit, such as the position of the connection structure CP10/CP20/CP30 in the second virtual pixel circuit. And the pattern is also the same to maintain uniformity of etching.
  • the positions of part of the signal lines of the third dummy pixel circuit and the corresponding signal lines in the pixel circuit may also be different. For example, in FIG.
  • the first power line VDD is located on the right side of the data line DATA and is not adjacent to the data line DATA.
  • the first power line VDD is adjacent to the data line DATA.
  • the specific patterns of each layer can be adjusted or fine-tuned as required, and are not specifically limited.
  • the light-emitting device has the first electrode but not the second electrode, so that the third dummy sub-pixel does not emit light.
  • FIG. 13B is an enlarged schematic view of a portion L1 of the racetrack-shaped opening of FIG. 13A including an arc-shaped routing
  • FIG. 13C is an enlarged schematic diagram of a portion L2 of the racetrack-shaped opening of FIG. 13A including a straight-line routing.
  • the first display area 2011 is located on the first side of the first opening area 202A
  • the second display area 2012 is located on the second side of the second opening area 201B.
  • first display area 2011 is located on the first side of the first opening area 202A
  • second display area 2012 is located on the second side of the first opening area 202A
  • the first side and the second side are opposite to each other in the first direction R1.
  • the planar shape of the first opening area 202A is a racetrack shape, and the planar shape of the first opening 201A included therein is also a racetrack shape, at least partially surrounding the first signal of the first opening 201A.
  • the line 2301/2305 includes arc and straight segments.
  • the linear portion 2301-1 of the first signal line from the first display area 2011 continues to extend to partially surround the first opening 201A, and the first wire of the first signal line surrounds the first opening 201A.
  • the part includes an arc-shaped part 2301-2.
  • the second winding portion of the second signal line extending in the second direction also includes an arc-shaped portion 241-2.
  • the arc-shaped portion 2301-2 of the first winding portion and the arc-shaped portion 241-2 of the second winding portion partially overlap in a direction perpendicular to the base substrate.
  • the first winding portion of the first signal line in the peripheral area of the first opening, includes a linear portion 2301-3.
  • the second winding portion of the second signal line extending in the second direction also includes a linear portion 241-1.
  • the linear portion 2301-3 of the first winding portion of the first signal line and the linear portion 241-1 of the second winding portion of the second signal line partially overlap in a direction perpendicular to the base substrate.
  • the linear portion 2301-1/2301-3 and the arc-shaped portion 2301-2 are included, and the first signal line is a gate scan signal line, and the gate scan signal line partially overlaps the second signal line.
  • the first signal line 2305 is a light-emitting control line. In other embodiments, the light-emitting control line may partially overlap the second signal line.
  • At least one embodiment of the present disclosure provides a display device including any of the above-mentioned display substrates.
  • the display device may be, for example, an organic light-emitting diode display device, a quantum dot light-emitting diode display device, or other devices with display functions or other types of devices, which are not limited in the embodiments of the present disclosure.
  • the display device provided by at least one embodiment of the present disclosure may be any product or component with a display function such as a display panel, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc.
  • a display function such as a display panel, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc.

Abstract

一种显示基板（10，20）以及显示装置。显示基板（10，20）包括第一信号线（23）和第二信号线（24）、第一开口区域（202A）、与第一开口区域（202A）相邻设置的第二开口区域（202B）、位于第一开口区域（202A）和第二开口区域（202B）之间的开口间区域（2014）和显示区域（201）。第一开口区域（202A）包括第一开口（201A）和围绕第一开口（201A）的第一开口周边区域（203A）；第二开口区域（202B）包括第二开口（201B）和围绕第二开口（201B）的第二开口周边区域（203B）；开口间区域（2014）、第一开口周边区域（203A）和第二开口周边区域（203B）中的至少一者包括虚拟子像素；显示区域（201）围绕这三个区域；第一信号线（23）穿过开口间区域（2014），给像素阵列提供显示信号且穿过虚拟子像素，虚拟子像素的虚拟像素电路包括补偿电容（COM1，COM10）。补偿电容（COM1，COM10）的第一极板（CE1，CE10）与第一信号线（23）同层且电连接；补偿电容（COM1，COM10）的第二极板（CE2，CE20）与第一极板（CE1，CE10）异层设置且至少部分重叠。

Description

显示基板以及显示装置
本申请要求于2020年6月05日递交的中国专利申请第202010507064.6号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种显示基板以及显示装置。
背景技术
目前，显示器件的显示屏正往大屏化、全屏化方向发展。通常，显示器件(例如手机、平板电脑等)具有摄像装置(或成像装置)，该摄像装置通常设置在显示屏的显示区域外的一侧。但是，由于摄像装置的安装需要占据一定的边框位置，因此不利于显示屏的全屏化、窄边框设计。例如，可以将摄像装置与显示屏的显示区域结合、重叠在一起，在显示区域中为摄像装置预留位置，以获得显示屏显示区域的最大化。
发明内容
本公开至少一实施例提供了一种显示基板，该显示基板包括衬底基板、第一信号线和第二信号线。衬底基板包括第一开口区域和显示区域；第一开口区域包括第一开口和围绕所述第一开口的第一开口周边区域；显示区域至少部分围绕所述第一开口区域，且包括第一显示区域和第二显示区域。第一显示区域位于所述第一开口区域的第一侧；第二显示区域位于所述第一开口区域的第二侧，所述第一侧与所述第二侧在第一方向上彼此相对，所述第一显示区域和所述第二显示区域包括第一像素阵列；第一信号线配置为给所述第一像素阵列提供第一显示信号，沿所述第一方向依次穿过所述第一显示区域、所述第一开口周边区域和所述第二显示区域，包括位于所述第一开口周边区域的第一引线部和第一绕线部；所述第一绕线部部分围绕所述第一开口 设置，所述第一引线部与所述第一绕线部连接；第二信号线配置为给所述第一像素阵列提供第二显示信号，沿与所述第一方向相交的第二方向穿过所述第一开口周边区域，包括位于所述第一开口周边区域的第二绕线部，其中，所述第二绕线部部分围绕所述第一开口设置；所述第一引线部在所述衬底基板上的正投影与所述第二信号线在所述衬底基板上的正投影具有第一交叠区，所述第一绕线部在所述衬底基板上的正投影与所述第二绕线部在所述衬底基板上的正投影具有第二重叠区，所述第一交叠区的面积小于所述第二重叠区的面积。
例如，在本公开提供的一种显示基板中，所述第一绕线部从所述第一开口的第一侧围绕所述第一开口地延伸至所述第一开口的第二侧，所述第一开口的第一侧与所述第一开口的第二侧在所述第一方向上彼此相对；所述第二绕线部从所述第一开口的第三侧围绕所述第一开口地延伸至所述第一开口的第四侧，所述第三侧与所述第四侧在所述第二方向上彼此相对。
例如，在本公开提供的一种显示基板中，所述第一像素阵列包括分别沿所述第一方向延伸的第一像素行和第二像素行，所述第一像素行和所述第二像素行均被所述第一开口区域断开；所述显示基板包括多条所述第一信号线，多条所述第一信号线包括：配置为给所述第一像素行提供所述第一显示信号的所述第一信号线，以及配置为给所述第二像素行提供所述第一显示信号的所述第一信号线；给所述第一像素行提供所述第一显示信号的所述第一信号线的第一绕线部在所述第一开口的第三侧部分地围绕所述第一开口；给所述第二像素行提供所述第一显示信号的所述第一信号线的第一绕线部在所述第一开口的第四侧部分地围绕所述第一开口。
例如，在本公开提供的一种显示基板中，所述第一像素阵列包括分别沿所述第二方向延伸的第一像素列和第二像素列；所述显示基板包括多条所述第二信号线，多条所述第二信号线包括：配置为给所述第一像素列提供所述第二显示信号的所述第二信号线，以及配置为给所述第二像素列提供所述第二显示信号的所述第二信号线；给所述第一像素列提供所述第二显示信号的所述第二信号线的第二绕线部朝向所述第一开口的第一侧凸出且在所述第一开口的第一侧部分地围绕所述第一开口；给所述第二像素列提供所述第二显 示信号的所述第二信号线的第二绕线部朝向所述第一开口的第二侧凸出且在所述第一开口的第二侧部分地围绕所述第一开口。
例如，在本公开提供的一种显示基板中，给所述第一像素行提供所述第一显示信号的所述第一信号线的所述第一绕线部，与给所述第二像素行提供所述第一显示信号的所述第一信号线的所述第一绕线部相对于沿所述第一方向的对称轴基本对称；给所述第一像素列提供所述第二显示信号的所述第二信号线的所述第二绕线部，与给所述第二像素列提供所述第二显示信号的所述第二信号线的所述第二绕线部相对于沿所述第二方向的对称轴基本对称。
例如，在本公开提供的一种显示基板中，所述第一绕线部的平面形状和所述第二绕线部的平面形状分别构成所述第一开口的平面形状的同心环的一部分。
例如，在本公开提供的一种显示基板中，所述第一绕线部的平面形状和所述第二绕线部的平面形状分别包括弧形，或者，分别包括弧形和直线段。
例如，在本公开提供的一种显示基板中，所述第一信号线为栅扫描信号线，所述第一显示信号为栅扫描信号。
例如，在本公开提供的一种显示基板中，所述显示区域包括多个像素，每个所述像素包括多个子像素，每个所述子像素包括像素电路，所述像素电路包括：晶体管、发光元件和存储电容。晶体管包括有源层、栅极和源漏极；发光元件与所述晶体管的源漏极之一连接；存储电容包括第一极板和第二极板，所述栅极、所述第一信号线与所述存储电容的第一极板同层设置。
例如，本公开提供的一种显示基板还包括第三显示区域和多条第三信号线。所述第三显示区域在所述第二方向上位于所述第一显示区域和所述第二显示区域的至少一侧，与所述第一显示区域和所述第二显示区域相接，且包括第二像素阵列；所述第二像素阵列包括多行多列像素；多条第三信号线，配置为分别给所述第二像素阵列包括的多行像素提供第三扫描信号且沿所述第一方向延伸，其中，所述第二信号线还配置为给所述第二像素阵列的多列像素提供所述第二显示信号。
例如，在本公开提供的一种显示基板中，所述第二像素阵列的每一行像素所包括的像素的数量多于所述第一像素阵列的所述第一像素行包括的像素 的数量以及所述第一像素阵列的所述第二像素行包括的像素的数量。
例如，在本公开提供的一种显示基板中，所述第二信号线包括数据线，数据线配置为给所述子像素提供用于控制所述子像素的发光灰度的数据信号。
例如，在本公开提供的一种显示基板还包括第一电源线。第一电源线连接第一电压端且配置为给所述像素电路提供第一电源电压，且与所述存储电容的第二极板连接，包括沿所述第一方向延伸的多条第一子走线和沿所述第二方向延伸的多条第二子走线；所述多条第一子走线中的第一部分第一子走线在所述第一开口区域断开，所述多条第一子走线中的第二部分第一子走线贯穿所述第三显示区域；所述多条第二子走线中的第一部分第二子走线在所述第一开口区域断开，所述多条第二子走线中的第二部分第二子走线依次贯穿第一显示区域和第三显示区域或者依次贯穿第二显示区域和第三显示区域；所述第一部分第一子走线与所述第二部分第二子走线中的至少一条第二子走线分别在所述第一显示区域和所述第二显示区域电连接，所述第一部分第二子走线与所述第二部分第一子走线中的至少一条第一子走线在所述第三显示区域电连接。
例如，在本公开提供的一种显示基板中，所述第一子走线和所述存储电容的第二极板同层设置；所述第二子走线与所述数据线同层设置。
例如，在本公开提供的一种显示基板还包括第一电源线。第一电源线连接第一电压端且配置为给所述像素电路提供第一电源电压，且与所述存储电容的第二极板连接，包括沿所述第一方向延伸的多条第一子走线和沿所述第二方向延伸的多条第二子走线；所述第二信号线包括所述第二子走线，所述第二子走线依次穿过所述第一开口周边区域和所述第三显示区域。
例如，本公开提供的一种显示基板还包括第二开口区域和开口间区域；第二开口区域与所述第一开口区域相邻，且包括第二开口和围绕所述第二开口的第二开口周边区域；开口间区域位于所述第一开口区域和所述第二开口区域之间。
例如，在本公开提供的一种显示基板中，所述第二开口区域与所述第一开口区域沿所述第一方向排列；所述第一显示区域位于所述第一开口区域的 远离所述开口间区域的一侧，所述第二显示区域位于所述第二开口区域的远离所述开口间区域的一侧；所述第一信号线沿所述第一方向依次穿过所述第一显示区域、所述第一开口周边区域、所述开口间区域、所述第二开口周边区域和所述第二显示区域。
例如，在本公开提供的一种显示基板中，所述第二开口区域与所述第一开口区域沿所述第二方向排列；所述第二信号线沿所述第二方向依次穿过所述第一开口周边区域、所述开口间区域、所述第二开口周边区域以及所述第三显示区域。
例如，在本公开提供的一种显示基板中，所述开口间区域、所述第一开口周边区域和所述第二开口周边区域三者中的至少一者包括第一虚拟子像素，所述第一虚拟子像素包括第一虚拟像素电路，所述第一虚拟像素电路包括第一补偿电容；所述第一补偿电容包括第一极板和第二极板。第一极板与所述第一信号线同层设置且与所述第一信号线电连接；第二极板与所述第一补偿电容的第一极板异层设置且绝缘；所述第一补偿电容的第一极板在所述衬底基板上的正投影与所述第一补偿电容的第二极板在所述衬底基板上的正投影至少部分重叠。
例如，在本公开提供的一种显示基板中，所述第一补偿电容的第二极板与所述存储电容的第二极板同层设置。
例如，在本公开提供的一种显示基板中，所述第一补偿电容的第一极板与所述第一虚拟像素电路的除了所述第一信号线的其他部分断开。
例如，在本公开提供的一种显示基板中，所述开口间区域包括第二虚拟子像素，所述第二虚拟子像素包括第二虚拟像素电路，所述第二虚拟像素电路包括第二补偿电容；所述第二补偿电容的第一极板与所述第一信号线同层设置且与所述第一信号线电连接；所述第一信号线在所述衬底基板上的正投影与所述第二补偿电容的第二极板在所述衬底基板上的正投影至少部分重叠。
例如，在本公开提供的一种显示基板中，所述第二补偿电容的第二极板包括第一主体部分和第一延伸部。第一主体部分位于所述第一信号线的在所述第二方向上的第一侧；第一延伸部自所述第一主体部分在所述第二方向上 朝向所述第一信号线延伸，所述第一信号线在所述衬底基板上的正投影与所述第一延伸部在所述衬底基板上的正投影至少部分重叠。
例如，在本公开提供的一种显示基板中，所述第二补偿电容的第二极板与所述第一补偿电容的第二极板同层设置。
例如，在本公开提供的一种显示基板中，所述第二补偿电容的第一极板包括第二主体部分、第二延伸部和第三延伸部。第二主体部分位于所述第一信号线的在所述第二方向上的第一侧；第二延伸部自所述第二主体部分在所述第二方向上朝向所述第一信号线延伸，位于所述第二主体部分与所述第一信号线的之间；所述第二主体部分通过所述第二延伸部与所述第一信号线电连接；第三延伸部自所述第一信号线在所述第二方向上向远离所述第二主体部分的方向延伸，位于所述第一信号线的在所述第二方向上的第二侧且与所述第一信号线电连接，所述第一信号线的第二侧与所述第一信号线的第一侧相对。
例如，在本公开提供的一种显示基板中，所述第二补偿电容的第一极板在所述衬底基板上的正投影位于所述第二补偿电容的第二极板在所述衬底基板上的正投影内。
例如，在本公开提供的一种显示基板中，所述第一主体部分与所述第一延伸部一体成型；所述第二主体部分、所述第二延伸部、所述第一信号线和所述第三延伸部一体成型。
例如，在本公开提供的一种显示基板中，所述第二虚拟子像素包括第一虚拟半导体层。第一虚拟半导体层位于所述第二补偿电容的第一极板的靠近所述衬底基板的一侧，包括间隔开以彼此不连接的第一部分和第二部分；所述第一部分位于所述第一信号线的所述第一侧，所述第二部分位于所述第一信号线的所述第二侧；所述第一信号线在所述衬底基板上的正投影与所述第一虚拟半导体层在所述衬底基板上的正投影不重叠。
例如，在本公开提供的一种显示基板中，所述第一虚拟半导体层的第一部分和第二部分均配置为通过所述第二虚拟像素电路被寄予电信号；所述第一虚拟半导体层的第一部分在所述第一方向上具有彼此相对的第一端和第二端，所述第二端配置为通过所述第二虚拟像素电路被寄予所述电信号，所述 第一端与所述第二端连接。
例如，在本公开提供的一种显示基板中，所述开口间区域还包括第三虚拟子像素，每个所述第三虚拟子像素包括第三虚拟像素电路，所述第三虚拟像素电路包括第二虚拟半导体层。所述第二虚拟半导体层包括间隔开以彼此不连接的第一部分和第二部分，所述第二虚拟半导体层的第一部分位于所述第一信号线的所述第一侧，所述第二虚拟半导体层的第一部分位于所述第一信号线的所述第二侧；所述第一信号线在所述衬底基板上的正投影与所述第二虚拟半导体层在所述衬底基板上的正投影不重叠。
例如，在本公开提供的一种显示基板中，所述第三虚拟像素电路与所述像素电路具有相同的电路设计，除了所述第二虚拟半导体层被断开之外。
本公开至少一实施例提供了一种显示基板，该显示基板包括：衬底基板、第一信号线和第二信号线。衬底基板包括：第一开口区域、第二开口区域、开口间区域和显示区域。第一开口区域包括第一开口和围绕所述第一开口的第一开口周边区域；第二开口区域与所述第一开口区域相邻设置，且包括第二开口和围绕所述第二开口的第二开口周边区域；开口间区域位于所述第一开口区域和所述第二开口区域之间，所述开口间区域、所述第一开口周边区域和所述第二开口周边区域三者中的至少一者包括第一虚拟子像素；显示区域至少部分围绕所述第一开口区域、所述第二开口区域和所述开口间区域，且包括像素阵列；第一信号线延伸穿过所述开口间区域，配置为给所述像素阵列提供第一显示信号且穿过所述第一虚拟子像素，所述第一虚拟子像素包括第一虚拟像素电路，所述第一虚拟像素电路包括第一补偿电容。所述第一补偿电容包括：第一极板和第二极板。第一极板与所述第一信号线同层设置且与第一信号线电连接；第二极板与所述第一极板异层设置且绝缘，其中，所述第一补偿电容的第二极板在所述衬底基板上的正投影与所述第一补偿电容的第一极板在所述衬底基板上的正投影至少部分重叠。
例如，在本公开提供的一种显示基板中，所述第一信号线沿第一方向延伸，所述第一开口区域和所述第二开口区域沿第一方向相邻设置；第二方向与所述第一方向垂直；所述第一补偿电容的第一极板包括第一主体部分和第一延伸部。第一主体部分，于所述第一信号线的在所述第二方向上的第一侧； 第一延伸部，所述第一主体部分朝向所述第一信号线延伸，位于所述第一信号线在所述第二方向上的第一侧，且位于所述第一主体部分与所述第一信号线的之间，其中，所述第一主体部分通过所述第一延伸部与所述第一信号线电连接。
例如，在本公开提供的一种显示基板中，所述第一补偿电容的第一极板还包括第二延伸部。第二延伸部自所述第一信号线朝向远离所述第一主体部分的方向延伸，位于所述第一信号线的在所述第二方向上的第二侧且与所述第一信号线电连接，所述第二侧与所述第一侧相对。
例如，在本公开提供的一种显示基板中，所述第一主体部分、所述第一延伸部、所述第一信号线和所述第二延伸部一体成型。
例如，在本公开提供的一种显示基板中，所述第一延伸部在所述第一方向上的宽度、所述第二延伸部在所述第一方向上的宽度与所述第一主体部分在所述第一方向上的宽度基本相等。
例如，在本公开提供的一种显示基板中，所述显示区域包括第一显示区域和第二显示区域。第一显示区域位于所述第一开口区域的远离所述开口间区域的一侧；第二显示区域位于所述第二开口区域的远离所述开口间区域的一侧，其中，所述第一显示区域和所述第二显示区域包括第一像素阵列，所述第一像素阵列包括分别沿所述第一方向延伸的第一像素行和第二像素行，所述第一像素行和所述第二像素行均被所述第一开口区域、所述开口间区域和所述第二开口区域三者构成的整体断开；所述第一信号线沿所述第一方向依次穿过所述第一显示区域、所述第一开口周边区域、所述开口间区域、所述第二开口周边区域和所述第二显示区域；所述显示基板包括：配置为给所述第一像素行提供所述第一显示信号的所述第一信号线，以及配置为给所述第二像素行提供所述第一显示信号的所述第一信号线。
例如，在本公开提供的一种显示基板中，所述开口间区域包括与所述第一像素行对应的第一虚拟子像素行和与所述第二像素行对应的第二虚拟子像素行；所述配置为给所述第一像素行提供所述第一显示信号的所述第一信号线穿过所述第一像素行和所述第一虚拟像素行，所述配置为给所述第二像素行提供所述第一显示信号的所述第一信号线穿过所述第二像素行和所述第二 虚拟像素行；所述第一像素行的像素的数量与所述第二像素行的像素的数量不相同，所述第一虚拟像素行中的所述第一补偿电容的数量与所述第二虚拟像素行中的所述第一补偿电容的数量不相同。
例如，在本公开提供的一种显示基板中，所述第一信号线为栅扫描信号线，所述第一显示信号为栅扫描信号。
例如，在本公开提供的一种显示基板中，所述显示区域包括多个像素，每个所述像素包括多个子像素，每个所述子像素包括像素电路；所述像素电路包括晶体管、发光元件和存储电容。晶体管包括有源层、栅极和源漏极；发光元件与所述晶体管的源漏极之一连接；存储电容包括第一极板和第二极板；所述栅极、所述第一信号线、所述存储电容的第一极板以及所述第一补偿电容的第一极板同层设置。
例如，在本公开提供的一种显示基板中，所述存储电容的第一极板与所述第一信号线彼此间隔开，且与所述栅极此间隔开。
例如，在本公开提供的一种显示基板中，所述第一补偿电容的第二极板和所述存储电容的第二极板同层设置。
例如，在本公开提供的一种显示基板中，所述第一补偿电容的第一极板与所述第一虚拟像素电路的除了所述第一信号线之外的其他部分断开。
例如，在本公开提供的一种显示基板中，所述第一虚拟像素电路还包括第一转接电极。第一转接电极与所述第一补偿电容的第一极板电连接，且与所述第一虚拟像素电路的除了所述第一信号线之外的其他部分断开。
例如，在本公开提供的一种显示基板中，所述第一虚拟像素电路包括第一虚拟半导体层，所述第一虚拟半导体层位于所述第一信号线的靠近所述衬底极板的一侧。所述显示基板还包括断开电极；断开电极与所述第一虚拟半导体层电连接，与所述第一转接电极同层设置，且与所述第一转接电极间隔开以彼此不连接。
例如，在本公开提供的一种显示基板中，所述第一虚拟像素电路和所述像素电路具有相同的电路设计，除了所述第一补偿电容的第一极板、以及所述第一补偿电容的第一极板与所述第一虚拟像素电路的其他部分断开之外。
例如，在本公开提供的一种显示基板中，所述开口间区域还包括第二虚 拟子像素；第二虚拟子像素包括第二虚拟像素电路。所述第二虚拟像素电路包括第二补偿电容；所述第二补偿电容的第一极板与所述第一信号线同层设置且与所述第一信号线电连接；所述第一信号线在所述衬底基板上的正投影与所述第二补偿电容的第二极板在所述衬底基板上的正投影至少部分重叠。
例如，在本公开提供的一种显示基板中，所述第二补偿电容的第二极板包括第二主体部分和第三延伸部分。第二主体部分位于所述第一信号线的在所述第二方向上的第一侧；第三延伸部分自所述第二主体部分在所述第二方向上朝向所述第一信号线延伸，所述第一信号线在所述衬底基板上的正投影与所述第三延伸部分在所述衬底基板上的正投影至少部分重叠。
例如，在本公开提供的一种显示基板中，所述第二补偿电容的第二极板与所述第一补偿电容的第二极板同层设置。
例如，在本公开提供的一种显示基板中，所述第二补偿电容的第一极板包括第三主体部分和第四延伸部分。第三主体部分位于所述第一信号线的在所述第二方向上的第一侧；第四延伸部分自所述第三主体部分在所述第二方向上朝向所述第一信号线延伸，位于所述第三主体部分与所述第一信号线的之间；所述第三主体部分通过所述第四延伸部与所述第一信号线电连接。
例如，在本公开提供的一种显示基板中，所述第二补偿电容的第一极板在所述衬底基板上的正投影位于所述第二补偿电容的第二极板在所述衬底基板上的正投影内。
例如，在本公开提供的一种显示基板中，所述第二虚拟子像素电路包括第二转接电极，所述第二转接电极与所述第一转接电极同层设置且与所述第二补偿电容的第二极板电连接。
例如，在本公开提供的一种显示基板中，所述第二虚拟子像素包括第一虚拟半导体层。第一虚拟半导体层包括间隔开以彼此不连接的第一部分和第二部分；所述第一部分位于所述第一信号线的所述第一侧，所述第二部分位于所述第一信号线的所述第二侧；所述第一信号线在所述衬底基板上的正投影与所述第一虚拟半导体层在所述衬底基板上的正投影不重叠。
例如，在本公开提供的一种显示基板中，所述第一虚拟半导体层的第二部分均配置为通过所述第二虚拟像素电路被寄予电信号；所述第一虚拟半导 体层的第一部分在所述第一方向上具有彼此相对的第一端和第二端，所述第二端配置为通过所述第二虚拟像素电路被寄予所述电信号，所述第一端与所述第二端连接。
例如，在本公开提供的一种显示基板中，所述开口间区域还包括第三虚拟子像素，所述第三虚拟子像素包括第三虚拟像素电路，所述第三虚拟像素电路包括第二虚拟半导体层。所述第二虚拟半导体层包括间隔开以彼此不连接的第一部分和第二部分，所述第二虚拟半导体层的第一部分位于所述第一信号线的所述第一侧，所述第二虚拟半导体层的第一部分位于所述第一信号线的所述第二侧；所述第一信号线在所述衬底基板上的正投影与所述第三虚拟半导体层在所述衬底基板上的正投影不重叠。
例如，在本公开提供的一种显示基板中，所述第三虚拟子像素与所述像素电路具有相同的电路设计，除了在所述第二虚拟半导体层被断开之外。
例如，在本公开提供的一种显示基板中，所述显示区域还包括第三显示区域。在所述第二方向上位于所述第一显示区域和所述第二显示区域的至少一侧，且同时与所述第一显示区域和所述第二显示区域相接，包括第二像素阵列；所述第二像素阵列包括多行多列像素，所述第三显示区域包括分别为所述多行多列像素中的每一行像素提供扫描信号且沿所述第一方向延伸的多条第三信号线；所述第二像素阵列的每一行像素所包括的像素的数量多于所述第一像素阵列的所述第一像素行包括的像素的数量以及所述第一像素阵列的所述第二像素行包括的像素的数量。
本公开至少一实施例提供一种显示装置，包括上述任一的显示基板。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为一种显示基板的平面示意图；
图2A为本公开一实施例提供的一种显示基板的平面示意图；
图2B为图2A中的第一开口区域的局部放大示意图；
图2C为沿图2B中的I-I’线的一种截面示意图；
图2D为本公开实施例的另一种显示基板的平面示意图；
图2E为本公开实施例的再一种显示基板的平面示意图；
图2F本公开一实施例提供的一种显示基板的第一开口区域附近的像素排布的平面示意图；
图3A为图2A中的显示基板的显示区域沿A-A’线的一种截面示意图；
图3B为图2A中的显示基板的显示区域沿A-A’线的另一种截面示意图；
图3C为图2A中的显示基板的显示区域沿A-A’线的又一种截面示意图；
图4为本公开一实施例提供的一种显示基板中的像素电路的等效电路图；
图5A为本公开一实施例提供的一种显示基板中的像素电路的平面布局示意图；
图5B为沿图5A中的A1-B1线的截面示意图；
图5C-5F为本公开一实施例提供的一种显示基板的像素电路的各层的示意图；
图6是图4所示的像素电路的工作过程的信号时序图；
图7A为图2A中的第一开口区域的局部放大示意图；
图7B为沿图7A中的H-H’线的一种截面示意图；
图8A为本公开一实施例提供的又一种显示基板的平面示意图；
图8B为图8A中的第一开口区域和第二开口区域的局部放大示意图；
图8C为本公开实施例提供的另一种显示基板的第一开口区域和第二开口区域的局部放大示意图；
图9为本公开至少一实施例提供的一种显示基板中的第一虚拟像素电路的等效电路图；
图10A为本公开一实施例提供的一种显示基板中的第一虚拟像素电路的平面布局示意图；
图10B为沿图10A中的A2-B2线的截面示意图；
图10C-10G为本公开一实施例提供的一种显示基板的第一虚拟像素电路的各层的示意图；
图11为本公开一实施例提供的一种显示基板的第一开口区域或第二开口区域附近的像素排布的平面示意图；
图12A为本公开一实施例提供的一种显示基板中的第二虚拟像素电路的平面布局示意图；
图12B为沿图12A中的A3-B3线的截面示意图；
图12C-12F为本公开一实施例提供的一种显示基板的第二虚拟像素电路的各层的示意图；
图13A为本公开实施例的又一种显示基板的平面示意图；
图13B为图13A的跑道形开口的包括弧形走线的局部L1的放大示意图；
图13C为图13A的跑道形开口的包括直线走线的局部L2的放大示意图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
在下面的描述中，当提及两个或更多部件“一体成型”时，表示这些部 件通过至少同一原料层形成，例如通过对同一膜层进行同一次构图工艺形成，由此彼此之间不存在界面而是连续的。
图1为一种显示基板的平面示意图。如图1所示，该显示基板10包括显示区域101和围绕显示区域101的周边区域102，显示区域101被设计为例如在至少一侧具有凹口103的不规则形状，该显示基板10可以在凹口103的区域中布置例如摄像头、距离传感器等器件，由此有助于实现显示基板10的窄边框设计。
如图1所示，显示区域101包括位于凹口103的左右两侧的第一显示区域1011和第二显示区域1012，第一显示区域1011与和第二显示区域1012相对于显示区域101的底边(图中下侧边缘)处于相同的水平位置，例如由图中相同的左右水平延伸的一条或多条扫描信号线(栅线)驱动。当然，在其他一些实施例中，第一显示区域与第二显示区域也可以处于不同的水平位置，例如当采用该显示基板的显示屏为异形(非矩形或非类似矩形)显示屏时，在异形屏中，例如第一显示区域与第二显示区域沿显示屏地弯曲的边缘排布，则第一显示区域与第二显示区域未必在同一水平位置。由于凹口103的存在，位于第一显示区域1011与和第二显示区域1012中的同一行像素的像素数量，比除了第一显示区域1011与和第二显示区域1012外的显示区域101中其他部分(例如图1中的中部)的一行像素的像素数量少。因此，在该显示基板10中，对于水平延伸的用于为第一显示区域1011与和第二显示区域1012中的同一行像素提供显示信号(例如扫描信号)的信号线所连接的像素数量，与用于为除了第一显示区域1011与和第二显示区域1012外的显示区域101中其他部分的一行像素提供电信号(例如扫描信号)的信号线所连接的像素数量不同，并且在凹口103为不规则形状(例如梯形、水滴形等)时，第一显示区域1011和第二显示区域1012中不同行像素的像素数量也可能不同。因此，在该显示基板10中，由于不同行像素的像素数量不同，导致连接不同行像素的信号线的负载不同，进而这些信号线传输信号的速度不同，实际的显示信号与设计值之间的偏差不同，这会影响显示基板的显示效果。
例如，可以对这些负载不同的信号线进行负载补偿，以使这些信号线的负载基本相同，从而减小由于设置凹口103对显示质量的不利影响。
本公开至少一实施例提供了一种显示基板，该显示基板包括衬底基板、第一信号线和第二信号线。衬底基板包括第一开口区域和显示区域；第一开口区域包括第一开口和围绕所述第一开口的第一开口周边区域；显示区域至少部分围绕所述第一开口区域，且包括第一显示区域和第二显示区域。第一显示区域位于所述第一开口区域的第一侧；第二显示区域位于所述第一开口区域的第二侧，所述第一侧与所述第二侧在第一方向上彼此相对，所述第一显示区域和所述第二显示区域包括第一像素阵列；第一信号线配置为给所述第一像素阵列提供第一显示信号，沿所述第一方向依次穿过所述第一显示区域、所述第一开口周边区域和所述第二显示区域，包括位于所述第一开口周边区域的第一引线部和第一绕线部；所述第一绕线部部分围绕所述第一开口设置，所述第一引线部与所述第一绕线部连接；第二信号线配置为给所述第一像素阵列提供第二显示信号，沿与所述第一方向相交的第二方向穿过所述第一开口周边区域，包括位于所述第一开口周边区域的第二绕线部，其中，所述第二绕线部部分围绕所述第一开口设置；所述第一引线部在所述衬底基板上的正投影与所述第二信号线在所述衬底基板上的正投影具有第一交叠区，所述第一绕线部在所述衬底基板上的正投影与所述第二绕线部在所述衬底基板上的正投影具有第二重叠区，所述第一交叠区的面积小于所述第二重叠区的面积。
本公开至少一实施例还提供一种显示基板，该显示基板包括：衬底基板、第一信号线和第二信号线。衬底基板包括：第一开口区域、第二开口区域、开口间区域和显示区域。第一开口区域包括第一开口和围绕所述第一开口的第一开口周边区域；第二开口区域与所述第一开口区域相邻设置，且包括第二开口和围绕所述第二开口的第二开口周边区域；开口间区域位于所述第一开口区域和所述第二开口区域之间，所述开口间区域、所述第一开口周边区域和所述第二开口周边区域三者中的至少一者包括第一虚拟子像素；显示区域至少部分围绕所述第一开口区域、所述第二开口区域和所述开口间区域，且包括像素阵列；第一信号线延伸穿过所述开口间区域，配置为给所述像素阵列提供第一显示信号且穿过所述第一虚拟子像素，所述第一虚拟子像素包括第一虚拟像素电路，所述第一虚拟像素电路包括第一补偿电容。所述第一 补偿电容包括：第一极板和第二极板。第一极板与所述第一信号线同层设置且与第一信号线电连接；第二极板与所述第一极板异层设置且绝缘，其中，所述第一补偿电容的第二极板在所述衬底基板上的正投影与所述第一补偿电容的第一极板在所述衬底基板上的正投影至少部分重叠。
下面通过几个具体的实施例对本公开进行说明。为了保持本发明实施例的以下说明清楚且简明，可省略已知功能和已知部件的详细说明。当本发明实施例的任一部件在一个以上的附图中出现时，该部件在每个附图中由相同的参考标号表示。
图2A为本公开实施例的一种显示基板的平面示意图，图2B为图2A中的第一开口区域的局部放大示意图。
如图2A和图2B所示，显示基板20包括衬底基板、第一信号线23和第二信号线24。衬底基板包括第一开口区域202A、显示区域201和边框区204。第一开口区域202A包括第一开口201A和围绕第一开口201A的第一开口周边区域203A；显示区域201围绕第一开口区域202A，边框区204围绕显示区域201。
显示区域201包括阵列排布的像素，每个像素包括一个或多个子像素，还包括用于向子像素传输各种电信号的各种信号线，以用于实现显示功能；边框区204包括各种驱动电路、电连接子像素的信号线、接触垫等，边框区204的信号线与显示区域201中的信号线(例如栅线、数据线等)电连接(或一体形成)以为子像素提供电信号(例如扫描信号、数据信号等)。
例如第一开口201A设置来允许来自显示基板的显示侧的光通过以到达摄像头、距离传感器，以实现光感应，从而实现图像拍摄、距离感应等功能；例如，第一开口201A所对应的区域中，在显示基板背侧(即与显示侧相对的一侧)可设置摄像头、距离传感器等器件，摄像头、距离传感器等至少部分通过第一开口201A暴露。
例如来自边框区204的各种信号线延伸穿过显示区域201，当遇到第一开口区域201A时，这些信号线穿过第一开口周边区域203A而绕过第一开口201A，然后再进入显示区域201中，以给途经的子像素提供电信号(例如扫描信号、数据信号等)，由此，可不在第一开口201A中设置这些信号线， 以增大第一开口201A的光透过率。
显示区域201包括第一显示区域2011和第二显示区域2012。第一显示区域2011位于第一开口区域202A的第一侧，第二显示区域2012位于第一开口区域202A的第二侧，该第一侧与该第二侧在第一方向R1(图中的水平方向)上彼此相对。例如，第一显示区域2011、第一开口周边区域203A和第二显示区域2012沿第一方向R1依次排列。第一显示区域2011和第二显示区域2012构成的整体包括第一像素阵列。例如，第一像素阵列包括多个呈阵列排布的像素，每个像素包括多个子像素，每个子像素包括像素电路。
以图2B中的第一信号线2301为例，例如显示基板包括多条第一信号线2301/2302/2303/2304/2305/2306，第一信号线2301配置为给第一像素阵列提供第一显示信号，且沿第一方向R1依次穿过第一显示区域2011、第一开口周边区域203A和第二显示区域2012，从而电连接位于第一开口201A的相对两侧的第一显示区域2011和第二显示区域2012中的子像素，例如为第一显示区域2011和第二显示区域2012中与第一开口周边区域203A中处于同一水平位置的多个像素的子像素提供第一显示信号。在各实施例中，该第一显示信号例如可以是栅扫描信号、发光控制信号或者复位电压信号等任何形式的电信号。例如，多条第一信号线2301/2302/2303/2304/2305/2306可以为显示区域第一显示区域2011和第二显示区域2012中的像素电路提供扫描信号、发光控制信号、复位电压信号等中的一种或多种。
图2C为沿图2B中的I-I’线的一种截面示意图。结合图2B与图2C，第一信号线2301包括位于第一开口周边区域203A的第一引线部E1A1/E2A2(即,以一条第一信号线为例，例如第一引线部为图2B中的直线段E1A1和直线段E2A2)和位于第一开口周边区域203A的第一绕线部A1A2(即第一绕线部为图2B中的曲线段A1A2)；第一绕线部A1A2部分围绕第一开口201A设置。第二信号线24配置为给第一像素阵列提供第二显示信号，沿与第一方向R1相交的第二方向R2穿过第一开口周边区域203A，包括位于第一开口周边区域203A的第二绕线部C1C2，即第二绕线部为图2B中的曲线段C1C2；第二绕线部C1C2部分围绕第一开口201A设置。第一引线部E1A1/E2A2在衬底基板上的正投影与第二信号线24在衬底基板上的正投影分别具 有第一交叠区S1/S2，即两者交叉处的区域。第一绕线部A1A2在衬底基板上的正投影与第二绕线部C1C2在衬底基板上的正投影具有第二重叠区，例如这两者在A1C1段和D1A2段重叠，第二重叠区为A1C1和D1A2所代表的区域。如此，由于第一交叠区和第二重叠区的形成，在垂直于衬底基板的方向上彼此重叠的第一信号线2301与第二信号线24之间形成补偿电容，补偿了第一信号线上的负载，从而减小由于第一像素阵列中不同行像素的像素数量不同而导致连接不同行像素的第一信号线的负载不同而造成的显示差异，使第一显示区域2011和第二显示区域2012的显示效果与显示区域201中不设置有第一开口区域202A的像素行的显示效果一致，提升显示质量。同时，上述走线方式还能够减小第一信号线与第二信号线的排布空间，尽可能减小当第一开口周边区域203A占用的面积。因此，例如当通过第一开口区域202A实现屏下摄像功能时减小第一开口区域202A对该区域显示效果的影响，或者，在其他实施例中，当第一开口周边区域203A位于边框区204中时，也可减小边框区204的宽度，进而有助于实现显示基板20的窄边框、大屏化设计。例如，如图2B所示，第一信号线2301的引线部E1A1在衬底基板上的正投影与第二信号线24的第二绕线部在衬底基板上的正投影具有第一交叠区。
例如，同一条第一信号线2301的引线部E1A1可以与多条第二信号线24形成第一交叠区，即同一条第一信号线2301的引线部E1A1可以与多条第二信号线24交叉，以更大程度地增大第一交叠区所形成的补偿电容，更大程度地增大第一信号线2301的负载。
需要说明的是，在本公开实施例中，例如，如图2B所示，第二重叠区在第一方向R1上和在第二方向R2方向上均有分量，即，第二重叠区不仅仅沿第一方向延伸，也不仅仅沿第二方向延伸。从而，相比于仅仅沿第一方向R1延伸的直线型的的信号线之间彼此重叠的情形或仅沿第二方向R2延伸的直线型的的信号线之间彼此重叠的情形，本公开实施例能够充分利用围绕第一开口的第一开口周边区域的空间满足更大范围的补偿电容的需求，可扩大由第二重叠区形成的补偿电容的幅值。
例如，第一绕线部A1A2从第一开口201A的第一侧围绕第一开口201A 地延伸至第一开口201A的第二侧，第一开口201A的第一侧与第一开口201A的第二侧在第一方向R1上彼此相对；第二绕线部C1C2从第一开口201A的第三侧围绕第一开口201A地延伸至第一开口201A的第四侧，第一开口201A的第三侧与第一开口201A的第四侧在第二方向R2上彼此相对。
例如，在上述图示的实施例中，第一绕线部A1A2的平面形状和第二绕线部C1C2的平面形状分别构成第一开口201A的平面形状的同心环的一部分。例如，第一开口201A的平面形状为圆形，第一绕线部A1A2的平面形状和第二绕线部C1C2的平面形状分别构成该圆形的同心环的一部分。此时，第一绕线部A1A2的平面形状和第二绕线部C1C2的平面形状均为圆弧，即第一绕线部的平面形状和第二绕线部的平面形状分别包括圆弧形。由此，第一绕线部A1A2和第二绕线部C1C2与第一开口201A和第一开口周边区域203A的形状相配合，这一设计充分利用第一开口周边区域203A的面积，以利于减小第一开口周边区域203A所占用的面积，减小第一开口区域202A占用的显示区域的面积，例如通过第一开口区域202A实现屏下摄像功能时，可以减小第一开口区域202A对该区域显示效果的不利影响。
例如，在一些实施例中，第一显示区域2011和第二显示区域2012包括被第一开口区域202A隔开的多行像素，并且，第一显示区域2011的多行像素和第二显示区域2012的多行像素彼此一一对应。例如，第一显示区域2011的第n行(n为正整数)像素和第二显示区域2012的第n行像素对应，从显示效果来看位于同一行中，因此在本文中视为显示区域201中的同一行像素。
例如，第一像素阵列包括分别沿第一方向R1延伸的第一像素行和第二像素行，第一像素行和第二像素行在第二方向R2上排列，第一像素行和第二像素行均被第一开口区域202A断开。例如，图2F示出了第一开口区域2011附近的像素排布的平面示意图。例如，在一些示例中，如图2F所示，假设第一行和第六行为满行的像素行，第二行到第五行为图2B中第一开口区域2011两侧的像素行，为非满行的像素行。如图2B所示，显示基板20包括多条第一信号线23，多条第一信号线23包括配置为给第一像素行提供第一显示信号的第一信号线2301以及配置为给第二像素行提供第一显示信号的第一信号线2302。例如，第一像素行和第二像素行可以为相邻的两个像 素行，例如分别为图2F中所示的第二行和第三行；又例如，第一像素行和第二像素行可以为不相邻的两个像素行，例如分别为图2F中所示的第二行和第四行。例如第一信号线2301与第一信号线2302同层设置。第一信号线2301的第一绕线部A1A2朝向第一开口201A的第三侧凸出且在第一开口201A的第三侧部分地围绕第一开口201A。第一信号线2302的第一绕线部B1B2朝向第一开口201A的第四侧凸出且在第一开口201A的第四侧部分地围绕第一开口201A。由此，第一信号线2301为第一显示区域2011和第二显示区域2012中沿第一方向R1排布的第一像素行提供第一显示信号。第一信号线2302为第一显示区域2011和第二显示区域2012中沿第一方向R1排布的第二像素行提供第一显示信号。例如，第一信号线2301和第一信号线2302为栅扫描信号线，对应地，第一显示信号为栅扫描信号。此时，第一信号线2301和第一信号线2302是给第一显示区域2011和第二显示区域2012中的不同的像素行提供栅扫描信号的栅扫描信号线(也可以简称为栅线)。
例如，图中的一条第二信号线24与两条不同的第一信号线在垂直于衬底基板的方向上至少部分重叠，这两条第一信号线分别给第一像素阵列的两个不同像素行提供第一显示信号。例如，第一信号线2302的第一绕线部B1B2与第二信号线24的第二绕线部C1C2在衬底基板上的正投影部分重叠，例如这两者在A1C1段和B1C2段重叠。由此，在垂直于衬底基板的方向上彼此重叠的第一信号线2302与第二信号线24之间形成补偿电容，补偿了第一信号线2302上的负载。
例如，第一像素阵列包括分别沿第二方向R2延伸的第一像素列和第二像素列，第一像素列和第二像素列在第一方向R1上排列。显示基板20包括多条第二信号线24，多条第二信号线24包括配置为给第一像素列提供第二显示信号的第二信号线241和配置为给第二像素列提供所述第二显示信号的第二信号线242。例如，在一些示例中，如图2F所示，第一像素列和第二像素列可以为相邻的两个像素列，例如分别为图2F中所示的第七列和第八行；又例如，第一像素列和第二像素列也可以为不相邻的两个像素列，例如分别为图2F中所示的第七列和第九列。第二信号线241的第二绕线部C1C2朝向第一开口201A的第一侧凸出且在第一开口201A的第一侧部分地围绕第一开 口201A；第二信号线242的第二绕线部D1D2朝向第一开口201A的第二侧凸出且在第一开口201A的第二侧部分地围绕第一开口201A，以避免影响第一开口201A的光透过率。
需要说明的是，图2F只是示例性的，本公开实施例中的像素行和像素列的个数不限于是图2F所示的个数。
例如，第一信号线2301的第一绕线部A1A2与第一信号线2302的第一绕线部B1B2相对于沿第一方向R1的对称轴基本对称。第二信号线241的第二绕线部C1C2与第二信号线242的第二绕线部D1D2相对于沿第二方向R2的对称轴基本对称。由此，第一绕线部A1A2和第二绕线部C1C2与第一开口201A和第一开口周边区域203A的形状相配合，这一设计充分利用第一开口周边区域203A的面积，以利于减小第一开口周边区域203A所占用的面积，减小第一开口区域202A占用的显示区域的面积，例如通过第一开口区域202A实现屏下摄像功能时，可以减小第一开口区域202A对该区域显示效果的不利影响。
当然，在其他一些实施例中，第一信号线2301的第一绕线部A1A2与第一信号线2302的第一绕线部B1B2也可以不相对于沿第一方向R1的对称轴对称；第二信号线241的第二绕线部C1C2与第二信号线242的第二绕线部D1D2也可以不相对于沿第二方向R2的对称轴基本对称。
与第一信号线2301和第一信号线2302类似，第一信号线2303和第一信号线2304也是如此。应该理解，本实施例仅以所示出的第一信号线和第二信号线为例，并不限于只有图2B所示出的第一信号线和第二信号线。
例如，如图2A和图2B所示，显示基板20还包括第三显示区域2013。例如，第三显示区域2013包括在第二方向R2上位于第一显示区域2011和第二显示区域2012的第一侧的第一部分2013C以及在第二方向R2上位于第一显示区域2011和第二显示区域2012的第二侧的第二部分2013D，第一显示区域2011和第二显示区域2012的第一侧与第一显示区域2011和第二显示区域2012的第二侧在第二方向R2上彼此相对；第一部分2013C和第二部分2013D均与第一显示区域2011和第二显示区域2012相接。
例如，第三显示区域2013的第一部分2013C的在第二方向R2上彼此相 对的两个边缘2013A和2013B，分别与第一显示区域2011的沿第二方向R2延伸且远离第一开口201A的边缘2011A、以及第二显示区域201的沿第二方向R2延伸且远离第一开口201A的边缘2012A对齐。第三显示区域2013包括第二像素阵列，第二像素阵列包括多行多列像素。显示基板20还包括多条第三信号线2307，多条第三信号线2307位于第三显示区域2013的第一部分2013C和第二部分2013D中。图2A和图2B示出一条位于第三显示区域2013的第一部分2031A的第三信号线2307，以作为示例。第三信号线2307配置为分别给第二像素阵列包括的多行像素提供第三扫描信号且沿第一方向R1延伸；例如，在本实施例中，第二信号线24沿第二方向R2依次穿过第三显示区域2013的第二部分2013D、第一开口周边区域203A和第三显示区域2013的第一部分2013C，且配置为给第二像素阵列的多列像素提供第二显示信号。
第三显示区域2013也包括多个像素，每个像素包括多个子像素，每个子像素包括像素电路。第三显示区域2013的每个像素可与第一显示区域和第二显示区域的每个像素的结构相同。例如，在一些实施例中，第三显示区域2013中的多行多列的子像素中的每一行像素所包括的像素数量基本相同。此时，多条第三信号线2037分别电连接的像素的数量基本相同，因此多条第三信号线2037具有基本相同的负载。例如，多行多列的像素中的每一行像素所包括的像素数量多于第一像素阵列的第一像素行包括的像素数量、多于第一像素阵列的第二像素行包括的像素数量。例如，经过负载补偿后的每条第一信号线2301/2302/2303/2304的负载与多条第三信号线2037的负载基本相同，进而每条第一信号线2301/2302/2303/2304与每条第三信号线2037传输信号的速度基本相同，传输给子像素的像素电路的实际显示信号与设计值之间的偏差基本一致，由此可以保持显示区域201的显示一致性，提高显示基板20的显示效果。
例如，如图2B所示，第二信号线24为数据线，且配置为给子像素提供用于控制子像素的发光灰度的数据信号。
如图2B所示，例如，显示基板20还包括第一电源线VDD，第一电源线VDD连接第一电压端，且配置为给一个或多个子像素的像素电路提供第 一电源电压。例如，第一电源线VDD包括沿第一方向R1延伸的多条第一子走线2421/2422和沿第二方向R2延伸的多条第二子走线2423/2424。多条第一子走线2421/2422中的第一部分第一子走线2421在第一开口区域202A断开，多条第一子走线2421/2422中的第二部分第一子走线2422贯穿第三显示区域。例如，在图2B中，第一子走线2422沿第一方向R1贯穿第三显示区域2013的第一部分2013C。多条第二子走线2423/2424中的第一部分第二子走线2423在第一开口区域202A断开，多条第二子走线2423/2424中的第二部分第二子走线2424依次贯穿第一显示区域2011和第三显示区域2013，例如，在本实施例中依次贯穿第三显示区域2013的第二部分2013D、第一显示区域2011和第三显示区域2013的第一部分2013C。或者，第二子走线2424依次贯穿第二显示区域2012和第三显示区域2013，例如在本实施例中依次贯穿第三显示区域2013的第二部分2013D、第二显示区域2012和第三显示区域2013的第一部分2013C。第一部分第一子走线2421与第二部分第二子走线2424中的至少一条第二子走线2424分别在第一显示区域2011和第二显示区域2012电连接，第一部分第二子走线2423与第二部分第一子走线2422中的至少一条第一子走线2422在第三显示区域2013电连接，以给第一像素阵列和第二像素阵列的各行各列的子像素均提供第一电源电压。
本公开至少一实施例提供的显示基板的第一开口区域的平面形状不限于是圆形，例如也可以为矩形、椭圆形等规则图形，或者为跑道形、水滴形等不规则图形。这些情形下，第一信号线和第二信号线的设置原则和技术效果与上述圆形的示例的相同或类似。
在本公开的实施例中，第一开口区域也不限于被显示区域完全围绕。例如，图2D为本公开实施例的另一种显示基板的平面示意图。在图2D所示的实施例中，第一开口区域202A为类似矩形的凹槽。第一开口区域202A位于显示区域201的一端，第一开口区域202A的上侧不存在显示区域，显示区域201部分围绕第一开口区域202A。又例如，在图2E所示的实施例中，第一开口区域202A位于整个显示基板的中部偏下的位置，例如在第一开口201A中设置光电转换器件以用于指纹识别；并且，第一开口区域202A的平面形状与第一开口201A的平面形状均为矩形，第一开口周边区域203A的平 面形状为围绕该矩形的矩形环。例如，在该第一开口周边区域203A中，第一信号线的弯折部分与第二信号线的弯折部分的平面形状分布构成围绕该矩形的矩形环的一部分，例如该矩形环是该矩形的同心环。
上述实施例只是示例性的，本公开对第一开口区域202A的平面形状、设置位置不作限定，可根据需要进行设计。
图3A为图2A中的显示基板的显示区域沿A-A’线的一种截面示意图，图3B为图2A中的显示基板的显示区域沿A-A’线的另一种截面示意图。
如图3A所示，显示基板20的显示区域201的每个子像素的像素电路包括晶体管，以薄膜晶体管(TFT)为例进行描述，、发光元件180和存储电容Cst。薄膜晶体管包括有源层120、栅极121和源漏极122/123；存储电容Cst包括第一极板CE1和第二电容极板CE2。发光元件180包括阴极183、阳极181以及阴极183和阳极181之间的发光层182，阳极181与薄膜晶体管TFT的源漏极122/123中之一，例如漏极123，电连接。例如，该发光元件例如可以为有机发光二极管(OLED)或量子点发光二极管(QLED)，相应地，发光层182为有机发光层或量子点发光层。
例如，栅极121、整个第一信号线2301与存储电容Cst的第一极板CE1同层设置。或者，在图3B所示的实施例中，上述图2B所示的第一信号线2301/2032的位于第一开口周边区域203A中的部分与第一信号线2301/2032的位于第一显示区域2011和第二显示区域2012中的部分异层设置(即与栅极121和存储电容Cst的第一极板CE1异层设置)。此时，第一信号线2301/2032的位于第一开口周边区域203A中的部分通过过孔与第一信号线2301/2032的位于第一显示区域2011和第二显示区域2012中的部分电连接。例如，栅极121与第一信号线2301/2032的位于第一显示区域2011和第二显示区域2012中的部分、以及存储电容Cst的第一极板CE1同层设置；第一信号线2301/2032的位于第一开口周边区域203A中的部分与存储电容Cst的第二极板CE2同层设置。同层设置的结构可通过一次构图工艺形成，由此可以简化显示基板20的制备工艺。图3B所示的实施例的其他结构均与图3A中的相同，请参考对于图3A的描述。
例如，如图3A所示，显示区域201还包括位于有源层120与栅极121 之间的第一栅绝缘层151、位于栅极121上方的第二栅绝缘层152以及层间绝缘层160，第二栅绝缘层152位于第一极板CE1和第二电容极板CE2之间，使得第一极板CE1、第二栅绝缘层152和第二电容极板CE2构成存储电容Cst。层间绝缘层160覆盖在第二电容极板CE2上。
例如，如图3A所示，显示区域201还包括覆盖像素电路的绝缘层113(例如钝化层)和第一平坦化层112。显示区域201还包括用于限定多个子像素的像素界定层170以及像素界定层170上的隔垫物(未示出)等结构。如图3A所示，在一些实施例中，绝缘层113位于源漏极122/123上方(例如钝化层，由氧化硅、氮化硅或者氮氧化硅等材料形成)，绝缘层113上方设置有第一平坦化层112，阳极181通过贯穿第一平坦化层112和绝缘层113的过孔与漏极123电连接。
例如，如图3A所示，显示基板20的第一开口周边区域203A还包括封装层291、292和293。显示区域201还包括封装层190，封装层190包括多个封装子层191/192/193。当然，封装层190不限于3层，还可以为2层，或者4层、5层或者更多层。例如，第一封装层291与封装层190中的第一封装子层191同层设置，第二封装层292与封装层190中的第二封装子层192同层设置，第三封装层293与封装层190中的第三封装子层193同层设置，例如，第一封装层291和第三封装层293均可以包括无机封装材料，例如包括氧化硅、氮化硅或者氮氧化硅等，第二封装层292可以包括有机材料，例如包括树脂材料等。显示区域201和第一开口周边区域203A多层封装结构可以达到更好的封装效果，以防止水汽或氧气等杂质渗入显示基板20内部。
在一些实施例中，如图3A所示，显示基板还包括位于衬底基板210上的缓冲层111，缓冲层111作为过渡层，可以防止衬底基板210中的有害物质侵入显示基板20的内部，又可以增加显示基板20中的膜层在衬底基板210上的附着力。例如，缓冲层111的材料可以包括氧化硅、氮化硅、氮氧化硅等绝缘材料形成的单层或多层结构。
图3C为图2A中的显示基板的显示区域沿A-A’线的又一种截面示意图，图3C只示出了显示区域的部分截面图。与图3A所示的显示区域不同的是，图3C示出的显示区域中，发光元件180的阳极181通过转接电极171与薄 膜晶体管TFT的漏极123电连接。此时，转接电极171上覆盖有第二平坦化层114，例如，在第一平坦化层112上方覆盖有第二平坦化层114。图3C中左侧的显示区201的截面图中的第二平坦化层114延伸至第一开口周边区域203A中，从而形成如图3C中右侧的第一开口周边区域203A的截面图所示的结构。
例如，在其他实施例中，显示基板的显示区域也可以不具有绝缘层113和第二平坦化层114。
例如，本公开的至少一个实施例中，衬底基板210可以为玻璃基板、石英基板、金属基板或树脂类基板等。例如，衬底基板210的材料可以包括有机材料，例如该有机材料可以为聚酰亚胺、聚碳酸酯、聚丙烯酸酯、聚醚酰亚胺、聚醚砜、聚对苯二甲酸乙二醇酯和聚萘二甲酸乙二醇酯等树脂类材料。例如，衬底基板210可以为柔性基板或非柔性基板，本公开的实施例对此不作限制。
例如，第一栅绝缘层151、第二栅绝缘层152、层间绝缘层160、第一平坦化层112、像素界定层170以及隔垫物中任一的材料可以包括氧化硅、氮化硅、氮氧化硅等无机绝缘材料，或者可以包括聚酰亚胺、聚酞亚胺、聚酞胺、丙烯酸树脂、苯并环丁烯或酚醛树脂等有机绝缘材料。本公开的实施例对第一栅绝缘层151、第二栅绝缘层152、层间绝缘层160、第一平坦化层112、像素界定层170以及隔垫物的材料均不做具体限定。例如，第一栅绝缘层151、第二栅绝缘层152、层间绝缘层160、第一平坦化层112、第二平坦化层114、像素界定层170以及隔垫物的材料可以彼此相同或部分相同，也可以彼此不相同，本公开的实施例对此不作限制。
例如，如图2B所示，显示基板20还可以包括位于第一开口周边区域203A中且至少部分围绕第一开口201A的阻隔墙28。例如，在垂直于衬底基板210的方向上，阻隔墙28与第一信号线和第二信号线至少部分重叠。阻隔墙28能够在第一开口周边区域203A提供阻隔和支撑作用，维持第一开口201A的稳定以及保护第一开口201A中的摄像头等光电传感器件，同时阻挡水汽、氧等有害杂质经由第一开口201A扩散到显示区域中，由此防止了有害杂质导致显示区域中的像素电路劣化。
图4为本公开至少一实施例提供的一种显示基板中的像素电路的等效电路图；图5A-5E为本公开一些实施例提供的一种显示基板中的像素电路的各层的示意图。
在一些实施例中，如图4所示，像素电路包括多个薄膜晶体管：第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7、连接到多个薄膜晶体管T1、T2、T3、T4、T5、T6和T7的多条信号线和存储电容Cst，也即，该实施例中像素电路为7T1C结构。相应地，多条信号线包括栅线GLn/GLn-1(即扫描信号线)、发光控制线EM、初始化线RL、数据线DATA和第一电源线VDD。栅线GLn/GLn-1可包括第一栅线GLn和第二栅线GLn-1。例如，第一栅线GLn用于传输栅极扫描信号，第二栅线GLn-1用于传输复位电压信号发光控制线EM用于传输发光控制信号，例如连接到第一发光控制端EM1(下文所称的第一发光控制线EM1指与第一发光控制端EM1连接且配置为给第一发光控制端EM1提供第一发光控制信号的信号线)和第二发光控制端EM2(下文所称的第二发光控制线EM2指与第二发光控制端EM2连接且配置为给第二发光控制端EM2提供第二发光控制信号的信号线)。第五晶体管T5的栅极与第一发光控制端EM1连接，或作为第一发光控制端EM1，以接收第一发光控制信号；第六晶体管T6的栅极与第二发光控制端EM2连接，或作为第二发光控制端EM2，以接收第二发光控制信号。例如，上述第一信号线为栅线GLn/GLn-1(即栅扫描信号线)，对应地，第一显示信号为栅扫描信号。
例如，在本公开一些实施例提供的显示基板中，第一信号线23还可以包括与发光控制端连接的发光控制线。例如，在本公开一些实施例中，图2B中所示的第一信号线2305/2306可以连接到第一发光控制端EM1或第二发光控制端EM2，可以使第一发光控制端EM1或第二发光控制端EM2与第二信号线至少部分重叠，以对第一发光控制端EM1或第二发光控制端EM2的负载进行补偿，提高整个显示区域201的显示均一性。
需要说明的是，本公开实施例包括但并不限于上述7T1C结构的像素电路，像素电路也可采用其他类型的电路结构，例如7T2C结构或者9T2C结构等，本公开实施例对此不作限制。
例如，如图4所示，第一薄膜晶体管T1的第一栅极与第三薄膜晶体管T3的第三漏极D3和第四薄膜晶体管T4的第四漏极D4电连接。第一薄膜晶体管T1的第一源极S1与第二薄膜晶体管T2的第二漏极D2和第五薄膜晶体管T5的第五漏极D5电连接。第一薄膜晶体管T1的第一漏极D1与第三薄膜晶体管T3的第三源极S3和第六薄膜晶体管T6的第六源极S6电连接。
例如，如图4所示，第二薄膜晶体管T2的第二栅极被配置为与第一栅线GLn电连接，以接收栅极扫描信号；第二薄膜晶体管T2的第二源极S2被配置为与数据线DATA电连接，以接收数据信号；第二薄膜晶体管T2的第二漏极D2与第一薄膜晶体管T1的第一源极S1电连接。
例如，如图4所示，第三薄膜晶体管T3的第三栅极被配置为与第一栅线GLn电连接，第三薄膜晶体管T3的第三源极S3与第一薄膜晶体管T1的第一漏电极D1电连接，第三薄膜晶体管T3的第三漏极D3与第一薄膜晶体管T1的第一栅极电连接。
例如，如图4所示，第四薄膜晶体管T4的第四栅极被配置为与第二栅线GLn-1电连接以接收复位电压信号，第四薄膜晶体管T4的第四源极S4被配置为与初始化线RL电连接以接收初始化电压信号，第四薄膜晶体管T4的第四漏极D4与第一薄膜晶体管T1的第一栅极电连接。
例如，如图4所示，第五薄膜晶体管T5的第五栅极被配置为与发光控制线EM电连接以接收发光控制信号，第五薄膜晶体管T5的第五源极S5被配置为与第一电源线VDD电连接以接收第一电源信号，第五薄膜晶体管T5的第五漏极D5与第一薄膜晶体管T1的第一源极S1电连接。
例如，如图4所示，第六薄膜晶体管T6的第六栅极被配置为与发光控制线EM电连接以接收发光控制信号，第六薄膜晶体管T6的第六源极S6与第一薄膜晶体管T1的第一漏极D1电连接，第六薄膜晶体管T6的第六漏极D6与发光元件180的第一显示电极(例如阳极)电连接。图3A-3C中的薄膜晶体管TFT即第六薄膜晶体管T6。
例如，如图4所示，第七薄膜晶体管T7的第七栅极被配置为与第二栅线GLn-1电连接以接收复位电压信号，第七薄膜晶体管T7的第七源极S7与发光元件180的第一显示电极(例如阳极181)电连接，第七薄膜晶体管T7 的第七漏极D7被配置为与初始化线RL电连接以接收初始化电压信号。例如，第七薄膜晶体管T7的第七漏极D7可以通过连接到第四薄膜晶体管T4的第四源极S4以实现与初始化线RL电连接。
例如，如图4和图5A所示，存储电容Cst包括第一极板CE1和第二极板CE2。第二极板CE2与第一电源线VDD电连接，第一极板CE1与第一薄膜晶体管T1的第一栅极和第三薄膜晶体管T3的第三漏极D3电连接。例如，第一电源线VDD包括第一子走线2422和第二子走线2424。第一电源线VDD连接第一电压端；例如，第二子走线2424与存储电容的第二极板CE2通过第三过孔VH3连接；例如第二子走线2424与存储电容的第二极板CE2一体成型，第二子走线2422与第一子走线2422通过第九过孔VH9连接。
例如，如图4所示，发光元件180的第二显示电极(例如阴极183)与第二电源线VSS电连接。
例如第一电源线VDD为像素电路提供高电压的电源线，第二电源线VSS连接第二电压端第二电源线VSS为像素电路提供低电压(低于前述高电压)的电源线。在如图4所示的实施例中，第一电源线VDD提供恒定的第一电源电压，第一电源电压为正电压；第二电源线VSS提供恒定的第二电源电压，第二电源电压可以为负电压等。例如，在一些示例中，第二电源电压可以为接地电压。
需要说明的是，上述的复位电压信号和上述的初始化电压信号可为同一信号。
需要说明的是，本公开的实施例中采用的晶体管可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件，薄膜晶体管可以包括氧化物半导体薄膜晶体管、非晶硅薄膜晶体管或多晶硅薄膜晶体管等。晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在物理结构上可以是没有区别的，本公开的实施例中全部或部分晶体管的源极和漏极根据需要是可以互换的。
在一些实施例中，如图5A所示，像素电路包括上述的薄膜晶体管T1、T2、T3、T4、T5、T6和T7、存储电容Cst、连接到多个薄膜晶体管T1、T2、T3、T4、T5、T6和T7的第一栅线GLn、第二栅线GLn-1、发光控制线EM、 初始化线RL、数据线DATA和第一电源线VDD。
下面，结合图4和图5A-5E对像素电路的结构进行说明。
例如，图5A为像素电路的半导体层、第一导电层、第二导电层和第三导电层的层叠位置关系的布局示意图。
图5C示出了像素电路的半导体层。例如，图5C所示的该半导体层包括图3A中所示的有源层120，该有源层120例如为第六薄膜晶体管T6的有源层。如图5C所示，半导体层可采用半导体材料层通过构图工艺形成。半导体层可用于制作上述的第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3、第四薄膜晶体管T4、第五薄膜晶体管T5、第六薄膜晶体管T6和第七薄膜晶体管T7的有源层，各有源层可包括源极区域、漏极区域以及源极区域和漏极区域之间的沟道区。例如，半导体层可采用非晶硅、多晶硅、氧化物半导体材料(例如，氧化铟镓锡(IGZO))等制作。需要说明的是，上述的源极区域和漏极区域可为掺杂有n型杂质或p型杂质的区域。
例如，该像素电路的半导体层可以与第一开口周边区域203A中的半导体图案同层形成(当第一开口周边区域203A包括第一虚拟像素时，该半导体图案为第一虚拟像素的半导体层，下文中将详细介绍)，即该像素电路的半导体层与第一开口周边区域203A中的半导体图案可采用相同的半导体材料层通过相同的构图工艺形成。
在本公开一些实施例提供的显示基板中，在上述的半导体层上形成有绝缘层；为了清楚起见，图5A、图5C-5F中未示出绝缘层。
图5D示出了像素电路的第一导电层。例如，如图5D所示，像素电路的第一导电层设置在上述绝缘层上，从而与图5D所示的半导体层绝缘。第一导电层可包括存储电容Cst的第一极板CE1、第一栅线GLn、第二栅线GLn-1、发光控制线EM、以及第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3、第四薄膜晶体管T4、第五薄膜晶体管T5、第六薄膜晶体管T6和第七薄膜晶体管T7的栅极。如图5C所示，第二薄膜晶体管T2、第四薄膜晶体管T4、第五薄膜晶体管T5、第六薄膜晶体管T6和第七薄膜晶体管T7的栅极为第一栅线GLn、第二栅线GLn-1与半导体层交叠的部分。第三薄膜晶体管T3可为双栅结构的薄膜晶体管，第三薄膜晶体管T3的一个栅极可为 第一栅线GLn与半导体层交叠的部分，第三薄膜晶体管T3的另一个栅极可为从第一栅线GLn突出的突出部；第一薄膜晶体管T1的栅极可为第一极板CE1。第四薄膜晶体管T4可为双栅结构的薄膜晶体管，两个栅极分别为第二栅线GLn-1与半导体层交叠的部分。
例如上述各个薄膜晶体管的栅极分别与相应的第一栅线GLn或第二栅线GLn-1一体成型。
例如，图2B中所示的第一信号线2301/2302/2303/2304为第一栅线GLn或第二栅线GLn-1，即各个薄膜晶体管的栅极、第一信号线与存储电容Cst的第一极板CE1同层设置，可通过同一次构图工艺同时形成。
例如，如图5D所示，上述第一信号线2301为第一栅线GLn；例如，在一些实施例中，第一信号线2301还可包括第二栅线GLn-1。下面以上述第一信号线2301为第一栅线GLn作为示例。例如，在一些实施例中，图2B所示的第一信号线2301的位于第一开口周边区域203A中的部分与第一信号线2301的位于第一显示区域2011和第二显示区域2012中的部分同层设置，即图5D中的第一栅线GLn从第一显示区域2011延伸进入第一开口周边区域203A，再从第一开口周边区域203A延伸至第二显示区域2012，第一栅线GLn的位于第一开口周边区域203A中的部分与第一栅线GLn的位于第一显示区域2011和第二显示区域2012中的部分同层设置。又由于多个薄膜晶体管的栅极和栅线同层设置例如一体成型，因此，这种情况即为如图3A所示的情形，整个第一栅线GLn(即第一信号线2301/2302)与栅极121、以及存储电容Cst的第一极板CE1同层设置。例如，第二栅线GLn-1也可以与第一栅线GLn同层设置。
例如，如图5D所示，存储电容Cst的第一极板CE1与第一栅线GLn即第一信号线2301彼此间隔开，以使这两者不电连接，在这两者之间也不存在任何其他的连接结构使两者电连接。例如栅极与第一栅线GLn一体成型，存储电容Cst的第一极板CE1与栅极也彼此间隔开，以使这两者不电连接。
或者，第一信号线2301的位于第一开口周边区域203A中的部分与第一信号线2301的位于第一显示区域2011和第二显示区域2012中的部分异层设置(即与栅极121异层设置)，即图5D中的第一栅线GLn从第一显示区域2011 延伸进入第一开口周边区域203A，再从第一开口周边区域203A延伸至第二显示区域2012，第一栅线GLn的位于第一开口周边区域203A中的部分与第一栅线GLn的位于第一显示区域2011和第二显示区域2012中的部分异层层设置。此时，第一栅线GLn的位于第一开口周边区域203A中的部分通过过孔与第一栅线GLn的位于第一显示区域2011和第二显示区域2012中的部分电连接。又由于多个薄膜晶体管的栅极和栅线同层设置例如一体成型，因此，这种情况即为如图3B所示的情形，第一栅线GLn(即第一信号线2301/2302)的位于第一开口周边区域203A中的部分与栅极121同层设置。例如，第一栅线GLn的位于第一开口周边区域203A中的部分通过穿过图3B所示的第二栅绝缘层152的过孔与第一栅线GLn的位于第一显示区域2011和第二显示区域2012中的部分。
在本公开一些实施例提供的显示基板中，在上述的第一导电层上形成有另一绝缘层，该绝缘层包括图5B中所示的第二栅绝缘层152，在图5A、图5C-5F中也未示出。
图5E示出了像素电路的第二导电层。例如，结合图5B与图5E，像素电路的第二导电层包括存储电容Cst的第二极板CE2、初始化线RL和第二子走线2422，即第二子走线2422与存储电容Cst的第二极板CE2同层设置。第二极板CE2与第一极板CE1至少部分重叠以形成存储电容Cst。
例如，图5E示出的第二极板CE2具有缺口K0，在一些实施例中，第二极板CE2也可以不具有该缺口。本公开的实施例对第二极板CE2的具体结构不做限定。
例如，第一开口周边区域203A中的第一信号线2301与像素电路的第二导电层同层形成，即第一开口周边区域203A中的第一信号线2301与像素电路的第二导电层通过相同的导电材料层并通过相同的构图工艺形成，也即第一信号线2301与第二极板CE2、初始化线RL通过相同的导电材料层并相同的构图工艺形成。
例如，在一些实施例中，第二导电层还可包括第一遮光部791和第二遮光部792。第一遮光部791在衬底基板210上的正投影覆盖第二薄膜晶体管T2的有源层、第三薄膜晶体管T3的漏极和第四薄膜晶体管T4的漏极之间 的有源层，从而防止外界光线对第二薄膜晶体管T2、第三薄膜晶体管T3和第四薄膜晶体管T4的有源层产生影响。第二遮光部792在衬底基板210上的正投影覆盖第三薄膜晶体管T3的两个栅极之间的有源层，从而防止外界光线对第三薄膜晶体管T3的有源层产生影响。第一遮光部791可与相邻像素电路的第二遮光部792为一体结构，并通过贯穿绝缘层中的第十过孔VH9’与第一电源线VDD电连接，如图5A所示。
在本公开一些实施例提供的显示基板中，在上述的第二导电层上形成有另一绝缘层，该绝缘层包括图3A中所示的层间绝缘层160，图5A、图5C-5F中未示出。
图5F示出了像素电路的第三导电层。例如，如图5F所示，像素电路的第三导电层包括数据线DATA(例如为图2A中的第二信号线241/242)和第一电源线VDD的第二子走线2424，即第二子走线2424与数据线DATA同层设置。结合图5A-5B和图5F所示，数据线DATA通过第一栅极绝缘层、第二栅绝缘层和层间绝缘层中的至少一个过孔(例如过孔VH1)与半导体层中的第二薄膜晶体管T2的源极区域相连。第一电源线VDD通过第一栅极绝缘层、第二栅绝缘层和层间绝缘层中的至少一个过孔(例如过孔VH2)与半导体层中对应第五薄膜晶体管T5的源极区域相连。第一电源线VDD通过层间绝缘层中的至少一个过孔(例如过孔VH3)与第二导电层中的第二极板CE2相连。
例如，结合图5A和图5F，第三导电层还包括第一连接部CP1、第二连接部CP2和第三连接部CP3。第一连接部CP1的一端通过第一栅极绝缘层、第二栅绝缘层和层间绝缘层中的至少一个过孔(例如过孔VH4)与半导体层中对应第三薄膜晶体管T3的漏极区域相连，第一连接部CP1的另一端通过第二栅绝缘层和层间绝缘层中的至少一个过孔(例如过孔VH5)与第一导电层中的第一薄膜晶体管T1的栅极相连。第二连接部CP2的一端通过层间绝缘层中的一个过孔(例如过孔VH6)与初始化线RL相连，第二连接部CP2的另一端通过第一栅极绝缘层、第二栅绝缘层和层间绝缘层中的至少一个过孔(例如过孔VH7)与半导体层中的第七薄膜晶体管T7的源极区域和第四薄膜晶体管T4的源极区域相连。第三连接部CP3通过第一栅极绝缘层、第 二栅绝缘层和层间绝缘层中的至少一个过孔(例如过孔VH8)与半导体层中的第六薄膜晶体管T6的漏极区域相连。
在本公开一些实施例提供的显示基板中，在上述的第三导电层上形成有保护层，该保护层包括图5B中所示的第一平坦化层112，图5A、图5C-5F中未示出。例如，第一开口周边区域203A中的阻隔墙28的一个子层与该保护层同层形成，即第一开口周边区域203A中的阻隔墙28的一个子层与该保护层采用相同的绝缘材料层并通过相同的构图工艺形成。
图6为图4所示像素电路的信号时序图。下面结合图6所示的信号时序图，对图4所示的像素电路的工作原理进行说明。例如，在此以图4中的第一发光控制线EM1与第二发光控制线EM2为同一条共用的发光控制线作为示例。在其他一些实施例中，第一发光控制线EM1与第二发光控制线EM2也可以分别为不同的信号线，分别提供不同的第一发光控制信号和第二发光控制信号。
另外，在此以图6所示的晶体管均为P型晶体管为例。各个P型晶体管的栅极在接入低电平时导通，而在接入高电平时截止。以下实施例与此相同，不再赘述。
如图6所示，像素电路的工作过程包括三个阶段，分别为初始化阶段P1、数据写入和补偿阶段P2以及发光阶段P3，图中示出了每个阶段中各个信号的时序波形。
在初始化阶段P1，第二栅线Gn-1提供复位信号Rst，第四晶体管T4和第七晶体管T7被复位信号的低电平导通，将初始化信号(低电平信号，例如可以接地或为其他低电平信号)施加至第一晶体管T1的第一栅极，并将初始化信号施加至N4节点，即将发光元件180复位，从而可以使发光元件180在发光阶段P3之前显示为黑态不发光，改善采用该像素电路的显示装置的对比度等显示效果。同时，第二晶体管T2、第三晶体管T3、第五晶体管T5和第六晶体管T6被各自接入的高电平信号截止。
在数据写入和补偿阶段P2，第一栅线GLn提供扫描信号Gn-1，数据线DATA提供数据信号Data，第二晶体管T2以及第三晶体管T3导通。同时，第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7被各自接 入的高电平信号截止。数据信号Data经过第二晶体管T2、第一晶体管T1和第三晶体管T3后对第一节点N1进行充电(即对存储电容Cst充电)，也就是说第一节点N1的电位逐渐增大。容易理解，由于第二晶体管T2开启，第二节点N2的电位保持为Vdata，同时根据第一晶体管T1的自身特性，当第一节点N1的电位增大到Vdata+Vth时，第一晶体管T1截止，充电过程结束。需要说明的是，Vdata表示数据信号Data的电压值，Vth表示第一晶体管T1的阈值电压，由于在本实施例中，第一晶体管T1是以P型晶体管为例就行说明的，所以此处阈值电压Vth可以是负值。
经过数据写入和补偿阶段P2后，第一节点N1和第三节点N3的电位均为Vdata+Vth，也就是说将带有数据信号Data和阈值电压Vth的电压信息被存储在存储电容Cst中，以用于后续在发光阶段时，提供灰度显示数据和对第一晶体管T1自身的阈值电压进行补偿。
在发光阶段P3，发光控制线提供发光控制信号EM，第五晶体管T5和第六晶体管T6被发光控制信号EM的低电平导通。第二晶体管T2、第三晶体管T3、第四晶体管T4和第七晶体管T7被各自接入的高电平而截止。同时，第一节点N1的电位Vdata+Vth，第二节点N2的电位为VDD，所以在此阶段第一晶体管T1也保持导通。发光元件180的阳极和阴极分别接入了第一电源线VDD提供的第一电源电压(高电压)和第二电压电压VSS(低电压)，从而，发光元件180在流经第一晶体管T1的驱动电流的作用下发光。
图7A为图2A中的第一开口区域的另一种局部放大示意图，图7B为沿图7A中的H-H’线的一种截面示意图。
图7A和图7B所示的实施例与图2B和图2C所示的实施例具有以下区别。如图7A和图7B所示，第二信号线241/242为第一电源线VDD的第二子走线，第二子走线241/242依次穿过第一开口周边区域203A和所述第三显示区域2013，例如在本实施例中，第二子走线241/242沿第二方向R2依次穿过第三显示区域2013的第二部分2013D、第一开口周边区域203A和第三显示区域2013的第一部分2013C。例如，如图7B所示，第二子走线241/242位于第一信号线2301/2302和发光控制线2305/2306的远离衬底基板210的 一侧。
本实施例提供的显示基板能够达到与上述实施例相同或相似的技术效果，在此不再赘述。本实施例提供的显示基板的其他特征及相应技术效果均与之前的实施例中的相同，请参考之前的描述。
示例性地，图8A为本公开实施例的又一种显示基板的平面示意图，图8B为图8A中的第一开口区域和第二开口区域的局部放大示意图。
在图8A和图8B所示的实施例与图2A所示的实施例具有以下区别。在图8A和图8B中，显示基板20包括开口区域200，开口区域200包括第一开口区域202A、与第一开口区域202A相邻的第二开口区域202B，以及包括开口间区域2014。第一开口区域202A包括第一开口201A和围绕第一开口201A的第一开口周边区域203A；第二开口区域202B包括第二开口201B和围绕第二开口201B的第二开口周边区域203B。开口间区域2014位于第一开口区域202A和第二开口区域202B之间。
例如，在图8A和图8B所示的实施例中，第二开口区域202B与第一开口区域202A沿第一方向R1排列，由此，开口间区域2014在第一方向R1上位于第一开口区域202A和第二开口区域202B之间。第一显示区域2011位于第一开口区域202A的远离开口间区域2014的一侧，第二显示区域2012位于第二开口区域202B的远离开口间区域2014的一侧。这种情况下，第一显示区域2011位于第一开口区域202A的第一侧，第二显示区域2012位于第二开口区域201B的第二侧。即，第一显示区域、第一开口区域、开口间区域、第二开口区域和第二显示区域沿所述第一方向依次排列。分别对于第一开口区域202A和第二开口区域201B来说，仍然满足第一显示区域2011位于第一开口区域202A的第一侧，第二显示区域2012位于第一开口区域202A的第二侧，该第一侧与该第二侧在第一方向R1上彼此相对。第一信号线23沿第一方向R1依次穿过第一显示区域2011、第一开口周边区域203A、开口间区域2014、第二开口周边区域203B和第二显示区域2012。第一信号线23和第二信号线24在第二开口区域202B中的排布情况与在上述实施例中的第一开口区域202A中的排布情况相同，相关技术特征请参考之前的描述，在此不再重复。
例如，在图8C所示的实施例中，第二开口区域202B之与第一开口区域202A沿第二方向R2排列，因此开口间区域2014在第二方向R2上位于第一开口区域202A和第二开口区域202B之间。第二信号线24沿第二方向R2依次穿过第一开口周边区域203A、开口间区域2014、第二开口周边区域203B以及第三显示区域2013。图8C所示的除了第二开口区域202B与第一开口区域202A的排列方向之外的其他特征均与图8B中的相同，这里不再赘述。这种情况下，对于第一开口区域202A，第二绕线部C1C2是从第一开口201A的第三侧围绕第一开口201A地延伸至第一开口201A的第四侧，第一开口201A的第三侧与第一开口201A的第四侧在第二方向R2上彼此相对；对于第二开口区域202B，位于第二开口区域202B的第二开口周边区域203B中的第二绕线部C1C2是从第二开口201B的第三侧围绕第二开口201B地延伸至第二开口201B的第四侧，第二开口201B的第三侧与第二开口201B的的第四侧在第二方向R2上彼此相对。
例如，对于图8B和图8C所示的显示基板，开口间区域2014、第一开口周边区域203A和第二开口周边区域203B三者中的至少之一者包括一个或多个第一虚拟子像素，该第一虚拟子像素虽然具有至少部分或基本完整的像素电路结构，但是在操作中并不会发光，因此不参与到显示操作中。例如，第一虚拟子像素包括第一虚拟像素电路，第一虚拟像素电路包括第一补偿电容，以用于对于信号线提供负载补偿。
图9为本公开至少一实施例提供的一种显示基板中的第一虚拟像素电路的等效电路图；图10A为本公开一实施例提供的一种显示基板中的第一虚拟像素电路的平面布局示意图；图10B为沿图10A中的A2-B2线的截面示意图；图10C-图10F为本公开一实施例提供的一种显示基板的像素电路的各层的示意图。如上所述，第一虚拟子像素的像素电路结构与显示区域的子像素的像素电路至少部分相同或基本相同，因此可结合图4以及图5A-图5F所示出的示意图理解。
结合图4和图9所示，第一虚拟子像素的像素电路与显示区域的子像素的像素电路的区别包括存储电容的连接方式不同。在图4所示的像素电路中，存储电容包括第一极板CE1和第二极板CE2，第二极板CE2与第一电源线 VDD电连接，第一极板CE1与第一薄膜晶体管T1的第一栅极和第三薄膜晶体管T3的第三漏极D3电连接。在图9所示的像素电路中，存储电容被转用为补偿电容，并且具有改变了的连接关系，其中一个极板连接到栅线GLn，且与第三薄膜晶体管T3的第三漏极D3断开。
如图10A和图10B所示，第一补偿电容COM1包括第一极板CE1和第二极板CE2。如图10B所示，第一补偿电容COM1的第一极板CE1与第一信号线2301同层设置且与第一信号线2301电连接，例如一补偿电容COM1的第一极板CE1与第一信号线2301一体成型。第一补偿电容COM1的第二极板CE2与第一补偿电容COM1的第一极板COM1异层设置且绝缘；例如，第一补偿电容COM1的第一极板CE1在衬底基板210上的正投影与第一补偿电容COM1的第二极板CE2在衬底基板210上的正投影至少部分重叠。第一补偿电容COM1为与之连接的第一信号线2301提供负载补偿。
例如，第一虚拟像素电路包括第一虚拟半导体层，第一虚拟半导体层位于所述第一信号线的靠近衬底极板的一侧。图10C示出了第一虚拟像素电路的第一虚拟半导体层的图案，例如，该第一虚拟半导体层的图案与显示区域的子像素的像素电路的半导体层的图案相同，以保持显示基板的刻蚀均一性，且简化第一虚拟像素电路的制备工艺，降低制造成本。
图10D示出了第一虚拟像素电路的位于第一导电层的一种结构，图10E示出了第一虚拟像素电路的位于第二导电层的结构。
结合图10A-图10B和图10D-图10E，第一补偿电容COM1的第一极板CE1包括第一主体部分CE10和第一延伸部CE11。
第一补偿电容COM1的第一极板CE1位于第一导电层，即像素电路的各个薄膜晶体管的栅极与存储电容CST的第一极板以及第一补偿电容COM1的第一极板同层设置。并且，第一补偿电容COM1的第一极板CE1位于第一信号线2301(例如第一信号线2301为第一栅线GLn)的在第二方向R2上的第一侧；第一延伸部CE11自第一主体部分朝向第一信号线延伸，位于第一信号线2301在第二方向上的第一侧，且位于第一主体部分CE10与第一信号线2301的之间。第一主体部分CE10通过第一延伸部CE11与第一信号线2301电连接。例如，第一主体部分CE10和第一延伸部CE11具有在 第一方向上具有基本相同的宽度；又例如，在第一方向上，第一主体部分CE10的宽度比第一延伸部CE11的宽度大，也即，在第一主体部分CE10与第一信号线2301通过二者之间的缩窄的第一延伸部CE11电连接；再例如，在第一方向上，第一主体部分CE10的宽度比第一延伸部CE11的宽度小，也即，在第一主体部分CE10与第一信号线2301通过二者之间的扩大的第一延伸部CE11电连接。
第一补偿电容COM1的第二极板CE2位于第二导电层，即第一补偿电容COM1的第二极板和存储电容CST的第二极板同层设置。并且，第一补偿电容COM1的第二极板CE2与第一补偿电容COM1的第一极板CE1在垂直于衬底基板210的方向上至少部分重叠，如图10B所示，从而形成第一补偿电容COM1。例如第一主体部分CE10的图案可以与显示区域的子像素中的像素电路的存储电容的第一极板的图案相同。
相比于图5B所示的显示区域的像素电路中的存储电容CST的第一极板CE1，在第一虚拟子像素中，由于第一延伸部CE11的存在，第一补偿电容COM1的第一极板CE1的面积被增大，从而可以增大第一补偿电容COM1的第一极板CE1与第一补偿电容COM1的第二极板CE2的重叠面积，以增大该第一补偿电容COM1的电容，从而进一步增大第一信号线2301的负载。
例如，如图10D所示，第一主体部分CE10、第一延伸部CE11、第一信号线2301一体成型。
图10G示出了第一虚拟像素电路的位于第一导电层的另一种结构。例如，如图10G所示，第一补偿电容COM1的第一极板CE1还包括第二延伸部CE12。第二延伸部CE12自第一信号线2301朝向远离第一主体部分2301的方向延伸，位于第一信号线2301的在第二方向R2上的第二侧且与第一信号线2301电连接，第一信号线2301的第二侧与第一信号线2301的第一侧相对，从而进一步增大第一补偿电容COM1的第一极板CE1的面积。由此，如果同时增大第一补偿电容COM1的第二极板的面积，则可进一步增大第一补偿电容COM1，满足对第一信号线的更大范围的补偿程度的需求。
例如，如图10G所示，第一主体部分CE10、第一延伸部CE11、第一信号线2301和第二延伸部CE12一体成型。
在至少一实施例中，例如，第一延伸部CE11在第一方向R1上的宽度、第二延伸部CE12在第一方向R1上的宽度与第一主体部分CE10在第一方向R1上的宽度基本相等，以充分利用有限的空间实现更大范围的补偿程度的需求。
第一显示区域2011和第二显示区域2012的第一像素阵列的第一像素行和第二像素行均被第一开口区域202A、开口间区域2014和第二开口区域202B三者构成的整体断开。
开口间区域2014包括与第一像素行对应的第一虚拟子像素行和与第二像素行对应的第二虚拟子像素行。配置为给第一像素行提供第一显示信号的第一信号线穿过第一像素行和第一虚拟像素行，配置为给第二像素行提供第一显示信号的第一信号线穿过第二像素行和第二虚拟像素行。第一像素行的像素的数量与第二像素行的像素的数量不相同。因此，配置为给第一像素行提供第一显示信号的第一信号线与配置为给第二像素行提供第一显示信号的第一信号线的负载不同，对此，例如第一虚拟像素行中的第一补偿电容COM1的数量与第二虚拟像素行中的第一补偿电容COM1的数量不相同，以对这些负载不同的第一信号线进行负载补偿，以使这些第一信号线的负载基本相同，从而减小由于设置第一开口区域对显示质量的不利影响。
例如，图11示出了第一开口区域或第二开口区域附近的六行像素。例如，在一些示例中，如图11所示，假设第六行子像素为满行的像素行，穿过满行像素的第一信号线的总负载为M。例如第一行到第五行像素为第一开口区域两侧的像素，为非满行的像素行，且从第一行到第五行，像素的数量逐渐增加。此时，通过为第一行到第五行像素中的子像素提供第一补偿电容COM1，以使每一行像素的第一信号线的负载趋近于或者基本等于M。例如，为第一行到第五行像素中的子像素提供的第一补偿电容COM1的总数量是逐步减少的。同样，下文所述的第二补偿电容的数量也可以类似地根据需要进行设计。
图10F示出了第一虚拟像素电路的位于第三导电层的结构。结合图10A-图10B和图10F，第一虚拟像素电路还包括第一转接电极CP1，第一转接电极CP1与第一补偿电容COM1的第一极板CE1电连接，且与第一虚拟像素 电路的除了第一信号线2301的其他部分通过间隔K1断开。显示基板还包括断开电极CP4，断开电极CP4与第一虚拟半导体通过过孔VH4电连接。
如图10B所示，第一虚拟半导体包括局部A1和局部A3，断开电极CP4通过过孔VH4与局部A1电连接。断开电极CP4与第一转接电极CP1同层设置，例如均位于图10F所示的第三导电层，且断开电极CP4与第一转接电极CP1间隔开以彼此不连接，从而使第一补偿电容COM1的第一极板CE1与第一虚拟像素电路的除了第一信号线2301的其他部分断开，从而使第一虚拟像素电路断路，第一虚拟子像素不执行显示功能，且不影响第一补偿电容COM1的两个基板。例如，断开电极CP4与第一转接电极CP1之间存在间隔K1，断开电极CP4与第一转接电极CP1被间隔K1断开。
对比图10F与图5F，两图中的数据线DATA、第一电源线VDD、第二连接部CP2和第三连接部CP3的图案均相同，将图5F中的CP1断开即得到图10F所示的第一转接电极CP1和断开电极CP4。第一虚拟像素电路和显示区域的像素电路具有相同的电路设计，除了第一补偿电容COM1的第一极板CE1的形状、以及第一补偿电容COM1的第一极板CE1与第一虚拟像素电路的其他部分断开之外。
如上所述，虽然在上述实施例中，图9所示的像素电路与图4所示的像素电路相比，区别包括第一补偿电容COM1的第一极板CE1的形状以及与第一信号线之间的连接关系，但是，在该实施例的其他示例中，图9所示的像素电路还可以进一步包括更多的区别，这些区别包括但不限于：晶体管T2与数据线断开(即不再接受数据线信号)、晶体管T2与节点N2断开、晶体管T6与OLED断开等。本公开的实施例对这些区别不作限制，至少使得第一虚拟子像素能够提供补偿电容，同时又基本不影响显示区域的显示操作即可。
图12A为本公开一实施例提供的一种显示基板中的一个第二虚拟子像素(图中右侧的在虚拟子像素)中的第二虚拟像素电路的平面布局示意图；图12B为沿图12A中的A3-B3线的截面示意图；图12C-图12F为本公开一实施例提供的一种显示基板的第二虚拟像素电路的各层的示意图。
在一些实施例中，例如，开口间区域2014还包括第二虚拟子像素，第二 虚拟子像素包括第二虚拟像素电路，如图12A所示。第二虚拟像素电路包括第二补偿电容COM10，第二补偿电容COM10包括第一极板CE10和第二极板CE20。
图12D示出了第二虚拟像素电路的位于第一导电层的一种结构，图12E示出了第二虚拟像素电路的位于第二导电层的结构。
结合图12A-图12B和图12D-图12E，第二补偿电容COM10的第一极板CE10与第一信号线2301同层设置，例如均位于第一导电层，并且，第二补偿电容COM10的第一极板CE10与第一信号线2301电连接。第一信号线2301在衬底基板210上的正投影与第二补偿电容COM10的第二极板CE20在衬底基板210上的正投影至少部分重叠。
如图12D所示，第二补偿电容COM10的第一极CE10板包括：第二主体部分CE100和第三延伸部CE101。第二主体部分CE100位于第一信号线2301的在第二方向R2上的第一侧；第三延伸部CE101自第二主体部分CE100在第二方向R2上朝向第一信号线2301延伸，位于第一信号线2301在第二方向上的第一侧，且位于第二主体部分CE100与第一信号线2301的之间，第二主体部分CE100通过第三延伸部CE101与第一信号线2301电连接。例如，第二补偿电容COM10的第一极CE20板包括第四延伸部CE102，第四延伸部CE102自第一信号线2301朝向远离第二主体部分CE100的方向延伸，位于第一信号线2301的在第二方向R2上的第二侧且与第一信号线2301电连接，第一信号线2301的第二侧与第一信号线2301的第一侧相对，从而进一步增大第二补偿电容COM10的第一极板CE10的面积，如果同时增大第二补偿电容COM10的第二极板的面积，则可进一步增大第二补偿电容COM10，满足对第一信号线的不同补偿程度的需求。
例如，第二主体部分CE100、第三延伸部CE101、第一信号线2301和第四延伸部CE102一体成型，从而可利用同一次构图工艺形成这些结构，简化显示基板的制作工艺。
结合图12A-图12B与图12E，第二补偿电容COM10的第二极板CE20包括第三主体部分CE200和第五延伸部CE201。第三主体部分CE200位于第一信号线2301的在第二方向R2上的第一侧；第五延伸部CE201自第三主 体部分CE200在第二方向R2上朝向第一信号线2301延伸，第一信号线2301在衬底基板210上的正投影与第五延伸部CE201在衬底基板210上的正投影至少部分重叠。
例如，如图12B所示，第二补偿电容COM10的第一极板CE10在衬底基板210上的正投影位于第二补偿电容COM10的第二极板CE20在所述衬底基板210上的正投影内，以最大化利用第二补偿电容COM10的第一极板CE10的面积，利用有限的空间形成所需的第二补偿电容的大小。
例如，如图12E所示，第二补偿电容COM10的第二极板CE20的一部分7921可以与显示区像素电路中的遮光部的位置和图案相同，以保持刻蚀均一性。
例如，第二虚拟子像素包括第二虚拟半导体层，第二虚拟半导体层位于第二补偿电容的第一极板的靠近衬底基板的一侧。图12C示出了第二虚拟子像素的图案，第二虚拟子像素为图12C中右侧的在虚拟子像素A02。结合图12A和图12C所示，第二虚拟半导体层包括间隔开以彼此不连接的第一部分AP21和第二部分AP22；第一部分AP21位于第一信号线2301的第一侧，第二部分AP22位于第一信号线2301的第二侧；第一信号线2301在衬底基板210上的正投影与第一虚拟半导体层在衬底基板210上的正投影不重叠，从而第二虚拟像素电路中不存在真正的薄膜晶体管，不实现显示功能。例如，第二补偿电容COM10在衬底基板210上的正投影与第一虚拟半导体层在衬底基板上的正投影不重叠。
图12F示出了第二虚拟像素电路的位于第三导电层的结构。结合图12A-图12B、图12E和图12F，第二虚拟像素电路包括第二转接电极CP10，第二转接电极CP10与第一虚拟像素电路的第一转接电极，以及显示区域的像素电路的第一连接部CP1同层设置，例如均位于第三导电层，且与第二补偿电容COM10的第二极板CE20电连接，例如，第二转接电极CP10通过过孔VH40和过孔VH50与第二补偿电容COM10的第二极板CE20电连接，以保持此处与显示基板的显示区域等其他位置的刻蚀均一性。
例如，结合图12A-图12B与图12E，第二补偿电容COM10的第二极板CE20通过过孔VH40和过孔VH50与第一电源线VDD连接，例如与第一电 源线VDD的第一走线2424连接，以给第二补偿电容COM10的第二极板CE20提供第一电源电压，以形成第二补偿电容COM10。
例如，第二虚拟半导体层的第二部分AP22均配置为通过第二虚拟像素电路被寄予电信号；第一虚拟半导体层的第一部分AP21在第一方向R1上具有彼此相对的第一端P21和第二端P22，第二端P22配置为通过第二虚拟像素电路被寄予所述电信号，第一端P21与第二端P22连接，从而可将来自第二端P2的电信号传输给第一端P21，防止由于第一端P21无信号输入导致的信号漂移。例如，如图12A所示，第二端P22与第一电源线VDD的第二子走线2424电连接，例如通过过孔VH20电连接，从而将来自第一电源线VDD的第二子走线2424的第一电源电压传输给第二端P22和第一端P21。
例如，为了保持刻蚀均一性，开口间区域2014还包括第三虚拟子像素(图12C中的左侧的虚拟子像素A01)，每个第三虚拟子像素包括第三虚拟像素电路，所述第三虚拟像素电路包括第三虚拟半导体层，第三虚拟半导体层与第二虚拟半导体层以及第一虚拟半导体层同层设置。第三虚拟半导体层包括间隔开以彼此不连接的第一部分AP11和第二部分AP12，第三虚拟半导体层的第一部分AP11位于第一信号线2301的第一侧，第三虚拟半导体层的第一部分AP11位于第一信号线2301的第二侧；第一信号线2301在衬底基板210上的正投影与第三虚拟半导体层在衬底基板上的正投影不重叠，从而在第三虚拟子像素中不形成真正的薄膜晶体管，第三虚拟子像素不执行显示功能。
例如，如图8B和图8C所示，在开口间区域2014的靠近显示区域的外侧区域2015中不设置第二虚拟半导体层，而设置第三虚拟像素电路，以维持外侧区域2015与显示区域的刻蚀均一性，避免影响显示均一性。
例如，在一些实施例中，除了第二虚拟半导体层被断开之外，第三虚拟像素电路与显示区域中的子像素的像素电路具有相同的电路设计。例如，图12F中第三虚拟像素电路的连接结构CP11/CP21/CP31可以与像素电路中相应位置的连接结构的图案相同，例如与第二虚拟像素电路中的连接结构CP10/CP20/CP30的位置和图案也相同，以保持刻蚀均一性。或者，第三虚拟像素电路的部分信号线与像素电路中相应的信号线的位置也可以不同，例如图12E中，第一电源线VDD位于数据线DATA的右侧且不与数据线DATA 相邻，而在图5F所示的像素电路的位于第三导电层的图案中，第一电源线VDD与数据线DATA相邻。在显示区的子像素、第一虚拟子像素、第二虚拟子像素和第三虚拟子像素中，各个层的具体图案可根据需要进行调整或微调，不作具体限定。例如第三虚拟子像素中，发光器件具有第一电极，但不具有第二电极，从而使的第三虚拟子像素不发光。
图13B为图13A的跑道形开口的包括弧形走线的局部L1的放大示意图；图13C为图13A的跑道形开口的包括直线走线的局部L2的放大示意图。这种情况下，第一显示区域2011位于第一开口区域202A的第一侧，第二显示区域2012位于第二开口区域201B的第二侧。分别对于第一开口区域202A和第二开口区域201B来说，仍然满足第一显示区域2011位于第一开口区域202A的第一侧，第二显示区域2012位于第一开口区域202A的第二侧，该第一侧与该第二侧在第一方向R1上彼此相对。
如图13B所示，在一些实施例中，第一开口区域202A的平面形状为跑道形，其包括的第一开口201A的平面形状也为跑道形，至少部分围绕第一开口201A的第一信号线2301/2305包括弧形和直线段。
如图13B所示，来自第一显示区域2011的第一信号线的直线形部分2301-1继续延伸而部分地围绕第一开口201A，第一信号线的围绕第一开口201A的第一绕线部包括弧形部分2301-2。沿第二方向延伸的第二信号线的第二绕线部也包括弧形部分241-2。例如，该第一绕线部的弧形部分2301-2与第二绕线部的弧形部分241-2在垂直于衬底基板的方向上部分重叠。
如图13C所示，在第一开口周边区域中，第一信号线的第一绕线部包括直线形部分2301-3。沿第二方向延伸的第二信号线的第二绕线部也包括直线形部分241-1。例如，第一信号线的第一绕线部的直线形部分2301-3与第二信号线的第二绕线部的直线形部分241-1在垂直于衬底基板的方向上部分重叠。
例如，在图13B和图13C中，包括直线部分2301-1/2301-3和弧形部分2301-2和第一信号线为栅扫描信号线，该栅扫描信号线与第二信号线部分重叠；第一信号线2305是发光控制线，在其他实施例中，也可以是发光控制线与第二信号线部分重叠。
本公开至少一实施例提供一种显示装置，包括上述任一的显示基板。该显示装置例如可以为有机发光二极管显示装置、量子点发光二极管显示装置等具有显示功能的装置或其他类型的装置，本公开的实施例对此不作限制。
本公开实施例提供的显示装置的结构、功能及技术效果等可以参考上述本公开实施例提供的显示基板中的相应描述，在此不再赘述。
例如，本公开至少一实施例提供的显示装置可以为显示面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件，本公开的实施例对此不作限制。
以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开的保护范围由所附的权利要求确定。

Claims (27)

  1. 一种显示基板，包括：
    衬底基板，包括：
    第一开口区域，包括第一开口和围绕所述第一开口的第一开口周边区域；
    第二开口区域，与所述第一开口区域相邻设置，且包括第二开口和围绕所述第二开口的第二开口周边区域；
    开口间区域，位于所述第一开口区域和所述第二开口区域之间，其中，所述开口间区域、所述第一开口周边区域和所述第二开口周边区域三者中的至少一者包括第一虚拟子像素；以及
    显示区域，至少部分围绕所述第一开口区域、所述第二开口区域和所述开口间区域，且包括像素阵列；
    第一信号线，延伸穿过所述开口间区域，配置为给所述像素阵列提供第一显示信号且穿过所述第一虚拟子像素，其中，所述第一虚拟子像素包括第一虚拟像素电路，所述第一虚拟像素电路包括第一补偿电容，所述第一补偿电容包括：
    第一极板，与所述第一信号线同层设置且与第一信号线电连接；以及
    第二极板，与所述第一极板异层设置且绝缘，其中，所述第一补偿电容的第二极板在所述衬底基板上的正投影与所述第一补偿电容的第一极板在所述衬底基板上的正投影至少部分重叠。
  2. 根据权利要求1所述的显示基板，其中，所述第一信号线沿第一方向延伸，所述第一开口区域和所述第二开口区域沿第一方向相邻设置；第二方向与所述第一方向垂直；
    所述第一补偿电容的第一极板包括：
    第一主体部分，位于所述第一信号线的在所述第二方向上的第一侧；
    第一延伸部，自所述第一主体部分朝向所述第一信号线延伸，位于所述第一信号线在所述第二方向上的第一侧，且位于所述第一主体部分与所述第一信号线的之间，其中，所述第一主体部分通过所述第一延伸部与所述第一信号线电连接。
  3. 根据权利要求2所述的显示基板，其中，所述第一补偿电容的第一极板还包括：
    第二延伸部，自所述第一信号线朝向远离所述第一主体部分的方向延伸，位于所述第一信号线的在所述第二方向上的第二侧且与所述第一信号线电连接，所述第二侧与所述第一侧相对。
  4. 根据权利要求3所述的显示基板，其中，所述第一主体部分、所述第一延伸部、所述第一信号线和所述第二延伸部一体成型。
  5. 根据权利要求3所述的显示基板，其中，所述第一延伸部在所述第一方向上的宽度、所述第二延伸部在所述第一方向上的宽度与所述第一主体部分在所述第一方向上的宽度基本相等。
  6. 根据权利要求1-5任一所述的显示基板，其中，所述显示区域包括：
    第一显示区域，位于所述第一开口区域的远离所述开口间区域的一侧；以及
    第二显示区域，位于所述第二开口区域的远离所述开口间区域的一侧，其中，所述第一显示区域和所述第二显示区域包括第一像素阵列，所述第一像素阵列包括分别沿所述第一方向延伸的第一像素行和第二像素行，所述第一像素行和所述第二像素行均被所述第一开口区域、所述开口间区域和所述第二开口区域三者构成的整体断开；
    所述第一信号线沿所述第一方向依次穿过所述第一显示区域、所述第一开口周边区域、所述开口间区域、所述第二开口周边区域和所述第二显示区域；所述显示基板包括：
    配置为给所述第一像素行提供所述第一显示信号的所述第一信号线，以及
    配置为给所述第二像素行提供所述第一显示信号的所述第一信号线。
  7. 根据权利要求6所述的显示基板，其中，所述开口间区域包括与所述第一像素行对应的第一虚拟子像素行和与所述第二像素行对应的第二虚拟子像素行；
    所述配置为给所述第一像素行提供所述第一显示信号的所述第一信号线穿过所述第一像素行和所述第一虚拟像素行，所述配置为给所述第二像素行 提供所述第一显示信号的所述第一信号线穿过所述第二像素行和所述第二虚拟像素行；
    所述第一像素行的像素的数量与所述第二像素行的像素的数量不相同，所述第一虚拟像素行中的所述第一补偿电容的数量与所述第二虚拟像素行中的所述第一补偿电容的数量不相同。
  8. 根据权利要求1-7任一所述的显示基板，其中，所述第一信号线为栅扫描信号线，所述第一显示信号为栅扫描信号。
  9. 根据权利要求1-8任一所述的显示基板，其中，所述显示区域包括多个像素，每个所述像素包括多个子像素，每个所述子像素包括像素电路；
    所述像素电路包括：
    晶体管，包括有源层、栅极和源漏极；
    发光元件，与所述晶体管的源漏极之一连接；以及
    存储电容，包括第一极板和第二极板，其中，
    所述栅极、所述第一信号线、所述存储电容的第一极板以及所述第一补偿电容的第一极板同层设置。
  10. 根据权利要求9所述的显示基板，其中，所述存储电容的第一极板与所述第一信号线彼此间隔开，且与所述栅极此间隔开。
  11. 根据权利要求9或10所述的显示基板，其中，所述第一补偿电容的第二极板和所述存储电容的第二极板同层设置。
  12. 根据权利要求1-11任一所述的显示基板，其中，所述第一补偿电容的第一极板与所述第一虚拟像素电路的除了所述第一信号线之外的其他部分断开。
  13. 根据权利要求12所述的显示基板，其中，所述第一虚拟像素电路还包括：
    第一转接电极，与所述第一补偿电容的第一极板电连接，且与所述第一虚拟像素电路的除了所述第一信号线之外的其他部分断开。
  14. 根据权利要求13所述的显示基板，其中，所述第一虚拟像素电路包括第一虚拟半导体层，所述第一虚拟半导体层位于所述第一信号线的靠近所述衬底极板的一侧；
    所述显示基板还包括：
    断开电极，与所述第一虚拟半导体层电连接，与所述第一转接电极同层设置，且与所述第一转接电极间隔开以彼此不连接。
  15. 根据权利要求13或14所述的显示基板，其中，所述第一虚拟像素电路和所述像素电路具有相同的电路设计，除了所述第一补偿电容的第一极板、以及所述第一补偿电容的第一极板与所述第一虚拟像素电路的其他部分断开之外。
  16. 根据权利要求1-15任一所述的显示基板，其中，所述开口间区域还包括：
    第二虚拟子像素，包括第二虚拟像素电路，其中，所述第二虚拟像素电路包括第二补偿电容；
    所述第二补偿电容的第一极板与所述第一信号线同层设置且与所述第一信号线电连接；
    所述第一信号线在所述衬底基板上的正投影与所述第二补偿电容的第二极板在所述衬底基板上的正投影至少部分重叠。
  17. 根据权利要求16所述的显示基板，其中，所述第二补偿电容的第二极板包括：
    第二主体部分，位于所述第一信号线的在所述第二方向上的第一侧；以及
    第三延伸部分，自所述第二主体部分在所述第二方向上朝向所述第一信号线延伸，所述第一信号线在所述衬底基板上的正投影与所述第三延伸部分在所述衬底基板上的正投影至少部分重叠。
  18. 根据权利要求16或17所述的显示基板，其中，所述第二补偿电容的第二极板与所述第一补偿电容的第二极板同层设置。
  19. 根据权利要求16-18任一所述的显示基板，其中，所述第二补偿电容的第一极板包括：
    第三主体部分，位于所述第一信号线的在所述第二方向上的第一侧；
    第四延伸部分，自所述第三主体部分在所述第二方向上朝向所述第一信号线延伸，位于所述第三主体部分与所述第一信号线的之间，其中，所述第 三主体部分通过所述第四延伸部与所述第一信号线电连接。
  20. 根据权利要求16-19任一所述的显示基板，其中，所述第二补偿电容的第一极板在所述衬底基板上的正投影位于所述第二补偿电容的第二极板在所述衬底基板上的正投影内。
  21. 根据权利要求16-20任一所述的显示基板，其中，所述第二虚拟子像素电路包括第二转接电极，所述第二转接电极与所述第一转接电极同层设置且与所述第二补偿电容的第二极板电连接。
  22. 根据权利要求16-21任一所述的显示基板，其中，所述第二虚拟子像素包括：
    第一虚拟半导体层，包括间隔开以彼此不连接的第一部分和第二部分，其中，所述第一部分位于所述第一信号线的所述第一侧，所述第二部分位于所述第一信号线的所述第二侧；
    所述第一信号线在所述衬底基板上的正投影与所述第一虚拟半导体层在所述衬底基板上的正投影不重叠。
  23. 根据权利要求22所述的显示基板，其中，所述第一虚拟半导体层的第二部分均配置为通过所述第二虚拟像素电路被寄予电信号；
    所述第一虚拟半导体层的第一部分在所述第一方向上具有彼此相对的第一端和第二端，所述第二端配置为通过所述第二虚拟像素电路被寄予所述电信号，所述第一端与所述第二端连接。
  24. 根据权利要求9-11任一所述的显示基板，其中，所述开口间区域还包括第三虚拟子像素，所述第三虚拟子像素包括第三虚拟像素电路，所述第三虚拟像素电路包括：
    第二虚拟半导体层，其中，所述第二虚拟半导体层包括间隔开以彼此不连接的第一部分和第二部分，所述第二虚拟半导体层的第一部分位于所述第一信号线的所述第一侧，所述第二虚拟半导体层的第一部分位于所述第一信号线的所述第二侧；
    所述第一信号线在所述衬底基板上的正投影与所述第三虚拟半导体层在所述衬底基板上的正投影不重叠。
  25. 根据权利要求24所述的显示基板，其中，所述第三虚拟子像素与所 述像素电路具有相同的电路设计，除了在所述第二虚拟半导体层被断开之外。
  26. 根据权利要求7-15任一所述的显示基板，其中，所述显示区域还包括：
    第三显示区域，在所述第二方向上位于所述第一显示区域和所述第二显示区域的至少一侧，且同时与所述第一显示区域和所述第二显示区域相接，包括第二像素阵列；
    所述第二像素阵列包括多行多列像素，所述第三显示区域包括分别为所述多行多列像素中的每一行像素提供扫描信号且沿所述第一方向延伸的多条第三信号线；
    所述第二像素阵列的每一行像素所包括的像素的数量多于所述第一像素阵列的所述第一像素行包括的像素的数量以及所述第一像素阵列的所述第二像素行包括的像素的数量。
  27. 一种显示装置，包括根据权利要求1-26任一所述的显示基板。
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