WO2021233347A1 - 电网中的电能质量等级确定方法、装置、设备和存储介质 - Google Patents

电网中的电能质量等级确定方法、装置、设备和存储介质 Download PDF

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WO2021233347A1
WO2021233347A1 PCT/CN2021/094665 CN2021094665W WO2021233347A1 WO 2021233347 A1 WO2021233347 A1 WO 2021233347A1 CN 2021094665 W CN2021094665 W CN 2021094665W WO 2021233347 A1 WO2021233347 A1 WO 2021233347A1
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current
harmonic
voltage
compensated
phase
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PCT/CN2021/094665
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English (en)
French (fr)
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窦保信
徐勇烈
林云志
金涛
余刚
周文钊
罗兵
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中铁电气化局集团有限公司
福州大学
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Priority to EP21809513.1A priority Critical patent/EP4064496A4/en
Publication of WO2021233347A1 publication Critical patent/WO2021233347A1/zh

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    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02JCIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J3/00Circuit arrangements for ac mains or ac distribution networks
    • H02J3/18Arrangements for adjusting, eliminating or compensating reactive power in networks
    • H02J3/1821Arrangements for adjusting, eliminating or compensating reactive power in networks using shunt compensators
    • H02J3/1835Arrangements for adjusting, eliminating or compensating reactive power in networks using shunt compensators with stepless control
    • H02J3/1842Arrangements for adjusting, eliminating or compensating reactive power in networks using shunt compensators with stepless control wherein at least one reactive element is actively controlled by a bridge converter, e.g. active filters
    • H02J3/1857Arrangements for adjusting, eliminating or compensating reactive power in networks using shunt compensators with stepless control wherein at least one reactive element is actively controlled by a bridge converter, e.g. active filters wherein such bridge converter is a multilevel converter
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02JCIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J3/00Circuit arrangements for ac mains or ac distribution networks
    • H02J3/01Arrangements for reducing harmonics or ripples
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02JCIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J3/00Circuit arrangements for ac mains or ac distribution networks
    • H02J3/001Methods to deal with contingencies, e.g. abnormalities, faults or failures
    • H02J3/0012Contingency detection
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E40/00Technologies for an efficient electrical power generation, transmission or distribution
    • Y02E40/20Active power filtering [APF]
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E40/00Technologies for an efficient electrical power generation, transmission or distribution
    • Y02E40/40Arrangements for reducing harmonics

Definitions

  • This application relates to the field of power grid control technology, and in particular to a method, device, equipment, and storage medium for determining the power quality level in the power grid.
  • active filters are widely used in three-phase systems to reduce harmonic pollution and improve power quality, and the active filter can be regarded as a controlled current source injection and power electronic equipment, non-linear load
  • the generated harmonic current is the opposite of the harmonic current, thereby effectively reducing the distortion in the current and voltage waveforms.
  • the harmonic current detected by the dq0 transformation method is compared with the actual compensation current, and the comparison result of the two is used as the input of the hysteresis comparator.
  • the input will generate the PWM signal that turns the switch on and off, and then adjust the compensation.
  • Current; the harmonic voltage detected by the dq0 transformation method generates a PWM signal and then enters the series active filter, and then controls the on and off of the inverter switch, so that the output compensation voltage signal is injected into the grid to compensate for the harmonic voltage.
  • the hysteresis comparator is used to compensate the harmonic current detected by the dq0 conversion method
  • the parallel active filter is used to compensate the harmonic voltage detected by the dq0 conversion method, resulting in accurate compensation of the harmonic voltage and harmonic current.
  • the degree is not high.
  • a method for determining the power quality level in a power grid comprising:
  • the actual compensation current includes a current adjustment inverter The actual output current
  • the voltage adjustment process is performed on the harmonic voltage to be compensated to obtain the harmonic voltage adjustment result; wherein, the target switching time includes controlling the active filter The switching and closing time of multiple sets of power conduction elements;
  • a target level of power quality in the power grid is determined.
  • it further includes:
  • the harmonic current to be compensated is greater than the actual compensation current, and the current difference is greater than or equal to the preset current threshold, the actual compensation current is controlled to increase based on the pulse width modulation signal, and the first harmonic current is finally output Adjustment result
  • the harmonic current to be compensated is less than or equal to the actual compensation current, and the current difference is less than the preset current threshold, the actual compensation current is controlled to decrease based on the pulse width modulation signal, and the second harmonic current is finally output Adjustment result
  • the first harmonic current adjustment result includes the current output when the harmonic current to be compensated is adjusted until it increases to a first preset current threshold
  • the pulse width modulation signal includes the harmonic current to be compensated.
  • the second harmonic current adjustment result includes the current output when the harmonic current to be compensated is adjusted until it is reduced to a second preset current threshold.
  • the first harmonic current adjustment result includes: using The result obtained
  • the second harmonic current adjustment result includes: adopting The results obtained
  • i * is the compensation current used for the hysteresis control switching moment
  • V dc is the DC side capacitor voltage in the inverter circuit
  • L s is the filter inductance used for harmonic current compensation.
  • the method further includes: dividing the vector space formed by the gh coordinate system from 0° as the starting point and dividing the sectors at a set angle interval to obtain multiple sectors;
  • the harmonic voltage adjustment circuit includes Multiple groups of power conduction elements and load elements are connected according to a preset connection manner, and the multiple groups of power conduction elements are turned on or off according to the target switching time.
  • the method further includes: calculating the switching time of sector I to the switching time of sector VI using the following formula:
  • T a , T b , T c are the three-phase switching time of the corresponding sector respectively
  • u ref_g is the g-axis voltage component of the reference voltage in the gh coordinate system
  • u ref_h is the h-axis of the reference voltage in the gh coordinate system voltage component
  • T s is the time required for each of the power-off element is turned on
  • V dc is the DC capacitor voltage of the inverter circuit
  • i sa, i sb, i sc are Is the current of the branch where the three-phase filter inductor is located, and isa , isb and isc are all positive in the direction of the inverter.
  • the method further includes: obtaining the three-phase harmonic current to be compensated at time t and the three-phase harmonic voltage to be compensated at time t by using the following formula:
  • i a1 , i b1 , and i c1 are the three-phase fundamental positive sequence currents of the phase-locked loop at time t, including:
  • i a1P, i b1P, i c1P time t are three-phase positive sequence fundamental active current component
  • i a1Q, i b1Q, i c1Q are three-phase positive sequence fundamental reactive current component at time t
  • G P is the DC component of the active conductance obtained by the low-pass filtering of the three-phase active conductance component of the phase-locked loop at time t
  • G Q is the low-pass filtering of the three-phase reactive conductance component of the phase-locked loop at time t.
  • the work conductance DC component, e a , e b , e c are the three-phase reference voltage of the phase-locked loop at time t, and I 1amp is the amplitude of the positive sequence current of the phase-locked loop, Is the angle between the phase-locked loop a-phase voltage and the fundamental positive sequence current, ⁇ is the angular frequency of the power grid, and ⁇ t is the phase angle change of the power grid at time t.
  • the method further includes: performing Fourier transform processing on the harmonic current adjustment result and the harmonic voltage adjustment result to obtain the total harmonic distortion rate of the grid-side current and voltage;
  • t+l ⁇ t as the new t and l+1 as the new l, and continue to perform the step of calculating the total harmonic distortion rate of the grid-side current and voltage; until the target level is obtained;
  • the calculation of the total harmonic distortion rate of the grid-side current and voltage includes the current harmonic distortion rate and the voltage harmonic distortion rate obtained by using the following formula:
  • THD I is the current harmonic distortion rate
  • I k is the k-th harmonic current effective value
  • I 1 is the fundamental current effective value
  • THD U is the voltage harmonic distortion rate
  • U k is the k-th harmonic voltage
  • the effective value, U 1 is the effective value of the fundamental voltage.
  • a device for determining a power quality level in a power grid comprising:
  • the acquisition module is used to acquire the harmonic current to be compensated and the harmonic voltage to be compensated in the power grid;
  • the first adjustment module is configured to perform current adjustment processing on the harmonic current to be compensated according to the current comparison result of the harmonic current to be compensated and the actual compensation current to obtain the harmonic current adjustment result; wherein, the actual compensation The current includes the actual output current of the current regulating inverter;
  • the second adjustment module is configured to perform voltage adjustment processing on the harmonic voltage to be compensated according to the harmonic voltage to be compensated and the target switching time obtained in advance to obtain the harmonic voltage adjustment result; wherein, the target switching time Including controlling the switching and closing time of multiple sets of power conduction elements in the active filter;
  • the determining module is used to determine the target level of power quality in the power grid according to the harmonic current adjustment result and the harmonic voltage adjustment result.
  • a computer device includes a memory and a processor, the memory stores a computer program, and the processor implements the following steps when the processor executes the computer program:
  • the actual compensation current includes a current adjustment inverter The actual output current
  • the voltage adjustment process is performed on the harmonic voltage to be compensated to obtain the harmonic voltage adjustment result; wherein, the target switching time includes controlling the active filter The switching and closing time of multiple sets of power conduction elements;
  • a target level of power quality in the power grid is determined.
  • a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the following steps are implemented:
  • the actual compensation current includes a current adjustment inverter The actual output current
  • the voltage adjustment process is performed on the harmonic voltage to be compensated to obtain the harmonic voltage adjustment result; wherein, the target switching time includes controlling the active filter The switching and closing time of multiple sets of power conduction elements;
  • a target level of power quality in the power grid is determined.
  • the current comparison result of the compensated harmonic current and the actual compensation current performs current adjustment processing on the to-be-compensated harmonic current, and performs a current adjustment process on the to-be-compensated harmonic voltage according to the to-be-compensated harmonic voltage and the target switching time obtained in advance
  • the voltage adjustment process obtains the harmonic current adjustment result and the harmonic voltage adjustment result, so as to realize the adjustment of the harmonic circuit through the current comparison result of the harmonic current to be compensated and the actual compensation current, and the harmonic voltage to be compensated
  • the adjustment of the harmonic voltage to be compensated is achieved with the target switching time, which avoids the use of hysteresis comparators to compensate the harmonic currents detected by the dq0 conversion method and
  • the compensation accuracy of the harmonic voltage and the harmonic current caused by the wave voltage is not high and the calculation amount is large, and the compensation accuracy and the compensation speed of the harmonic current and the harmonic voltage are improved; further, according to the harmonic
  • the current adjustment result and the harmonic voltage adjustment result determine the target level of power quality in the power grid, so as to achieve the goal of obtaining the target level of power quality corresponding to the harmonic current adjustment result and the harmonic voltage adjustment result, and also achieve the current
  • the higher the target level, the higher the compensation accuracy of the harmonic current adjustment result and the harmonic voltage adjustment result determined, the purpose is to improve the accuracy and reliability of the harmonic current adjustment result and the harmonic voltage adjustment result.
  • FIG. 1 is a schematic flowchart of a method for determining a power quality level in a power grid in an embodiment
  • FIG. 2 is a schematic flowchart of a method for determining a power quality level in a power grid in another embodiment
  • FIG. 3 is a schematic diagram of harmonic current compensation performed by a current compensation inverter circuit controlled by a hysteresis controller in an embodiment
  • FIG. 4 is a schematic flowchart of a method for determining a power quality level in a power grid in another embodiment
  • Figure 5 is a circuit diagram of an active filter in an embodiment
  • Fig. 6A is a space vector diagram of 27 vectors of a three-level 3D-SVPWM in an embodiment
  • 6B is a schematic diagram of 27 space vectors in an ⁇ coordinate system and a gh coordinate system in an embodiment
  • FIG. 7 is a schematic flowchart of a method for determining a power quality level in a power grid in another embodiment
  • FIG. 8 is a schematic flowchart of a method for determining a power quality level in a power grid in another embodiment
  • FIG. 9 is a schematic flowchart of a method for determining a power quality level in a power grid in another embodiment
  • FIG. 10 is a schematic flowchart of a method for determining a power quality level in a power grid in another embodiment
  • Fig. 11 is a structural block diagram of an apparatus for determining a power quality level in a power grid in an embodiment
  • Fig. 12 is a diagram of the internal structure of a computer device in an embodiment.
  • the method for determining the power quality level in the power grid may be executed by the power quality level determining device in the power grid, and the power quality level determining device in the power grid may be implemented by software, hardware, or a combination of software and hardware.
  • the computer device may be a personal computer (PC), portable device, notebook computer, smart phone, tablet computer, portable wearable device, and other electronic devices with built-in power quality adjustment systems, such as tablet computers, For mobile phones, etc., the embodiments of the present application do not limit the specific form of the computer equipment.
  • execution subject of the following method embodiments may be part or all of the above-mentioned computer equipment.
  • the following method embodiments are described with an example in which the execution subject is a computer device.
  • a method for determining the power quality level in a power grid includes the following steps:
  • Step S11 Obtain the harmonic current to be compensated and the harmonic voltage to be compensated in the power grid.
  • the harmonic current to be detected may be a harmonic current detected according to the FBD method
  • the harmonic voltage to be compensated may be a harmonic voltage detected according to the dq0 method.
  • the load in the actual circuit can be equivalent to an ideal conductance element, and the power in the actual circuit can be set to be lost to the Li Xiang conductance element, Transmission circuits, switching devices, and other types of loss energy are not changed, and then the product of the equivalent conductance of the ideal conductance element and the three-phase reference voltage generated by the phase-locked loop can be used as the current to be compensated.
  • the computer equipment when the computer equipment uses the dq0 method to detect the harmonic voltage, it can first be based on the positive and negative sequence amplitudes of the nth harmonic of the harmonic voltage in the power grid, and the initial phase of the positive and negative sequence of the nth harmonic of the harmonic voltage in the power grid.
  • Step S12 according to the current comparison result of the harmonic current to be compensated and the actual compensation current, current adjustment processing is performed on the harmonic current to be compensated to obtain a harmonic current adjustment result; wherein, the actual compensation current includes current adjustment The actual output current of the inverter.
  • the computer device may input the harmonic current to be compensated and the actual compensation current into a hysteresis comparator for harmonic current adjustment, and the harmonic current to be compensated may include three-phase harmonic currents to be compensated.
  • the actual compensation current may also include three-phase actual compensation current, the loop width of the hysteresis comparator is 2h, and then the difference between the three-phase to-be-compensated harmonic current and the three-phase actual compensation current may be taken as three Phase current deviation.
  • Step S121 Determine whether the harmonic current to be compensated is greater than the actual compensation current, and whether the current difference between the harmonic current to be compensated and the actual compensation current is greater than or equal to a preset current threshold.
  • the preset current threshold may include the half-loop width of the hysteresis comparator.
  • the computer device can determine the control hysteresis comparator by judging the magnitude relationship between the harmonic current to be compensated and the actual compensation current, and the magnitude relationship between the current difference and the preset current threshold.
  • the increase or decrease of the actual compensation current realizes compensation processing for the harmonic current to be compensated.
  • step S122 if the harmonic current to be compensated is greater than the actual compensation current, and the current difference is greater than or equal to the preset current threshold, step S122 is entered; otherwise, if the harmonic current to be compensated is If the actual compensation current is less than or equal to the actual compensation current, and the current difference is less than the preset current threshold, step S123 is entered.
  • Step S122 If the harmonic current to be compensated is greater than the actual compensation current, and the current difference is greater than or equal to the preset current threshold, control the actual compensation current to increase based on the pulse width modulation signal, and finally output the first Harmonic current adjustment result; wherein, the first harmonic current adjustment result includes the current output when the harmonic current to be compensated is adjusted until it increases to a first preset current threshold, and the pulse width modulation signal includes The signal generated after the harmonic current to be compensated and the actual compensation current are input to the hysteresis comparator.
  • the computer equipment can realize the action of the power device of the upper bridge arm of the current compensation inverter circuit a/b/c phase through the hysteresis controller as shown in Figure 3 to achieve the compensation operation for the harmonic current, that is, the hysteresis
  • the loop controller outputs a positive level according to the pulse width modulation signal, drives the upper bridge arm power device to turn on, and the transformer frequency converter outputs a positive voltage, so that the actual compensation current increases, and when it increases to equal to the harmonic current to be compensated
  • the hysteresis controller still maintains a positive output, and the high-side power device is still turned on, making the actual compensation current continue to increase until the actual compensation current and the preset current
  • the hysteresis controller reverses, outputs a negative level, turns off the power device of the upper bridge arm and then turns on the power device of
  • the inverter circuit may include a device combination consisting of 12 groups of insulated gate bipolar transistors (Insulated Gate Bipolar Transistor, IGBT) power conduction diodes, anti-parallel diodes, and two capacitors C 1 and C 2 in FIG. 5. Constitute the circuit.
  • IGBT Insulated Gate Bipolar Transistor
  • Step S123 if the harmonic current to be compensated is less than or equal to the actual compensation current, and the current difference is less than the preset current threshold, control the actual compensation current to decrease based on the pulse width modulation signal, and finally output the second Harmonic current adjustment result; wherein, the second harmonic current adjustment result includes the current output when the harmonic current to be compensated is adjusted until it is reduced to a second preset current threshold.
  • the computer equipment can also realize the action of the power device of the lower bridge arm of the current compensation inverter circuit a/b/c phase through the hysteresis controller as shown in Figure 3 to achieve the compensation operation of the harmonic current, that is,
  • the hysteresis controller outputs a negative level according to the pulse width modulation signal, drives the lower-arm power device to turn on, and the transformer frequency converter outputs a negative voltage, so that the actual compensation current is reduced, and when it is reduced to equal to the harmonic current to be compensated
  • the hysteresis controller still maintains a negative level output, and the lower-arm power device is still turned on, so that the actual compensation current continues to decrease until the actual compensation current and the preset current
  • the hysteresis controller flips, outputs a positive level, turns off the lower-arm power device and then turns on the upper-arm
  • the second harmonic current adjustment result output by the computer equipment including the use of The results obtained.
  • the harmonic current component in the computer equipment can be effectively reduced, thereby effectively improving the accuracy of the effective current in the computer equipment And reliability.
  • Step S13 Perform voltage adjustment processing on the harmonic voltage to be compensated according to the harmonic voltage to be compensated and the target switching time obtained in advance to obtain a harmonic voltage adjustment result; wherein, the target switching time includes control active The switching and closing time of multiple sets of power conduction elements in the filter.
  • the process of the computer device performing voltage adjustment processing on the harmonic voltage to be compensated may be as shown in FIG. 4, including the following sub-steps:
  • step S131 the vector space formed by the gh coordinate system is divided into sectors from 0° as the starting point and at a set angle interval to obtain multiple sectors.
  • the computer device can divide the vector space formed by the gh coordinate system from 0° as the starting point and 60° as the set angle interval to divide into sectors to obtain sector I, sector II, sector III, and sector IV. , Sector V and Sector VI.
  • the computer equipment can first divide 36 sectors according to the 2D-SVPWM method to calculate the action time of each vector completely, and then calculate the action time of the positive and negative small vectors according to the voltage zero sequence component, and finally get the action time of each switch . It is concluded that the switching time only needs to be divided into 12 sectors for calculation according to the phase of the reference vector, so the division of sub-sectors can be removed, the calculation amount is reduced, and the division error of sub-sectors can be eliminated.
  • the DC side capacitor voltage indirectly controls the upper and lower voltage balance through the zero sequence component.
  • the output of the converter is connected to the power grid through a filter inductor, and each phase has 4 switch tubes, 6 diodes, and two upper and lower capacitors on the DC side.
  • L s is the filter inductance
  • R s is the parasitic resistance of the inductance
  • Sua , Su ub , Su uc are the switching states of phase a, b, and c, respectively, S da , S db , S dc , respectively
  • S da is the switching states of the lower bridge arms of phases a, b, and c
  • e a , e b , and e c are the three-phase reference voltages of the phase-locked loop at time t
  • C 1 and C 2 are the DC-side capacitors
  • u dc1 , u dc2 is the voltage corresponding to C 1 and C 2 respectively
  • isa , isb , and isc are the currents of the branches where the phase a, b, and c filter inductors are located (the direction to the inverter is positive).
  • This formula needs to be obtained by Clarke transformation from the abc coordinate to ⁇ 0 coordinate:
  • S u ⁇ , S u ⁇ , S u0 is S ua, S ub, S uc converted from abc coordinates to the upper arm switching state of ⁇ 0 coordinates
  • S d ⁇ , S d ⁇ , S d0 is S da
  • S db and S dc are transformed from the abc coordinate system to the lower bridge arm switch state under the ⁇ 0 coordinate system
  • i s ⁇ , i s ⁇ , i s0 are i sa , i sb
  • i sc are transformed from the abc coordinate system to the ⁇ 0 coordinate system
  • e ⁇ , e ⁇ , and e 0 are e a , e b
  • the three-level 3D-SVPWM has a total of 27 vectors.
  • the values of 27 kinds of space vectors in ⁇ 0 coordinate system with DC voltage V dc are shown in Appendix Table 1, 27 kinds of space vectors are in ⁇ coordinate system and gh coordinate system
  • the following schematic diagram is shown in Figure 6B.
  • the modulation action time needs to be calculated after conversion by the gh coordinate method.
  • the vector space (gh coordinate system) is divided into 6 sectors (60 degrees each) from 0°, and each zone is further divided into 4 sub-sectors.
  • the reference voltage U ref is expressed as (u ref_g , u ref_h ) in the gh coordinate system, and the conversion relationship between ⁇ and the abc coordinate system is:
  • U magnitude of the DC voltage V dc shall be determined according to need (which may include; of formula (3), u ref_g for the g-axis component U ref at gh coordinate system, u ref_h for the h-axis component U ref at gh coordinates
  • the sum of dc1 and u dc2 ), U ref is determined based on the value of the three-phase unitized in V dc.
  • each of the 6 sectors is divided into 4 sub-sectors.
  • the division method is as follows:
  • the A area and C are divided into A1, A2 and C1, C2 according to the reference vector phase (u ref_g , u ref_h ).
  • the most recent vector is used to fit the switching time.
  • the time required for the fitting is shown in Table 2 in the appendix (take the first sector as an example).
  • the 3D-SVPWM voltage vector action time is:
  • V ⁇ 0r is the reference voltage vector in the ⁇ 0 coordinate system
  • V ⁇ 0zn and V ⁇ 0zp are the corresponding vectors of the positive and negative small vectors of the zero vector in the ⁇ 0 coordinate system
  • V ⁇ 0i , V ⁇ 0j are the corresponding vectors of the remaining vectors in the ⁇ 0 coordinate system
  • T zp and T zn are the action times corresponding to the positive and negative small vectors of the zero vector respectively
  • T i and T j are the action times corresponding to the other vectors respectively.
  • the zero vector is not considered first, the same as the 2D-SVPWM method in the ⁇ coordinate system, the action time of the three vectors is calculated as:
  • V ⁇ r is the reference voltage vector in the ⁇ coordinate system
  • V ⁇ i , V ⁇ j , and V ⁇ z are the corresponding vectors in the same area in the ⁇ coordinate system
  • T z is the action time corresponding to the zero vector.
  • V 0_r is the zero sequence reference voltage
  • V 0i , V 0j , V 0zn , and V 0zp respectively correspond to different vectors in the same area
  • T z is the action time of the zero vector.
  • the switch states corresponding to V 1 , V 12 , V 01p, and V 01n are (1,-1,-1), (1,0,-1), (1,0,0) respectively , (0,-1,-1).
  • each phase switching state is symmetrical on both sides, that is, the sequence is (1,0,0) ⁇ (1,0,-1) ⁇ (1, -1,-1) ⁇ (0,-1,-1) ⁇ (1,-1,-1) ⁇ (1,0,-1) ⁇ (1,0,0).
  • the switch duration corresponding to each switch state in this sequence is as follows:
  • the vector action time of each sub-sector is calculated through the methods (1) to (12). It is determined that the action time of all switches is divided into two groups by i sb ⁇ 0, i sb >0. Therefore, there is no need to divide the molecular sector again. Eliminate sub-sector division errors, that is, determine to divide the vector space formed by the gh coordinate system into sector I, sector II, sector III, sector IV, sector V, and sector VI.
  • Step S132 Obtain the sector switching time of each sector, and select one sector switching time from the obtained multiple sector switching times as the target switching time; wherein, the sector switching time is used to characterize Corresponding to the switching time of the inverter circuit power device under the sector.
  • the computer device may first determine the target sector for multiple sectors divided by the vector space formed by the gh coordinate system, and the target sector may be the sector corresponding to the position of the reference vector phase (u ref_g , u ref_h) , And then determine the target sector switching time corresponding to the target sector.
  • the inverter circuit may include a circuit composed of 12 groups of IGBTs and anti-parallel diode devices in FIG. 5, and the power devices of the inverter circuit may include power conduction elements.
  • Step S133 Input the harmonic voltage to be compensated into the preset harmonic voltage adjustment circuit, and use the output voltage of the harmonic voltage adjustment model circuit as the harmonic voltage adjustment result; wherein, the harmonic voltage
  • the adjustment circuit includes a plurality of groups of power conduction elements and load elements connected in a preset connection manner, and the plurality of groups of power conduction elements are turned on or off according to the target switching time.
  • the computer device may input the harmonic voltage to be compensated into a preset harmonic voltage adjustment circuit (such as a shunt active filter) for harmonic voltage adjustment, that is, first obtain the harmonic voltage to be compensated.
  • a preset harmonic voltage adjustment circuit such as a shunt active filter
  • the target pulse width modulation signal corresponding to the voltage, and then the target pulse width modulation signal is input into the shunt active filter, and the inverter is switched on and off according to the target switching time, and finally passes through the harmonic voltage adjustment circuit
  • the voltage output by the corresponding power conduction element and the load is the result of the harmonic voltage adjustment.
  • each group of power conduction elements may be a combination formed by an IGBT and an anti-parallel diode.
  • the parallel active filter may also be as shown in FIG. 5, and the parallel active filter may include a midpoint clamped three-level inverter, and 4 groups of phase a Power devices, 4 sets of power devices included in phase b, 4 sets of power devices included in phase c, two clamping diodes and loads, all 4 sets of power devices are S *1 , S *2 , S *3 , S *4 .
  • the compensation process for the harmonic voltage to be compensated is realized through the acquired target switching time and the preset harmonic voltage adjustment circuit, which can effectively reduce the harmonic voltage component in the computer equipment, thereby effectively improving the efficiency of the computer equipment. The accuracy and reliability of the voltage.
  • Step S14 Determine a target level of power quality in the power grid according to the harmonic current adjustment result and the harmonic voltage adjustment result.
  • the computer equipment can determine the target level of power quality in the power grid as shown in Figure 7, including the following steps:
  • Step S141 Perform Fourier transform processing on the harmonic current adjustment result and the harmonic voltage adjustment result to obtain the total harmonic distortion rate of the grid-side current and voltage.
  • the total harmonic distortion rate may include the current harmonic distortion rate and the voltage harmonic distortion rate obtained by using the following formula:
  • THD I is the current harmonic distortion rate
  • I k is the k-th harmonic current effective value
  • I 1 is the fundamental current effective value
  • THD U is the voltage harmonic distortion rate
  • U k is the k-th harmonic voltage
  • the effective value, U 1 is the effective value of the fundamental voltage.
  • Step S142 Determine whether the total harmonic distortion rate meets a preset distortion rate threshold.
  • the computer device when it obtains the total harmonic distortion rate, it may further determine whether the total harmonic distortion rate is less than or equal to a preset distortion rate threshold, and the preset distortion rate threshold may be used to characterize the pending distortion rate.
  • the remaining harmonic current and the remaining harmonic voltage obtained after the compensation harmonic current and the harmonic voltage to be compensated are respectively compensated do not affect the effectiveness of the effective current and effective voltage in the power grid.
  • step S143 when the computer device determines that the total harmonic distortion rate meets the preset distortion rate threshold, it proceeds to step S143; otherwise, when the computer device determines that the total harmonic distortion rate does not meet the preset distortion rate threshold, it enters Step S144.
  • step S143 if it is satisfied, the corresponding target level is determined according to the total harmonic distortion rate.
  • the computer device determines that the total harmonic distortion rate satisfies the preset distortion rate threshold, which can indicate that the total harmonic distortion rate is less than or equal to the preset distortion rate threshold, and it can also indicate that the harmonic distortion to be compensated this time
  • the residual harmonic current and residual harmonic voltage obtained after compensation of the current and the harmonic voltage to be compensated respectively do not affect the validity of the effective current and effective voltage in the power grid.
  • the total obtained this time can be further determined.
  • the target level corresponding to the harmonic distortion rate for example, when the preset distortion rate threshold is 2%, if the total harmonic distortion rate calculated this time is 1%, the target level can be good, if this time
  • the calculated total harmonic distortion rate is 0.5%, and the target level may be high quality.
  • the computer itself determines that the total harmonic distortion rate does not meet the preset distortion rate threshold, which can indicate that the total harmonic distortion rate is greater than the preset distortion rate threshold, and it can also indicate that the harmonic current to be compensated for this time
  • the residual harmonic current and residual harmonic voltage obtained after the compensation and the harmonic voltage to be compensated respectively will affect the effectiveness of the effective current and effective voltage in the power grid.
  • t+l ⁇ t can be further taken as the new t, and l+1 as the new l, continue to perform the steps of calculating the total harmonic distortion rate of grid-side current and voltage; until the target level of power quality in the grid is determined; so as to ensure that the harmonic current to be compensated and the total harmonic distortion
  • the flexibility and reliability of the harmonic current adjustment results and the harmonic voltage adjustment results after the harmonic voltages are respectively compensated are described, so as to ensure the effectiveness and stability of the power quality in the power grid.
  • the adjustment of the harmonic circuit is realized through the current comparison result of the harmonic current to be compensated and the actual compensation current, and the adjustment of the harmonic voltage to be compensated is realized through the harmonic voltage to be compensated and the target switching time, so as to avoid
  • the hysteresis comparator is used to compensate the harmonic current detected by the dq0 conversion method
  • the parallel active filter is used to compensate the harmonic voltage and the harmonic current detected by the d
  • the compensation accuracy of the harmonic voltage and the harmonic current is not high. And the problem of large amount of calculation has improved the compensation accuracy and compensation speed of harmonic current and harmonic voltage; further, according to the harmonic current adjustment result and the harmonic voltage adjustment result, the power quality in the power grid is determined In order to achieve the goal of obtaining the target level of power quality corresponding to the harmonic current adjustment result and the harmonic voltage adjustment result, it can also achieve the harmonic current adjustment result and harmonics determined when the target level is higher.
  • the purpose of the higher the compensation accuracy of the voltage adjustment result is to improve the accuracy and reliability of obtaining the harmonic current adjustment result and the harmonic voltage adjustment result.
  • the acquisition process of the harmonic current to be compensated in step S11 is acquired after being detected by the FBD detection method, and may specifically include the following sub-steps:
  • Step S111 Determine the three-phase reference voltage generated by the phase-locked loop and the three-phase current of the phase-locked loop.
  • the computer device obtains the three-phase reference voltage and the three-phase current, it can be obtained by using the following formula:
  • e a, e b, e c are three-phase phase-locked loop reference voltage at time t
  • i a, i b, i c are three-phase current of the phase locked loop at time t
  • Is the angle between the phase-locked loop a-phase voltage and the fundamental positive sequence current, They are the initial phases of the n-th harmonic current of the positive sequence, negative sequence, and zero sequence of the phase-locked loop current.
  • I 1n , I 2n and I 0n are the n-th harmonics of the positive sequence, negative sequence, and zero sequence of the phase-locked loop current, respectively.
  • the current amplitude, ⁇ is the angular frequency of the power grid
  • ⁇ t is the phase angle change of the power grid at time t.
  • Step S112 Determine the three-phase active conductance component generated by the phase-locked loop and the three-phase reactive conductance component generated by the phase-locked loop according to the three-phase reference voltage and the three-phase current.
  • the three-phase active conductance component and the three-phase reactive conductance component can be obtained by using the following formula:
  • G P (t) is the three-phase active conductance component generated by the phase-locked loop at time t
  • G Q (t) is the three-phase reactive conductance component generated by the phase-locked loop at time t
  • P ⁇ is the three-phase reactive conductance component generated by the phase-locked loop at time t.
  • phase reference power u is the ideal three-phase voltage obtained after passing through the phase-locked loop
  • i is the three-phase current obtained after passing through the phase-locked loop
  • u * is the reference voltage obtained after phase-locking the phase shift of the system voltage
  • ⁇ u,i> is the inner product of u and i
  • ⁇ u,u> is the inner product of u and u
  • ⁇ u * ,i> is the inner product of u and u.
  • the inner product of u * and i, ⁇ u * ,u> is the inner product of u * and u
  • ⁇ u,i> is the inner product of u and i.
  • Step S113 according to the three-phase active conductance component and the three-phase reactive conductance component, determine the active conductance direct current component and the reactive conductance direct current component.
  • the active conductance direct current component and the reactive conductance direct current component may be obtained after low-pass filtering the three-phase active conductance component and the three-phase reactive conductance component, and may be obtained by using the following formula:
  • G P is the DC component of active conductance at time t
  • G Q is the DC component of reactive conductance at time t
  • I 1amp is the amplitude of the positive sequence current of the phase-locked loop, It is the angle between the phase-locked loop a-phase voltage and the fundamental positive sequence current.
  • Step S114 Obtain a three-phase fundamental positive sequence active current component and a three-phase fundamental positive sequence reactive current component according to the active conductance direct current component, the reactive conductance direct current component and the three-phase reference voltage.
  • the computer device can obtain the three-phase fundamental positive sequence active current component and the three-phase fundamental positive sequence reactive current component according to the following formula:
  • i a1P, i b1P, i c1P time t are three-phase positive sequence fundamental active current component
  • i a1Q, i b1Q, i c1Q are three-phase positive sequence fundamental reactive current component at time t.
  • Step S115 Obtain the harmonic current to be compensated according to the three-phase current, the three-phase fundamental positive-sequence active current component, and the three-phase fundamental positive-sequence reactive current component.
  • the harmonic current to be compensated may include the three-phase harmonic current to be compensated at time t, and the computer device may use the following formula to obtain the three-phase harmonic current to be compensated at time t:
  • i a1, i b1, i c1 at time t respectively PLL phase fundamental positive sequence currents, i a, i b, i c are three-phase current of the phase locked loop at time t, They are the three-phase to-be-compensated harmonic currents at time t.
  • the computer equipment determines the harmonic current to be compensated in the power grid through the process of detecting the harmonic current in the power grid by the FBD detection method.
  • the acquisition process of the harmonic current to be compensated in step S11 may be detected and acquired using the dq0 detection method, which may specifically include the following sub-steps:
  • Step S21 Obtain the three-phase power supply voltage in the power grid.
  • the computer equipment can use the following formula to obtain the three-phase power supply voltage at time t in the power grid:
  • u a , u b , u c are the three-phase power supply voltage at time t in the power grid
  • u 0 is the zero sequence component of the fundamental voltage in the power grid
  • Are the three-phase positive sequence components of the voltage in the power grid at time t Are the three-phase negative sequence components of the voltage in the power grid at time t
  • U + and U - are the positive and negative sequence amplitudes of the fundamental voltage of the power grid, respectively
  • is the angular frequency of the power
  • Step S22 Perform dq0 coordinate system conversion processing on the three-phase power supply voltage to obtain the d-axis positive sequence component of the three-phase power supply voltage in the dq0 coordinate system and the q-axis positive sequence component of the three-phase power supply voltage in the dq0 coordinate system.
  • the computer device can use the following formula to perform the three-phase power supply voltage in the dq0 coordinate system to obtain the d-axis positive sequence component of the three-phase power supply voltage at time t in the dq0 coordinate system and the three-phase power supply voltage in the dq0 coordinate system
  • the q-axis positive sequence component at time t :
  • u d is the d-axis component of the three-phase power supply voltage in the dq0 coordinate system
  • u q is the q-axis component of the three-phase power supply voltage in the dq0 coordinate system
  • the computer equipment can also use the following formula to obtain the negative sequence component of the d-axis of the three-phase power supply voltage at time t in the dq0 coordinate system and the negative sequence component of the q-axis of the three-phase power supply voltage at time t in the dq0 coordinate system:
  • Step S23 Perform low-pass filtering on the d-axis positive sequence component and the q-axis positive sequence component to obtain the d-axis DC component of the three-phase power supply voltage and the q-axis DC component of the three-phase power supply voltage.
  • the computer equipment can obtain the d-axis DC component of the three-phase power supply voltage at time t and the q-axis DC component of the three-phase power supply voltage at time t using the following formula:
  • the nth positive sequence component in abc coordinates will be transformed into the n-1th component in dq0 coordinates, and the nth negative sequence component will be transformed into the n+1th order in dq0 coordinates.
  • the DC component in the dq0 coordinate is transformed from the fundamental wave component in the abc coordinate system through the Park transformation equation (26), and needs to be separated by a low-pass filter.
  • Step S24 Perform dq0 inverse transformation processing on the d-axis DC component and the q-axis DC component to obtain the three-phase positive sequence component of the voltage in the power grid.
  • the computer equipment can use the following formula to obtain the three-phase positive sequence component of the voltage in the power grid at time t:
  • Step S25 Determine the harmonic voltage to be compensated according to the three-phase positive sequence component of the voltage in the power grid and the three-phase power supply voltage.
  • the computer equipment can use the following formula to obtain the three-phase harmonic voltage to be compensated at time t:
  • u ac , u bc , u cc are the three-phase harmonic voltages to be compensated at time t respectively.
  • u a , u bc , u cc are the three-phase power supply voltages in the power grid at time t, respectively.
  • the computer device determines the harmonic voltage to be compensated in the power grid through the process of detecting the harmonic voltage in the power grid through the dq0 detection method, which can be combined with the ease of implementation and flexibility of the dq0 detection method to quickly obtain
  • the purpose of the harmonic voltage to be compensated is to improve the reliability and accuracy of the voltage to be compensated.
  • the obtaining of the sector switching time of each sector in step S132 can be obtained by the sub-sector division method of the improved 3D-SVPWM method, which specifically may include the following sub-steps :
  • Step S1321 Determine the g-axis voltage component of the three-phase power supply voltage in the gh coordinate system and the h-axis voltage component of the three-phase power supply voltage in the gh coordinate system according to the three-phase power supply voltage in the power grid.
  • the computer device can obtain the g-axis voltage component and the h-axis voltage component by using the following formula:
  • u a , u b , u c are the three-phase power supply voltage in the power grid
  • u ref_g is the g-axis voltage component of the three-phase power supply voltage in the gh coordinate system
  • u ref_h is the three-phase power supply voltage in the gh coordinate system h-axis voltage component.
  • Step S1322 according to the pre-acquired time required for on-off of each group of power conduction elements, the zero sequence reference voltage, the DC side capacitor voltage in the inverter circuit, the g-axis voltage component and the h-axis voltage component, Determine the sector switching time of each sector.
  • the sector switching time determined by the computer device may include the sector I switching time, the sector II switching time, the sector III switching time, the sector IV switching time, the sector V switching time, and the sector VI. Switching time, and use the following formula to get:
  • T a , T b , T c are the three-phase switching time of the corresponding sector
  • u ref_g is the g-axis voltage component of the reference voltage in the gh coordinate system
  • u ref_h is the h-axis voltage of the reference voltage in the gh coordinate system component
  • T s is the time required for each of the power-off element is turned on
  • V dc is the DC capacitor voltage of the inverter circuit
  • i sa, i sb, i sc three The current of the branch where the phase filter inductor is located, and isa , isb and isc are all positive in the direction of the inverter.
  • the computer device divides the vector space formed by the gh coordinate system into 6 sectors through the improved 3D-SVPWM method, which avoids the sub-sector division of each sector in the traditional 3D-SVPWM method.
  • the calculation error and the difficulty of controlling the zero-sequence component have improved the superiority and reliability of dividing 6 sub-sectors; further, the switching time of the inverter current power unit under each sector is obtained as the corresponding sector Sector switching time, thereby improving the flexibility and reliability of obtaining the sector switching time.
  • a device for determining a power quality level in a power grid including: an acquisition module 11, a first adjustment module 12, a second adjustment module 13, and a determination module 14, wherein:
  • the obtaining module 11 is used to obtain the harmonic current to be compensated and the harmonic voltage to be compensated in the power grid;
  • the first adjustment module 12 is configured to perform current adjustment processing on the harmonic current to be compensated according to the current comparison result of the harmonic current to be compensated and the actual compensation current to obtain the harmonic current adjustment result; wherein, the actual The compensation current includes the actual output current of the current regulation inverter;
  • the second adjustment module 13 is configured to perform voltage adjustment processing on the harmonic voltage to be compensated according to the harmonic voltage to be compensated and the target switching time obtained in advance to obtain the harmonic voltage adjustment result; wherein, the target switch The time includes the time to control the switching and closing of multiple groups of power conduction elements in the active filter;
  • the determining module 14 is configured to determine the target level of power quality in the power grid according to the harmonic current adjustment result and the harmonic voltage adjustment result.
  • the obtaining module 11 may be specifically used to obtain the three-phase harmonic current to be compensated at time t and the three-phase harmonic voltage to be compensated at time t by using the following formula:
  • the acquiring module 11 may also be specifically configured to acquire the three-phase fundamental positive sequence current of the phase-locked loop at time t, including:
  • i a1, i b1, i c1 at time t respectively PLL phase fundamental positive sequence current, i a1P, i b1P, i c1P time t are three-phase positive sequence fundamental active current component, i a1Q , i b1Q , i c1Q are the three-phase fundamental positive sequence reactive current components at time t respectively, and G P is the active conductance DC component of the three-phase active conductance component of the phase-locked loop at time t after low-pass filtering.
  • G Q is the reactive conductance DC component obtained by low-pass filtering of the three-phase reactive conductance component of the phase-locked loop at time t
  • e a , e b , and e c are the three-phase reference of the phase-locked loop at time t Voltage
  • I 1amp is the amplitude of the positive sequence current of the phase-locked loop
  • Is the angle between the phase-locked loop a-phase voltage and the fundamental positive sequence current
  • is the angular frequency of the power grid
  • ⁇ t is the phase angle change of the power grid at time t.
  • the first adjustment module may specifically include: a first judgment sub-module, a first adjustment sub-module, and a second adjustment sub-module.
  • the first judging sub-module can be used to judge whether the harmonic current to be compensated is greater than the actual compensation current, and whether the current difference between the harmonic current to be compensated and the actual compensation current is greater than or equal to a preset value.
  • Set a current threshold the first adjustment sub-module can be used to control based on a pulse width modulation signal if the harmonic current to be compensated is greater than the actual compensation current, and the current difference is greater than or equal to the preset current threshold The actual compensation current increases, and finally the first harmonic current adjustment result is output; the second adjustment sub-module can be used if the harmonic current to be compensated is less than or equal to the actual compensation current, and the current difference is less than the
  • the preset current threshold value is based on the pulse width modulation signal to control the actual compensation current to decrease, and finally output the second harmonic current adjustment result; wherein, the first harmonic current adjustment result includes adjusting the to-be-compensated harmonic current until it increases.
  • the output current when the current is as large as the first preset current threshold, the pulse width modulation signal includes a signal generated after inputting the harmonic current to be compensated and the actual compensation current into a hysteresis comparator, and the second harmonic current
  • the adjustment result includes adjusting the current to be output when the harmonic current to be compensated is reduced to a second preset current threshold.
  • the first adjustment sub-module can be used to adopt The results obtained.
  • the second adjustment sub-module can be used to adopt The result obtained; where i * is the compensation current used for the hysteresis control switching moment, V dc is the DC side capacitor voltage in the inverter circuit, and L s is the filter inductance used for harmonic current compensation.
  • the second adjustment module may specifically include: a segmentation sub-module, a first determination sub-module, and a third adjustment sub-module.
  • the segmentation sub-module can be used to divide the vector space formed by the gh coordinate system from 0° as the starting point and at a set angle interval to obtain multiple sectors; the first determining sub-module can be used to Acquire the sector switching time of each sector, and select a sector switching time from the obtained multiple sector switching time as the target switching time; the third adjustment sub-module can be used to adjust the to-be-compensated
  • the harmonic voltage is input to the preset harmonic voltage adjustment circuit, and the output voltage of the harmonic voltage adjustment model circuit is used as the harmonic voltage adjustment result; wherein, the sector switching time is used to characterize the corresponding sector
  • the harmonic voltage adjustment circuit includes multiple sets of power conduction elements and load elements connected according to a preset connection mode, and the multiple sets of power conduction elements conduct according to the target switching time Pass or cut off.
  • the segmentation sub-module can also be specifically used to calculate the switching time of sector I to the switching time of sector VI using the following formula:
  • T a , T b , T c are the three-phase switching time of the corresponding sector respectively
  • u ref_g is the g-axis voltage component of the reference voltage in the gh coordinate system
  • u ref_h is the h-axis of the reference voltage in the gh coordinate system voltage component
  • T s is the time required for each of the power-off element is turned on
  • V dc is the DC capacitor voltage of the inverter circuit
  • i sa, i sb, i sc are Is the current of the branch where the three-phase filter inductor is located, and isa , isb and isc are all positive in the direction of the inverter.
  • the determining module 14 may specifically include: a second determining sub-module, a second determining sub-module, a third determining sub-module, and a fourth determining sub-module.
  • the second determining sub-module may be used to perform Fourier transform processing on the harmonic current adjustment result and the harmonic voltage adjustment result to obtain the total harmonic distortion rate of the grid-side current and voltage;
  • the judging sub-module can be used to judge whether the total harmonic distortion rate meets the preset distortion rate threshold;
  • the third determining sub-module can be used to determine the corresponding target level according to the total harmonic distortion rate if it is satisfied;
  • the second determining sub-module can also be specifically used for the current harmonic distortion rate and voltage harmonic distortion rate obtained by using the following formula:
  • THD I is the current harmonic distortion rate
  • I k is the k-th harmonic current effective value
  • I 1 is the fundamental current effective value
  • THD U is the voltage harmonic distortion rate
  • U k is the k-th harmonic voltage
  • the effective value, U 1 is the effective value of the fundamental voltage.
  • the various modules in the device for determining the power quality level in the power grid can be implemented in whole or in part by software, hardware, and combinations thereof.
  • the above-mentioned modules may be embedded in the form of hardware or independent of the processor in the computer equipment, or may be stored in the memory of the computer equipment in the form of software, so that the processor can call and execute the operations corresponding to the above-mentioned modules.
  • a computer device is provided.
  • the computer device may be a terminal, and its internal structure diagram may be as shown in FIG. 12.
  • the computer equipment includes a processor, a memory, a communication interface, a display screen and an input device connected through a system bus.
  • the processor of the computer device is used to provide calculation and control capabilities.
  • the memory of the computer device includes a non-volatile storage medium and an internal memory.
  • the non-volatile storage medium stores an operating system and a computer program.
  • the internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium.
  • the communication interface of the computer device is used to communicate with an external terminal in a wired or wireless manner, and the wireless manner can be implemented through WIFI, an operator's network, NFC (near field communication) or other technologies.
  • the computer program is executed by the processor to realize a method for determining the power quality level in the power grid.
  • the display screen of the computer equipment can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer equipment can be a touch layer covered on the display screen, or it can be a button, a trackball or a touchpad set on the housing of the computer equipment , It can also be an external keyboard, touchpad, or mouse.
  • FIG. 12 is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied.
  • the specific computer device may Including more or fewer parts than shown in the figure, or combining some parts, or having a different arrangement of parts.
  • a computer device including a memory and a processor, a computer program is stored in the memory, and the processor implements the following steps when the processor executes the computer program:
  • the actual compensation current includes a current adjustment inverter The actual output current
  • the voltage adjustment process is performed on the harmonic voltage to be compensated to obtain the harmonic voltage adjustment result; wherein, the target switching time includes controlling the active filter The switching and closing time of multiple sets of power conduction elements;
  • a target level of power quality in the power grid is determined.
  • the processor further implements the following steps when executing the computer program:
  • the first harmonic current adjustment result includes adjusting the to-be-compensated harmonic current until it increases to a first preset current threshold, and the pulse-width modulation signal includes combining the to-be-compensated harmonic current with the actual The compensation current is input to the signal generated by the hysteresis comparator, and the second harmonic current adjustment result
  • the processor further implements the following steps when executing the computer program:
  • the first harmonic current adjustment result includes: adopting The result obtained
  • the second harmonic current adjustment result includes: adopting The result obtained; where i * is the compensation current used for the hysteresis control switching moment, V dc is the DC side capacitor voltage in the inverter circuit, and L s is the filter inductance used for harmonic current compensation.
  • the processor further implements the following steps when executing the computer program:
  • the vector space formed by the gh coordinate system is divided into sectors from 0° as the starting point and at a set angle interval to obtain multiple sectors; obtain the sector switching time of each sector, and obtain multiple sectors from the obtained Select a sector switching time from the zone switching time as the target switching time; input the to-be-compensated harmonic voltage into a preset harmonic voltage adjustment circuit, and adjust the output voltage of the model circuit by the harmonic voltage As a result of harmonic voltage regulation; wherein, the sector switching time is used to characterize the switching time of the inverter circuit power device under the corresponding sector; the harmonic voltage regulation circuit includes multiple sets of power conduction components and load components according to A preset connection manner is connected, and the multiple groups of power conduction elements are turned on or off according to the target switching time.
  • the processor further implements the following steps when executing the computer program:
  • T a , T b , T c are the three-phase switching time of the corresponding sector respectively
  • u ref_g is the g-axis voltage component of the reference voltage in the gh coordinate system
  • u ref_h is the h-axis of the reference voltage in the gh coordinate system voltage component
  • T s is the time required for each of the power-off element is turned on
  • V dc is the DC capacitor voltage of the inverter circuit
  • i sa, i sb, i sc are Is the current of the branch where the three-phase filter inductor is located, and isa , isb and isc are all positive in the direction of the inverter.
  • the processor further implements the following steps when executing the computer program:
  • the processor further implements the following steps when executing the computer program:
  • the i a1 , i b1 , and i c1 are respectively the three-phase fundamental positive sequence currents of the phase-locked loop at time t, including:
  • i a1P, i b1P, i c1P time t are three-phase positive sequence fundamental active current component
  • i a1Q, i b1Q, i c1Q are three-phase positive sequence fundamental reactive current component at time t
  • G P is the DC component of the active conductance obtained by the low-pass filtering of the three-phase active conductance component of the phase-locked loop at time t
  • G Q is the low-pass filtering of the three-phase reactive conductance component of the phase-locked loop at time t.
  • the work conductance DC component, e a , e b , e c are the three-phase reference voltage of the phase-locked loop at time t, and I 1amp is the amplitude of the positive sequence current of the phase-locked loop, Is the angle between the phase-locked loop a-phase voltage and the fundamental positive sequence current, ⁇ is the angular frequency of the power grid, and ⁇ t is the phase angle change of the power grid at time t.
  • the processor further implements the following steps when executing the computer program:
  • t+l ⁇ t as the new t and l+1 as the new l, and continue to perform the step of calculating the total harmonic distortion rate of the grid-side current and voltage; until the target level is obtained;
  • the processor further implements the following steps when executing the computer program:
  • the calculation of the total harmonic distortion rate of the grid-side current and voltage includes the current harmonic distortion rate and the voltage harmonic distortion rate obtained by using the following formula:
  • THD I is the current harmonic distortion rate
  • I k is the k-th harmonic current effective value
  • I 1 is the fundamental current effective value
  • THD U is the voltage harmonic distortion rate
  • U k is the k-th harmonic voltage
  • the effective value, U 1 is the effective value of the fundamental voltage.
  • a computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, the following steps are implemented:
  • the actual compensation current includes a current adjustment inverter The actual output current
  • the voltage adjustment process is performed on the harmonic voltage to be compensated to obtain the harmonic voltage adjustment result; wherein, the target switching time includes controlling the active filter The switching and closing time of multiple sets of power conduction elements;
  • a target level of power quality in the power grid is determined.
  • the first harmonic current adjustment result includes adjusting the to-be-compensated harmonic current until it increases to a first preset current threshold, and the pulse-width modulation signal includes combining the to-be-compensated harmonic current with the actual The compensation current is input to the signal generated by the hysteresis comparator, and the second harmonic current adjustment result
  • the first harmonic current adjustment result includes: adopting The result obtained
  • the second harmonic current adjustment result includes: adopting The result obtained; where i * is the compensation current used for the hysteresis control switching moment, V dc is the DC side capacitor voltage in the inverter circuit, and L s is the filter inductance used for harmonic current compensation.
  • the vector space formed by the gh coordinate system is divided into sectors from 0° as the starting point and at a set angle interval to obtain multiple sectors; obtain the sector switching time of each sector, and obtain multiple sectors from the obtained Select a sector switching time from the zone switching time as the target switching time; input the to-be-compensated harmonic voltage into a preset harmonic voltage adjustment circuit, and adjust the output voltage of the model circuit by the harmonic voltage As a result of harmonic voltage regulation; wherein, the sector switching time is used to characterize the switching time of the inverter circuit power device under the corresponding sector; the harmonic voltage regulation circuit includes multiple sets of power conduction components and load components according to A preset connection manner is connected, and the multiple groups of power conduction elements are turned on or off according to the target switching time.
  • T a , T b , T c are the three-phase switching time of the corresponding sector respectively
  • u ref_g is the g-axis voltage component of the reference voltage in the gh coordinate system
  • u ref_h is the h-axis of the reference voltage in the gh coordinate system voltage component
  • T s is the time required for each of the power-off element is turned on
  • V dc is the DC capacitor voltage of the inverter circuit
  • i sa, i sb, i sc are Is the current of the branch where the three-phase filter inductor is located, and isa , isb and isc are all positive in the direction of the inverter.
  • the i a1 , i b1 , and i c1 are respectively the three-phase fundamental positive sequence currents of the phase-locked loop at time t, including:
  • i a1P, i b1P, i c1P time t are three-phase positive sequence fundamental active current component
  • i a1Q, i b1Q, i c1Q are three-phase positive sequence fundamental reactive current component at time t
  • G P is the DC component of the active conductance obtained by the low-pass filtering of the three-phase active conductance component of the phase-locked loop at time t
  • G Q is the low-pass filtering of the three-phase reactive conductance component of the phase-locked loop at time t.
  • the work conductance DC component, e a , e b , e c are the three-phase reference voltage of the phase-locked loop at time t, and I 1amp is the amplitude of the positive sequence current of the phase-locked loop, Is the angle between the phase-locked loop a-phase voltage and the fundamental positive sequence current, ⁇ is the angular frequency of the power grid, and ⁇ t is the phase angle change of the power grid at time t.
  • t+l ⁇ t as the new t and l+1 as the new l, and continue to perform the step of calculating the total harmonic distortion rate of the grid-side current and voltage; until the target level is obtained;
  • the calculation of the total harmonic distortion rate of the grid-side current and voltage includes the current harmonic distortion rate and the voltage harmonic distortion rate obtained by using the following formula:
  • THD I is the current harmonic distortion rate
  • I k is the k-th harmonic current effective value
  • I 1 is the fundamental current effective value
  • THD U is the voltage harmonic distortion rate
  • U k is the k-th harmonic voltage
  • the effective value, U 1 is the effective value of the fundamental voltage.
  • Non-volatile memory may include read-only memory (Read-Only Memory, ROM), magnetic tape, floppy disk, flash memory, or optical storage.
  • Volatile memory may include random access memory (RAM) or external cache memory.
  • RAM can be in various forms, such as static random access memory (Static Random Access Memory, SRAM) or dynamic random access memory (Dynamic Random Access Memory, DRAM), etc.

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Abstract

本申请涉及一种电网中的电能质量等级确定方法、装置、设备和存储介质。所述方法包括:获取电网中的待补偿谐波电流与待补偿谐波电压;根据所述待补偿谐波电流与实际补偿电流的电流比较结果,对所述待补偿谐波电流进行电流调节处理,得到谐波电流调节结果;根据所述待补偿谐波电压与预先获取的目标开关时间,对所述待补偿谐波电压进行电压调节处理,得到谐波电压调节结果;根据所述谐波电流调节结果和所述谐波电压调节结果,确定电网中电能质量的目标等级;其中,所述实际补偿电流包括电流调节逆变器的实际输出电流;所述目标开关时间包括控制有源滤波器中多组功率导通元件开关和闭合的时间。采用本方法能够提高电网中谐波电压和谐波电流的补偿精确度。

Description

电网中的电能质量等级确定方法、装置、设备和存储介质 技术领域
本申请涉及电网控制技术领域,特别涉及一种电网中的电能质量等级确定方法、装置、设备和存储介质。
背景技术
目前,有源滤波器(APF)在三相系统中被广泛应用,以减少谐波污染及改善电能质量,并且可以将有源滤波器看作受控电流源注入与电力电子设备、非线性负载产生的谐波电流相反的谐波电流,从而有效减少电流和电压波形中的失真。
传统技术中,使用dq0变换法检测的谐波电流与实际的补偿电流进行比较,将两者的比较结果作为滞环比较器的输入,该输入会产生令开关通断的PWM信号,进而调节补偿电流;使用dq0变换法检测的谐波电压生成PWM信号后进入串联型有源滤波器,进而控制逆变器开关通断,使其输出补偿电压信号注入电网补偿谐波电压。
然而,传统技术中是使用滞环比较器补偿dq0变换法检测的谐波电流,以及使用并联型有源滤波器补偿dq0变换法检测的谐波电压,导致谐波电压和谐波电流的补偿精确度不高。
发明内容
基于此,有必要针对上述技术问题,提供一种能够提高电网中谐波电压和谐波电流的补偿精确度的电网中的电能质量等级确定方法、装置、设备和存储介质。
一种电网中的电能质量等级确定方法,所述方法包括:
获取电网中的待补偿谐波电流与待补偿谐波电压;
根据所述待补偿谐波电流与实际补偿电流的电流比较结果,对所述待补偿谐波电流进行电流调节处理,得到谐波电流调节结果;其中,所述实际补偿电流包括电流调节逆变器的实际输出电流;
根据所述待补偿谐波电压与预先获取的目标开关时间,对所述待补偿谐波电压进行电压调节处理,得到谐波电压调节结果;其中,所述目标开关时间包括控制有源滤波器中多组功率导通元件开关和闭合的时间;
根据所述谐波电流调节结果和所述谐波电压调节结果,确定电网中电能质量的目标等级。
在其中一个实施例中,还包括:
判断所述待补偿谐波电流是否大于所述实际补偿电流,且所述待补偿谐波电流与所述实际补偿电流的电流差值是否大于等于预设电流阈值;
若所述待补偿谐波电流大于所述实际补偿电流,且所述电流差值大于等于所述预设电流阈值,则基于脉宽调制信号控制实际补偿电流增大,最终输出第一谐波电流调节结果;
若所述待补偿谐波电流小于等于所述实际补偿电流,且所述电流差值小于所述预设电流阈值,则基于脉宽调制信号控制实际补偿电流减小,最终输出第二谐波电流调节结果;
其中,所述第一谐波电流调节结果包括调节所述待补偿谐波电流直至增大至第一预设电流阈值时输出的电流,所述脉宽调制信号包括将所述待补偿谐波电流与实际补偿电流输入至滞环比较器后生成的信号,所述第二谐波电流调节结果包括调节所述待补偿谐波电流直至减小至第二预设电流阈值时输出的电流。
在其中一个实施例中,还包括:所述第一谐波电流调节结果包括:采用
Figure PCTCN2021094665-appb-000001
得到的结果,所述第二谐波电流调节结果包括:采用
Figure PCTCN2021094665-appb-000002
得到的结果;
其中,i *为用于滞环控制切换时刻的补偿电流,V dc为逆变器电路中的直流侧电容电压,L s为用于谐波电流补偿的滤波电感。
在其中一个实施例中,还包括:将由gh坐标系构成的矢量空间从0°为起始点、以设定角度间隔进行扇区划分,得到多个扇区;
获取每个扇区的扇区开关时间,并从获取得到的多个扇区开关时间中选取一个扇区开关时间作为所述目标开关时间;其中,所述扇区开关时间用于表征对应扇区下的逆变电路功率器件的开关时间;
将所述待补偿谐波电压输入至预先设置的谐波电压调节电路中,并将所述谐波电压调节模型电路的输出电压作为谐波电压调节结果;其中,所述谐波电压调节电路包括多组功率导通元件和负载元件按照预设连接方式连接,且所述多组功率导通元件根据所述目标开关时间导通或者截止。
在其中一个实施例中,还包括:采用下式计算扇区I开关时间至扇区VI开关时间:
Figure PCTCN2021094665-appb-000003
其中,T a、T b、T c分别为对应扇区的三相开关时间,u ref_g为参考电压在gh坐标系下的g轴电压分量,u ref_h为参考电压在gh坐标系下的h轴电压分量,T s为每个功率导通元件的通断所需时间,V 0_r为零序参考电压,V dc为逆变器电路中的直流侧电容电压;i sa、i sb、i sc分别为三相滤波电感所在支路的电流,且i sa、i sb、i sc均以指向逆变器方向为正。
在一个实施例中,还包括:采用下式获取时刻t的三相待补偿谐波电流和时刻t的三相待补偿谐波电压:
Figure PCTCN2021094665-appb-000004
其中,
Figure PCTCN2021094665-appb-000005
分别为时刻t的三相待补偿谐波电流,i a、i b、i c分别为锁相环在时刻t的三相电流,i a1、i b1、i c1分别为锁相环在时刻t的三相基波正序电流;u ac、u bc、u cc分别为时刻t的三相待补偿谐波电压,
Figure PCTCN2021094665-appb-000006
分别为电网中电压在时刻t的三相正序分量,u a、u b、u c 分别为电网中时刻t的三相电源电压。
在其中一个实施例中,还包括:所述i a1、i b1、i c1为锁相环在时刻t的三相基波正序电流,包括:
Figure PCTCN2021094665-appb-000007
Figure PCTCN2021094665-appb-000008
其中,i a1P、i b1P、i c1P分别为时刻t的三相基波正序有功电流分量,i a1Q、i b1Q、i c1Q分别为时刻t的三相基波正序无功电流分量,G P为锁相环在时刻t的三相有功电导分量经过低通滤波后得到的有功电导直流分量,G Q为锁相环在时刻t的三相无功电导分量经过低通滤波后得到的无功电导直流分量,e a、e b、e c分别为锁相环在时刻t的三相参考电压,I 1amp为锁相环的正序电流幅值,
Figure PCTCN2021094665-appb-000009
为锁相环a相电压与基波正序电流夹角,ω为电网的角频率,ωt为电网在时刻t的相角变化。
在其中一个实施例中,还包括:对所述谐波电流调节结果和所述谐波电压调节结果进行傅里叶变换处理,得到电网侧电流和电压的总谐波畸变率;
判断所述总谐波畸变率是否满足预设畸变率阈值;
如果满足,则根据所述总谐波畸变率确定对应的目标等级;
如果不满足,则将t+lΔt作为新的t,将l+1作为新的l,继续执行所述计算电网侧电流和电压的总谐波畸变率的步骤;直至得到所述目标等级;其中,l的取值为大于等于0的整数,l=0、1、2、3、......,l为重新计算总谐波畸变率的次数且初值为0,Δt为预先设定的时间间隔。
在其中一个实施例中,还包括:所述计算电网侧电流和电压的总谐波畸变率,包括采用下式得到的电流谐波畸变率和电压谐波畸变率:
Figure PCTCN2021094665-appb-000010
其中,THD I为电流谐波畸变率,I k为第k次谐波电流有效值,I 1为基波电流有效值,THD U为电压谐波畸变率,U k为第k次谐波电压有效值,U 1为基波电压有效值。
一种电网中的电能质量等级确定装置,所述装置包括:
获取模块,用于获取电网中的待补偿谐波电流与待补偿谐波电压;
第一调节模块,用于根据所述待补偿谐波电流与实际补偿电流的电流比较结果,对所述待补偿谐波电流进行电流调节处理,得到谐波电流调节结果;其中,所述实际补偿电流包括电流调节逆变器的实际输出电流;
第二调节模块,用于根据所述待补偿谐波电压与预先获取的目标开关时间,对所述待补偿谐波电压进行电压调节处理,得到谐波电压调节结果;其中,所述目标开关时间包括控制有源滤波器中多组功率导通元件开关和闭合的时间;
确定模块,用于根据所述谐波电流调节结果和所述谐波电压调节结果,确定电网中电能质量的目标等级。
一种计算机设备,包括存储器和处理器,所述存储器存储有计算机程序,所述处理器执行所述计算机程序时实现以下步骤:
获取电网中的待补偿谐波电流与待补偿谐波电压;
根据所述待补偿谐波电流与实际补偿电流的电流比较结果,对所述待补偿谐波电流进行电流调节处理,得到谐波电流调节结果;其中,所述实际补偿电流包括电流调节逆变器的实际输出电流;
根据所述待补偿谐波电压与预先获取的目标开关时间,对所述待补偿谐波电压进行电压调节处理,得到谐波电压调节结果;其中,所述目标开关时间包括控制有源滤波器中多组功率导通元件开关和闭合的时间;
根据所述谐波电流调节结果和所述谐波电压调节结果,确定电网中电能质量的目标等级。
一种计算机可读存储介质,其上存储有计算机程序,所述计算机程序被处理器执行时实现以下步骤:
获取电网中的待补偿谐波电流与待补偿谐波电压;
根据所述待补偿谐波电流与实际补偿电流的电流比较结果,对所述待补偿谐波电流进行电流调节处理,得到谐波电流调节结果;其中,所述实际补偿电流包括电流调节逆变器的实际输出电流;
根据所述待补偿谐波电压与预先获取的目标开关时间,对所述待补偿谐波电压进行电压调节处理,得到谐波电压调节结果;其中,所述目标开关时间包括控制有源滤波器中多组功率导通元件开关和闭合的时间;
根据所述谐波电流调节结果和所述谐波电压调节结果,确定电网中电能质量的目标等级。
上述电网中的电能质量等级确定方法、装置、设备和存储介质,其中所述电网中的电能质量等级确定方法首先获取电网中的待补偿谐波电流和待补偿谐波电压,并根据所述待补偿谐波电流与实际补偿电流的电流比较结果对所述待补偿谐波电流进行电流调节处理,以及根据所述待补偿谐波电压与预先获取的目标开关时间对所述待补偿谐波电压进行电压调节处理来得到谐波电流调节结果和谐波电压调节结果,以此通过所述待补偿谐波电流与实际补偿电流的电流比较结果实现谐波电路的调节、通过所述待补偿谐波电压与目标开关时间实现对所述待补偿谐波电压的调节,避免了传统技术中使用滞环比较器补偿dq0变换法检测的谐波电流、使用串联型有源滤波器补偿dq0变换法检测的谐波电压导致的谐波电压和谐波电流的补偿精确度不高及计算量较大的问题,提高了谐波电流和谐波电压的补偿精确度及补偿速度;进一步地,根据所述谐波电流调节结果和所述谐波电压调节结果,确定电网中电能质量的目标等级,以此实现获取谐波电流调节结果和谐波电压调节结果对应的电能质量的目标等级的目的,也能够实现当目标等级越高时所确定出的谐波电流调节结果和谐波电压调节结果的补偿精确度也越高的目的,提高了获取谐波电流调节结果和谐波电压调节结果的准确性和可靠性。
附图说明
图1为一个实施例中电网中的电能质量等级确定方法的流程示意图;
图2为另一实施例中电网中的电能质量等级确定方法的流程示意图;
图3为一个实施例中通过滞环控制器控制电流补偿逆变电路进行谐波电流补偿的示意图;
图4为再一实施例中电网中的电能质量等级确定方法的流程示意图;
图5为一个实施例中的有源滤波器电路图;
图6A为一个实施例中三电平3D-SVPWM的27个矢量的空间矢量图;
图6B为一个实施例中27种空间矢量在αβ坐标系与gh坐标系下的示意图;
图7为又一实施例中电网中的电能质量等级确定方法的流程示意图;
图8为又一实施例中电网中的电能质量等级确定方法的流程示意图;
图9为又一实施例中电网中的电能质量等级确定方法的流程示意图;
图10为又一实施例中电网中的电能质量等级确定方法的流程示意图;
图11为一个实施例中电网中的电能质量等级确定装置的结构框图;
图12为一个实施例中计算机设备的内部结构图。
具体实施方式
为了使本申请的目的、技术方案及优点更加清楚明白,以下结合附图及实施例,对本申请进行进一步详细说明。应当理解,此处描述的具体实施例仅仅用以解释本申请,并不用于限定本申请。
本申请提供的电网中的电能质量等级确定方法,其执行主体可以是电网中的电能质量等级确定装置,所述电网中的电能质量等级确定装置可以通过软件、硬件或者软硬件结合的方式实现成为计算机设备的部分或者全部。可选的,该计算机设备可以为个人计算机(Persodal Computer,PC)、便携式设备、笔记本电脑、智能手机、平板电脑和便携式可穿戴设备等其它内设电能质量调节系统的电子设备,例如平板电脑、手机等等,本申请实施例对计算机设备的具体形式并不做限定。
需要说明的是,下述方法实施例的执行主体可以是上述计算机设备的部分或者全部。下述方法实施例以执行主体为计算机设备为例进行说明。
在一个实施例中,如图1所示,提供了一种电网中的电能质量等级确定方法,包括以下步骤:
步骤S11,获取电网中的待补偿谐波电流与待补偿谐波电压。
其中,所述待检测谐波电流可以是根据FBD法检测到的谐波电流,所述待补偿谐波电压可以是根据dq0法检测到的谐波电压。
具体地,计算机设备在使用FBD法进行谐波电流检测时,可以将实际电路中的负载等效为理想电导元件,并可以设定实际电路中的功率都损耗在所述李想电导元件上,传输电路、开关器件等其它产生的各类损耗能量没有改变,然后可以将所述理想电导元件的等值电导与锁相环生成的三相参考电压之间的乘积,作为所述待补偿电流。
并且,计算机设备使用dq0法检测谐波电压时,可以首先根据电网中的谐波电压n次谐波正、负序幅值,以及电网中的谐波电压n次谐波正、负序初相位确定三相电压正序分量转化后的dq0坐标系下d轴正序分量和三相电压转化后的dq0坐标系下q轴正序分量,然后对所述d轴正序分量和所述q轴正序分量分别依次进行低通滤波处理、dq0反变化处理后,得到电网中的三相基波电压正序分量,再根据电网中的三相电源电压和所述三相基波电压正序分量,得到所述待补偿电压。
步骤S12,根据所述待补偿谐波电流与实际补偿电流的电流比较结果,对所述待补偿谐波电流进行电流调节处理,得到谐波电流调节结果;其中,所述实际补偿电流包括电流调节逆变器的实际输出电流。
具体地,计算机设备可以将所述待补偿谐波电流与实际补偿电流输入至滞环比较器中进行谐波电流调节,并且所述待补偿谐波电流可以包括三相待补偿谐波电流,所述实际补偿电流也可以包括三相实际补偿电流,所述滞环比较器的环宽为2h,然后可以将所述三相待补偿谐波电流与所述三相实际补偿电流的差值作为三相电流偏差,当所述三相电流偏差分别大于(或小于)h时,经滞环控制器控制电流补偿逆变电路a/b/c相的上(或下)桥臂的功率器件动作,具体调节过程如图2所示,可以包括以下子步骤:
步骤S121,判断所述待补偿谐波电流是否大于所述实际补偿电流,且所述待补偿谐波电流与所述实际补偿电流的电流差值是否大于等于预设电流阈值。
其中,所述预设电流阈值可以包括滞环比较器的半环宽。
具体地,计算机设备可以通过判断所述待补偿谐波电流与所述实际补偿电流的大小关系,以及所述电流差值与所述预设电流阈值之间的大小关系,确定控制滞环比较器驱动电流补偿逆变电路a/b/c相的上桥臂的功率器件动作或者确定控制滞环比较器驱动电流补偿逆变电路a/b/c相的下桥臂的功率器件动作,从而通过对实际补偿电流增大或减小实现对所述待补偿谐波电流的补偿处理。
在实际处理过程中,若所述待补偿谐波电流大于所述实际补偿电流,且所述电流差值大于等于所述预设电流阈值,进入步骤S122;反之,若所述待补偿谐波电流小于等于所述实际补偿电流,且所述电流差值小于所述预设电流阈值,进入步骤S123。
步骤S122,若所述待补偿谐波电流大于所述实际补偿电流,且所述电流差值大于等于所述 预设电流阈值,则基于脉宽调制信号控制实际补偿电流增大,最终输出第一谐波电流调节结果;其中,所述第一谐波电流调节结果包括调节所述待补偿谐波电流直至增大至第一预设电流阈值时输出的电流,所述脉宽调制信号包括将所述待补偿谐波电流与实际补偿电流输入至滞环比较器后生成的信号。
具体地,计算机设备可以如图3所示实现经滞环控制器控制电流补偿逆变电路a/b/c相的上桥臂的功率器件动作,达到对谐波电流的补偿操作,也即滞环控制器根据所述脉宽调制信号输出正电平,驱动上桥臂功率器件导通,变压变频器输出正电压,使得实际补偿电流增大,当增长到与待补偿谐波电流相等时,虽然滞环比较器的输入信号符号发生变化,但滞环控制器仍保持正电平输出,上桥臂功率器件依然导通,使得实际补偿电流继续增大,直到实际补偿电流和预设电流阈值之和与待补偿谐波电流相等时,滞环控制器翻转,输出负电平,关断上桥臂功率器件后导通下桥臂功率器件。经过逆变电路的谐波电流补偿,使得计算机设备中的谐波电流分量减小,从而最终输出第一谐波电流调节结果。
在实际处理过程中,计算机设备输出的第一谐波电流调节结果,包括采用
Figure PCTCN2021094665-appb-000011
得到的结果;其中,i *为用于滞环控制切换时刻的补偿电流,V dc为逆变器电路中的直流侧电容电压,L s为用于谐波电流补偿的滤波电感。可选地,逆变器电路可以包括图5中由12组绝缘栅双极型晶体管(Insulated Gate Bipolar Transistor,IGBT)功率导通二极管、反并联二极管的器件组合、2个电容C 1和C 2构成的电路。
步骤S123,若所述待补偿谐波电流小于等于所述实际补偿电流,且所述电流差值小于所述预设电流阈值,则基于脉宽调制信号控制实际补偿电流减小,最终输出第二谐波电流调节结果;其中,所述第二谐波电流调节结果包括调节所述待补偿谐波电流直至减小至第二预设电流阈值时输出的电流。
具体地,计算机设备也可以如图3所示实现经滞环控制器控制电流补偿逆变电路a/b/c相的下桥臂的功率器件动作,达到对谐波电流的补偿操作,也即滞环控制器根据所述脉宽调制信号输出负电平,驱动下桥臂功率器件导通,变压变频器输出负电压,使得实际补偿电流减小,当减小到与待补偿谐波电流相等时,虽然滞环比较器的输入信号符号发生变化,但滞环控制器仍保持负电平输出,下桥臂功率器件依然导通,使得实际补偿电流继续减小,直到实际补偿电流和预设电流阈值之差与待补偿谐波电流相等时,滞环控制器翻转,输出正电平,关断下桥臂功率器件后导通上桥臂功率器件。经过逆变电路的谐波电流补偿,从而使得系统中的谐波电流分量减小。
在实际处理过程中,计算机设备输出的第二谐波电流调节结果,包括采用
Figure PCTCN2021094665-appb-000012
得到的结果。通过所述第一谐波电流调级结果和所述第二谐波电流调节结果的调节过程,能够有效降低计算机设备中的谐波电流分量,从而也能够有效提高计算机设备中有效电流的准确性和可靠性。
步骤S13,根据所述待补偿谐波电压与预先获取的目标开关时间,对所述待补偿谐波电压进行电压调节处理,得到谐波电压调节结果;其中,所述目标开关时间包括控制有源滤波器中多组功率导通元件开关和闭合的时间。
具体地,计算机设备对所述待补偿谐波电压进行电压调节处理的过程可以如图4所示,包括以下子步骤:
步骤S131,将由gh坐标系构成的矢量空间从0°为起始点、以设定角度间隔进行扇区划分,得到多个扇区。
具体地,计算机设备可以将由gh坐标系构成的矢量空间从0°为起始点、以60°为设定角度间隔进行扇区划分,得到扇区I、扇区II、扇区III、扇区IV、扇区V以及扇区VI。
在实际处理过程中,计算机设备可以先按2D-SVPWM法划分36个扇区完整计算各矢量的作用时间,再根据电压零序分量计算正负小矢量的作用时间,最后得到各开关的作用时间。经归纳发现开关时间只需根据参考矢量的相位划分为12个扇区进行计算,因此可以去除子扇区的划 分,减少了计算量,消除子扇区划分误差。直流侧电容电压通过零序分量间接控制上下电压平衡。变换器输出经滤波电感接到电网,每相有4个开关管,6个二极管,直流侧有上下两个电容。
如图5所示的滤波器中,有如下表达式:
Figure PCTCN2021094665-appb-000013
式(1)中,L s为滤波电感,R s为电感寄生电阻;S ua、S ub、S uc分别为a、b、c相上桥臂开关状态,S da、S db、S dc分别为a、b、c相下桥臂开关状态,e a、e b、e c分别为锁相环在时刻t的三相参考电压;C 1、C 2分别为直流侧电容,u dc1、u dc2分别为C 1、C 2对应的电压大小;i sa、i sb、i sc分别为a、b、c相滤波电感所在支路的电流(以指向逆变器方向为正)。该式由abc坐标转化到αβ0坐标下需通过Clarke变换得到:
Figure PCTCN2021094665-appb-000014
式(2)中,S 、S 、S u0为S ua、S ub、S uc由abc坐标系转化到αβ0坐标系下的上桥臂开关状态;S 、S 、S d0为S da、S db、S dc由abc坐标系转化到αβ0坐标系下的下桥臂开关状态;i 、i 、i s0为i sa、i sb、i sc由abc坐标系转化到αβ0坐标系下的滤波电感所在支路的电流;e α、e β、e 0为e a、e b、e c由abc坐标系转化到αβ0坐标系下的电网电压。
三电平3D-SVPWM共有27个矢量,如图6A所示,有源滤波器左侧的逆变器模块,根据各相通断的功率管号,1、2通命名为S=1;2、3通命名为S=0;3、4通命名为S=-1,三相的状态各不同可有3*3*3即27个矢量,其中6个大矢量,6个中矢量,12个小矢量和3个零矢量,具体矢量图详见表1。27种空间矢量在αβ0坐标系用直流电压V dc单位化的值见附录表1,27种空间矢量在αβ坐标系与gh坐标系下的示意图如图6B所示。调制作用时间需通过gh坐标法转化后进行计算,将矢量空间(gh坐标系)从0°开始分为6个扇区(各60度),每个区再分为4个子扇区。参考电压U ref在gh坐标系中表示为(u ref_g,u ref_h),αβ与abc坐标系的转换关系为:
Figure PCTCN2021094665-appb-000015
式(3)中,u ref_g为U ref在gh坐标系下的g轴分量,u ref_h为U ref在gh坐标系下的h轴分量;直流电压V dc的大小根据需要自行确定(可以包括u dc1与u dc2之和),U ref为根据三相以V dc单位化后的值进行确定。
表1
Figure PCTCN2021094665-appb-000016
再根据(u ref_g,u ref_h)的大小将6个扇区中每个扇区分为4个子扇区,划分方法为:
Figure PCTCN2021094665-appb-000017
在计算各开关的通断时间时又根据参考矢量相位(u ref_g,u ref_h)将A区、C区分为A1、A2 与C1、C2。采用最近的矢量对开关作用时间进行拟合,拟合所需时间如附录表2所示(以第I扇区为例)。
表2
Figure PCTCN2021094665-appb-000018
3D-SVPWM电压矢量作用时间为:
Figure PCTCN2021094665-appb-000019
式(4)中,针对同一扇区内,V αβ0r为αβ0坐标系下的参考电压矢量;V αβ0zn、V αβ0zp分别为αβ0坐标系下零矢量正、负小矢量的对应矢量;V αβ0i、V αβ0j分别为αβ0坐标系下其余矢量的对应矢量;T zp、T zn分别为零矢量正、负小矢量对应的作用时间;T i、T j分别为其余矢量分别对应的作用时间。
为方便计算先不考虑零矢量,同2D-SVPWM法在αβ坐标系下计算出3个矢量的作用时间为:
Figure PCTCN2021094665-appb-000020
式(5)中,V αβr为αβ坐标系下的参考电压矢量,V αβi、V αβj、V αβz分别为αβ坐标系下的同一区内对应矢量,T z为零矢量对应的作用时间。
再考虑零序分量计算零矢量的正负小矢量作用时间为:
Figure PCTCN2021094665-appb-000021
式(6)中,V 0_r为零序参考电压;V 0i、V 0j、V 0zn、V 0zp分别为对应同一区下的不同矢量;T z为零矢量的作用时间。
以第I扇区B子扇区为例,由式(4)得到:
Figure PCTCN2021094665-appb-000022
然后得到基于gh坐标系下的SVPWM作用时间:
Figure PCTCN2021094665-appb-000023
再计算得到零序分量表达式:
Figure PCTCN2021094665-appb-000024
即:
Figure PCTCN2021094665-appb-000025
由附表1知,V 1、V 12、V 01p、V 01n所对应的开关状态分别为(1,-1,-1)、(1,0,-1)、(1,0,0)、(0,-1,-1)。基于8段合成参考电压法,从零矢量的正矢量开始,每变一相开关状态,两侧对称,即顺序为(1,0,0)→(1,0,-1)→(1,-1,-1)→(0,-1,-1)→(1,-1,-1)→(1,0,-1)→(1,0,0)。该顺序内各开关状态所对应的开关时长依次为:
Figure PCTCN2021094665-appb-000026
此处定义开关状态为0时为开关作用状态,则得到第I扇区B子扇区的三相开关作用时间为:
Figure PCTCN2021094665-appb-000027
将式(4)中的B子扇区作用时间、式(10)代入式(11)中,得到电压补偿模块的三相有源滤波器的逆变模块开关的作用时间为:
Figure PCTCN2021094665-appb-000028
经过(1)至(12)方式计算得到各子扇区的矢量作用时间,确定所有开关的作用时间由i sb<0、i sb>0分成两组,因此可以不用再区分子扇区,从而消除子扇区划分误差,也即确定将由gh坐标系构成的矢量空间划分为扇区I、扇区II、扇区III、扇区IV、扇区V以及扇区VI。
步骤S132,获取每个扇区的扇区开关时间,并从获取得到的多个扇区开关时间中选取一个扇区开关时间作为所述目标开关时间;其中,所述扇区开关时间用于表征对应扇区下的逆变电路功率器件的开关时间。
具体地,计算机设备可以针对由gh坐标系构成的矢量空间划分的多个扇区先确定目标扇区,所述目标扇区可以为参考矢量相位(u ref_g,u ref_h)所在位置对应的扇区,然后确定出所述目标扇区对应的目标扇区开关时间。
在实际处理过程中,逆变电路可以包括图5中12组IGBT、反并联二极管的器件组合构成的电路,逆变电路功率器件可以包括功率导通元件。
步骤S133,将所述待补偿谐波电压输入至预先设置的谐波电压调节电路中,并将所述谐波电压调节模型电路的输出电压作为谐波电压调节结果;其中,所述谐波电压调节电路包括多组功率导通元件和负载元件按照预设连接方式连接,且所述多组功率导通元件根据所述目标开关时间导通或者截止。
具体地,计算机设备可以将所述待补偿谐波电压输入至预先设置的谐波电压调节电路(比如并联型有源滤波器)中进行谐波电压调节,也即先获取所述待补偿谐波电压对应的目标脉宽调制信号,再将所述目标脉宽调制信号输入至并联型有源滤波器中,通过所述目标开关时间控制逆变器开关通断,最终经过谐波电压调节电路中的对应功率导通元件和负载输出的电压,即为所述谐波电压调节结果。可选地,每组功率导通元件可以为由IGBT与反并联二极管形成的组合。
在实际处理过程中,所述并联型有源滤波器也可以如图5所示,所述并联型有源滤波器可以包括中点钳位型三电平逆变器、a相包括的4组功率器件、b相包括的4组功率器件、c相包括的4组功率器件、两个钳位二极管以及负载,4组功率器件都为S *1、S *2、S *3、S *4。通过所获取的目标开关时间和预先设置的谐波电压调节电路实现对所述待补偿谐波电压的补偿过程,能够有效降低计算机设备中的谐波电压分量,从而也能够有效提高计算机设备中有效电压的准确性和可靠性。
步骤S14,根据所述谐波电流调节结果和所述谐波电压调节结果,确定电网中电能质量的目标等级。
具体地,计算机设备确定电网中电能质量的目标等级可以如图7所示,包括以下步骤:
步骤S141,对所述谐波电流调节结果和所述谐波电压调节结果进行傅里叶变换处理,得到电网侧电流和电压的总谐波畸变率。
具体地,所述总谐波畸变率可以包括采用下式得到的电流谐波畸变率和电压谐波畸变率:
Figure PCTCN2021094665-appb-000029
其中,THD I为电流谐波畸变率,I k为第k次谐波电流有效值,I 1为基波电流有效值,THD U为电压谐波畸变率,U k为第k次谐波电压有效值,U 1为基波电压有效值。
步骤S142,判断所述总谐波畸变率是否满足预设畸变率阈值。
具体地,计算机设备获取到所述总谐波畸变率时,可以进一步判断所述总谐波畸变率是否小于或等于预设畸变率阈值,所述预设畸变率阈值可以用于表征所述待补偿谐波电流和所述待补偿谐波电压分别经过补偿后得到的剩余谐波电流和剩余谐波电压不影响电网中有效电流和有效电压的有效性。
在实际处理过程中,计算机设备确定所述总谐波畸变率满足预设畸变率阈值时,进入步骤S143;反之,计算机设备确定所述总谐波畸变率不满足预设畸变率阈值时,进入步骤S144。
步骤S143,如果满足,则根据所述总谐波畸变率确定对应的目标等级。
具体地,计算机设备确定所述总谐波畸变率满足预设畸变率阈值,可以说明所述总谐波畸变率小于或等于预设畸变率阈值,也可以表征此次对所述待补偿谐波电流和所述待补偿谐波电压分别经过补偿后得到的剩余谐波电流和剩余谐波电压不影响电网中有效电流和有效电压的有效性,此时可以进一步确定此次所得到的所述总谐波畸变率对应的目标等级;比如,当预设畸变率阈值为2%时,如果此次计算出的所述总谐波畸变率为1%,所述目标等级可以为良好,如果此次计算出的所述总谐波畸变率为0.5%,所述目标等级可以为优质。
步骤S144,如果不满足,则将t+lΔt作为新的t,将l+1作为新的l,继续执行所述计算电网侧电流和电压的总谐波畸变率的步骤;直至得到所述目标等级;其中,l的取值为大于等于0的整数,l=0、1、2、3、......,l为重新计算总谐波畸变率的次数且初值为0,Δt为预先设定的时间间隔。
具体地,计算机身确定所述总谐波畸变率不满足预设畸变率阈值,可以说明所述总谐波畸变率大于预设畸变率阈值,也可以表征此次对所述待补偿谐波电流和所述待补偿谐波电压分别经过补偿后得到的剩余谐波电流和剩余谐波电压会影响电网中有效电流和有效电压的有效性,此时可以进一步将t+lΔt作为新的t,将l+1作为新的l,继续执行所述计算电网侧电流和电压的总谐波畸变率的步骤;直至确定出电网中电能质量的目标等级;以此确保所述待补偿谐波电流和所述待谐波电压分别经过补偿后的谐波电流调节结果和谐波电压调节结果的灵活性和可靠性,从而确保电网中电能质量的有效性和稳定性。
上述电网中的电能质量等级确定方法中,首先获取电网中的待补偿谐波电流和待补偿谐波电压,并根据所述待补偿谐波电流与实际补偿电流的电流比较结果对所述待补偿谐波电流进行电流调节处理,以及根据所述待补偿谐波电压与预先获取的目标开关时间对所述待补偿谐波电压进行电压调节处理来得到谐波电流调节结果和谐波电压调节结果,以此通过所述待补偿谐波电流与实际补偿电流的电流比较结果实现谐波电路的调节、通过所述待补偿谐波电压与目标开关时间实现对所述待补偿谐波电压的调节,避免了传统技术中使用滞环比较器补偿dq0变换法检测的谐波电流、使用并联型有源滤波器补偿dq0变换法检测的谐波电压导致的谐波电压和谐波电流的补偿精确度不高及计算量较大的问题,提高了谐波电流和谐波电压的补偿精确度及补偿速度;进一步地,根据所述谐波电流调节结果和所述谐波电压调节结果,确定电网中电能质量的目标等级,以此实现获取谐波电流调节结果和谐波电压调节结果对应的电能质量的目标等级的目的,也能够实现当目标等级越高时所确定出的谐波电流调节结果和谐波电压调节结果的补偿精确度也越高的目的,提高了获取谐波电流调节结果和谐波电压调节结果的准确性和可靠性。
在一个实施例中,如图8所示,步骤S11中所述待补偿谐波电流的获取过程,是通过FBD检测法检测后获取的,具体可以包括以下子步骤:
步骤S111,确定锁相环生成的三相参考电压和锁相环的三相电流。
具体地,计算机设备在获取所述三相参考电压和所述三相电流时,可以通过采用下式得到:
Figure PCTCN2021094665-appb-000030
Figure PCTCN2021094665-appb-000031
其中,e a、e b、e c分别为锁相环在时刻t的三相参考电压,i a、i b、i c分别为锁相环在时刻t的三相电流,
Figure PCTCN2021094665-appb-000032
为锁相环a相电压与基波正序电流夹角,
Figure PCTCN2021094665-appb-000033
分别为锁相环电流正序、负序、零序的n次谐波电流初相位,I 1n、I 2n、I 0n分别为锁相环电流正序、负序、零序的n次谐波电流幅值,ω为电网的角频率,ωt为电网在时刻t的相角变化。
步骤S112,根据所述三相参考电压和所述三相电流,确定锁相环生成的三相有功电导分量和锁相环生成的三相无功电导分量。
具体地,所述三相有功电导分量和所述三相无功电导分量可以采用下式得到:
Figure PCTCN2021094665-appb-000034
其中,G P(t)为锁相环在时刻t生成的三相有功电导分量,G Q(t)为锁相环在时刻t生成的三相无功电导分量,P 为锁相环三相参考功率之和,u为经过锁相环后得到的理想三相电压,i为经过锁相环后得到的三相电流,u *为锁相得到系统电压相位移后的参考电压,
Figure PCTCN2021094665-appb-000035
分别为锁相环三相位移后的具体参考电压,<u,i>为求u与i的内积,<u,u>为求u与u的内积,<u *,i>为求u *与i的内积,<u *,u>为求u *与u的内积,<u,i>为求u与i的内积。
步骤S113,根据所述三相有功电导分量和所述三相无功电导分量,确定有功电导直流分量和无功电导直流分量。
具体地,所述有功电导直流分量和无功电导直流分量可以是对所述三相有功电导分量和所述三相无功电导分量进行低通滤波后得到的,并可以采用下式得到:
Figure PCTCN2021094665-appb-000036
其中,G P为时刻t的有功电导直流分量,G Q为时刻t的无功电导直流分量,I 1amp为锁相环的正序电流幅值,
Figure PCTCN2021094665-appb-000037
为锁相环a相电压与基波正序电流夹角。
步骤S114,根据所述有功电导直流分量、所述无功电导直流分量以及所述三相参考电压,得到三相基波正序有功电流分量和三相基波正序无功电流分量。
具体地,计算机设备可以根据下式得到所述三相基波正序有功电流分量和所述三相基波正序无功电流分量:
Figure PCTCN2021094665-appb-000038
其中,i a1P、i b1P、i c1P分别为时刻t的三相基波正序有功电流分量,i a1Q、i b1Q、i c1Q分别为时刻t的三相基波正序无功电流分量。
步骤S115,根据所述三相电流、所述三相基波正序有功电流分量和所述三相基波正序无功电流分量,得到所述待补偿谐波电流。
具体地,所述待补偿谐波电流可以包括时刻t的三相待补偿谐波电流,并且计算机设备可以采用下式得到时刻t的三相待补偿谐波电流:
Figure PCTCN2021094665-appb-000039
其中,i a1、i b1、i c1分别为锁相环在时刻t的三相基波正序电流,i a、i b、i c分别为锁相环在时刻t的三相电流,
Figure PCTCN2021094665-appb-000040
分别为时刻t的三相待补偿谐波电流。
本实施例中,计算机设备通过FBD检测法检测电网中的谐波电流的过程确定出电网中的待补偿谐波电流,能够结合FBD检测法的易实现性和较高的实时性的优点实现快速获取所述待补偿谐波电流的目的,从而提高了所述待补偿电流的可靠性和准确性。
在一个实施例中,如图9所示,步骤S11中所述待补偿谐波电流的获取过程,可以是使用dq0检测法检测获取的,具体可以包括以下子步骤:
步骤S21,获取电网中的三相电源电压。
具体地,计算机设备可以采用下式得到电网中时刻t的三相电源电压:
Figure PCTCN2021094665-appb-000041
其中,u a、u b、u c分别为电网中时刻t的三相电源电压,u 0为电网中的基波电压零序分量,
Figure PCTCN2021094665-appb-000042
分别为电网中电压在时刻t的三相正序分量,
Figure PCTCN2021094665-appb-000043
分别为电网中电压在时刻t的三相负序分量,
Figure PCTCN2021094665-appb-000044
分别为电网中电压在时刻t的三相n次谐波的正序分量,
Figure PCTCN2021094665-appb-000045
Figure PCTCN2021094665-appb-000046
分别为电网中电压在时刻t的三相n次谐波的负序分量,U +、U -分别为电网中的基波电压基波正、负序幅值;
Figure PCTCN2021094665-appb-000047
分别为电网中的基波电压基波正、负序相位,
Figure PCTCN2021094665-appb-000048
分别为电网中的谐波电压n次谐波正、负序幅值,
Figure PCTCN2021094665-appb-000049
分别为电网中的谐波电压n次谐波正、负序相位,ω为电网的角频率,ωt为电网在时刻t的相角变化。
步骤S22,将所述三相电源电压进行dq0坐标系转换处理,得到三相电源电压在dq0坐标系下的d轴正序分量和三相电源电压在dq0坐标系下的q轴正序分量。
具体地,计算机设备可以采用下式将所述三相电源电压进行dq0坐标系下,得到三相电源电压在dq0坐标系下时刻t的d轴正序分量和三相电源电压在dq0坐标系下时刻t的q轴正序分量:
Figure PCTCN2021094665-appb-000050
Figure PCTCN2021094665-appb-000051
Figure PCTCN2021094665-appb-000052
其中,u d为三相电源电压在dq0坐标系下的d轴分量,u q为三相电源电压在dq0坐标系下的q轴分量,
Figure PCTCN2021094665-appb-000053
分别为电网中电压在时刻t的三相n次谐波的正序分量,
Figure PCTCN2021094665-appb-000054
Figure PCTCN2021094665-appb-000055
分别为电网中电压在时刻t的三相n次谐波的负序分量,
Figure PCTCN2021094665-appb-000056
为三相电源电压在dq0坐标系下 时刻t的d轴正序分量,
Figure PCTCN2021094665-appb-000057
为三相电源电压在dq0坐标系下时刻t的q轴正序分量。
在实际处理过程中,计算机设备还可以采用下式得到三相电源电压在dq0坐标系下时刻t的d轴负序分量和三相电源电压在dq0坐标系下时刻t的q轴负序分量:
Figure PCTCN2021094665-appb-000058
其中,
Figure PCTCN2021094665-appb-000059
为电网中的谐波电压n次谐波负序幅值,
Figure PCTCN2021094665-appb-000060
为电网中的谐波电压n次谐波负序相位,
Figure PCTCN2021094665-appb-000061
为三相电源电压在dq0坐标系下时刻t的d轴负序分量,
Figure PCTCN2021094665-appb-000062
为三相电源电压在dq0坐标系下时刻t的q轴负序分量。
步骤S23,对所述d轴正序分量和所述q轴正序分量进行低通滤波处理,得到三相电源电压的d轴直流分量和三相电源电压的q轴直流分量。
具体地,计算机设备可以采用下式得到三相电源电压在时刻t的d轴直流分量和三相电源电压在时刻t的q轴直流分量:
Figure PCTCN2021094665-appb-000063
其中,
Figure PCTCN2021094665-appb-000064
为三相电源电压在时刻t的d轴直流分量,
Figure PCTCN2021094665-appb-000065
为三相电源电压在时刻t的q轴直流分量,
Figure PCTCN2021094665-appb-000066
为电网中的基波电压基波正序相位,U +为电网中的基波电压基波正序幅值。
在实际处理过程中,abc坐标中的第n次正序分量将转化为dq0坐标中的第n-1次分量,而第n次负序分量则将转化为dq0坐标中的第n+1次分量。dq0坐标中的直流分量是由abc坐标系统中的基波分量通过Park变换式(26)转化而来,需通过低通滤波器进行分离。
步骤S24,对所述d轴直流分量和所述q轴直流分量进行dq0反变换处理,得到电网中电压的三相正序分量。
具体地,计算机设备可以采用下式得到电网中电压在时刻t的三相正序分量:
Figure PCTCN2021094665-appb-000067
其中,
Figure PCTCN2021094665-appb-000068
为电网中电压在时刻t的三相正序分量,
Figure PCTCN2021094665-appb-000069
为三相电源电压在时刻t的d轴直流分量,
Figure PCTCN2021094665-appb-000070
为三相电源电压在时刻t的q轴直流分量,
Figure PCTCN2021094665-appb-000071
为电网中的基波电压基波正序相位,U +为电网中的基波电压基波正序幅值。
步骤S25,根据所述电网中电压的三相正序分量和所述三相电源电压,确定所述待补偿谐波电压。
具体地,计算机设备可以采用下式得到时刻t的三相待补偿谐波电压:
Figure PCTCN2021094665-appb-000072
其中,u ac、u bc、u cc分别为时刻t的三相待补偿谐波电压,
Figure PCTCN2021094665-appb-000073
分别为电网中电压在时刻t的三相正序分量,u a、u b、u c分别为电网中时刻t的三相电源电压。
本实施例中,计算机设备通过dq0检测法检测电网中的谐波电压的过程确定出电网中的待补偿谐波电压,能够结合dq0检测法的易实现性和灵活性的优点实现快速获取所述待补偿谐波电压的目的,从而提高了所述待补偿电压的可靠性和准确性。
在一个实施例中,如图10所示,步骤S132中所述获取每个扇区的扇区开关时间,可以通 过改进的3D-SVPWM法的子扇区划分方法获取,具体可以包括以下子步骤:
步骤S1321,根据电网中的三相电源电压,确定三相电源电压在gh坐标系下的g轴电压分量和三相电源电压在gh坐标系下的h轴电压分量。
具体地,计算机设备可以采用下式得到所述g轴电压分量和所述h轴电压分量:
Figure PCTCN2021094665-appb-000074
其中,u a、u b、u c为电网中的三相电源电压,u ref_g为三相电源电压在gh坐标系下的g轴电压分量,u ref_h为三相电源电压在gh坐标系下的h轴电压分量。
步骤S1322,根据预先获取的每组功率导通元件的通断所需时间、零序参考电压、逆变器电路中的直流侧电容电压、所述g轴电压分量和所述h轴电压分量,确定每个扇区的扇区开关时间。
具体地,计算机设备所确定出的所述扇区开关时间可以包括扇区I开关时间、扇区II开关时间、扇区III开关时间、扇区IV开关时间、扇区V开关时间、扇区VI开关时间,并且采用下式得到:
Figure PCTCN2021094665-appb-000075
其中,T a、T b、T c为对应扇区的三相开关时间,u ref_g为参考电压在gh坐标系下的g轴电压分量,u ref_h为参考电压在gh坐标系下的h轴电压分量,T s为每个功率导通元件的通断所需时间,V 0_r为零序参考电压,V dc为逆变器电路中的直流侧电容电压;i sa、i sb、i sc为三相滤波电感所在支路的电流,且i sa、i sb、i sc均以指向逆变器方向为正。
本实施例中,计算机设备通过改进的3D-SVPWM法将由gh坐标系构成的矢量空间划分为6个扇区的方式,避免了传统3D-SVPWM法进行各个扇区的子扇区划分所导致的计算误差和零序分量难以控制的问题,提高了划分6个子扇区的优越性和可靠性;进一步地,再通过获取每个扇区下的逆变电流功率器的开关时间作为对应扇区的扇区开关时间,从而提高了获取所述扇区开关时间的灵活性和可靠性。
应该理解的是,虽然图1、图2、图4、图7-10的流程图中的各个步骤按照箭头的指示依次显示,但是这些步骤并不是必然按照箭头指示的顺序依次执行。除非本文中有明确的说明,这些步骤的执行并没有严格的顺序限制,这些步骤可以以其它的顺序执行。而且,图1、图2、图4、图7-10中的至少一部分步骤可以包括多个步骤或者多个阶段,这些步骤或者阶段并不必然是在同一时刻执行完成,而是可以在不同的时刻执行,这些步骤或者阶段的执行顺序也不必然是依次进行,而是可以与其它步骤或者其它步骤中的步骤或者阶段的至少一部分轮流或者交替地执行。
在一个实施例中,如图11所示,提供了一种电网中的电能质量等级确定装置,包括:获取模块11、第一调节模块12、第二调节模块13和确定模块14,其中:
获取模块11,用于获取电网中的待补偿谐波电流与待补偿谐波电压;
第一调节模块12,用于根据所述待补偿谐波电流与实际补偿电流的电流比较结果,对所述待补偿谐波电流进行电流调节处理,得到谐波电流调节结果;其中,所述实际补偿电流包括电流调节逆变器的实际输出电流;
第二调节模块13,用于根据所述待补偿谐波电压与预先获取的目标开关时间,对所述待补偿谐波电压进行电压调节处理,得到谐波电压调节结果;其中,所述目标开关时间包括控制有源滤波器中多组功率导通元件开关和闭合的时间;
确定模块14,用于根据所述谐波电流调节结果和所述谐波电压调节结果,确定电网中电能质量的目标等级。
所述获取模块11,可以具体用于采用下式获取时刻t的三相待补偿谐波电流和时刻t的三相待补偿谐波电压:
Figure PCTCN2021094665-appb-000076
其中,
Figure PCTCN2021094665-appb-000077
分别为时刻t的三相待补偿谐波电流,i a、i b、i c分别为锁相环在时刻t的三相电流,i a1、i b1、i c1分别为锁相环在时刻t的三相基波正序电流;u ac、u bc、u cc为时刻t的三相待补偿谐波电压,
Figure PCTCN2021094665-appb-000078
分别为电网中电压在时刻t的三相正序分量,u a、u b、u c分别为电网中时刻t的三相电源电压。
所述获取模块11,还可以具体用于获取锁相环在时刻t的三相基波正序电流,包括:
Figure PCTCN2021094665-appb-000079
Figure PCTCN2021094665-appb-000080
其中,i a1、i b1、i c1分别为锁相环在时刻t的三相基波正序电流,i a1P、i b1P、i c1P分别为时刻t的三相基波正序有功电流分量,i a1Q、i b1Q、i c1Q分别为时刻t的三相基波正序无功电流分量,G P为锁相环在时刻t的三相有功电导分量经过低通滤波后得到的有功电导直流分量,G Q为锁相环在时刻t的三相无功电导分量经过低通滤波后得到的无功电导直流分量,e a、e b、e c分别为锁相环在时刻t的三相参考电压,I 1amp为锁相环的正序电流幅值,
Figure PCTCN2021094665-appb-000081
为锁相环a相电压与基波正序电流夹角,ω为电网的角频率,ωt为电网在时刻t的相角变化。
第一调节模块,可以具体包括:第一判断子模块、第一调节子模块和第二调节子模块。
具体地,第一判断子模块,可以用于判断所述待补偿谐波电流是否大于所述实际补偿电流,且所述待补偿谐波电流与所述实际补偿电流的电流差值是否大于等于预设电流阈值;第一调节子模块,可以用于若所述待补偿谐波电流大于所述实际补偿电流,且所述电流差值大于等于所述预设电流阈值,则基于脉宽调制信号控制实际补偿电流增大,最终输出第一谐波电流调节结果;第二调节子模块,可以用于若所述待补偿谐波电流小于等于所述实际补偿电流,且所述电流差值小于所述预设电流阈值,则基于脉宽调制信号控制实际补偿电流减小,最终输出第二谐波电流调节结果;其中,所述第一谐波电流调节结果包括调节所述待补偿谐波电流直至增大至第一预设电流阈值时输出的电流,所述脉宽调制信号包括将所述待补偿谐波电流与实际补偿电流输入至滞环比较器后生成的信号,所述第二谐波电流调节结果包括调节所述待补偿谐波电流直至减小至第二预设电流阈值时输出的电流。
所述第一调节子模块,可以用于采用
Figure PCTCN2021094665-appb-000082
得到的结果。
所述第二调节子模块,可以用于采用
Figure PCTCN2021094665-appb-000083
得到的结果;其中,i *为用于滞环控制切换时刻的补偿电流,V dc为逆变器电路中的直流侧电容电压,L s为用于谐波电流补偿的滤波电感。
第二调节模块,可以具体包括:分割子模块、第一确定子模块和第三调节子模块。
具体地,分割子模块,可以用于将由gh坐标系构成的矢量空间从0°为起始点、以设定角度间隔进行扇区划分,得到多个扇区;第一确定子模块,可以用于获取每个扇区的扇区开关时间,并从获取得到的多个扇区开关时间中选取一个扇区开关时间作为所述目标开关时间;第三调节子模块,可以用于将所述待补偿谐波电压输入至预先设置的谐波电压调节电路中,并将所述谐波电压调节模型电路的输出电压作为谐波电压调节结果;其中,所述扇区开关时间用于表征对应扇区下的逆变电路功率器件的开关时间;所述谐波电压调节电路包括多组功率导通元件和负载元件按照预设连接方式连接,且所述多组功率导通元件根据所述目标开关时间导通或者截止。
分割子模块,还可以具体用于采用下式计算扇区I开关时间至扇区VI开关时间:
Figure PCTCN2021094665-appb-000084
Figure PCTCN2021094665-appb-000085
其中,T a、T b、T c分别为对应扇区的三相开关时间,u ref_g为参考电压在gh坐标系下的g轴电压分量,u ref_h为参考电压在gh坐标系下的h轴电压分量,T s为每个功率导通元件的通断所需时间,V 0_r为零序参考电压,V dc为逆变器电路中的直流侧电容电压;i sa、i sb、i sc分别为三相滤波电感所在支路的电流,且i sa、i sb、i sc均以指向逆变器方向为正。
确定模块14,可以具体包括;第二确定子模块、第二判断子模块、第三确定子模块和第四确定子模块。
具体地,第二确定子模块,可以用于对所述谐波电流调节结果和所述谐波电压调节结果进行傅里叶变换处理,得到电网侧电流和电压的总谐波畸变率;第二判断子模块,可以用于判断所述总谐波畸变率是否满足预设畸变率阈值;第三确定子模块,可以用于如果满足,则根据所述总谐波畸变率确定对应的目标等级;第四确定子模块,可以用于如果不满足,则将t+lΔt作为新的t,将l+1作为新的l,继续执行所述计算电网侧电流和电压的总谐波畸变率的步骤;直至得到所述目标等级;其中,l的取值为大于等于0的整数,l=0、1、2、3、......,l为重新计算总谐波畸变率的次数且初值为0,Δt为预先设定的时间间隔。
第二确定子模块,还可以具体用于采用下式得到的电流谐波畸变率和电压谐波畸变率:
Figure PCTCN2021094665-appb-000086
其中,THD I为电流谐波畸变率,I k为第k次谐波电流有效值,I 1为基波电流有效值,THD U为电压谐波畸变率,U k为第k次谐波电压有效值,U 1为基波电压有效值。
关于电网中的电能质量等级确定装置的具体限定可以参见上文中对于电网中的电能质量等级确定方法的限定,在此不再赘述。上述电网中的电能质量等级确定装置中的各个模块可全部或部分通过软件、硬件及其组合来实现。上述各模块可以硬件形式内嵌于或独立于计算机设备中的处理器中,也可以以软件形式存储于计算机设备中的存储器中,以便于处理器调用执行以上各个模块对应的操作。
在一个实施例中,提供了一种计算机设备,该计算机设备可以是终端,其内部结构图可以如图12所示。该计算机设备包括通过系统总线连接的处理器、存储器、通信接口、显示屏和输入装置。其中,该计算机设备的处理器用于提供计算和控制能力。该计算机设备的存储器包括非易失性存储介质、内存储器。该非易失性存储介质存储有操作系统和计算机程序。该内存储器为非易失性存储介质中的操作系统和计算机程序的运行提供环境。该计算机设备的通信接口用于与外部的终端进行有线或无线方式的通信,无线方式可通过WIFI、运营商网络、NFC(近场通信)或其他技术实现。该计算机程序被处理器执行时以实现一种电网中的电能质量等级确定方法。该计算机设备的显示屏可以是液晶显示屏或者电子墨水显示屏,该计算机设备的输入装置可以是显示屏上覆盖的触摸层,也可以是计算机设备外壳上设置的按键、轨迹球或触控板,还可以是外接的键盘、触控板或鼠标等。
本领域技术人员可以理解,图12中示出的结构,仅仅是与本申请方案相关的部分结构的框图,并不构成对本申请方案所应用于其上的计算机设备的限定,具体的计算机设备可以包括比 图中所示更多或更少的部件,或者组合某些部件,或者具有不同的部件布置。
在一个实施例中,提供了一种计算机设备,包括存储器和处理器,存储器中存储有计算机程序,该处理器执行计算机程序时实现以下步骤:
获取电网中的待补偿谐波电流与待补偿谐波电压;
根据所述待补偿谐波电流与实际补偿电流的电流比较结果,对所述待补偿谐波电流进行电流调节处理,得到谐波电流调节结果;其中,所述实际补偿电流包括电流调节逆变器的实际输出电流;
根据所述待补偿谐波电压与预先获取的目标开关时间,对所述待补偿谐波电压进行电压调节处理,得到谐波电压调节结果;其中,所述目标开关时间包括控制有源滤波器中多组功率导通元件开关和闭合的时间;
根据所述谐波电流调节结果和所述谐波电压调节结果,确定电网中电能质量的目标等级。
在一个实施例中,处理器执行计算机程序时还实现以下步骤:
判断所述待补偿谐波电流是否大于所述实际补偿电流,且所述待补偿谐波电流与所述实际补偿电流的电流差值是否大于等于预设电流阈值;若所述待补偿谐波电流大于所述实际补偿电流,且所述电流差值大于等于所述预设电流阈值,则基于脉宽调制信号控制实际补偿电流增大,最终输出第一谐波电流调节结果;若所述待补偿谐波电流小于等于所述实际补偿电流,且所述电流差值小于所述预设电流阈值,则基于脉宽调制信号控制实际补偿电流减小,最终输出第二谐波电流调节结果;其中,所述第一谐波电流调节结果包括调节所述待补偿谐波电流直至增大至第一预设电流阈值时输出的电流,所述脉宽调制信号包括将所述待补偿谐波电流与实际补偿电流输入至滞环比较器后生成的信号,所述第二谐波电流调节结果包括调节所述待补偿谐波电流直至减小至第二预设电流阈值时输出的电流。
在一个实施例中,处理器执行计算机程序时还实现以下步骤:
所述第一谐波电流调节结果包括:采用
Figure PCTCN2021094665-appb-000087
得到的结果,所述第二谐波电流调节结果包括:采用
Figure PCTCN2021094665-appb-000088
得到的结果;其中,i *为用于滞环控制切换时刻的补偿电流,V dc为逆变器电路中的直流侧电容电压,L s为用于谐波电流补偿的滤波电感。
在一个实施例中,处理器执行计算机程序时还实现以下步骤:
将由gh坐标系构成的矢量空间从0°为起始点、以设定角度间隔进行扇区划分,得到多个扇区;获取每个扇区的扇区开关时间,并从获取得到的多个扇区开关时间中选取一个扇区开关时间作为所述目标开关时间;将所述待补偿谐波电压输入至预先设置的谐波电压调节电路中,并将所述谐波电压调节模型电路的输出电压作为谐波电压调节结果;其中,所述扇区开关时间用于表征对应扇区下的逆变电路功率器件的开关时间;所述谐波电压调节电路包括多组功率导通元件和负载元件按照预设连接方式连接,且所述多组功率导通元件根据所述目标开关时间导通或者截止。
在一个实施例中,处理器执行计算机程序时还实现以下步骤:
采用下式计算扇区I开关时间至扇区VI开关时间:
Figure PCTCN2021094665-appb-000089
Figure PCTCN2021094665-appb-000090
其中,T a、T b、T c分别为对应扇区的三相开关时间,u ref_g为参考电压在gh坐标系下的g轴电压分量,u ref_h为参考电压在gh坐标系下的h轴电压分量,T s为每个功率导通元件的通断所需时间,V 0_r为零序参考电压,V dc为逆变器电路中的直流侧电容电压;i sa、i sb、i sc分别为三相滤波电感所在支路的电流,且i sa、i sb、i sc均以指向逆变器方向为正。
在一个实施例中,处理器执行计算机程序时还实现以下步骤:
采用下式获取时刻t的三相待补偿谐波电流和时刻t的三相待补偿谐波电压:
Figure PCTCN2021094665-appb-000091
Figure PCTCN2021094665-appb-000092
其中,
Figure PCTCN2021094665-appb-000093
分别为时刻t的三相待补偿谐波电流,i a、i b、i c分别为锁相环在时刻t的三相电流,i a1、i b1、i c1分别为锁相环在时刻t的三相基波正序电流;u ac、u bc、u cc分别为时刻t的三相待补偿谐波电压,
Figure PCTCN2021094665-appb-000094
分别为电网中电压在时刻t的三相正序分量,u a、u b、u c分别为电网中时刻t的三相电源电压。
在一个实施例中,处理器执行计算机程序时还实现以下步骤:
所述i a1、i b1、i c1分别为锁相环在时刻t的三相基波正序电流,包括:
Figure PCTCN2021094665-appb-000095
其中,i a1P、i b1P、i c1P分别为时刻t的三相基波正序有功电流分量,i a1Q、i b1Q、i c1Q分别为时刻t的三相基波正序无功电流分量,G P为锁相环在时刻t的三相有功电导分量经过低通滤波后得到的有功电导直流分量,G Q为锁相环在时刻t的三相无功电导分量经过低通滤波后得到的无功电导直流分量,e a、e b、e c分别为锁相环在时刻t的三相参考电压,I 1amp为锁相环的正序电流幅值,
Figure PCTCN2021094665-appb-000096
为锁相环a相电压与基波正序电流夹角,ω为电网的角频率,ωt为电网在时刻t的相角变化。
在一个实施例中,处理器执行计算机程序时还实现以下步骤:
对所述谐波电流调节结果和所述谐波电压调节结果进行傅里叶变换处理,得到电网侧电流和电压的总谐波畸变率;
判断所述总谐波畸变率是否满足预设畸变率阈值;
如果满足,则根据所述总谐波畸变率确定对应的目标等级;
如果不满足,则将t+lΔt作为新的t,将l+1作为新的l,继续执行所述计算电网侧电流和电压的总谐波畸变率的步骤;直至得到所述目标等级;其中,l的取值为大于等于0的整数,l=0、1、2、3、......,l为重新计算总谐波畸变率的次数且初值为0,Δt为预先设定的时间间隔。
在一个实施例中,处理器执行计算机程序时还实现以下步骤:
所述计算电网侧电流和电压的总谐波畸变率,包括采用下式得到的电流谐波畸变率和电压谐波畸变率:
Figure PCTCN2021094665-appb-000097
其中,THD I为电流谐波畸变率,I k为第k次谐波电流有效值,I 1为基波电流有效值,THD U为电压谐波畸变率,U k为第k次谐波电压有效值,U 1为基波电压有效值。
应当清楚的是,本申请实施例中处理器执行计算机程序的过程,与上述方法中各个步骤的执行过程一致,具体可参见上文中的描述。
在一个实施例中,提供了一种计算机可读存储介质,其上存储有计算机程序,计算机程序被处理器执行时实现以下步骤:
获取电网中的待补偿谐波电流与待补偿谐波电压;
根据所述待补偿谐波电流与实际补偿电流的电流比较结果,对所述待补偿谐波电流进行电流调节处理,得到谐波电流调节结果;其中,所述实际补偿电流包括电流调节逆变器的实际输出电流;
根据所述待补偿谐波电压与预先获取的目标开关时间,对所述待补偿谐波电压进行电压调节处理,得到谐波电压调节结果;其中,所述目标开关时间包括控制有源滤波器中多组功率导通元件开关和闭合的时间;
根据所述谐波电流调节结果和所述谐波电压调节结果,确定电网中电能质量的目标等级。
在一个实施例中,计算机程序被处理器执行时还实现以下步骤:
判断所述待补偿谐波电流是否大于所述实际补偿电流,且所述待补偿谐波电流与所述实际补偿电流的电流差值是否大于等于预设电流阈值;若所述待补偿谐波电流大于所述实际补偿电流,且所述电流差值大于等于所述预设电流阈值,则基于脉宽调制信号控制实际补偿电流增大,最终输出第一谐波电流调节结果;若所述待补偿谐波电流小于等于所述实际补偿电流,且所述电流差值小于所述预设电流阈值,则基于脉宽调制信号控制实际补偿电流减小,最终输出第二谐波电流调节结果;其中,所述第一谐波电流调节结果包括调节所述待补偿谐波电流直至增大至第一预设电流阈值时输出的电流,所述脉宽调制信号包括将所述待补偿谐波电流与实际补偿电流输入至滞环比较器后生成的信号,所述第二谐波电流调节结果包括调节所述待补偿谐波电流直至减小至第二预设电流阈值时输出的电流。
在一个实施例中,计算机程序被处理器执行时还实现以下步骤:
所述第一谐波电流调节结果包括:采用
Figure PCTCN2021094665-appb-000098
得到的结果,所述第二谐波电流调节结果包括:采用
Figure PCTCN2021094665-appb-000099
得到的结果;其中,i *为用于滞环控制切换时刻的补偿电流,V dc为逆变器电路中的直流侧电容电压,L s为用于谐波电流补偿的滤波电感。
在一个实施例中,计算机程序被处理器执行时还实现以下步骤:
将由gh坐标系构成的矢量空间从0°为起始点、以设定角度间隔进行扇区划分,得到多个扇区;获取每个扇区的扇区开关时间,并从获取得到的多个扇区开关时间中选取一个扇区开关时间作为所述目标开关时间;将所述待补偿谐波电压输入至预先设置的谐波电压调节电路中,并将所述谐波电压调节模型电路的输出电压作为谐波电压调节结果;其中,所述扇区开关时间用于表征对应扇区下的逆变电路功率器件的开关时间;所述谐波电压调节电路包括多组功率导 通元件和负载元件按照预设连接方式连接,且所述多组功率导通元件根据所述目标开关时间导通或者截止。
在一个实施例中,计算机程序被处理器执行时还实现以下步骤:
采用下式计算扇区I开关时间至扇区VI开关时间:
Figure PCTCN2021094665-appb-000100
其中,T a、T b、T c分别为对应扇区的三相开关时间,u ref_g为参考电压在gh坐标系下的g轴电压分量,u ref_h为参考电压在gh坐标系下的h轴电压分量,T s为每个功率导通元件的通断所需时间,V 0_r为零序参考电压,V dc为逆变器电路中的直流侧电容电压;i sa、i sb、i sc分别为三相滤波电感所在支路的电流,且i sa、i sb、i sc均以指向逆变器方向为正。
在一个实施例中,计算机程序被处理器执行时还实现以下步骤:
采用下式获取时刻t的三相待补偿谐波电流和时刻t的三相待补偿谐波电压:
Figure PCTCN2021094665-appb-000101
Figure PCTCN2021094665-appb-000102
其中,
Figure PCTCN2021094665-appb-000103
分别为时刻t的三相待补偿谐波电流,i a、i b、i c分别为锁相环在时刻t的三相电流,i a1、i b1、i c1分别为锁相环在时刻t的三相基波正序电流;u ac、u bc、u cc分别为时刻t的三相待补偿谐波电压,
Figure PCTCN2021094665-appb-000104
分别为电网中电压在时刻t的三相正序分量,u a、u b、u c分别为电网中时刻t的三相电源电压。
在一个实施例中,计算机程序被处理器执行时还实现以下步骤:
所述i a1、i b1、i c1分别为锁相环在时刻t的三相基波正序电流,包括:
Figure PCTCN2021094665-appb-000105
Figure PCTCN2021094665-appb-000106
其中,i a1P、i b1P、i c1P分别为时刻t的三相基波正序有功电流分量,i a1Q、i b1Q、i c1Q分别为时刻t的三相基波正序无功电流分量,G P为锁相环在时刻t的三相有功电导分量经过低通滤波后得到的有功电导直流分量,G Q为锁相环在时刻t的三相无功电导分量经过低通滤波后得到的无功电导直流分量,e a、e b、e c分别为锁相环在时刻t的三相参考电压,I 1amp为锁相环的正序电流幅值,
Figure PCTCN2021094665-appb-000107
为锁相环a相电压与基波正序电流夹角,ω为电网的角频率,ωt为电网在时刻t的相角变化。
在一个实施例中,计算机程序被处理器执行时还实现以下步骤:
对所述谐波电流调节结果和所述谐波电压调节结果进行傅里叶变换处理,得到电网侧电流和电压的总谐波畸变率;
判断所述总谐波畸变率是否满足预设畸变率阈值;
如果满足,则根据所述总谐波畸变率确定对应的目标等级;
如果不满足,则将t+lΔt作为新的t,将l+1作为新的l,继续执行所述计算电网侧电流和电压的总谐波畸变率的步骤;直至得到所述目标等级;其中,l的取值为大于等于0的整数,l=0、1、2、3、......,l为重新计算总谐波畸变率的次数且初值为0,Δt为预先设定的时间间隔。
在一个实施例中,计算机程序被处理器执行时还实现以下步骤:
所述计算电网侧电流和电压的总谐波畸变率,包括采用下式得到的电流谐波畸变率和电压谐波畸变率:
Figure PCTCN2021094665-appb-000108
其中,THD I为电流谐波畸变率,I k为第k次谐波电流有效值,I 1为基波电流有效值,THD U为电压谐波畸变率,U k为第k次谐波电压有效值,U 1为基波电压有效值。
应当清楚的是,本申请实施例中处理器执行计算机程序的过程,与上述方法中各个步骤的执行过程一致,具体可参见上文中的描述。
本领域普通技术人员可以理解实现上述实施例方法中的全部或部分流程,是可以通过计算机程序来指令相关的硬件来完成,所述的计算机程序可存储于一非易失性计算机可读取存储介质中,该计算机程序在执行时,可包括如上述各方法的实施例的流程。其中,本申请所提供的各实施例中所使用的对存储器、存储、数据库或其它介质的任何引用,均可包括非易失性和易失性存储器中的至少一种。非易失性存储器可包括只读存储器(Read-Only Memory,ROM)、磁带、软盘、闪存或光存储器等。易失性存储器可包括随机存取存储器(Random Access Memory,RAM)或外部高速缓冲存储器。作为说明而非局限,RAM可以是多种形式,比如静态随机存取存储器(Static Random Access Memory,SRAM)或动态随机存取存储器(Dynamic Random Access Memory,DRAM)等。
以上实施例的各技术特征可以进行任意的组合,为使描述简洁,未对上述实施例中的各个技术特征所有可能的组合都进行描述,然而,只要这些技术特征的组合不存在矛盾,都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式,其描述较为具体和详细,但并不能因此而理解为对发明专利范围的限制。应当指出的是,对于本领域的普通技术人员来说,在不脱离本申请构思的前提下,还可以做出若干变形和改进,这些都属于本申请的保护范围。因此,本申请专利的保护范围应以所附权利要求为准。

Claims (12)

  1. 一种电网中的电能质量等级确定方法,其特征在于,所述方法包括:
    获取电网中的待补偿谐波电流与待补偿谐波电压;
    根据所述待补偿谐波电流与实际补偿电流的电流比较结果,对所述待补偿谐波电流进行电流调节处理,得到谐波电流调节结果;其中,所述实际补偿电流包括电流调节逆变器的实际输出电流;
    根据所述待补偿谐波电压与预先获取的目标开关时间,对所述待补偿谐波电压进行电压调节处理,得到谐波电压调节结果;其中,所述目标开关时间包括控制有源滤波器中多组功率导通元件开关和闭合的时间;
    根据所述谐波电流调节结果和所述谐波电压调节结果,确定电网中电能质量的目标等级。
  2. 根据权利要求1所述的方法,其特征在于,所述根据所述待补偿谐波电流与实际补偿电流的电流比较结果,对所述待补偿谐波电流进行电流调节处理,得到谐波电流调节结果,包括:
    判断所述待补偿谐波电流是否大于所述实际补偿电流,且所述待补偿谐波电流与所述实际补偿电流的电流差值是否大于等于预设电流阈值;
    若所述待补偿谐波电流大于所述实际补偿电流,且所述电流差值大于等于所述预设电流阈值,则基于脉宽调制信号控制实际补偿电流增大,最终输出第一谐波电流调节结果;
    若所述待补偿谐波电流小于等于所述实际补偿电流,且所述电流差值小于所述预设电流阈值,则基于脉宽调制信号控制实际补偿电流减小,最终输出第二谐波电流调节结果;
    其中,所述第一谐波电流调节结果包括调节所述待补偿谐波电流直至增大至第一预设电流阈值时输出的电流,所述脉宽调制信号包括将所述待补偿谐波电流与实际补偿电流输入至滞环比较器后生成的信号,所述第二谐波电流调节结果包括调节所述待补偿谐波电流直至减小至第二预设电流阈值时输出的电流。
  3. 根据权利要求2所述的方法,其特征在于,所述第一谐波电流调节结果包括:采用
    Figure PCTCN2021094665-appb-100001
    得到的结果,所述第二谐波电流调节结果包括:采用
    Figure PCTCN2021094665-appb-100002
    得到的结果;
    其中,i *为用于滞环控制切换时刻的补偿电流,V dc为逆变器电路中的直流侧电容电压,L s为用于谐波电流补偿的滤波电感。
  4. 根据权利要求1所述的方法,其特征在于,所述根据所述待补偿谐波电压与预先获取的目标开关时间,对所述待补偿谐波电压进行电压调节处理,得到谐波电压调节结果,包括:
    将由gh坐标系构成的矢量空间从0°为起始点、以设定角度间隔进行扇区划分,得到多个扇区;
    获取每个扇区的扇区开关时间,并从获取得到的多个扇区开关时间中选取一个扇区开关时间作为所述目标开关时间;其中,所述扇区开关时间用于表征对应扇区下的逆变电路功率器件的开关时间;
    将所述待补偿谐波电压输入至预先设置的谐波电压调节电路中,并将所述谐波电压调节模型电路的输出电压作为谐波电压调节结果;其中,所述谐波电压调节电路包括多组功率导通元件和负载元件按照预设连接方式连接,且所述多组功率导通元件根据所述目标开关时间导通或者截止。
  5. 根据权利要求4所述的方法,其特征在于,所述扇区所述计算每个扇区的扇区开关时间,包括:采用下式计算扇区I开关时间至扇区VI开关时间:
    Figure PCTCN2021094665-appb-100003
    Figure PCTCN2021094665-appb-100004
    Figure PCTCN2021094665-appb-100005
    其中,T a、T b、T c分别为对应扇区的三相开关时间,u ref_g为参考电压在gh坐标系下的g轴电压分量,u ref_h为参考电压在gh坐标系下的h轴电压分量,T s为每个功率导通元件的通断所需时间,V 0_r为零序参考电压,V dc为逆变器电路中的直流侧电容电压;i sa、i sb、i sc分别为三相滤波电感所在支路的电流,且i sa、i sb、i sc均以指向逆变器方向为正。
  6. 根据权利要求1所述的方法,其特征在于,所述获取电网中的待补偿谐波电流与待补偿谐波电压,包括:采用下式获取时刻t的三相待补偿谐波电流和时刻t的三相待补偿谐波电压:
    Figure PCTCN2021094665-appb-100006
    其中,
    Figure PCTCN2021094665-appb-100007
    分别为时刻t的三相待补偿谐波电流,i a、i b、i c分别为锁相环在时刻t的三相电流,i a1、i b1、i c1分别为锁相环在时刻t的三相基波正序电流;u ac、u bc、u cc分别为时刻t的三相待补偿谐波电压,
    Figure PCTCN2021094665-appb-100008
    分别为电网中电压在时刻t的三相正序分量,u a、u b、u c分别为电网中时刻t的三相电源电压。
  7. 根据权利要求6所述的方法,其特征在于,所述i a1、i b1、i c1分别为锁相环在时刻t的三相基波正序电流,包括:
    Figure PCTCN2021094665-appb-100009
    其中,i a1P、i b1P、i c1P分别为时刻t的三相基波正序有功电流分量,i a1Q、i b1Q、i c1Q分别为时刻t的三相基波正序无功电流分量,G P为锁相环在时刻t的三相有功电导分量经过低通滤波后得到的有功电导直流分量,G Q为锁相环在时刻t的三相无功电导分量经过低通滤波后得到的无功电导直流分量,e a、e b、e c分别为锁相环在时刻t的三相参考电压,I 1amp为锁相环的正序电流幅值,
    Figure PCTCN2021094665-appb-100010
    为锁相环a相电压与基波正序电流夹角,ω为电网的角频率,ωt为电网在时刻t的相角变化。
  8. 根据权利要求7所述的方法,其特征在于,所述根据所述谐波电流调节结果和所述谐波电压调节结果,确定电网中电能质量的目标等级,包括:对所述谐波电流调节结果和所述谐波电压调节结果进行傅里叶变换处理,得到电网侧电流和电压的总谐波畸变率;
    判断所述总谐波畸变率是否满足预设畸变率阈值;
    如果满足,则根据所述总谐波畸变率确定对应的目标等级;
    如果不满足,则将t+lΔt作为新的t,将l+1作为新的l,继续执行所述计算电网侧电流和电压的总谐波畸变率的步骤;直至得到所述目标等级;其中,l的取值为大于等于0的整数,l=0、1、2、3、……,l为重新计算总谐波畸变率的次数且初值为0,Δt为预先设定的时间间隔。
  9. 根据权利要求8所述的方法,其特征在于,所述计算电网侧电流和电压的总谐波畸变率,包括采用下式得到的电流谐波畸变率和电压谐波畸变率:
    Figure PCTCN2021094665-appb-100011
    其中,THD I为电流谐波畸变率,I k为第k次谐波电流有效值,I 1为基波电流有效值,THD U为电压谐波畸变率,U k为第k次谐波电压有效值,U 1为基波电压有效值。
  10. 一种电网中的电能质量等级确定装置,其特征在于,所述装置包括:
    获取模块,用于获取电网中的待补偿谐波电流与待补偿谐波电压;
    第一调节模块,用于根据所述待补偿谐波电流与实际补偿电流的电流比较结果,对所述待补偿谐波电流进行电流调节处理,得到谐波电流调节结果;其中,所述实际补偿电流包括电流调节逆变器的实际输出电流;
    第二调节模块,用于根据所述待补偿谐波电压与预先获取的目标开关时间,对所述待补偿谐波电压进行电压调节处理,得到谐波电压调节结果;其中,所述目标开关时间包括控制有源滤波器中多组功率导通元件开关和闭合的时间;
    确定模块,用于根据所述谐波电流调节结果和所述谐波电压调节结果,确定电网中电能质量的目标等级。
  11. 一种计算机设备,包括存储器和处理器,所述存储器存储有计算机程序,其特征在于,所述处理器执行所述计算机程序时实现权利要求1至9中任一项所述的方法的步骤。
  12. 一种计算机可读存储介质,其上存储有计算机程序,其特征在于,所述计算机程序被处理器执行时实现权利要求1至9中任一项所述的方法的步骤。
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