WO2021232601A1 - 一种复合型串联数字功放 - Google Patents

一种复合型串联数字功放 Download PDF

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WO2021232601A1
WO2021232601A1 PCT/CN2020/110401 CN2020110401W WO2021232601A1 WO 2021232601 A1 WO2021232601 A1 WO 2021232601A1 CN 2020110401 W CN2020110401 W CN 2020110401W WO 2021232601 A1 WO2021232601 A1 WO 2021232601A1
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stage
output
module
voltage
resistor
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PCT/CN2020/110401
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French (fr)
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张金路
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张金路
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F3/217—Class D power amplifiers; Switching amplifiers
    • H03F3/2171—Class D power amplifiers; Switching amplifiers with field-effect devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • the invention relates to the technical field of digital power amplifiers, in particular to a composite series digital power amplifier suitable for high-voltage and high-power systems.
  • the current Class D digital power amplifier is composed of half-bridge MOS or full-bridge MOS plus a control circuit, but there are the following defects or difficulties in high-voltage and high-power digital power amplifiers:
  • the switching loss of the high-voltage circuit is large.
  • the MOS device selected for the Class D digital power amplifier has a characteristic, the higher the voltage, the worse the performance, which is reflected in two aspects. 1.
  • the higher the withstand voltage the worse the characteristics of the parasitic diode.
  • Even a specially designed high-voltage MOS cannot adapt to high-frequency operation and requires the use of complex circuits or the use of expensive silicon carbide devices.
  • the switching loss is proportional to the square of the operating voltage. For example, when the voltage increases ten times, the loss increases one hundred times.
  • the operating frequency of the circuit is inversely proportional to the voltage, which means that the low-voltage circuit can easily work at high frequencies.
  • the present invention provides a technical solution for a composite series digital power amplifier.
  • a composite series digital power amplifier including a front-end module and a back-end module, the front-end module and the back-end module are connected in series;
  • the front-end module uses high-voltage power supply, high-voltage switching devices and control loops. In order to reduce switching losses, it can work at a lower frequency and provide high-voltage and high-power output, but it does not require high-precision detailed control capabilities, and its dynamic characteristics can be poor. , The output ripple is large;
  • the back-end modules including floating low-voltage power supplies, low-voltage switching devices and control loops, work at a high switching frequency, with small output ripple and fine output voltage control. At the same time, they can be designed as soft switching and avoid dead zone effects. The characteristics enable the overall circuit to meet high power while achieving extremely high performance in terms of distortion and other indicators, and at the same time increase the cost very low.
  • the preceding module provides the main power output of the entire circuit, including the preceding voltage feedback unit, the preceding current loop and the PWM generating unit, the MOS driving module, the preceding switching unit, and the preceding LC unit which are connected in sequence;
  • the downstream modules include floating power supply, downstream MOS drive module, downstream voltage feedback unit, downstream current loop and PWM generating unit, downstream switching unit and downstream LC unit.
  • the floating power supply is connected to the downstream switching unit, and the downstream voltage
  • the feedback unit, the subsequent current loop and the PWM generation unit and the subsequent MOS drive module are connected in turn, the subsequent MOS drive module drives the subsequent switch unit;
  • the midpoint of the floating power supply is based on the previous output voltage VC, and the previous L3 output penetrates the latter
  • the capacitance of the MOS tube and the subsequent floating power supply acts on C5, the VC voltage is fed back to the previous stage voltage feedback unit, and the current is fed back to the previous stage current loop and PWM generating unit;
  • the output voltage VOUT voltage is fed back to the subsequent stage voltage feedback unit, and the current is fed back to The back-end current loop and PWM generation unit;
  • the front-end module maintains VC to track the output voltage VOUT.
  • the pre-stage voltage feedback unit includes an operational amplifier U1, a resistor R3, a resistor R2, a resistor R1, and a capacitor C2.
  • the audio signal is connected to the negative input terminal of the operational amplifier U1 through the resistor R1, and the negative input terminal and the output terminal are different from each other.
  • the negative input terminal of the operational amplifier U1 is connected to the VC terminal of the subsequent module through the parallel resistor R2, resistor R3 and capacitor C2.
  • the previous-stage current loop and PWM generation unit includes a comparator U2, a resistor R4, and a resistor R5.
  • the output terminal of the operational amplifier U1 is connected to the positive input terminal of the comparator U2 through a resistor R4,
  • the positive input terminal of the comparator U2 is connected to the output terminal of the comparator U2 through the resistor R5, and the output terminal of the comparator U2 is connected to the MOS drive module.
  • the LC unit includes an inductor L3 and a capacitor C5.
  • the common terminal of the MOS tube M5 and the MOS tube M6 is connected to the inductor L3.
  • the output terminal of the inductor L3 is connected to the MID terminal of the rear module.
  • the output of the front L3 penetrates the rear MOS tube and the rear
  • the capacitance of the floating power supply acts on C5.
  • the output terminal VC of the preceding module is connected to the floating power supply, and is connected to the positive and negative ends of the power supply V2 through the parallel capacitor C3, the resistor R7, and the parallel capacitor C4, and the resistor R9 respectively; both ends of the power supply V2 are connected
  • the post-switch unit, the post-voltage feedback unit includes operational amplifier U3, resistor R6, resistor R10, resistor R11, capacitor C7, and capacitor C6.
  • the negative input of operational amplifier U3 is connected to signal input terminal VIN through resistor R6, and the operational amplifier U3
  • the negative input terminal is connected to the output terminal of the operational amplifier U3 through a capacitor C6 to form an integrating circuit, the negative input terminal is connected to the signal output terminal VOUT through a parallel resistor R10, a resistor R11, and a capacitor C7, and the positive input terminal of the operational amplifier U3 is grounded;
  • the current loop and PWM generation unit includes a comparator U4, a resistor R12, and a resistor R13.
  • the output terminal of the operational amplifier U3 is connected to the positive input terminal of the comparator U4 through a resistor R12, and the positive input terminal is connected to the output terminal through a resistor R13.
  • the current sampling is fed back to the negative input terminal of the comparator U4.
  • the output terminal of the comparator U4 is connected to the rear-stage MOS driver module, which drives the rear-stage switch unit; the latter-stage switch unit includes the MOS tube M7 and the MOS tube M8.
  • the first-level LC unit includes an inductor L4 and a capacitor C10.
  • the output terminal MID of the previous module is connected to the common terminal of the MOS tube M7 and the MOS tube M8, and is output through the inductor L4, the output terminal is VOUT, and the output terminal VOUT is grounded through the capacitor C10, and the current It is fed back to the negative input terminal of the comparator U4, and the VC terminal serves as the virtual midpoint of the floating power supply.
  • the front-stage module is provided with an output inductor L3, the rear-stage module is provided with an output inductor L4, the rear-stage switch unit is provided with a MOS half-bridge, and the front-stage output inductor L3 is directly connected to the rear-stage switch unit of the latter module.
  • the output voltage of the previous stage is equal to that of the latter stage.
  • the latter power supply does not need to provide power, but only needs to maintain a stable voltage; at the same time, the latter switching unit MOS tube only needs to provide the front and rear inductors L3 and L4.
  • the current difference is very small, and a low-voltage MOS with a relatively small current can be used.
  • the front-stage module is provided with an output inductor L3
  • the subsequent-stage module is provided with an output inductor L4.
  • the current sampling of the front-end module combines the combined currents of the two output capacitors C5 and C10 of the front and rear stages, because the current of the inductor L4 of the later stage also flows through the capacitor C5 of the front-stage, which will affect the inductor L3 of the previous stage.
  • the fluctuating current of the back-stage inductor L4 cancels each other out in the two capacitors C5 and C10, so that the detected fluctuating current is the front-stage inductor, and the control is more stable.
  • the output of the front-level module is used as a reference for the floating power supply of the back-level module
  • the size of the floating power supply LV+ is the superposition of one-half of the output of the front-level module and the V1 power supply
  • the size of the floating power supply LV- is the front-level module
  • the difference between the output and the V1 power supply is one-half, and the floating power supplies LV+ and LV- provide power for the subsequent MOS. In fact, it does not consume power in theory, but mainly maintains the voltage.
  • the floating power supply adopts a switch-type neutral point balance circuit, and the downstream module uses a low-voltage power supply, and the control loop switch unit uses a low-voltage MOS tube.
  • the pre-stage frequency can be reduced to 1/2 or 1/3, and the switching loss is proportional to the frequency, which is correspondingly reduced by that much.
  • the switching loss occupies most of the digital power amplifier, which means that the pre-stage power amplifier is greatly reduced. The loss.
  • the switching loss at the same frequency is mainly related to the square of the voltage.
  • the MOS current of the latter stage only provides the fluctuation of the current difference between the front and rear stages. Therefore, the latter low-voltage MOS can choose a much smaller current tube to achieve very low loss and cost. very low.
  • the latter circuit is the extra part, because its cost and loss account for a very small proportion in the high-power circuit, it can greatly improve the performance.
  • the frequency of the front stage is reduced, and cheap ordinary and fewer MOS transistors can be used.
  • the front stage greatly reduces the cost of high-voltage MOS, and the later stage increases the cost by a small amount, and the total cost can be greatly reduced.
  • Figure 1 is a connection block diagram of Embodiment 1 of the present invention.
  • Figure 2 is an output curve diagram of the present invention
  • 1-previous module 2-previous voltage feedback unit; 3-previous current loop and PWM generating unit; 4-MOS drive module; 5-previous switching unit; 6-post module; 7-floating power supply 8-post-MOS drive module; 9-post-level voltage feedback unit; 10-post-level current loop and PWM generating unit; 11-post-level switch unit; 12-pre-level LC unit; 13-post-level LC unit.
  • a composite series digital power amplifier includes a front-end module and a back-end module, and the front-end module and the back-end module are connected in series.
  • the front-end module high-voltage power supply, is the same as the traditional digital power amplifier.
  • the operating frequency can be adjusted several times lower than that of the traditional power amplifier. It can provide high-voltage and high-power output. high frequency.
  • the latter module includes a floating low-voltage power supply and a control loop.
  • the floating low-voltage power supply supplies power to the control loop.
  • the gain of the control loop is the same as that of the previous module, but the dynamic characteristics are much higher than that of the previous module.
  • the digital switching circuit is mainly considered here, and the analog power amplifier structure is also an optional structure, and current-type control is recommended. Working under low pressure, it can be ten times the frequency of the previous stage, and the existence of the previous stage does not affect the independent loop control characteristics of the latter stage. While using high frequency control, the loss is greatly reduced.
  • the output of the front module is used as the reference for the floating power supply of the rear module.
  • the size of the floating power supply LV+ is the superposition of the front module output and the V1 power supply
  • the size of the floating power supply LV- is the front module.
  • the difference between the output and the V1 power supply is one-half.
  • Floating power supplies LV+ and LV- provide power for the control loop.
  • the front-end module which is the same as the traditional digital power amplifier, provides the main power output of the entire circuit, allowing the use of lower frequency operation to reduce switching losses.
  • the output ripple voltage of this stage can be relatively large, the dynamic performance can also be relatively poor, pay more attention to the efficiency of the circuit.
  • the downstream module uses a floating low-voltage positive and negative power supply, such as 1/10 of the main circuit voltage.
  • the actual power consumption of this power supply is very small and only provides the power lost in the downstream.
  • the output current will cause the unilateral capacitor to boost, so a switch-type midpoint balance circuit is used, and then a small floating single-channel power supply is provided.
  • This switch type midpoint balance circuit can work at about 200KHZ, for example. Because the latter module uses low-voltage power supply, low-voltage MOS is selected. The performance is very high, and the parasitic diode characteristics are also very good.
  • the dynamic performance of the circuit is directly proportional to the operating frequency. Therefore, the dynamic performance of this circuit can reach more than ten times that of the traditional digital power amplifier, that is, the working bandwidth is increased ten times.
  • the selection of the output LC components of the downstream module is also very easy, because the power supply of the downstream module is very low, the power of the inductor is actually very small, and the capacitor can be equivalent to the traditional power amplifier, because the frequency is increased by ten times, and the output ripple can be reduced by ten times. , The tracking ability and fineness of the audio signal have been improved by an order of magnitude.
  • the digital power amplifier includes a front-end module 1 and a back-end module 2.
  • the front-stage module 1 includes a front-stage voltage feedback unit 2, a previous-stage current loop and PWM generation unit 3, a MOS drive module 4, a previous-stage switch unit 5 and a previous-stage LC unit 12, a previous-stage voltage feedback unit 2 and a previous-stage current loop
  • the PWM generation unit 3 constitutes a previous-stage loop control circuit, and the previous-stage current loop and the PWM generation unit 3 have a current feedback function.
  • the front-stage voltage feedback unit 2 includes an operational amplifier U1, a resistor R3, a resistor R2, a resistor R1, and a capacitor C2.
  • the audio signal is connected to the negative input terminal of the operational amplifier U1 through the resistor R1, and a capacitor C1 is arranged between the negative input terminal and the output terminal.
  • An integral circuit is formed.
  • the negative input terminal of the operational amplifier U1 is connected to the VC terminal of the subsequent module 2 through the parallel resistor R2, the resistor R3 and the capacitor C2.
  • the VC terminal is grounded through the capacitor C5, and the combined current sampling of the capacitor C5 and the capacitor C10 is fed back to The negative input terminal of comparator U2.
  • the front-stage current loop and PWM generation unit 3 includes a comparator U2, a resistor R4, and a resistor R5.
  • the output terminal of the operational amplifier U1 is connected to the positive input terminal of the comparator U2 through a resistor R4, and the positive input terminal of the comparator U2 is connected through a resistor R5 for comparison.
  • the output terminal of the comparator U2, the output terminal of the comparator U2 is connected to the MOS driver module 4, the MOS driver module 4 drives the front-stage switch unit 5, the front-stage switch unit 5 includes a MOS tube M5 and a MOS tube M6, and the front-stage LC unit 12 includes an inductor L3 and Capacitor C5, the output terminal VC of the previous module 1 is grounded through the capacitor C5, the common terminal of the MOS tube M5 and the MOS tube M6 is connected to the inductor L3, and the output terminal of the inductor L3 is connected to the MID terminal of the subsequent module 6.
  • the back-end module 6 is shown in Figure 1, including a floating power supply 7, a back-stage MOS drive module 8, a back-stage voltage feedback unit 9, a back-stage current loop and PWM generation unit 10, a back-stage switch unit 11, and a back-stage LC unit 13 ,
  • the latter-stage voltage feedback unit 9 and the latter-stage current loop and PWM generation unit 10 constitute a latter-stage loop control circuit, and the latter-stage current loop and the PWM generation unit 10 have a current feedback function.
  • the output terminal VC of the front-end module 1 is connected to the floating power supply 7, and is connected to the positive and negative ends of the power supply V2 through the parallel capacitor C3, the resistor R7, and the parallel capacitor C4 and the resistor R9.
  • the center reference of the floating power source 7 is with the previous module 1 output VC. Both ends of the power supply V2 are connected to the post-switching unit 11.
  • the post-preprocessing unit 9 includes an operational amplifier U3, a resistor R6, a resistor R10, a resistor R11, a capacitor C7, and a capacitor C6.
  • the negative input of the operational amplifier U3 is connected to a signal through a resistor R6
  • the negative input terminal of the operational amplifier U3 is connected to the output terminal of the operational amplifier U3 through a capacitor C6 to form an integrating circuit, and the negative input terminal is connected to the signal output terminal VOUT through a parallel resistor R10, a resistor R11 and a capacitor C7.
  • the positive input terminal of U3 is grounded.
  • the latter-stage current loop and PWM generating unit 10 includes a comparator U4, a resistor R12, and a resistor R13.
  • the output terminal of the operational amplifier U3 is connected to the positive input terminal of the comparator U4 through a resistor R12, and the positive input terminal is connected to the output terminal through a resistor R13.
  • the current sampling of the capacitor C10 is fed back to the negative input terminal of the comparator U4, and the output terminal of the comparator U4 is connected to the subsequent MOS drive module, and the subsequent MOS drive module 8 drives the subsequent switch unit 11.
  • the rear-stage switch unit 11 includes a MOS tube M7 and a MOS tube M8, and the rear-stage LC unit 13 includes L4 and C10.
  • the output terminal MID of the front-stage module 1 is connected to the common terminal of the MOS tube M7 and the MOS tube M8, and outputs through the inductor L4, The output terminal is VOUT, the output terminal VOUT is grounded through the capacitor C10, and the current sampling is fed back to the negative input terminal of the comparator U4.
  • the front-stage voltage feedback unit and the rear-stage voltage feedback unit can be any digital power amplifier control method, and the front-end module maintains VC to track the output voltage VOUT, and other control methods can be used.
  • the front and rear stages are connected in a clever way.
  • the front-end output inductor is not directly connected to the output capacitor, but directly connected to the midpoint of the back-stage MOS half-bridge, so the front-end output voltage is equal to the back-end.
  • the back-end power supply does not need to provide power, but only needs to be stable. Voltage.
  • the rear MOS only needs to provide the current difference between the front and rear inductors L3 and L4. This current value is very small, and a low-voltage MOS with a relatively small current can be selected.
  • the current fluctuations of the inductance L4 of the downstream module 6 can be designed to be greater than the current fluctuations of the inductance L3 of the previous module 2.
  • the downstream switching unit 11MOS tube works under soft switching conditions, and at the same time the influence of the dead zone on the downstream is eliminated, which greatly improves the distortion rate index .
  • a hysteresis control method of output capacitor current is used here.
  • a clever way is also used.
  • the current sampling of the front stage combines the combined current of the two output capacitors C5 and C10 of the front and rear stages, because the current of the inductor L4 of the back stage also flows through the capacitor C5 of the front stage, which will affect the inductance of the front stage.
  • L3 current detection After merging, the fluctuating current of the back-stage inductor L4 cancels each other out in the two capacitors C5 and C10, so that the detected fluctuating current is the front-stage inductor, and the control is more stable.
  • the control method of the front stage Because the front-stage current and the rear-stage current are connected in series, the average value is the same, so the latter-stage current is filtered as the feedforward. Then need to control VOUT roughly at the midpoint of LV+ and LV-. The final result is to ensure that LV+ and LV- always track changes in VOUT.
  • the latter stage can also use the traditional analog power amplifier circuit, which can still get very high efficiency, and at the same time can get the performance of the analog power amplifier.
  • the performance has reached or surpassed the performance of the analog power amplifier, and it is of little significance to use the analog post-stage.
  • V(VC) is the output waveform of the previous stage
  • V(LV+) is the upper rail of the floating low-voltage power supply
  • V(LV-) is the lower rail of the floating low-voltage power supply
  • V(OUT) is the output waveform of the subsequent stage.
  • the pre-stage work is around 250KHZ
  • the post-stage work is around 1.5MHZ.
  • V(VC) is the output characteristic of a digital power amplifier with a single-stage structure. It can be seen that the output waveform of V(OUT) is much better than V(VC).

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Abstract

一种复合型串联数字功放，属于数字功放技术领域。前级模块和后级模块之间串联连接；前级模块，采用高压供电、高压的开关器件和控制环路，为了降低开关损耗可以工作在较低的频率，提供高压大功率的输出，但是不需要细节控制能力，输出纹波较大；后级模块，包括浮动低压电源、低压的开关器件和控制环路，工作在很高的开关频率上，输出纹波很小，输出电压控制精细，使得整体电路满足大功率的同时在失真等指标达到极高性能，本发明能极大的提高数字功放的输出性能。前级频率降低，可以使用便宜的普通和更少的MOS管，前级大幅降低高压MOS成本，后级少量增加成本，总成本可以大幅降低。

Description

一种复合型串联数字功放 技术领域
本发明涉及数字功放技术领域，具体涉及一种适用于高压大功率系统的复合型串联数字功放。
背景技术
当前D类数字功放由半桥MOS或全桥MOS加控制电路构成，但是在高压大功率数字功放中存在以下缺陷或难点：
1.为了提升音质，电路开关频率越高越好，但是频率越高电路的损耗越大，一般取为400K-1000K之间，如果提升到更高频率会有更好的音质。实际现有产品在功耗和音质上做了权衡。
2.高压电路的开关损耗大。D类数字功放在选用的MOS器件有个特点，电压越高性能越差，体现在两个个方面。一，耐压越高，寄生二极管特性越差，即便是专门设计的高压MOS也无法适应高频率工作，需要使用复杂的电路或者使用昂贵的碳化硅器件。二，开关损耗跟工作电压的平方成正比，比如电压增加十倍，损耗是增加一百倍。越是大功率的功放，越是要高压MOS，这就有个不可调和的矛盾，使得大功率时频率难以提高，对音质造成影响。
3.同样的DV/DT，电路的工作频率与电压成反比，也就是说低压电路能轻松的工作在高频上。
4，高压电路无法实现高频的同时，输出高频纹波较大，电压控制的动态特性和精细度不够。
现有电路没有办法实现大功率的同时，保证音频的质量。
发明内容
针对现有技术的不足，本发明提供了一种复合型串联数字功放的技术方案。
一种复合型串联数字功放，包括前级模块和后级模块，前级模块和后级模块之间串联连接；
前级模块，采用高压供电、高压的开关器件和控制环路，为了降低开关损耗可以工作在较低的频率，提供高压大功率的输出，但是不需要高精度细节控制能力,动态特性可以较差，输出纹波较大；
后级模块，包括浮动低压电源、低压的开关器件和控制环路，工作在很高的开关频率上，输 出纹波很小，输出电压控制精细，同时可以设计成软开关并且避免死区影响的特性，使得整体电路满足大功率的同时在失真等指标达到极高性能，同时增加成本很低。
进一步的，所述的前级模块提供整个电路的主要功率输出，包括依次连接的前级电压反馈单元、前级电流环及PWM生成单元、MOS驱动模块、前级开关单元和前级LC单元；后级模块包括浮动电源、后级MOS驱动模块、后级电压反馈单元、后级电流环及PWM生成单元、后级开关单元和后级LC单元，浮动电源与后级开关单元连接，后级电压反馈单元、后级电流环及PWM生成单元和后级MOS驱动模块依次连接，后级MOS驱动模块驱动后级开关单元；浮动电源中点基于前级输出电压VC，前级L3输出穿透后级MOS管和后级浮动电源的电容作用于C5，VC电压反馈至前级电压反馈单元，电流反馈至前级电流环及PWM生成单元；输出电压VOUT电压反馈至后级电压反馈单元，电流反馈至后级电流环及PWM生成单元；前级模块维持VC对输出电压VOUT的跟踪。
进一步的，所述的前级电压反馈单元包括运算放大器U1、电阻R3、电阻R2、电阻R1和电容C2，音频信号经过电阻R1与运算放大器U1的负输入端连接，负输入端与输出端之间设有电容C1形成积分电路，同时运算放大器U1的负输入端通过并联的电阻R2、电阻R3和电容C2连接后级模块的VC端，VC端通过电容C5接地，电容C5和电容C10合并电流采样反馈至比较器U2的负输入端；所述前级电流环及PWM生成单元包括比较器U2、电阻R4和电阻R5，运算放大器U1的输出端通过电阻R4连接比较器U2的正输入端，比较器U2的正输入端通过电阻R5连接比较器U2输出端，比较器U2输出端连接MOS驱动模块，MOS驱动模块驱动前级开关单元，前级开关单元包括MOS管M5和MOS管M6，前级LC单元包括电感L3和电容C5，MOS管M5和MOS管M6的公共端连接电感L3，电感L3的输出端与后级模块的MID端连接，前级L3输出穿透后级MOS管和后级浮动电源的电容作用于C5。
进一步的，所述的前级模块的输出端VC连接浮动电源，并分别通过并联的电容C3、电阻R7和并联的电容C4、电阻R9连接电源V2的正和负两端；电源V2的两端连接后级开关单元，后级电压反馈单元包括运算放大器U3、电阻R6、电阻R10、电阻R11、电容C7和电容C6，运算放大器U3的负输入端通过电阻R6连接信号输入端VIN，运算放大器U3的负输入端通过电容C6连接运算放大器U3的输出端形成积分电路，负输入端通过并联的电阻R10、电阻R11和电容C7连接信号的输出端VOUT，运算放大器U3的正输入端接地；所述后级电流环及PWM生成单元包括比较器U4、电阻R12和电阻R13，运算放大器U3的输出端通过电阻R12连接比较器U4的正输入端，且正输入端通过电阻R13连接输 出端，电容C10的电流采样反馈至比较器U4的负输入端，比较器U4的输出端连接后级MOS驱动模块，后级MOS驱动模块驱动后级开关单元；后级开关单元包括MOS管M7和MOS管M8,后级LC单元包括电感L4和电容C10，前级模块的输出端MID连接MOS管M7和MOS管M8的公共端，并通过电感L4输出，输出端为VOUT，输出端VOUT通过电容C10接地，并且电流反馈至比较器U4的负输入端，VC端作为浮动电源的虚拟中点。
进一步的，所述的前级模块设有输出电感L3，后级模块设有输出电感L4，后级开关单元设有MOS半桥，前级输出电感L3直接连接到后级模块的后级开关单元MOS半桥中点上，因而前级输出电压与后级相等，原理上后级电源不需要提供功率，只需要维持稳定的电压；同时后级开关单元MOS管只需要提供前后级电感L3和L4电流差值，这个电流值非常小，可以选用比较小电流的低压MOS。
进一步的，所述的前级模块设有输出电感L3，后级模块设有输出电感L4，当设计成后级模块的电感L4电流波动大于前级模块电感L3电流波动，后级开关单元MOS管工作在软开关条件下，同时死区对后级的影响消除，大大提高失真率指标。
进一步的，所述的前级模块的电流采样合并了前后级两个输出电容C5和C10合并的电流，因为后级的电感L4电流也流过前级的电容C5，会影响前级的电感L3电流检测，合并后，后级电感L4波动电流在两个电容C5和C10里互相抵消，使得检测波动电流就是前级电感的，控制更为平稳。
进一步的，所述的前级模块的输出作为后级模块浮动电源的基准，浮动电源LV+的大小为前级模块输出与V1电源二分之一的叠加，浮动电源LV-的大小为前级模块输出与V1电源二分之一的差值，浮动电源LV+和LV-为后级MOS供电。实际不理论上不消耗功率，主要是维持电压。
进一步的，所述的浮动电源采用开关式中点平衡电路，后级模块因为使用低压供电，控制环路开关单元选用低压MOS管。
前级损耗计算。前级频率可以降低到1/2或1/3，开关损耗跟频率成正比，也就相应的降低这么多，而开关损耗在数字功放里占大部分，也就是大幅度减小了前级功放的损耗。
后级损耗计算。同频率下开关损耗主要跟电压的平方相关，同时后级MOS电流只是提供前后级电流差值的波动，所以后级低压MOS可以选小得多电流的管子，就能达到非常低的损耗，成本非常低。总的来说，虽然后级电路是多出来的部分，因为它的成本及损耗在大功率电路中占比非常小，但是能大幅度提升性能。
前级频率降低，可以使用便宜的普通和更少的MOS管，前级大幅降低高压MOS成 本，后级少量增加成本，总成本可以大幅降低。
附图说明
图1为本发明实施例1连接框图；
图2为本发明输出曲线图；
其中：1-前级模块；2-前级电压反馈单元；3-前级电流环及PWM生成单元；4-MOS驱动模块；5-前级开关单元；6-后级模块；7-浮动电源；8-后级MOS驱动模块；9-后级电压反馈单元；10-后级电流环及PWM生成单元；11-后级开关单元；12-前级LC单元；13-后级LC单元。
具体实施方式
下面结合说明书附图对本发明的技术方案作进一步说明。
一种复合型串联数字功放，包括前级模块和后级模块，前级模块和后级模块之间串联连接。
前级模块，高压供电，和传统数字功放大致相同，工作频率可以比传统功放调低几倍，能够提供高压大功率的输出，但是不需要高的动态控制和细节控制能力，也无需工作在超高频。
后级模块，包括浮动低压电源和控制环路，浮动低压电源给控制环路供电，控制环路增益和前级模块相同，但是动态特性远高于前级模块。这里主要考虑数字开关工作电路，模拟功放结构也是可选的结构，推荐使用电流型控制。在低压下工作，可以十倍于前级的频率，并且前级的存在不影响后级独立的环路控制特性。在使用高频控制的同时，大幅减小损耗。
如图1所示，前置模块的输出作为后级模块浮动电源的基准，浮动电源LV+的大小为前置模块输出与V1电源二分之一的叠加，浮动电源LV-的大小为前级模块输出与V1电源二分之一的差值。浮动电源LV+和LV-为控制环路供电。
前级模块，和传统数字功放大致相同，提供整个电路的主要功率输出，允许使用低一些的频率工作来降低开关损耗。此级的输出纹波电压可以比较大，动态性能也可以比较差，更注重电路工作效率方面。
后级模块使用浮动的低压正负电源供电，比如用主电路1/10的电压，这个电源实际消耗功率很小，只提供后级损耗的功率。但是输出电流时会造成单边电容升压，所以使用一个开关式中点平衡电路，然后提供一个小的浮动单路电源。这个开关式中点平衡电路可以工作在比如200KHZ左右。后级模块因为使用低压供电，所以选用低压的MOS，性能非常的 高，而且寄生二极管特性也非常好，可以工作在比传统数字功放高的多的频率上，轻松达到几兆的工作频率，而电路的动态性能跟工作频率是成正比的。所以此电路动态性能可以达到传统数字功放的十倍以上，也就是工作带宽提高十倍。
后级模块的输出LC器件选择上也非常轻松，因为后级供电电压非常低，电感的功率实际非常小，电容可以跟传统功放相当，因为频率提高了十倍，输出纹波可减小十倍，对音频信号的跟踪能力和精细度提高了一个数量级。
具体电路如图1所示，数字功放包括前级模块1和后级模块2。前级模块1包括前级电压反馈单元2、前级电流环及PWM生成单元3、MOS驱动模块4、前级开关单元5和前级LC单元12，前级电压反馈单元2和前级电流环及PWM生成单元3构成前级环路控制电路，同时前级电流环及PWM生成单元3具有电流反馈的功能。前级电压反馈单元2包括运算放大器U1、电阻R3、电阻R2、电阻R1和电容C2，音频信号经过电阻R1与运算放大器U1的负输入端连接，负输入端与输出端之间设有电容C1形成积分电路，同时运算放大器U1的负输入端通过并联的电阻R2、电阻R3和电容C2连接后级模块2的VC端，VC端通过电容C5接地，电容C5和电容C10合并的电流采样反馈至比较器U2的负输入端。前级电流环及PWM生成单元3包括比较器U2、电阻R4和电阻R5，运算放大器U1的输出端通过电阻R4连接比较器U2的正输入端，比较器U2的正输入端通过电阻R5连接比较器U2输出端，比较器U2输出端连接MOS驱动模块4，MOS驱动模块4驱动前级开关单元5，前级开关单元5包括MOS管M5和MOS管M6，前级LC单元12包括电感L3和电容C5，前级模块1的输出端VC通过电容C5接地，MOS管M5和MOS管M6的公共端连接电感L3，电感L3的输出端与后级模块6的MID端连接。
后级模块6如图1所示，包括浮动电源7、后级MOS驱动模块8、后级电压反馈单元9、后级电流环及PWM生成单元10、后级开关单元11和后级LC单元13，后级电压反馈单元9和后级电流环及PWM生成单元10构成后级环路控制电路，同时后级电流环及PWM生成单元10具有电流反馈的功能。前级模块1的输出端VC连接浮动电源7，并分别通过并联的电容C3、电阻R7和并联的电容C4、电阻R9连接电源V2的正和负两端，浮动电源7的中心基准与前级模块1的输出端VC。电源V2的两端连接后级开关单元11，后级预处理单元9包括运算放大器U3、电阻R6、电阻R10、电阻R11、电容C7和电容C6，运算放大器U3的负输入端通过电阻R6连接信号输入端VIN，同时，运算放大器U3的负输入端通过电容C6连接运算放大器U3的输出端形成积分电路，负输入端通过并联的电阻R10、电阻R11和电容C7连接信号的输出端VOUT，运算放大器U3的正输入端接地。所 述后级电流环及PWM生成单元10包括比较器U4、电阻R12和电阻R13，运算放大器U3的输出端通过电阻R12连接比较器U4的正输入端，且正输入端通过电阻R13连接输出端，电容C10的电流采样反馈至比较器U4的负输入端，比较器U4的输出端连接后级MOS驱动模块，后级MOS驱动模块8驱动后级开关单元11。后级开关单元11包括MOS管M7和MOS管M8,后级LC单元13包括L4和C10，前级模块1的输出端MID连接MOS管M7和MOS管M8的公共端，并通过电感L4输出，输出端为VOUT，输出端VOUT通过电容C10接地，并且电流采样反馈至比较器U4的负输入端。
前级电压反馈单元和后级电压反馈单元可以是任何一种数字功放控制方式，前级模块维持VC对输出电压VOUT的跟踪，可以是其他控制方式。
前后级用巧妙的方式连接。前级输出电感不直接连接到输出电容，而是直接连接到后级MOS半桥中点上，因而前级输出电压与后级相等，原理上后级电源不需要提供功率，只需要维持稳定的电压。同时后级MOS只需要提供前后级电感L3和L4电流差值，这个电流值非常小，可以选用比较小电流的低压MOS。
后级模块6的电感L4电流波动可以设计成大于前级模块2电感L3电流波动，后级开关单元11MOS管工作在软开关条件下，同时死区对后级的影响消除，大大提高失真率指标。
这里使用了一种输出电容电流滞环控制方式。也使用了一种巧妙方式，前级的电流采样合并了前后级两个输出电容C5和C10合并的电流，因为后级的电感L4电流也流过前级的电容C5，会影响前级的电感L3电流检测。合并后，后级电感L4波动电流在两个电容C5和C10里互相抵消，使得检测波动电流就是前级电感的，控制更为平稳。
前级的控制方式：因为前级电流和后级电流时串联关系，平均值是相同的，所以使用后级电流滤波后作为前馈。然后需要控制VOUT大致处于LV+和LV-的中点。最后的结果是保证LV+和LV-始终跟踪VOUT的变化。
尽可能的让L4波动范围大于L3，这样后级MOS可以处于软开关，利于工作到极高频率。
后级最好使用电流内环控制模式或相当性能电路，因为前级输出是由比较大的高频纹波，普通数字电源也这样，如果后级电路对这个纹波敏感的话，就会影响后级输出。如果使用电流模式传递函数不包含前级输出电压部分，天然就对前级输出纹波免疫。
后级也可以使用传统模拟功放电路，仍然可以得到很高的效率，同时可以得到模拟功放的性能。不过因为数字式后级频率大幅提高后，性能已经达到或超过模拟功放的性能， 再使用模拟后级意义不大。
VIN输入10KHZ梯形波后的波形，如图2所示。V(VC)为前级输出波形，V(LV+)为浮动低压电源上轨，V(LV-)为浮动低压电源下轨，V(OUT)为后级输出波形。前级工作在250KHZ左右，后级工作在1.5MHZ左右。V(VC)就是单级结构的数字功放的输出特性，可以看出V(OUT)输出波形远好于V(VC)。

Claims (9)

  1. 一种复合型串联数字功放，包括前级模块和后级模块，其特征在于前级模块(1)和后级模块(6)之间串联连接；
    前级模块(1)，采用高压供电、高压的开关器件和控制环路，为了降低开关损耗可以工作在较低的频率，提供高压大功率的输出，但是不需要高精度细节控制能力,动态特性可以较差，输出纹波较大；
    后级模块(6)，包括浮动低压电源、低压的开关器件和控制环路，工作在很高的开关频率上，输出纹波很小，输出电压控制精细，可以设计成软开关并且避免死区影响的特性，使得整体电路满足大功率的同时在失真等指标达到极高性能。
  2. 根据权利要求1所述的一种复合型串联数字功放，其特征在于所述的前级模块(1)提供整个电路的主要功率输出，包括依次连接的前级电压反馈单元(2)、前级电流环及PWM生成单元(3)、MOS驱动模块(4)、前级开关单元(5)和前级LC单元(12)；后级模块(6)包括浮动电源(7)、后级MOS驱动模块(8)、后级电压反馈单元(9)、后级电流环及PWM生成单元(10)、后级开关单元(11)和后级LC单元(13)，浮动电源(7)与后级开关单元(11)连接，后级电压反馈单元(9)、后级电流环及PWM生成单元(10)和后级MOS驱动模块(8)依次连接，后级MOS驱动模块(8)驱动后级开关单元(11)；浮动电源(7)中点基于前级输出电压VC，前级L3输出穿透后级MOS管和后级浮动电源的电容作用于C5，VC电压反馈至前级电压反馈单元(2)，电流反馈至前级电流环及PWM生成单元(3)；输出电压VOUT电压反馈至后级电压反馈单元(9)，电流反馈至后级电流环及PWM生成单元(10)；前级模块(1)维持VC对输出电压VOUT的跟踪。
  3. 根据权利要求2所述的一种复合型串联数字功放，其特征在于所述的前级电压反馈单元(2)包括运算放大器U1、电阻R3、电阻R2、电阻R1和电容C2，音频信号经过电阻R1与运算放大器U1的负输入端连接，负输入端与输出端之间设有电容C1形成积分电路，同时运算放大器U1的负输入端通过并联的电阻R2、电阻R3和电容C2连接后级模块(6)的VC端，VC端通过电容C5接地，电容C5和电容C10合并的电流采样反馈至比较器U2的负输入端；所述前级电流环及PWM生成单元(3)包括比较器U2、电阻R4和电阻R5，运算放大器U1的输出端通过电阻R4连接比较器U2的正输入端，比较器U2的正输入端通过电阻R5连接比较器U2输出端，比较器U2输出端连接MOS驱动模块(4)，MOS驱动模块(4)驱动前级开关单元(5)，前级开关单元(5)包括MOS管M5和MOS管M6，前级LC单元(12)包括电感L3和电容C5，MOS管M5和MOS管M6的公共端连接电感L3，电感L3的输出端与后级模块(6)的MID端连接，前级L3输出穿透后级MOS管和后级浮 动电源的电容作用于C5。
  4. 根据权利要求2所述的一种复合型串联数字功放，其特征在于所述的前级模块(1)的输出端VC连接浮动电源(7)，并分别通过并联的电容C3、电阻R7和并联的电容C4、电阻R9连接电源V2的正和负两端；电源V2的两端连接后级开关单元(11)，后级电压反馈单元(9)包括运算放大器U3、电阻R6、电阻R10、电阻R11、电容C7和电容C6，运算放大器U3的负输入端通过电阻R6连接信号输入端VIN，运算放大器U3的负输入端通过电容C6连接运算放大器U3的输出端形成积分电路，负输入端通过并联的电阻R10、电阻R11和电容C7连接信号的输出端VOUT，运算放大器U3的正输入端接地；所述后级电流环及PWM生成单元(10)包括比较器U4、电阻R12和电阻R13，运算放大器U3的输出端通过电阻R12连接比较器U4的正输入端，且正输入端通过电阻R13连接输出端，电容C10的电流采样反馈至比较器U4的负输入端，比较器U4的输出端连接后级MOS驱动模块，后级MOS驱动模块(8)驱动后级开关单元(11)；后级开关单元(11)包括MOS管M7和MOS管M8,后级LC单元(13)包括电感L4和电容C10，前级模块(1)的输出端MID连接MOS管M7和MOS管M8的公共端，并通过电感L4输出，输出端为VOUT，输出端VOUT通过电容C10接地，并且电流反馈至比较器U4的负输入端，VC端作为浮动电源(7)的虚拟中点。
  5. 根据权利要求2所述的一种复合型串联数字功放，其特征在于所述的前级模块(1)设有输出电感L3，后级模块(6)设有输出电感L4，后级开关单元(11)设有MOS半桥，输出电感L3直接连接到后级模块(6)的后级开关单元(11)MOS半桥中点上，因而前级输出电压与后级相等，原理上后级电源不需要提供功率，只需要维持稳定的电压；同时后级开关单元(11)MOS管只需要提供前后级电感L3和L4电流差值，这个电流值非常小，可以选用比较小电流的低压MOS。
  6. 根据权利要求2所述的一种复合型串联数字功放，其特征在于所述的前级模块(1)设有输出电感L3，后级模块(6)设有输出电感L4，后级模块(6)的电感L4电流波动可以设计成大于前级模块(2)电感L3电流波动，后级开关单元(11)MOS管工作在软开关条件下，同时死区对后级的影响消除，大大提高失真率指标。
  7. 根据权利要求1所述的一种复合型串联数字功放，其特征在于所述的前级模块(1)的电流采样合并了前后级两个输出电容C5和C10合并的电流，因为后级的电感L3电流也流过前级的电容C5，会影响前级的电感电流检测，合并后，后级电感L4波动电流在两个电容C5和C10里互相抵消，使得检测波动电流就是前级电感的，控制更为平稳。
  8. 根据权利要求2-7任一所述的一种复合型串联数字功放，其特征在于所述的前级模块(1)的输出作为后级模块浮动电源的基准，浮动电源(7)LV+的大小为前级模块(1)输出与V1电源二分之一的叠加，浮动电源(7)LV-的大小为前级模块(1)输出与V1电源二分之一的差值，浮动电源(7)LV+和LV-为后级MOS供电，实际不理论上不消耗功率，主要是维持电压。
  9. 根据权利要求2-7任一所述的一种复合型串联数字功放，其特征在于所述的浮动电源(7)采用开关式中点平衡电路，后级模块因为使用低压供电，控制环路开关单元选用低压MOS管。
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