WO2021227109A1 - 液晶显示面板 - Google Patents

液晶显示面板 Download PDF

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Publication number
WO2021227109A1
WO2021227109A1 PCT/CN2020/091322 CN2020091322W WO2021227109A1 WO 2021227109 A1 WO2021227109 A1 WO 2021227109A1 CN 2020091322 W CN2020091322 W CN 2020091322W WO 2021227109 A1 WO2021227109 A1 WO 2021227109A1
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WO
WIPO (PCT)
Prior art keywords
low
voltage signal
auxiliary
auxiliary wiring
signal line
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PCT/CN2020/091322
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English (en)
French (fr)
Inventor
于喆
彭邦银
金一坤
Original Assignee
深圳市华星光电半导体显示技术有限公司
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Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Priority to US16/770,966 priority Critical patent/US11435633B2/en
Publication of WO2021227109A1 publication Critical patent/WO2021227109A1/zh

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509—Filters, e.g. light shielding masks
    • G02F1/133514—Colour filters

Definitions

  • This application relates to the field of display technology, and specifically to a liquid crystal display panel.
  • the purpose of the embodiments of the present application is to provide a liquid crystal display panel, which can reduce the resistance of the low voltage region, thereby achieving the beneficial effect of reducing the RC delay.
  • An embodiment of the present application provides a liquid crystal display panel, including:
  • a color filter substrate, at least one first auxiliary wiring is provided on the lower surface of the color filter substrate;
  • the array substrate has a low-voltage area provided on its upper surface, and the low-voltage area is provided with a plurality of low-voltage signal lines;
  • each of the connecting metal pairs includes two connecting metals, and the two connecting metals are arranged between the color filter substrate and the array substrate to connect the low voltage signal line Two ends are electrically connected to two ends of the first auxiliary wiring;
  • the number of the first auxiliary wiring is multiple;
  • the number of the connecting metal pairs is the same as the number of the first auxiliary wiring and corresponds to each other one to one;
  • the two connecting metals of each of the connecting metal pairs respectively electrically connect a first auxiliary trace to the two ends of the corresponding low-voltage signal line, so that each of the first auxiliary traces is connected to the corresponding low-voltage signal line.
  • the voltage signal lines are connected in parallel; the connecting metal is a connecting metal ball.
  • each of the first auxiliary wiring and the corresponding low-voltage signal line are directly opposite to each other and have the same shape and size.
  • each of the first auxiliary wirings is partially opposite to the corresponding low-voltage signal line, and the opposite part has the same shape.
  • the number of the first auxiliary wiring is multiple;
  • Part of the low-voltage signal lines in the plurality of low-voltage signal lines are electrically connected to the plurality of first auxiliary wirings in a one-to-one correspondence through a plurality of connecting metal pairs.
  • the plurality of low-voltage signal lines include a plurality of first low-voltage signal lines
  • the at least one first auxiliary wiring includes a plurality of second auxiliary wiring
  • Part or all of the first low-voltage signal lines in the plurality of first low-voltage signal lines are connected in one-to-one correspondence with the plurality of second auxiliary wirings through connecting metal pairs, so that the first low-voltage signal lines
  • the parallel equivalent resistance of the signal line and the corresponding second auxiliary wiring is a constant value.
  • some or all of the second auxiliary wires in the plurality of second auxiliary wires have different widths or lengths.
  • the array substrate includes a substrate, a first metal layer, an insulating layer, and a second metal layer.
  • the first metal layer is disposed on the substrate, and the insulating layer Disposed on the first metal layer, and the second metal layer is disposed on the insulating layer;
  • the second metal layer forms the plurality of low voltage signal lines in the low voltage area
  • the first metal layer forms at least one third auxiliary wiring
  • the insulating layer is provided with at least one pair of conductive metallized holes, each pair of conductive metallized holes includes two conductive metallized holes, and the two conductive metallized holes of each pair of conductive metallized holes have one Two ends of the third auxiliary wiring are electrically connected to two ends of the low voltage signal line.
  • the number of the third auxiliary wiring is multiple;
  • the number of the conductive metallized hole pairs is the same as the number of the third auxiliary wiring and corresponds to one by one;
  • each pair of conductive metallized holes respectively electrically connect a third auxiliary trace to the two ends of the corresponding low-voltage signal line, so that each of the third auxiliary traces is connected to the two ends of the corresponding low-voltage signal line.
  • the embodiment of the present application also provides a liquid crystal display panel, including:
  • a color filter substrate, at least one first auxiliary wiring is provided on the lower surface of the color filter substrate;
  • the array substrate has a low-voltage area provided on its upper surface, and the low-voltage area is provided with a plurality of low-voltage signal lines;
  • each of the connecting metal pairs includes two connecting metals, and the two connecting metals are arranged between the color filter substrate and the array substrate to connect the low voltage signal line The two ends are electrically connected to the two ends of the first auxiliary wiring.
  • auxiliary wirings are connected in parallel at both ends of the low-voltage signal line to reduce the resistance value of the low-voltage signal line, thereby achieving the purpose of reducing the resistance in the low-voltage area, thereby achieving the beneficial effect of reducing the RC delay.
  • the number of the first auxiliary wiring is multiple;
  • the number of the connecting metal pairs is the same as the number of the first auxiliary wiring and corresponds to each other one to one;
  • the two connecting metals of each of the connecting metal pairs respectively electrically connect a first auxiliary trace to the two ends of the corresponding low-voltage signal line, so that each of the first auxiliary traces is connected to the corresponding low-voltage signal line.
  • the voltage signal lines are connected in parallel.
  • each of the first auxiliary wiring and the corresponding low-voltage signal line are directly opposite to each other and have the same shape and size.
  • each of the first auxiliary wirings is partially opposite to the corresponding low-voltage signal line, and the opposite part has the same shape.
  • the number of the first auxiliary wiring is multiple;
  • Part of the low-voltage signal lines in the plurality of low-voltage signal lines are electrically connected to the plurality of first auxiliary wirings in a one-to-one correspondence through a plurality of connecting metal pairs.
  • the plurality of low-voltage signal lines include a plurality of first low-voltage signal lines
  • the at least one first auxiliary wiring includes a plurality of second auxiliary wiring
  • Part or all of the first low-voltage signal lines in the plurality of first low-voltage signal lines are connected in one-to-one correspondence with the plurality of second auxiliary wirings through connecting metal pairs, so that the first low-voltage signal lines
  • the parallel equivalent resistance of the signal line and the corresponding second auxiliary wiring is a constant value.
  • some or all of the second auxiliary wires in the plurality of second auxiliary wires have different widths or lengths.
  • the connecting metal is a connecting metal ball.
  • the array substrate includes a substrate, a first metal layer, an insulating layer, and a second metal layer.
  • the first metal layer is disposed on the substrate, and the insulating layer Disposed on the first metal layer, and the second metal layer is disposed on the insulating layer;
  • the second metal layer forms the plurality of low voltage signal lines in the low voltage area
  • the first metal layer forms at least one third auxiliary wiring
  • the insulating layer is provided with at least one pair of conductive metallized holes, each pair of conductive metallized holes includes two conductive metallized holes, and the two conductive metallized holes of each pair of conductive metallized holes have one Two ends of the third auxiliary wiring are electrically connected to two ends of the low voltage signal line.
  • the number of the third auxiliary wiring is multiple;
  • the number of the conductive metallized hole pairs is the same as the number of the third auxiliary wiring and corresponds to one by one;
  • each pair of conductive metallized holes respectively electrically connect a third auxiliary trace to the two ends of the corresponding low-voltage signal line, so that each of the third auxiliary traces is connected to the two ends of the corresponding low-voltage signal line.
  • auxiliary wirings are connected in parallel at both ends of the low-voltage signal line to reduce the resistance value of the low-voltage signal line, thereby achieving the purpose of reducing the resistance in the low-voltage area, thereby achieving the beneficial effect of reducing the RC delay.
  • FIG. 1 is a schematic diagram of the first structure of a liquid crystal display panel provided by an embodiment of the application.
  • FIG. 2 is a schematic diagram of a second structure of a liquid crystal display panel provided by an embodiment of the application.
  • FIG. 3 is a schematic diagram of a third structure of a liquid crystal display panel provided by an embodiment of the application.
  • FIG. 4 is a schematic diagram of a fourth structure of a liquid crystal display panel provided by an embodiment of the application.
  • the liquid crystal display panel includes an array substrate 10, a color filter substrate 20, a liquid crystal molecular layer 40 sandwiched between the array substrate 10 and the color filter substrate 20, and at least one connecting metal pair 30.
  • the upper surface of the array substrate 10 is provided with a low voltage area 10a and a high voltage area 10b
  • the high voltage area 10b is provided with a plurality of high voltage signal traces
  • the low voltage area 10a is provided with a plurality of low voltage signal traces 11.
  • At least one first auxiliary wiring 21 is provided on the lower surface of the color filter substrate 20.
  • the connecting metal pair 30 includes two connecting metals 31, and the two connecting metals 31 are arranged between the color filter substrate 20 and the array substrate 10 to connect two ends of the low-voltage signal line 11 to each other.
  • the two ends of the first auxiliary wiring 21 are electrically connected, thereby reducing the resistance of the low-voltage signal line 11 and achieving the effect of reducing the RC delay.
  • the connecting metal 31 is a connecting metal ball.
  • the low voltage area 10a is located in the non-display area of the array substrate 10.
  • the array substrate 10 is also provided with other TFT array driving structures, which are prior art and need not be described too much.
  • the color film substrate 20 is also provided with other optical functional layers, which belong to the prior art and need not be described too much.
  • the liquid crystal molecule layer 40 can adopt existing commonly used liquid crystal molecules, which belong to the prior art and need not be described too much.
  • the first auxiliary wiring 21 may be formed of ITO metal, and the ITO metal layer formed on the lower surface of the color filter substrate may be formed by using a photomask process to form the first auxiliary traces corresponding to the low-voltage signal lines 11 on the array substrate.
  • An auxiliary wiring 21 may be formed of ITO metal, and the ITO metal layer formed on the lower surface of the color filter substrate may be formed by using a photomask process to form the first auxiliary traces corresponding to the low-voltage signal lines 11 on the array substrate.
  • the number of the first auxiliary wiring 21 is multiple; the number of the connecting metal pairs 30 is the same as the number of the first auxiliary wiring 21 and corresponds to each other; Two connecting metals 31 respectively electrically connect a first auxiliary wiring 21 to the two ends of the corresponding low-voltage signal line 11, so that each of the first auxiliary wiring 21 is connected to the corresponding low-voltage signal line 11, respectively. in parallel.
  • the number of the first auxiliary wiring 21 is multiple; part of the low-voltage signal lines 11 of the multiple low-voltage signal lines 11 are connected to the multiple first auxiliary wires 30 through multiple connecting metal pairs 30.
  • the auxiliary wires 21 are electrically connected in a one-to-one correspondence. That is, each low-voltage signal line 11 is connected in parallel with a first auxiliary wiring 21, and different low-voltage signal lines 11 are connected in parallel with different first auxiliary wirings 21.
  • the number of the first auxiliary wiring 21 is multiple; part of the low-voltage signal lines 11 among the multiple low-voltage signal lines 11 are connected to the multiple first auxiliary wires through the multiple connecting metal pairs 30.
  • the wires 21 are electrically connected in a one-to-one correspondence. In other words, some low-voltage signal lines 11 have a first auxiliary wiring 21 in parallel, and some low-voltage signal lines 11 do not have a first auxiliary wiring 21 in parallel.
  • each of the first auxiliary wiring 21 and the corresponding low-voltage signal line 11 are directly opposite to each other and have the same shape and size.
  • each of the first auxiliary wirings is partially opposite to the corresponding low-voltage signal line, and the opposite part has the same shape.
  • the plurality of low-voltage signal lines 21 include a plurality of first low-voltage signal lines; the at least one first auxiliary wiring 11 includes a plurality of second auxiliary wirings; for example, the first low-voltage signal
  • the wires are all cathode wires or low-level clock signal wires. Some or all of the first low-voltage signal lines in the plurality of first low-voltage signal lines are respectively connected to the plurality of second auxiliary wirings in a one-to-one correspondence through connecting metal pairs, so that the first low-voltage signal
  • the parallel equivalent resistance of the wire and the corresponding second auxiliary wire is a constant value.
  • the second auxiliary traces can be connected in parallel or not in parallel, and the resistance of the parallel auxiliary traces is based on the fixed value. To set it up. For example, some or all of the second auxiliary wires in the plurality of second auxiliary wires have different widths or lengths.
  • the resistance value of the low-voltage signal line is reduced by using the auxiliary wiring arranged at both ends of the low-voltage signal line in parallel to achieve the purpose of reducing the resistance of the low-voltage area, thereby achieving the beneficial effect of reducing the RC delay.
  • the array substrate includes a substrate 101, a first metal layer 102, an insulating layer 103, and a second metal layer 104.
  • the first metal layer 102 is disposed on the substrate 101, and the insulating layer 103 is disposed on the first metal layer 102, and the second metal layer 104 is disposed on the insulating layer 103.
  • the second metal layer 103 forms the plurality of low voltage signal lines 21 in the low voltage area; the first metal layer 102 forms at least one third auxiliary wiring 1021; the insulating layer is provided with at least one conductive metallized hole Yes, each pair of conductive metallized holes includes two conductive metallized holes 1031, and the two conductive metallized holes 1031 of each pair of conductive metallized holes connect both ends of a third auxiliary trace 1021 It is electrically connected to both ends of the low-voltage signal line 21.
  • the number of the third auxiliary wiring 1021 is multiple; the number of conductive metallized hole pairs 1031 is the same as the number of the third auxiliary wiring 1021 and corresponds to one by one;
  • the two conductive metallized holes 1031 of each pair of conductive metallized holes respectively electrically connect a third auxiliary trace 1021 to the two ends of the corresponding low-voltage signal line 21, so that each of the third auxiliary traces respectively It is connected in parallel with the corresponding low-voltage signal line 21.
  • the equivalent resistances of each low-voltage signal line 21 and its parallel third auxiliary wiring 1021 and the first auxiliary wiring are the same. Therefore, in order to achieve the same equivalent resistance, it is necessary to The resistance of the third auxiliary wiring 1021 and the resistance of the first auxiliary wiring are designed in combination with the resistance of the low-voltage signal line 21, so as to achieve the same equivalent resistance.
  • the number of the third auxiliary wiring 1021 is less than the number of the low-voltage signal line 21, that is, only a part of the low-voltage signal wiring 21 of the plurality of low-voltage signal wirings 21 21 is connected with a third auxiliary wiring 1021 in parallel.
  • some of the low-voltage signal lines 21 of the plurality of low-voltage signal lines 21 correspond one-to-one with the plurality of first auxiliary traces on the lower surface of the color filter substrate 20, and the plurality of low-voltage signal lines 21
  • the other parts of the low voltage signal lines 21 in the voltage signal line 21 correspond to a plurality of third auxiliary wirings 1021 formed by the first metal layer in a one-to-one correspondence, so that each low voltage signal line 21 is connected in parallel with an auxiliary wiring.
  • the low-voltage signal lines 21 provided with the first auxiliary wiring on the color filter substrate 20 and the low-voltage signal lines 21 provided with the third auxiliary wiring on the first metal layer are sequentially spaced apart. Therefore, by separately distributing the auxiliary wires on the lower surface of the color filter substrate and the first metal layer of the array substrate, the separation distance between the auxiliary wires can be reduced, and the beneficial effect of reducing interference can be achieved.
  • the resistance value of the low-voltage signal line is reduced by using the auxiliary wiring arranged at both ends of the low-voltage signal line in parallel to achieve the purpose of reducing the resistance of the low-voltage area, thereby achieving the beneficial effect of reducing the RC delay.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种液晶显示面板，包括：彩膜基板(20)，其下表面设置有至少一条第一辅助走线(21)；阵列基板(10)，其上表面设置有低电压区(10a)，低电压区(10a)设置有多条低电压信号线(11)；至少一个连接金属对(30)，每一连接金属对(30)包括两个连接金属(31)，两个连接金属(31)设置于彩膜基板(20)与阵列基板(10)之间，以将一低电压信号线(11)的两端与一第一辅助走线(21)的两端电连接。

Description

液晶显示面板 技术领域
本申请涉及显示技术领域，具体而言，涉及一种液晶显示面板。
 背景技术
在8K TFT-LCD液晶显示面板中，由于尺寸大，信号线路多且长度较大，使得信号线路的负载过大。在LOC时低电压区的电阻过大，会导致面内RC延迟严重，影响显示面板的显示质量。
因此，现有技术存在缺陷，急需改进。
 技术问题
本申请实施例的目的在于提供一种液晶显示面板，具有降低低电压区的电阻，从而达到降低RC延迟的有益效果。
 技术解决方案
本申请实施例提供了一种液晶显示面板，包括：
彩膜基板，其下表面设置有至少一条第一辅助走线；
阵列基板，其上表面设置有低电压区，所述低电压区设置有多条低电压信号线；
至少一个连接金属对，每一所述连接金属对包括两个连接金属，所述两个连接金属设置于所述彩膜基板与所述阵列基板之间，以将一所述低电压信号线的两端与一所述第一辅助走线的两端电连接；
所述第一辅助走线的数量为多条；
所述连接金属对的数量与所述第一辅助走线的数量相同并一一对应；
每一所述连接金属对的两个连接金属分别将一第一辅助走线与对应的低电压信号线的两端电连接，从而使得每一所述第一辅助走线分别与对应所述低电压信号线并联；所述连接金属为连接金属球。
在本申请实施例所述的液晶显示面板中，每一所述第一辅助走线与对应的低电压信号线相互正对且形状及尺寸相同。
在本申请实施例所述的液晶显示面板中，每一所述第一辅助走线与对应的低电压信号线局部相对，且相对的部分形状相同。
在本申请实施例所述的液晶显示面板中，所述第一辅助走线的数量为多条；
所述多条低电压信号线中的部分低电压信号线通过多个连接金属对与多条第一辅助走线一一对应地电连接。
在本申请实施例所述的液晶显示面板中，所述多条低电压信号线包括多条第一低电压信号线；
所述至少一条第一辅助走线包括多条第二辅助走线；
所述多条第一低电压信号线中的部分或全部第一低电压信号线分别通过连接金属对与所述多条第二辅助走线一一对应地连接，从而使得所述第一低电压信号线与对应第二辅助走线的并联等效电阻为定值。
在本申请实施例所述的液晶显示面板中，所述多条第二辅助走线中的部分或全部第二辅助走线具有不同的宽度或者长度。
在本申请实施例所述的液晶显示面板中，所述阵列基板包括基板、第一金属层、绝缘层以及第二金属层，所述第一金属层设置于所述基板上，所述绝缘层设置于所述第一金属层上，所述第二金属层设置于所述绝缘层上；
所述第二金属层在所述低电压区形成所述多条低电压信号线；
所述第一金属层形成至少一条第三辅助走线；
所述绝缘层设置有至少一导电金属化孔对，每一所述导电金属化孔对包括两个导电金属化孔，每一所述导电金属化孔对的两个导电金属化孔将一所述第三辅助走线的两端与一所述低电压信号线的两端电连接。
在本申请实施例所述的液晶显示面板中，所述第三辅助走线的数量为多条；
所述导电金属化孔对的数量与所述第三辅助走线的数量相同并一一对应；
每一所述导电金属化孔对的两个导电金属化孔分别将一第三辅助走线与对应的低电压信号线的两端电连接，从而使得每一所述第三辅助走线分别与对应所述低电压信号线并联。
本申请实施例还提供了一种液晶显示面板，包括：
彩膜基板，其下表面设置有至少一条第一辅助走线；
阵列基板，其上表面设置有低电压区，所述低电压区设置有多条低电压信号线；
至少一个连接金属对，每一所述连接金属对包括两个连接金属，所述两个连接金属设置于所述彩膜基板与所述阵列基板之间，以将一所述低电压信号线的两端与一所述第一辅助走线的两端电连接。
本申请实施例通过采用设置在低电压信号线的两端并联辅助走线从而降低其电阻值，达到降低低电压区的电阻的目的，从而达到降低RC延迟的有益效果。
在本申请实施例所述的液晶显示面板中，所述第一辅助走线的数量为多条；
所述连接金属对的数量与所述第一辅助走线的数量相同并一一对应；
每一所述连接金属对的两个连接金属分别将一第一辅助走线与对应的低电压信号线的两端电连接，从而使得每一所述第一辅助走线分别与对应所述低电压信号线并联。
在本申请实施例所述的液晶显示面板中，每一所述第一辅助走线与对应的低电压信号线相互正对且形状及尺寸相同。
在本申请实施例所述的液晶显示面板中，每一所述第一辅助走线与对应的低电压信号线局部相对，且相对的部分形状相同。
在本申请实施例所述的液晶显示面板中，所述第一辅助走线的数量为多条；
所述多条低电压信号线中的部分低电压信号线通过多个连接金属对与多条第一辅助走线一一对应地电连接。
在本申请实施例所述的液晶显示面板中，所述多条低电压信号线包括多条第一低电压信号线；
所述至少一条第一辅助走线包括多条第二辅助走线；
所述多条第一低电压信号线中的部分或全部第一低电压信号线分别通过连接金属对与所述多条第二辅助走线一一对应地连接，从而使得所述第一低电压信号线与对应第二辅助走线的并联等效电阻为定值。
在本申请实施例所述的液晶显示面板中，所述多条第二辅助走线中的部分或全部第二辅助走线具有不同的宽度或者长度。
在本申请实施例所述的液晶显示面板中，所述连接金属为连接金属球。
在本申请实施例所述的液晶显示面板中，所述阵列基板包括基板、第一金属层、绝缘层以及第二金属层，所述第一金属层设置于所述基板上，所述绝缘层设置于所述第一金属层上，所述第二金属层设置于所述绝缘层上；
所述第二金属层在所述低电压区形成所述多条低电压信号线；
所述第一金属层形成至少一条第三辅助走线；
所述绝缘层设置有至少一导电金属化孔对，每一所述导电金属化孔对包括两个导电金属化孔，每一所述导电金属化孔对的两个导电金属化孔将一所述第三辅助走线的两端与一所述低电压信号线的两端电连接。
在本申请实施例所述的液晶显示面板中，所述第三辅助走线的数量为多条；
所述导电金属化孔对的数量与所述第三辅助走线的数量相同并一一对应；
每一所述导电金属化孔对的两个导电金属化孔分别将一第三辅助走线与对应的低电压信号线的两端电连接，从而使得每一所述第三辅助走线分别与对应所述低电压信号线并联。
 有益效果
本申请实施例通过采用设置在低电压信号线的两端并联辅助走线从而降低其电阻值，达到降低低电压区的电阻的目的，从而达到降低RC延迟的有益效果。
 附图说明
为了更清楚地说明本申请实施例的技术方案，下面将对本申请实施例中所需要使用的附图作简单地介绍，应当理解，以下附图仅示出了本申请的某些实施例，因此不应被看作是对范围的限定，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他相关的附图。
图1为本申请实施例提供的液晶显示面板的第一种结构示意图。
图2为本申请实施例提供的液晶显示面板的第二种结构示意图。
图3为本申请实施例提供的液晶显示面板的第三种结构示意图。
图4为本申请实施例提供的液晶显示面板的第四种结构示意图。
 本发明的实施方式
下面将结合本申请实施例中附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。通常在此处附图中描述和示出的本申请实施例的组件可以以各种不同的配置来布置和设计。因此，以下对在附图中提供的本申请的实施例的详细描述并非旨在限制要求保护的本申请的范围，而是仅仅表示本申请的选定实施例。基于本申请的实施例，本领域技术人员在没有做出创造性劳动的前提下所获得的所有其他实施例，都属于本申请保护的范围。
应注意到：相似的标号和字母在下面的附图中表示类似项，因此，一旦某一项在一个附图中被定义，则在随后的附图中不需要对其进行进一步定义和解释。同时，在本申请的描述中，术语“第一”、“第二”等仅用于区分描述，而不能理解为指示或暗示相对重要性。
请参照图1以及图2。该液晶显示面板，包括：阵列基板10、彩膜基板20以及夹设在阵列基板10、彩膜基板20之间的液晶分子层40、以及至少一个连接金属对30。
其中，该阵列基板10的上表面设置有低电压区10a以及高电压区10b，该高电压区10b设置有多条高电压信号走线，该低电压区10a设置有多条低电压信号走线11。该彩膜基板20的下表面设置有至少一条第一辅助走线21。该连接金属对30包括两个连接金属31，所述两个连接金属31设置于所述彩膜基板20与所述阵列基板10之间，以将一所述低电压信号线11的两端与一所述第一辅助走线21的两端电连接，从而降低该低电压信号线11的电阻，达到降低RC延迟的作用。
其中，该连接金属31为连接金属球。
其中，该低电压区10a位于该阵列基板10的非显示区域。该阵列基板10还设置有其他TFT阵列驱动结构，其为现有技术，无需过多描述。
该彩膜基板20还设置有其他光学功能层，其属于现有技术，无需过多描述。
该液晶分子层40可以采用现有常用的液晶分子，其属于现有技术，无需过多描述。
具体地，该第一辅助走线21可以采用ITO金属形成，形成于该彩膜基板的下表面的ITO金属层可以采用光罩工艺，形成与阵列基板上的低电压信号线11对应分布的第一辅助走线21。
在一些实施例中，该第一辅助走线21的数量为多条；该连接金属对30的数量与所述第一辅助走线21的数量相同并一一对应；每一连接金属对30的两个连接金属31分别将一第一辅助走线21与对应的低电压信号线11的两端电连接，从而使得每一所述第一辅助走线21分别与对应所述低电压信号线11并联。
可以理解地，在一些实施例中，该第一辅助走线21的数量为多条；多条低电压信号线11中的部分低电压信号线11通过多个连接金属对30与多条第一辅助走线21一一对应地电连接。也即是，每一条低电压信号线11都并联了一条第一辅助走线21，且，不同的低电压信号线11并联不同的第一辅助走线21。
可以理解地，在一些实施例中，第一辅助走线21的数量为多条；多条低电压信号线11中的部分低电压信号线11通过多个连接金属对30与多条第一辅助走线21一一对应地电连接。也即是说，部分低电压信号线11并联有一第一辅助走线21，部分低电压信号线11未并联第一辅助走线21。
其中，为了便于第一辅助走线21的布局以及连接，每一所述第一辅助走线21与对应的低电压信号线11相互正对且形状及尺寸相同。或者，在一些实施例中，每一所述第一辅助走线与对应的低电压信号线局部相对，且相对的部分形状相同。
在一些实施例中，该多条低电压信号线21包括多条第一低电压信号线；该至少一条第一辅助走线11包括多条第二辅助走线；例如，该第一低电压信号线均为阴极走线或者低电平时钟信号走线。该多条第一低电压信号线中的部分或全部第一低电压信号线分别通过连接金属对与所述多条第二辅助走线一一对应地连接，从而使得所述第一低电压信号线与对应第二辅助走线的并联等效电阻为定值。也即是说，为了达到使得该多条第一低电压信号线的等效电阻相同的目的，其可以选择并联或者不并联第二辅助走线，并联的辅助走线的阻值根据该定值来进行设置。例如，该多条第二辅助走线中的部分或全部第二辅助走线具有不同的宽度或者长度。
由上可知，本申请实施例，通过采用设置在低电压信号线的两端并联辅助走线从而降低其电阻值，达到降低低电压区的电阻的目的，从而达到降低RC延迟的有益效果。
请参照图3以及图4，该阵列基板包括基板101、第一金属层102、绝缘层103以及第二金属层104，所述第一金属层102设置于所述基板101上，所述绝缘层103设置于所述第一金属层102上，所述第二金属层104设置于所述绝缘层103上。
其中，该第二金属层103在所述低电压区形成所述多条低电压信号线21；第一金属层102形成至少一条第三辅助走线1021；绝缘层设置有至少一导电金属化孔对，每一所述导电金属化孔对包括两个导电金属化孔1031，每一所述导电金属化孔对的两个导电金属化孔1031将一所述第三辅助走线1021的两端与一所述低电压信号线21的两端电连接。
其中，在一些实施例中，该第三辅助走线1021的数量为多条；导电金属化孔对1031的数量与所述第三辅助走线1021的数量相同并一一对应；
每一导电金属化孔对的两个导电金属化孔1031分别将一第三辅助走线1021与对应的低电压信号线21的两端电连接，从而使得每一所述第三辅助走线分别与对应所述低电压信号线21并联。可以理解地，在一些实施例中，每一低电压信号线21及其并联的第三辅助走线1021以及第一辅助走线的等效电阻相同，因此，为了实现等效电阻相同，则需要结合该低电压信号线21的阻值来设计该第三辅助走线1021以及第一辅助走线的阻值，从而实现等效电阻相同。
可以理解地，在一些实施例中，该第三辅助走线1021的数量小于该低电压信号线21的数量，也即说，该多条低电压信号走线21中仅仅部分低电压信号走线21并联有第三辅助走线1021。
可以理解地，在一些实施例中，该多条低电压信号线21中的部分低电压信号线21与该彩膜基板20下表面的多条第一辅助走线一一对应，该多条低电压信号线21中的其他部分低电压信号线21与该第一金属层形成的多条第三辅助走线1021一一对应，从而使得每一低电压信号线21均并联有一条辅助走线。优选地，在一些实施例中，在彩膜基板20上设置第一辅助走线的低电压信号线21与在第一金属层设置第三辅助走线的低电压信号线21依次间隔排布，从而通过将辅助走线分开分布在彩膜基板的下表面以及该阵列基板的第一金属层从而可以降低辅助走线之间的间隔距离，可以达到降低干扰的有益效果。
由上可知，本申请实施例，通过采用设置在低电压信号线的两端并联辅助走线从而降低其电阻值，达到降低低电压区的电阻的目的，从而达到降低RC延迟的有益效果。
在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。
以上所述仅为本申请的实施例而已，并不用于限制本申请的保护范围，对于本领域的技术人员来说，本申请可以有各种更改和变化。凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (18)

  1. 一种液晶显示面板，其包括：
    彩膜基板，其下表面设置有至少一条第一辅助走线；
    阵列基板，其上表面设置有低电压区，所述低电压区设置有多条低电压信号线；
    至少一个连接金属对，每一所述连接金属对包括两个连接金属，所述两个连接金属设置于所述彩膜基板与所述阵列基板之间，以将一所述低电压信号线的两端与一所述第一辅助走线的两端电连接；
    所述第一辅助走线的数量为多条；
    所述连接金属对的数量与所述第一辅助走线的数量相同并一一对应；
    每一所述连接金属对的两个连接金属分别将一第一辅助走线与对应的低电压信号线的两端电连接，从而使得每一所述第一辅助走线分别与对应所述低电压信号线并联；所述连接金属为连接金属球。
  2. 根据权利要求1所述的液晶显示面板，其中，每一所述第一辅助走线与对应的低电压信号线相互正对且形状及尺寸相同。
  3. 根据权利要求1所述的液晶显示面板，其中，每一所述第一辅助走线与对应的低电压信号线局部相对，且相对的部分形状相同。
  4. 根据权利要求1所述的液晶显示面板，其中，所述第一辅助走线的数量为多条；
    所述多条低电压信号线中的部分低电压信号线通过多个连接金属对与多条第一辅助走线一一对应地电连接。
  5. 根利要求1所述的液晶显示面板，其中，所述多条低电压信号线包括多条第一低电压信号线；
    所述至少一条第一辅助走线包括多条第二辅助走线；
    所述多条第一低电压信号线中的部分或全部第一低电压信号线分别通过连接金属对与所述多条第二辅助走线一一对应地连接，从而使得所述第一低电压信号线与对应第二辅助走线的并联等效电阻为定值。
  6. 根据权利要求5述的液晶显示面板，其中，所述多条第二辅助走线中的部分或全部第二辅助走线具有不同的宽度或者长度。
  7. 根据权利要求1所述的液晶显示面板，其中，所述阵列基板包括基板、第一金属层、绝缘层以及第二金属层，所述第一金属层设置于所述基板上，所述绝缘层设置于所述第一金属层上，所述第二金属层设置于所述绝缘层上；
    所述第二金属层在所述低电压区形成所述多条低电压信号线；
    所述第一金属层形成至少一条第三辅助走线；
    所述绝缘层设置有至少一导电金属化孔对，每一所述导电金属化孔对包括两个导电金属化孔，每一所述导电金属化孔对的两个导电金属化孔将一所述第三辅助走线的两端与一所述低电压信号线的两端电连接。
  8. 根据权利要求7所述的液晶显示面板，其中，所述第三辅助走线的数量为多条；
    所述导电金属化孔对的数量与所述第三辅助走线的数量相同并一一对应；
    每一所述导电金属化孔对的两个导电金属化孔分别将一第三辅助走线与对应的低电压信号线的两端电连接，从而使得每一所述第三辅助走线分别与对应所述低电压信号线并联。
  9. 一种液晶显示面板，其包括：
    彩膜基板，其下表面设置有至少一条第一辅助走线；
    阵列基板，其上表面设置有低电压区，所述低电压区设置有多条低电压信号线；
    至少一个连接金属对，每一所述连接金属对包括两个连接金属，所述两个连接金属设置于所述彩膜基板与所述阵列基板之间，以将一所述低电压信号线的两端与一所述第一辅助走线的两端电连接。
  10. 根据权利要求9所述的液晶显示面板，其中，所述第一辅助走线的数量为多条；
    所述连接金属对的数量与所述第一辅助走线的数量相同并一一对应；
    每一所述连接金属对的两个连接金属分别将一第一辅助走线与对应的低电压信号线的两端电连接，从而使得每一所述第一辅助走线分别与对应所述低电压信号线并联。
  11. 根据权利要求10所述的液晶显示面板，其中，每一所述第一辅助走线与对应的低电压信号线相互正对且形状及尺寸相同。
  12. 根据权利要求10所述的液晶显示面板，其中，每一所述第一辅助走线与对应的低电压信号线局部相对，且相对的部分形状相同。
  13. 根据权利要求10所述的液晶显示面板，其中，所述第一辅助走线的数量为多条；
    所述多条低电压信号线中的部分低电压信号线通过多个连接金属对与多条第一辅助走线一一对应地电连接。
  14. 根利要求10所述的液晶显示面板，其中，所述多条低电压信号线包括多条第一低电压信号线；
    所述至少一条第一辅助走线包括多条第二辅助走线；
    所述多条第一低电压信号线中的部分或全部第一低电压信号线分别通过连接金属对与所述多条第二辅助走线一一对应地连接，从而使得所述第一低电压信号线与对应第二辅助走线的并联等效电阻为定值。
  15. 根据权利要求14述的液晶显示面板，其中，所述多条第二辅助走线中的部分或全部第二辅助走线具有不同的宽度或者长度。
  16. 根据权利要求9所述的液晶显示面板，其中，所述连接金属为连接金属球。
  17. 根据权利要求9所述的液晶显示面板，其中，所述阵列基板包括基板、第一金属层、绝缘层以及第二金属层，所述第一金属层设置于所述基板上，所述绝缘层设置于所述第一金属层上，所述第二金属层设置于所述绝缘层上；
    所述第二金属层在所述低电压区形成所述多条低电压信号线；
    所述第一金属层形成至少一条第三辅助走线；
    所述绝缘层设置有至少一导电金属化孔对，每一所述导电金属化孔对包括两个导电金属化孔，每一所述导电金属化孔对的两个导电金属化孔将一所述第三辅助走线的两端与一所述低电压信号线的两端电连接。
  18. 根据权利要求17所述的液晶显示面板，其中，所述第三辅助走线的数量为多条；
    所述导电金属化孔对的数量与所述第三辅助走线的数量相同并一一对应；
    每一所述导电金属化孔对的两个导电金属化孔分别将一第三辅助走线与对应的低电压信号线的两端电连接，从而使得每一所述第三辅助走线分别与对应所述低电压信号线并联。
PCT/CN2020/091322 2020-05-12 2020-05-20 液晶显示面板 WO2021227109A1 (zh)

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