WO2021218433A1 - 电路板组件、显示装置、终端和信号处理系统 - Google Patents

电路板组件、显示装置、终端和信号处理系统 Download PDF

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Publication number
WO2021218433A1
WO2021218433A1 PCT/CN2021/080271 CN2021080271W WO2021218433A1 WO 2021218433 A1 WO2021218433 A1 WO 2021218433A1 CN 2021080271 W CN2021080271 W CN 2021080271W WO 2021218433 A1 WO2021218433 A1 WO 2021218433A1
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WO
WIPO (PCT)
Prior art keywords
circuit board
pin
differential signal
line
differential
Prior art date
Application number
PCT/CN2021/080271
Other languages
English (en)
French (fr)
Inventor
王中杰
彭凡
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/629,792 priority Critical patent/US11839026B2/en
Publication of WO2021218433A1 publication Critical patent/WO2021218433A1/zh

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/148—Arrangements of two or more hingeably connected rigid printed circuit boards, i.e. connected by flexible means
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
    • H05K1/0219—Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H05K1/0245—Lay-out of balanced signal pairs, e.g. differential lines or twisted lines
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10196—Variable component, e.g. variable resistor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/1031—Surface mounted metallic connector elements
    • H05K2201/10318—Surface mounted metallic pins

Definitions

  • the present disclosure relates to, but is not limited to, the field of display technology, and particularly relates to a circuit board assembly, a display device, a terminal, and a signal processing system.
  • AMOLED Flexible Active Matrix Organic Light-Emitting Diode
  • the present disclosure provides a circuit board assembly, including: a first circuit board, a second circuit board, a third circuit board, and a plurality of differential signal lines; the first circuit board and the second circuit board Are respectively located on opposite sides of the third circuit board; each differential signal line includes: a first differential line and a second differential line;
  • the first circuit board includes: a first connector, the first connector includes: a first pin group and a second pin group arranged in a first direction; the first pin group includes: N First pins arranged in a second direction, and the second pin group includes: N second pins arranged in the second direction;
  • the second circuit board includes: a second connector, the second connector includes: a third pin group and a fourth pin group arranged in a first direction; the third pin group includes: N Three third pins arranged in the second direction, and the fourth pin group includes: N fourth pins arranged in the second direction;
  • the multiple i-th pins correspond to the multiple i+2-th pins one-to-one, the i-th pin and the corresponding i+2-th pin are arranged along the first direction, and i is a positive integer less than or equal to 2;
  • the first differential line of the jth differential signal line is connected to the 2j-1th pin and the 2j-1th i+2th pin respectively, and the second differential line of the jth differential signal line is connected to the 2j-1th pin and the i+2th pin. 2j i-th pin and 2j-th i+2 pin are connected;
  • the first direction is an arrangement direction of the first circuit board and the second circuit board, and the second direction is perpendicular to the first direction, and 1 ⁇ j ⁇ N/2.
  • the polarities of the first differential line and the second differential line located in the same differential signal line are opposite, and the widths along the second direction are the same.
  • the circuit board assembly further includes: a ground wire;
  • the ground wire is located between adjacent differential signal wires.
  • the k-th first pin is located between the k-th second pin and the k+1-th second pin
  • the N-th second pin is located between the N-1th and N-1th pins. Between a pin and the Nth first pin, 1 ⁇ k ⁇ N-1.
  • the kth second pin is located between the kth first pin and the k+1th first pin
  • the Nth first pin is located between the N-1th first pin and the N-1th first pin. Between the second pin and the Nth second pin; 1 ⁇ k ⁇ N-1.
  • the ground line between the jth differential signal line and the j+1th differential signal line is connected to the 2j+1th second pin and the 2jth differential signal line. +1 fourth pin connection;
  • the ground line located between the jth differential signal line and the j+1th differential signal line is connected to the 2jth first pin and the 2jth third pin.
  • the ground line between the jth differential signal line and the j+1th differential signal line is connected to the 2jth second pin and the 2jth Four-pin connection;
  • the ground line located between the jth differential signal line and the j+1th differential signal line is connected to the 2j+1th first pin and the 2j+1th third pin .
  • a timing controller is provided on the first circuit board or the second circuit board;
  • the timing controller is connected to the differential signal line, and is configured to convert the received display signal into a differential signal, and send the differential signal to the differential signal line.
  • the distance between the third circuit board and the first connector is greater than zero, and the distance between the third circuit board and the second connector is greater than zero.
  • the third circuit board is a flexible printed circuit board
  • the third circuit board is divided into a first connection part, a circuit board body and a second connection part arranged along a first direction;
  • the first connecting portion is connected to the first circuit board, and the second connecting portion is connected to the second circuit board.
  • the first connection portion is press-fitted on the first circuit board
  • the second connection portion is press-fitted on the second circuit board
  • the present disclosure also provides a display device, including: a display panel and the above-mentioned circuit board assembly;
  • the first circuit board and the second circuit board in the circuit board assembly are respectively connected with the display panel.
  • the present disclosure also provides a terminal, including: the above-mentioned display device.
  • the present disclosure also provides a signal processing system, including: a client and the above-mentioned terminal;
  • the client terminal is used to send a display signal to the terminal
  • the terminal is used to convert the display signal into a differential signal.
  • the terminal includes: a timing controller provided on the circuit board assembly;
  • the timing controller is connected to the client, and is used to convert the display signal sent by the client into a differential signal.
  • FIG. 1 is a first schematic diagram of a circuit board assembly provided by an embodiment of the disclosure
  • FIG. 2 is a second schematic diagram of a circuit board assembly provided by an embodiment of the disclosure.
  • FIG. 3 is a third schematic diagram of a circuit board assembly provided by an embodiment of the disclosure.
  • FIG. 4 is a fourth schematic diagram of a circuit board assembly provided by an embodiment of the disclosure.
  • Fig. 5 is a schematic structural diagram of a circuit board assembly provided by an exemplary embodiment
  • FIG. 6 is a schematic structural diagram of a display device provided by an embodiment of the disclosure.
  • FIG. 7 is a schematic structural diagram of a signal processing system provided by an embodiment of the disclosure.
  • the AMOLED folding notebook includes: a left circuit board, a right circuit board, and a flexible printed circuit board arranged between the left circuit board and the right circuit board.
  • the left side circuit board and the right side circuit board are provided with connecting wires for connecting the differential signal wires.
  • the power supply, gate signal, differential display signal and many other signals of the circuit board on one side of the AMOLED folding notebook must be bridged to the other side of the circuit board through the FPC; on the other hand, the AMOLED folding notebook pair connector
  • the AMOLED folding notebook pair connector There are strict restrictions on the size. These two aspects together determine that only dual-row pin connectors can be used on each circuit board, and the spacing between the pins and the width of the pins are very small. This will cause two problems: First, the differential signal line cannot be symmetrically routed at the connector; second, due to the extremely small line width and line spacing, the differential signal line on the flexible printed circuit board cannot control the differential impedance according to the 100 ohm specification. In turn, the impedance of the differential signal line path is discontinuous, which aggravates the crosstalk and reflection of the differential signal, and seriously affects the display quality of the product.
  • the circuit board assembly provided by the embodiments of the present disclosure includes: a first circuit board 1, a second circuit board 2, a third circuit board 3, and a plurality of differential signal lines S; the first circuit board 1 and The second circuit board 2 is respectively located on two opposite sides of the third circuit board 3; each differential signal line S includes: a first differential line S1 and a second differential line S2.
  • the first circuit board 1 includes: a first connector 10.
  • the first connector 10 includes a first pin group 11 and a second pin group 12 arranged in a first direction.
  • the first pin group 11 includes: N first pins 110 arranged in the second direction
  • the second pin group 12 includes: N second pins 120 arranged in the second direction.
  • the second circuit board 2 includes: a second connector 20.
  • the second connector 20 includes a third pin group 21 and a fourth pin group 22 arranged along the first direction.
  • the third pin group 21 includes: N third pins 210 arranged along the second direction
  • the fourth pin group includes: N fourth pins 220 arranged along the second direction.
  • the multiple i-th pins correspond to the multiple i+2-th pins one-to-one, and the i-th pins and the corresponding i+2-th pins are arranged along the first direction, and i is a positive integer less than or equal to 2.
  • the first differential line S1 of the j-th differential signal line S is connected to the 2j-1th pin and the 2j-1th i+2th pin, respectively, and the second differential line of the jth differential signal line S S2 is respectively connected to the 2jth i-th pin and the 2jth i+2th pin.
  • the first direction is the arrangement direction of the first circuit board 1 and the second circuit board 2, and the second direction is perpendicular to the first direction, and 1 ⁇ j ⁇ N/2.
  • i-th pins correspond to multiple i+2th pins one-to-one, i-th pins and corresponding i+2th pins are arranged along the first direction, i is a positive integer less than or equal to 2, that is, more One first pin corresponds to a plurality of third pins, the first pin and the corresponding third pin are arranged along the first direction, and the plurality of second pins correspond to the plurality of fourth pins one-to-one , The second pin and the corresponding third pin are arranged along the first direction.
  • the first circuit board 1 and the second circuit board 2 may be printed circuit boards.
  • the first differential line and the second differential line of the same differential signal line are respectively connected to the adjacent i-th pin and the i+2th pin corresponding to the adjacent i-th pin, so that they are located on the first differential signal line of the same differential signal line.
  • the first differential line and the second differential line are parallel to each other, and there is no staggered arrangement, which can ensure that the first differential line and the second differential line of the same differential signal line are symmetrically arranged. Since the interval between adjacent i-th pins is relatively large, the width of the first differential line and the second differential line can be adjusted, and the differential impedance can be controlled on the third circuit board according to a specification of 100 ohms.
  • the circuit board assembly includes: a first circuit board, a second circuit board, a third circuit board and a plurality of differential signal lines; the first circuit board and the second circuit board are respectively located opposite to the third circuit board On both sides; each differential signal line includes: a first differential line and a second differential line; the first circuit board includes: a first connector, the first connector includes: a first pin group arranged in a first direction and The second pin group; the first pin group includes: N first pins arranged in the second direction, the second pin group includes: N second pins arranged in the second direction; second The circuit board includes: a second connector, the second connector includes: a third pin group and a fourth pin group arranged in a first direction; the third pin group includes: N pins arranged in a second direction The third pin and the fourth pin group include: N fourth pins arranged in the second direction; multiple i-th pins correspond to multiple i+2-th pins one-to-one, and the i-th pin corresponds to The
  • the second differential line of the j-th differential signal line is connected to the 2j-th pin and the 2j-th pin i+2 respectively;
  • the first direction is the first circuit board and the second The arrangement direction of the circuit board, the second direction is perpendicular to the first direction, 1 ⁇ j ⁇ N/2.
  • the first differential line S located in the same differential signal line S! The polarity of the second differential line S2 is opposite, and the width along the second direction is the same.
  • the widths of the first differential lines in the different differential signal lines along the second direction may be equal or unequal, which is determined according to the specifications of the circuit board assembly.
  • the polarity of the first differential line may be positive, and the polarity of the second differential line may be negative, or the polarity of the first differential line may be negative, and the polarity of the second differential line may be negative.
  • the polarity can be negative.
  • the plurality of first pins in the first pin group and the plurality of second pins in the second pin group are alternately arranged. Since the multiple first pins in the first pin group correspond to the multiple third pins in the third pin group one-to-one, the multiple second pins and the fourth pins in the second pin group The multiple fourth pins in the middle and south of the group correspond one-to-one. Therefore, the multiple second pins in the second pin group and the multiple fourth pins in the fourth pin group are alternately arranged.
  • the staggered arrangement of the plurality of first pins in the first pin group and the plurality of second pins in the second pin group may be:
  • the k first pins are located between the k second pin and the k+1 second pin
  • the N second pin is located between the N-1 first pin and the N first pin Between pins, 1 ⁇ k ⁇ N-1.
  • the staggered arrangement of the plurality of first pins in the first pin group and the plurality of second pins in the second pin group may be:
  • the k second pins are located between the k first pin and the k+1 first pin
  • the N first pin is located between the N-1 second pin and the N second pin Between pins; 1 ⁇ k ⁇ N-1.
  • the circuit board assembly further includes: a ground line GND; the ground line GND is located between adjacent differential signal lines.
  • the ground line GND located between adjacent differential signal lines can avoid crosstalk between adjacent differential signal lines and improve the display effect of the display product.
  • no signal line or power line is connected between the 2jth second pin and the 2jth fourth pin, and the jth differential signal line can be adjusted
  • the line width and line distance of the first differential line and the second differential line are used to realize the impedance control of the differential signal line.
  • no signal line or power line is connected between the 2j-1 second pin and the 2j-1 fourth pin, and the jth pin can be adjusted.
  • the line width and line distance of the first differential line and the second differential line in the differential signal line are used to realize the impedance control of the differential signal line.
  • no signal line or power line is connected between the 2j-1th first pin and the 2j-1th third pin, and the jth pin can be adjusted.
  • the line width and line distance of the first differential line and the second differential line in the differential signal line are used to realize the impedance control of the differential signal line.
  • no signal line or power line is connected between the 2jth first pin and the 2jth third pin, and the jth differential signal line can be adjusted
  • the line width and line distance of the first differential line and the second differential line are used to realize the impedance control of the differential signal line.
  • the first connector and the second connector in the circuit board assembly include: a pin connected to a differential signal line, a pin connected to a ground line, and a pin not connected to any signal line or power line.
  • the distance between the third circuit board 3 and the first connector 10 is greater than 0, and the distance between the third circuit board 3 and the second connector 20 Greater than 0.
  • Fig. 5 is a schematic structural diagram of a circuit board assembly provided by an exemplary embodiment.
  • a timing controller 13 is provided on the first circuit board 1 or the second circuit board 2.
  • the timing controller 13 is connected to the differential signal line, and is configured to convert the received display signal into a differential signal, and send the differential signal to the differential signal line.
  • the differential signal is sent from the first circuit board to the second circuit board through the first connector, the third circuit board, and the second connector.
  • the timing controller may be arranged on the first circuit board 1, or may be arranged on the second circuit board 2. As shown in FIG. 5, the timing controller is arranged on the first circuit board 1. Examples are explained.
  • the third circuit board is a flexible printed circuit board, and the third circuit board is a flexible printed circuit board, which can realize flexible display and has foldable performance.
  • the third circuit board 3 is divided into a first connection portion 31, a circuit board body 33 and a second connection portion 32 arranged along the first direction.
  • the first connecting portion 31 is connected to the first circuit board 1, and the second connecting portion 32 is connected to the second circuit board 2.
  • the first connecting portion 31 is pressed onto the first circuit board 1, and the second connecting portion 32 is pressed onto the second circuit board 2.
  • FIG. 6 is a schematic structural diagram of a display device provided by an embodiment of the disclosure. As shown in FIG. 6, an embodiment of the present disclosure further provides a display device.
  • the display device includes a display panel 100 and a circuit board assembly 200.
  • the first circuit board 1 and the second circuit board 2 in the circuit board assembly 200 are respectively connected to the display panel 100 through the flip chip technology.
  • the display panel may be an OLED display panel.
  • the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.
  • the circuit board assembly is the circuit board assembly provided in any of the foregoing embodiments, and the implementation principle and effect are similar, and will not be repeated here.
  • An embodiment of the present disclosure also provides a terminal, including: the display device provided in any of the foregoing embodiments.
  • the terminal includes the display device provided in any of the foregoing embodiments, and the implementation principles and implementation effects are similar, and will not be repeated here.
  • FIG. 7 is a schematic structural diagram of a signal processing system provided by an embodiment of the disclosure.
  • the signal processing system provided by the embodiment of the present disclosure includes: a client 300 and a terminal 400 provided in any of the foregoing embodiments; the client 300 is used to send a display signal to the terminal 400; and the terminal 400 is used to display a signal Convert to differential signal.
  • the signal processing system includes the terminal provided in any of the foregoing embodiments, and the implementation principle and implementation effect are similar, and will not be repeated here.
  • the terminal 300 includes: a timing controller 13 provided on a circuit board assembly.
  • the timing controller 13 is connected to the client 400 and is used to convert the display signal sent by the client into a differential signal.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Electromagnetism (AREA)
  • Structure Of Printed Boards (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种电路板组件（200）、显示装置、终端和信号处理系统，电路板组件（200）包括：第一电路板（1）、第二电路板（2）、第三电路板（3）和多个差分信号线（S）；第一电路板（1）包括：第一连接器（10），第一连接器（10）包括：第一引脚组（11）和第二引脚组（12）；第一引脚组（11）包括：N个第一引脚（110），第二引脚组（12）包括：N个第二引脚（120）；第二电路板（2）包括：第二连接器（20），第二连接器（20）包括：第三引脚组（21）和第四引脚组（22）；第三引脚组（21）包括：N个第三引脚（210），第四引脚组（22）包括：N个第四引脚（220）；多个第i引脚与多个第i+2引脚一一对应，第i引脚与对应的第i+2引脚沿第一方向排布；第j个差分信号线（S）的第一差分线（S1）分别与第2j-1个第i引脚和第2j-1个第i+2引脚连接，第j个差分信号线（S）的第二差分线（S2）分别与第2j个第i引脚和第2j个第i+2引脚连接。

Description

电路板组件、显示装置、终端和信号处理系统
本申请要求于2020年4月30日提交中国专利局、申请号为202010366326.1、发明名称为“电路板组件、显示装置、终端和信号处理系统”的中国专利申请的优先权，其内容应理解为通过引用的方式并入本申请中。
技术领域
本公开涉及但不限于显示技术领域，特别涉及一种电路板组件、显示装置、终端和信号处理系统。
背景技术
柔性有源矩阵有机发光二极管(Active Matrix Organic Light-Emitting Diode，简称AMOLED)显示产品具有自发光、无背光、可折叠、广视角、高色域、反应速度快、对比度高、视角广等诸多优点，是目前受到广泛关注的一种显示产品，其中，AMOLED折叠笔记本是常用的显示产品。
为了保证正常显示，显示产品需要通过差分信号线来传输高速差分信号。而高速差分信号会因为路径上的阻抗不连续发生串扰或者反射，降低了显示产品的显示效果。
发明概述
以下是对本公开详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
第一方面，本公开提供了一种电路板组件，包括：第一电路板、第二电路板、第三电路板和多个差分信号线；所述第一电路板和所述第二电路板分别位于所述第三电路板相对设置的两侧；每个差分信号线包括：第一差分线和第二差分线；
所述第一电路板包括：第一连接器，所述第一连接器包括：沿第一方向排布的第一引脚组和第二引脚组；所述第一引脚组包括：N个沿第二方向排 布的第一引脚，所述第二引脚组包括：N个沿第二方向排布的第二引脚；
所述第二电路板包括：第二连接器，所述第二连接器包括：沿第一方向排布的第三引脚组和第四引脚组；所述第三引脚组包括：N个沿第二方向排布的第三引脚，所述第四引脚组包括：N个沿第二方向排布的第四引脚；
多个第i引脚与多个第i+2引脚一一对应，第i引脚与对应的第i+2引脚沿所述第一方向排布，i为小于等于2的正整数；
第j个差分信号线的第一差分线分别与第2j-1个第i引脚和第2j-1个第i+2引脚连接，第j个差分信号线的第二差分线分别与第2j个第i引脚和第2j个第i+2引脚连接；
所述第一方向为所述第一电路板和所述第二电路板的排布方向，所述第二方向垂直于所述第一方向，1≤j≤N/2。
在一些可能的实现方式中，位于同一差分信号线中的第一差分线和第二差分线的极性相反，且沿第二方向的宽度相等。
在一些可能的实现方式中，所述电路板组件还包括：地线；
所述地线位于相邻差分信号线之间。
在一些可能的实现方式中，第k个第一引脚位于第k个第二引脚和第k+1个第二引脚之间，第N个第二引脚位于第N-1个第一引脚和第N个第一引脚之间，1≤k≤N-1。
在一些可能的实现方式中，第k个第二引脚位于第k个第一引脚和第k+1个第一引脚之间，第N个第一引脚位于第N-1个第二引脚和第N个第二引脚之间；1≤k≤N-1。
在一些可能的实现方式中，当i＝1时，位于所述第j个差分信号线和第j+1个差分信号线之间的地线与第2j+1个第二引脚和第2j+1个第四引脚连接；
当i＝2时，位于所述第j个差分信号线和所述第j+1个差分信号线之间的地线与第2j个第一引脚和第2j个第三引脚连接。
在一些可能的实现方式中，当i＝1时，位于所述第j个差分信号线和第j+1个差分信号线之间的地线与第2j个第二引脚和第2j个第四引脚连接；
当i＝2时，位于所述第j个差分信号线和第j+1个差分信号线之间的地线与第2j+1个第一引脚和第2j+1个第三引脚连接。
在一些可能的实现方式中，所述第一电路板或所述第二电路板上设置有时序控制器；
所述时序控制器，与所述差分信号线连接，被配置为将接收到的显示信号转换为差分信号，并将所述差分信号发送至所述差分信号线。
在一些可能的实现方式中，所述第三电路板与所述第一连接器之间的间距大于0，所述第三电路板与所述第二连接器之间的间距大于0。
在一些可能的实现方式中，所述第三电路板为柔性印刷电路板；
所述第三电路板被划分为沿第一方向排布的第一连接部、电路板本体和第二连接部；
所述第一连接部与所述第一电路板连接，所述第二连接部与所述第二电路板连接。
在一些可能的实现方式中，所述第一连接部压合在所述第一电路板上，所述第二连接部压合在所述第二电路板上。
第二方面，本公开还提供了一种显示装置，包括：显示面板和上述电路板组件；
所述电路板组件中的第一电路板和第二电路板分别与所述显示面板连接。
第三方面，本公开还提供了一种终端，包括：上述显示装置。
第四方面，本公开还提供了一种信号处理系统，包括：客户端和上述终端；
所述客户端用于向所述终端发送显示信号；
所述终端用于将显示信号转换为差分信号。
在一些可能的实现方式中，所述终端包括：设置在电路板组件上的时序控制器；
所述时序控制器与所述客户端连接，用于将客户端发送的显示信号转换为差分信号。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图概述
附图用来提供对本公开技术方案的理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。
图1为本公开实施例提供的电路板组件的第一示意图；
图2为本公开实施例提供的电路板组件的第二示意图；
图3为本公开实施例提供的电路板组件的第三示意图；
图4为本公开实施例提供的电路板组件的第四示意图；
图5为一种示例性实施例提供的电路板组件的结构示意图；
图6为本公开实施例提供的显示装置的结构示意图；
图7为本公开实施例提供的信号处理系统的结构示意图。
详述
下文中将结合附图对本申请的实施例进行详细说明。在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互任意组合。
本公开描述了多个实施例，但是该描述是示例性的，而不是限制性的，并且对于本领域的普通技术人员来说，在本公开所描述的实施例包含的范围内可以有更多的实施例和实现方案。尽管在附图中示出了许多可能的特征组合，并在具体实施方式中进行了讨论，但是所公开的特征的许多其它组合方式也是可能的。除非特意加以限制的情况以外，任何实施例的任何特征或元件可以与任何其它实施例中的任何其他特征或元件结合使用，或可以替代任何其它实施例中的任何其他特征或元件。
本公开包括并设想了与本领域普通技术人员已知的特征和元件的组合。本公开已经公开的实施例、特征和元件也可以与任何常规特征或元件组合，以形成由权利要求限定的技术方案。任何实施例的任何特征或元件也可以与 来自其它技术方案的特征或元件组合，以形成另一个由权利要求限定的技术方案。因此，应当理解，在本公开中示出和/或讨论的任何特征可以单独地或以任何适当的组合来实现。因此，除了根据所附权利要求及其等同替换所做的限制以外，实施例不受其它限制。此外，可以在所附权利要求的保护范围内进行各种修改和改变。
除非另外定义，本公开公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述的对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
AMOLED折叠笔记本包括：左侧电路板、右侧电路板和设置左侧电路板和右侧电路板之间的柔性印刷电路板。左侧电路板和右侧电路板上设置有连接差分信号线的连接线。
对于AMOLED折叠笔记本而言，AMOLED折叠笔记本的一侧电路板的电源、栅极信号、差分显示信号等诸多信号都要通过FPC桥接至另一侧电路板；另一方面，AMOLED折叠笔记本对连接器的尺寸有严格的限制。这两方面共同决定了在每个电路板上只能使用双排引脚的连接器，且引脚之间的间距和引脚的宽度都非常小。这样会引起两个问题：一，差分信号线在连接器处无法对称走线；二，由于线宽和线距极小，差分信号线在柔性印刷电路板无法按100欧姆的规格管控差分阻抗，进而导致差分信号线路径上的阻抗不连续，加剧差分信号的串扰、反射，严重影响产品显示质量。
图1为本公开实施例提供的电路板组件的第一示意图，图2为本公开实施例提供的电路板组件的第二示意图，图3为本公开实施例提供的电路板组件的第三示意图，图4为本公开实施例提供的电路板组件的第四示意图。如图1至4所示，本公开实施例提供的电路板组件包括：第一电路板1、第二 电路板2、第三电路板3和多个差分信号线S；第一电路板1和第二电路板2分别位于第三电路板3相对设置的两侧；每个差分信号线S包括：第一差分线S1和第二差分线S2。
第一电路板1包括：第一连接器10。第一连接器10包括：沿第一方向排布的第一引脚组11和第二引脚组12。第一引脚组11包括：N个沿第二方向排布的第一引脚110，第二引脚组12包括：N个沿第二方向排布的第二引脚120。
第二电路板2包括：第二连接器20。第二连接器20包括：沿第一方向排布的第三引脚组21和第四引脚组22。第三引脚组21包括：N个沿第二方向排布的第三引脚210，第四引脚组包括：N个沿第二方向排布的第四引脚220。
多个第i引脚与多个第i+2引脚一一对应，第i引脚与对应的第i+2引脚沿第一方向排布，i为小于等于2的正整数。第j个差分信号线S的第一差分线S1分别与第2j-1个第i引脚和第2j-1个第i+2引脚连接，第j个差分信号线S的第二差分线S2分别与第2j个第i引脚和第2j个第i+2引脚连接。
第一方向为所述第一电路板1和第二电路板2的排布方向，第二方向垂直于第一方向，1≤j≤N/2。
多个第i引脚与多个第i+2引脚一一对应，第i引脚与对应的第i+2引脚沿第一方向排布，i为小于等于2的正整数，即多个第一引脚和多个第三引脚一一对应，第一引脚和对应的第三引脚沿第一方向排布，多个第二引脚和多个第四引脚一一对应，第二引脚和对应的第三引脚沿第一方向排布。
在一种示例性实施例中，第一电路板1和第二电路板2可以为印刷电路板。
本公开中同一差分信号线的第一差分线和第二差分线分别与相邻第i引脚和相邻第i引脚对应的第i+2引脚连接，使得位于同一差分信号线的第一差分线和第二差分线相互平行，且不存在交错设置，可以保证同一差分信号线的第一差分线和第二差分线对称设置。由于相邻第i引脚之间的间隔较大，第一差分线和第二差分线的宽度可以调节，可以实现在第三电路板上按照100欧姆的规格管控差分阻抗。
本公开实施例提供的电路板组件包括：第一电路板、第二电路板、第三电路板和多个差分信号线；第一电路板和第二电路板分别位于第三电路板相对设置的两侧；每个差分信号线包括：第一差分线和第二差分线；第一电路板包括：第一连接器，第一连接器包括：沿第一方向排布的第一引脚组和第二引脚组；第一引脚组包括：N个沿第二方向排布的第一引脚，第二引脚组包括：N个沿第二方向排布的第二引脚；第二电路板包括：第二连接器，第二连接器包括：沿第一方向排布的第三引脚组和第四引脚组；第三引脚组包括：N个沿第二方向排布的第三引脚，第四引脚组包括：N个沿第二方向排布的第四引脚；多个第i引脚与多个第i+2引脚一一对应，第i引脚与对应的第i+2引脚沿第一方向排布，i＝1或2；第j个差分信号线的第一差分线分别与第2j-1个第i引脚和第2j-1个第i+2引脚连接，第j个差分信号线的第二差分线分别与第2j个第i引脚和第2j个第i+2引脚连接；第一方向为第一电路板和第二电路板的排布方向，第二方向垂直于第一方向，1≤j≤N/2。本公开通过差分信号线中第一差分线和第二差分线的连接方式，可以实现差分信号线的对称设置和阻抗管控，提升了显示产品的显示效果。
在一种示例性实施例中，位于同一差分信号线S中的第一差分线S！和第二差分线S2的极性相反，且沿第二方向的宽度相等。
在一种示例性实施例中，不同差分信号线中的第一差分线沿第二方向的宽度可以相等，也可以不相等，根据电路板组件的规格确定。
在一种示例性实施例中，第一差分线的极性可以为正性，第二差分线的极性可以为负性，或者第一差分线的极性可以为负性，第二差分线的极性可以为负性。
在一种示例性实施例中，第一引脚组中的多个第一引脚与第二引脚中的多个第二引脚交错设置。由于第一引脚组中的多个第一引脚与第三引脚组中的多个第三引脚一一对应，第二引脚组中的多个第二引脚与第四引脚组中南的多个第四引脚一一对应，因此，第二引脚组中的多个第二引脚与第四引脚组中的多个第四引脚交错设置。
在一种示例性实施例中，如图1和3所示，第一引脚组中的多个第一引脚与第二引脚中的多个第二引脚交错设置方式可以为：第k个第一引脚位于 第k个第二引脚和第k+1个第二引脚之间，第N个第二引脚位于第N-1个第一引脚和第N个第一引脚之间，1≤k≤N-1。
在一种示例性实施例中，如图2和4所示，第一引脚组中的多个第一引脚与第二引脚中的多个第二引脚交错设置方式可以为：第k个第二引脚位于第k个第一引脚和第k+1个第一引脚之间，第N个第一引脚位于第N-1个第二引脚和第N个第二引脚之间；1≤k≤N-1。
在一种示例性实施例中，如图1至4所示，电路板组件还包括：地线GND；地线GND位于相邻差分信号线之间。位于相邻差分信号线之间的地线GND可以避免相邻差分信号线之间的串扰，提升显示产品的显示效果。
在一种示例性实施例中，如图1所示，当第一引脚组中的多个第一引脚与第二引脚中的多个第二引脚交错设置方式为图1所设置的方式时，当i＝1时，即第j个差分信号线S的第一差分线S1分别与第2j-1个第一引脚和第2j-1个第三引脚连接，第j个差分信号线S的第二差分线S2分别与第2j个第一引脚和第2j个第三引脚连接，此时，位于第j个差分信号线S和第j+1个差分信号线S之间的地线与第2j+1个第二引脚和第2j+1个第四引脚连接。
在一种示例性实施例中，如图1所示，第2j个第二引脚和第2j个第四引脚之间不连接任何信号线或者电源线，可以调整第j个差分信号线中第一差分线和第二差分线的线宽和线距，以实现差分信号线的阻抗管控。
在一种示例性实施例中，如图2所示，当第一引脚组中的多个第一引脚与第二引脚中的多个第二引脚交错设置方式为图2所设置的方式时，当i＝1时，即第j个差分信号线S的第一差分线S1分别与第2j-1个第一引脚和第2j-1个第三引脚连接，第j个差分信号线S的第二差分线S2分别与第2j个第一引脚和第2j个第三引脚连接，此时，位于第j个差分信号线和第j+1个差分信号线之间的地线与第2j个第二引脚和第2j个第四引脚连接。
在一种示例性实施例中，如图2所示，第2j-1个第二引脚和第2j-1个第四引脚之间不连接任何信号线或者电源线，可以调整第j个差分信号线中第一差分线和第二差分线的线宽和线距，以实现差分信号线的阻抗管控。
在一种示例性实施例中，如图3所示，当第一引脚组中的多个第一引脚与第二引脚中的多个第二引脚交错设置方式为图3所设置的方式时，当i＝2 时，即第j个差分信号线S的第一差分线S1分别与第2j-1个第二引脚和第2j-1个第四引脚连接，第j个差分信号线S的第二差分线S2分别与第2j个第二引脚和第2j个第四引脚连接，此时，位于第j个差分信号线和第j+1个差分信号线之间的地线与第2j个第一引脚和第2j个第三引脚连接。
在一种示例性实施例中，如图3所示，第2j-1个第一引脚和第2j-1个第三引脚之间不连接任何信号线或者电源线，可以调整第j个差分信号线中第一差分线和第二差分线的线宽和线距，以实现差分信号线的阻抗管控。
在一种示例性实施例中，如图4所示，当第一引脚组中的多个第一引脚与第二引脚中的多个第二引脚交错设置方式为图4所设置的方式时，当i＝2时，即第j个差分信号线S的第一差分线S1分别与第2j-1个第二引脚和第2j-1个第四引脚连接，第j个差分信号线S的第二差分线S2分别与第2j个第二引脚和第2j个第四引脚连接，此时，位于第j个差分信号线和第j+1个差分信号线之间的地线与第2j+1个第一引脚和第2j+1个第三引脚连接。
在一种示例性实施例中，如图4所示，第2j个第一引脚和第2j个第三引脚之间不连接任何信号线或者电源线，可以调整第j个差分信号线中第一差分线和第二差分线的线宽和线距，以实现差分信号线的阻抗管控。
电路板组件中的第一连接器和第二连接器包括：与差分信号线连接的引脚、与地线连接的引脚和不与任何信号线或者电源线连接的引脚。
在一种示例性实施例中，如图1至4所示，第三电路板3与第一连接器10之间的间距大于0，第三电路板3与第二连接器20之间的间距大于0。
图5为一种示例性实施例提供的电路板组件的结构示意图。如图5所示，在一种示例性实施例中，第一电路板1或第二电路板2上设置有时序控制器13。时序控制器13，与差分信号线连接，被配置为将接收到的显示信号转换为差分信号，并将差分信号发送至差分信号线。
在一种示例性实施例中，差分信号通过第一连接器、第三电路板和第二连接器从第一电路板发送至第二电路板中。
在一种示例性实施例中，时序控制器可以设置在第一电路板1上，或者，可以设置在第二电路板2上，图5是以时序控制器设置在第一电路板1上为 例进行说明的。
在一种示例性实施例中，第三电路板为柔性印刷电路板，第三电路板为柔性印刷电路板可以实现柔性显示，且具有可折叠的性能。
在一种示例性实施例中，如图5所示，第三电路板3被划分为沿第一方向排布的第一连接部31、电路板本体33和第二连接部32。
第一连接部31与第一电路板1连接，第二连接部32与第二电路板2连接。
在一种示例性实施例中，第一连接部31压合在第一电路板1上，第二连接部32压合在第二电路板2上。
图6为本公开实施例提供的显示装置的结构示意图。如图6所示，本公开实施例还提供一种显示装置，显示装置包括：显示面板100和电路板组件200。
电路板组件200中的第一电路板1和第二电路板2通过覆晶薄膜技术分别与显示面板100连接。
在一种示例性实施例中，显示面板可以为OLED显示面板。
在一种示例性实施例中，显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
电路板组件为前述任一实施例提供的电路板组件，实现原理和实现效果类似，在此不再赘述。
本公开实施例还提供一种终端，包括：前述任一实施例提供的显示装置。
终端包括前述任一实施例提供的显示装置，实现原理和实现效果类似，在此不再赘述。
图7为本公开实施例提供的信号处理系统的结构示意图。如图7所示，本公开实施例提供的信号处理系统包括：客户端300和前述任一实施例提供的终端400；客户端300用于向终端400发送显示信号；终端400用于将显示信号转换为差分信号。
信号处理系统包括前述任一实施例提供的终端，实现原理和实现效果类 似，在此不再赘述。
在一种示例性实施例中，终端300包括：设置在电路板组件上的时序控制器13。
时序控制器13与客户端400连接，用于将客户端发送的显示信号转换为差分信号。
本公开中的附图只涉及本公开实施例涉及到的结构，其他结构可参考通常设计。
为了清晰起见，在用于描述本公开的实施例的附图中，层或微结构的厚度和尺寸被放大。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本公开。任何本公开所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本公开的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (15)

  1. 一种电路板组件，包括：第一电路板、第二电路板、第三电路板和多个差分信号线；所述第一电路板和所述第二电路板分别位于所述第三电路板相对设置的两侧；每个差分信号线包括：第一差分线和第二差分线；
    所述第一电路板包括：第一连接器，所述第一连接器包括：沿第一方向排布的第一引脚组和第二引脚组；所述第一引脚组包括：N个沿第二方向排布的第一引脚，所述第二引脚组包括：N个沿第二方向排布的第二引脚；
    所述第二电路板包括：第二连接器，所述第二连接器包括：沿第一方向排布的第三引脚组和第四引脚组；所述第三引脚组包括：N个沿第二方向排布的第三引脚，所述第四引脚组包括：N个沿第二方向排布的第四引脚；
    多个第i引脚与多个第i+2引脚一一对应，第i引脚与对应的第i+2引脚沿第一方向排布，i为小于等于2的正整数；
    第j个差分信号线的第一差分线分别与第2j-1个第i引脚和第2j-1个第i+2引脚连接，第j个差分信号线的第二差分线分别与第2j个第i引脚和第2j个第i+2引脚连接；
    所述第一方向为所述第一电路板和所述第二电路板的排布方向，所述第二方向垂直于所述第一方向，1≤j≤N/2。
  2. 根据权利要求1所述的电路板组件，其中，位于同一差分信号线中的第一差分线和第二差分线的极性相反，且沿第二方向的宽度相等。
  3. 根据权利要求1或2所述的电路板组件，其中，所述电路板组件还包括：地线；
    所述地线位于相邻差分信号线之间。
  4. 根据权利要求3所述的电路板组件，其中，第k个第一引脚位于第k个第二引脚和第k+1个第二引脚之间，第N个第二引脚位于第N-1个第一引脚和第N个第一引脚之间，1≤k≤N-1。
  5. 根据权利要求3所述的电路板组件，其中，第k个第二引脚位于第k个第一引脚和第k+1个第一引脚之间，第N个第一引脚位于第N-1个第二引 脚和第N个第二引脚之间；1≤k≤N-1。
  6. 根据权利要求4所述的电路板组件，其中，
    当i＝1时，位于所述第j个差分信号线和第j+1个差分信号线之间的地线与第2j+1个第二引脚和第2j+1个第四引脚连接；
    当i＝2时，位于所述第j个差分信号线和所述第j+1个差分信号线之间的地线与第2j个第一引脚和第2j个第三引脚连接。
  7. 根据权利要求5所述的电路板组件，其中，
    当i＝1时，位于所述第j个差分信号线和第j+1个差分信号线之间的地线与第2j个第二引脚和第2j个第四引脚连接；
    当i＝2时，位于所述第j个差分信号线和第j+1个差分信号线之间的地线与第2j+1个第一引脚和第2j+1个第三引脚连接。
  8. 根据权利要求1所述的电路板组件，其中，所述第一电路板或所述第二电路板上设置有时序控制器；
    所述时序控制器，与所述差分信号线连接，被配置为将接收到的显示信号转换为差分信号，并将所述差分信号发送至所述差分信号线。
  9. 根据权利要求1所述的电路板组件，其中，所述第三电路板与所述第一连接器之间的间距大于0，所述第三电路板与所述第二连接器之间的间距大于0。
  10. 根据权利要求1或9所述的电路板组件，其中，所述第三电路板为柔性印刷电路板；
    所述第三电路板被划分为沿第一方向排布的第一连接部、电路板本体和第二连接部；
    所述第一连接部与所述第一电路板连接，所述第二连接部与所述第二电路板连接。
  11. 根据权利要求10所述的电路板组件，其中，所述第一连接部压合在所述第一电路板上，所述第二连接部压合在所述第二电路板上。
  12. 一种显示装置，包括：显示面板和如权利要求1至11任一项所述的 电路板组件；
    所述电路板组件中的第一电路板和第二电路板分别与所述显示面板连接。
  13. 一种终端，包括：如权利要求12所述的显示装置。
  14. 一种信号处理系统，包括：客户端和如权利要求13所述的终端；
    所述客户端用于向所述终端发送显示信号；
    所述终端用于将显示信号转换为差分信号。
  15. 根据权利要求14所述的系统，其中，所述终端包括：设置在电路板组件上的时序控制器；
    所述时序控制器与所述客户端连接，用于将客户端发送的显示信号转换为差分信号。
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