WO2021218390A1 - 显示基板、显示装置 - Google Patents
显示基板、显示装置 Download PDFInfo
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- WO2021218390A1 WO2021218390A1 PCT/CN2021/079653 CN2021079653W WO2021218390A1 WO 2021218390 A1 WO2021218390 A1 WO 2021218390A1 CN 2021079653 W CN2021079653 W CN 2021079653W WO 2021218390 A1 WO2021218390 A1 WO 2021218390A1
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- 239000000758 substrate Substances 0.000 title claims abstract description 60
- 239000003990 capacitor Substances 0.000 claims description 18
- 239000010410 layer Substances 0.000 description 22
- 230000000694 effects Effects 0.000 description 9
- 239000011229 interlayer Substances 0.000 description 8
- 238000010586 diagram Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 4
- 230000009977 dual effect Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000004364 calculation method Methods 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
Definitions
- the embodiments of the present disclosure relate to the field of display technology, and particularly to display substrates and display devices.
- Each pixel unit is usually provided with multiple transistors for transmitting signals to realize the display function.
- the state of a certain transistor is unstable, it may cause the signal transmitted through it to change, thereby affecting the display effect of the pixel unit.
- the embodiments of the present disclosure provide a display substrate and a display device, which can at least partially solve the technical problem that the state of some dual-gate transistors in the existing display substrate is unstable, thereby affecting the display effect.
- embodiments of the present disclosure provide a display substrate including a base and a plurality of pixel units arranged in an array arranged on the base, the array having opposite first and second sides; wherein,
- Each of the pixel units includes at least one constant voltage terminal and at least one double-gate transistor; each of the double-gate transistors includes two gates arranged at intervals, and the active region of the double-gate transistor is located between the two gates The part is the middle part;
- each of the other pixel units also includes a compensation structure; the compensation structure is connected to a constant voltage end of the pixel unit where it is located, and compensates in the direction close to the first side At least one double-gate transistor of a pixel unit adjacent to the pixel unit where it is located;
- the compensation structure and the middle part of the double-gate transistor that it compensates are overlapped and insulated; the compensation structure and the two gates of the double-gate transistor that it compensates are located in the active area of the double-gate transistor relative to the substrate. Same side
- the pixel unit closest to the second side is a redundant pixel unit, and the redundant pixel unit is not used for display.
- each pixel unit further includes a first constant voltage terminal, a second constant voltage terminal, and a driving transistor and a light emitting device connected in series between the first constant voltage terminal and the second constant voltage terminal;
- the driving transistor is used to control the current passing through it according to the voltage of its gate
- the light emitting device of the redundant pixel unit has no light emitting function.
- the light-emitting device is an organic light-emitting diode.
- the compensation structure is connected to the first constant voltage end of the pixel unit where it is located.
- the compensation structure is connected to the second constant voltage end of the pixel unit where it is located.
- each of the pixel units includes a first double-gate transistor; the first electrode of the first double-gate transistor is connected to the gate of the driving transistor; the first double-gate transistor is used to transmit a data voltage To the gate of the drive transistor
- the first dual-gate transistor of each other pixel unit is compensated by the compensation structure.
- the second electrode of the first dual-gate transistor is connected to the second electrode of the driving transistor.
- each of the pixel units further includes a data terminal, a gate line terminal, a control terminal, a switching transistor, a first control transistor, a second control transistor, and a storage capacitor;
- the gate of the first control transistor is connected to the control terminal, the first electrode is connected to the first constant voltage terminal, and the second electrode is connected to the first electrode of the driving transistor;
- the gate of the second control transistor is connected to the control terminal, the first electrode is connected to the second electrode of the driving transistor, and the second electrode is connected to the first electrode of the light emitting device;
- the second pole of the light emitting device is connected to the second constant voltage terminal
- the gate of the switch transistor is connected to the gate line terminal, the first electrode is connected to the first electrode of the driving transistor, and the second electrode is connected to the data terminal;
- the gate of the first double-gate transistor is connected to the gate terminal
- the first pole of the storage capacitor is connected to the first constant voltage terminal, and the second pole is connected to the gate of the driving transistor.
- each of the pixel units further includes an initial signal terminal, a reset terminal, a first reset transistor, and a second reset transistor;
- the gate of the first reset transistor is connected to the reset terminal, the first electrode is connected to the gate of the driving transistor, and the second electrode is connected to the initial signal terminal;
- the gate of the second reset transistor is connected to the reset terminal, the first electrode is connected to the first electrode of the light emitting device, and the second electrode is connected to the initial signal terminal.
- the plurality of pixel units in the array are arranged in rows and columns;
- Each row of the pixel unit is connected to a gate line, and each column of the pixel unit is connected to a data line;
- the direction from the first side to the second side is parallel to the row direction
- the pixel units in the column closest to the second side are redundant pixel units.
- a display device which includes:
- the display device further includes:
- a frame provided on the light emitting side of the display substrate
- the orthographic projection of the frame on the display substrate covers the redundant pixel unit and does not overlap with other pixel units except the redundant pixel unit.
- FIG. 1 is a schematic diagram of a top view structure of a display substrate provided by an embodiment of the disclosure
- FIG. 2 is a schematic diagram of a top view of a dual-gate transistor in the related art
- Fig. 3 is a schematic cross-sectional structure view along AA' in Fig. 2;
- FIG. 4 is a partial top view structural diagram of a dual-gate transistor and a compensation structure in a part of pixel units in a display substrate provided by an embodiment of the present disclosure
- Fig. 5 is a schematic cross-sectional structure view along BB' in Fig. 4;
- FIG. 6 is a schematic diagram of an equivalent circuit structure of a pixel unit in a display substrate provided by an embodiment of the disclosure.
- FIG. 7 is a schematic diagram of a driving sequence of a pixel unit in a display substrate provided by an embodiment of the disclosure.
- FIG. 8 is a schematic view of a partial top view of a partial pixel unit in a display substrate according to an embodiment of the present disclosure
- Pixel unit 2. Compensation structure; 51, gate; 52, active area; 521, middle part; 531, source; 532, drain; 8. substrate; 81, gate insulating layer; 82, first Interlayer insulating layer; 83, second interlayer insulating layer; 89, via hole; 91, gate line; 92, data line; TD, driving transistor; TK, switching transistor; TC1, first control transistor; TC2, first Two control transistors; TR1, first reset transistor; TR2, second reset transistor; TS, first double gate transistor; CST, storage capacitor; DATA, data terminal; GATE, gate line terminal; EM, control terminal; RESET, reset terminal; VINT, initial signal terminal; VDD, first constant voltage terminal; VSS, second constant voltage terminal.
- embodiments of the present disclosure provide a display substrate.
- the display substrate of the embodiment of the present disclosure is a substrate used in a display device to realize a display function.
- the display substrate may be an array substrate for organic light emitting diode (OLED) display.
- OLED organic light emitting diode
- the display substrate of the embodiment of the present disclosure includes a base 8 and a plurality of pixel units 1 arranged on the base 8 in an array.
- the array has a first side and a second side opposite to each other.
- each pixel unit 1 includes at least one constant voltage terminal and at least one double-gate transistor; each double-gate transistor includes two gates arranged at intervals, and the active area 52 of the double-gate transistor is located between the two gates 51. Part is the middle part 521.
- each other pixel unit 1 also includes a compensation structure 2; At least one dual-gate transistor of the pixel unit 1 adjacent to the pixel unit 1;
- the compensation structure 2 and the middle part 521 of the double-gate transistor that it compensates are overlapped and insulated; the compensation structure 2 and the two gates 51 of the double-gate transistor that it compensates are located in the active area of the double-gate transistor relative to the substrate 8 52 on the same side;
- the pixel unit 1 closest to the second side is the redundant pixel unit 11, and the redundant pixel unit 11 is not used for display.
- a plurality of pixel units 1 arranged on a base 8 are displayed on a frame of a substrate.
- Each pixel unit 1 is a minimum unit that can independently control its display content.
- the pixel unit 1 is also called a "sub-pixel” or a "pixel”.
- a plurality of pixel units 1 are arranged in an array, so that a desired picture can be displayed together.
- the above array has a first side and a second side opposite to each other, such as the left side and the right side in FIG. 1.
- Each pixel unit 1 has a pixel circuit for realizing display, and the pixel circuit includes a plurality of transistor edges, and at least one of these transistors is a double-gate transistor (double-gate transistor).
- the double-gate transistor has an active region 52, and both ends of the active region 52 are respectively connected to the source 531 and the drain 532 (that is, the first electrode and the second electrode of the transistor).
- the double-gate transistor also includes two gates 51 arranged at intervals. Of course, the two gates 51 should be electrically connected to each other, so they always have the same signal.
- the portion (channel) of the active region 52 between the source electrode 531 and the drain electrode 532 overlaps the two gates and is separated by the gate insulating layer 81 to be insulated from each other.
- the active region 52 also has One part corresponds to the interval between the two gates 51, and this part is called the middle part 521 of the double-gate transistor.
- each of the other pixel units 1 also has a "compensation structure 2", which is 2 is connected to a constant voltage terminal of the pixel unit 1 where it is located, so it has a fixed voltage during operation.
- each pixel unit 1 also extends to the pixel unit 1 adjacent to the pixel unit 1 in the first side direction (as shown in Figure 1 for each pixel unit 1
- the compensation structure 2 extends to the pixel unit 1 on the left side thereof, and compensates for the double-gate transistor therein.
- the compensation structure 2 and the gate 51 of the double-gate transistor for compensation should be located on the same side of the active area 52 of the double-gate transistor with respect to the substrate 8 (that is, the side where external light may enter, as shown in FIG. 4).
- the upper side of the source region 52 for example, are all on the side of the active region 52 close to the substrate 8, or all on the side of the active region 52 away from the substrate 8.
- the double-gate transistor is of the top-gate type as an example, that is, the gate 51 is located on the side of the active region 52 away from the substrate 8; therefore, the compensation structure 2 in FIG. 4 should also be located in the active area.
- the area 52 is away from the side of the substrate 8 and the light incident from the outside should come from the side of the active area 52 away from the substrate 8 (ie, incident from top to bottom in FIG. 4 ).
- the display substrate also has other structures such as a first interlayer insulating layer 81 and a second interlayer insulating layer 82, which will be described in detail later.
- the dual-gate transistor is of a bottom-gate type, or other structures are different, it is also feasible.
- the above compensation structure 2 may specifically be that after a certain constant voltage end of the pixel unit 1 is connected, it extends in the direction of the first side (such as the left side) and enters the pixel unit 1 adjacent to the first side. , And overlap the middle portion 521 of the active region 52 of the corresponding first transistor.
- FIG. 4 only shows the compensation structure 2 and the compensated dual-gate transistor, but this does not mean that the pixel unit 1 only has the structure shown in the figure.
- Double-gate transistors have better electrical performance than conventional transistors. For example, the leakage current of double-gate transistors is generally lower.
- the part of the active region 52 of the double-gate transistor between the two gates 51 does not have a corresponding gate, so it may be irradiated by light from outside, which affects the performance of the double-gate transistor, and thus Affect the display.
- the above compensation structure 2 overlaps with the middle part 521 of the double gate transistor, so the two are equivalent to forming a capacitor. Therefore, the voltage change in the compensation structure 2 will change the voltage of the middle part 521 through induction, which will also affect show. For this reason, the compensation structure 2 should be connected to the constant voltage terminal so that the voltage therein is fixed, which is equivalent to fixing the voltage at one end of the above capacitor, so that the above capacitor can stabilize the voltage of the middle part 521 of the double gate transistor and improve display effect.
- the position closest to the second side of the above array (the rightmost column in FIG. 1) is a dummy pixel unit 11 (dummy pixel), and the redundant pixel unit 11 is not actually used for display.
- pixel units 1 except for the redundant pixel units 11 should be pixel units 1 (normal pixel units 12) that can be used for display.
- a column of pixel units can be set aside for arranging a column of redundant pixel units 11
- the column of redundant pixel units 11 can protect the conventional pixel units 12 and facilitate layout design, but it is not used for actual display.
- the redundant pixel unit 11 is not used for actual display.
- the pixel unit 1 uses an organic light-emitting diode (OLED) as a light-emitting device for display, it may be that the organic light-emitting diode of the redundant pixel unit 11 lacks one or more of the cathode, the light-emitting layer, and the anode and cannot emit light; or It may also be that the pixel defining layer (PDL) of the redundant pixel unit 11 has no openings, so that the light-emitting layer of the redundant pixel unit 11 is not in contact with one of the cathode and the anode and cannot emit light.
- OLED organic light-emitting diode
- the redundant pixel unit 11 lacks one or more structures (such as transistors, wires, etc.), or the wires are disconnected at some positions, so that the circuit cannot realize the display function.
- the redundant pixel unit 11 lacks a part of the structure, so that it loses the display function (because the compensation structure 2 is not directly related to the display function, the redundant pixel unit 11 It must have a compensation structure 2); but for the structures in both the redundant pixel unit 11 and the conventional pixel unit 12, the relative position, shape, size, layer, etc. of the structure in the redundant pixel unit 11 should be the same as those of the conventional The corresponding structures in the pixel unit 12 are the same.
- the redundant pixel unit 11 may have only one constant voltage end and the compensation structure 2 (but at this time, it is still regarded as one pixel unit 1).
- the redundant pixel unit 11 may not input part (such as data voltage) so that it cannot be displayed. Specifically, it may be that the redundant pixel unit 11 is not connected to the corresponding signal port (such as the port of the driver chip). It can be that the corresponding signal port does not output a signal,
- the redundant pixel unit 11 is blocked by other additional structures, so that although it can emit light, it will not be seen by the user, and thus will not be actually displayed.
- each pixel unit 1 since the compensation structure 2 of each pixel unit 1 compensates for the double-gate transistor of the pixel unit 1 on its first side (such as the left side), most of the conventional pixel units 12 that are actually used for display All double-gate transistors can be compensated.
- the second side of the conventional pixel unit 12 on the second side does not have a conventional pixel unit, so the dual-gate transistor therein will not be compensated by the compensation structure 2 in other conventional pixel units 12.
- the conventional pixel unit 12 on the second side (such as the rightmost side) is different from other conventional pixel units 12, that is, the second side (such as The middle portion 521 of the dual-gate transistor of the conventional pixel unit 12 on the far right side is not blocked and cannot form a capacitor, so the display effect of the conventional pixel unit 12 on the second side (such as the far right side) will be similar to that of other conventional pixels.
- the pixel unit 12 is different, which causes poor display (for example, a dark line appears on the far right side).
- the double-gate transistor in the conventional pixel unit 12 closest to the second side is compensated by providing redundant pixel units 11 (of course, there is a compensation structure 2).
- the intermediate portion 521 of the double-gate transistor in the conventional pixel unit 12 in all positions is formed to be shielded and form the same capacitance, so its signal transmission performance is also the same, to avoid the display effect of the conventional pixel unit 12 being different, that is, to avoid The display is poor; and the redundant pixel unit 11 does not display at all, so although the dual gate transistors therein are not compensated, the display effect will not be affected.
- a plurality of pixel units 1 in the array are arranged in rows and columns;
- Each row of pixel units 1 is connected to a gate line 91, and each column of pixel units 1 is connected to a data line 92;
- the direction from the first side to the second side is parallel to the row direction
- the column of pixel units 1 closest to the second side is a redundant pixel unit 11.
- the above multiple pixel units 1 can be arranged in an array in rows and columns, and the above first side and second side are the two sides along the row direction (the left and right sides in FIG. 1). Side), so the redundant pixel unit 11 is the column of pixel units 1 closest to the second side (the rightmost column of pixel units 1 in FIG. 1).
- each row of pixel units 1 is connected to a gate line 91 (for example, the gate line terminal GATE of the pixel unit 1 is connected to a gate line 91), and each column of pixel units 1 is connected to a data line 92 (for example, the data terminal DATA of the pixel unit 1). Connect a data line 92).
- each pixel unit 1 further includes a first constant voltage terminal VDD, a second constant voltage terminal VSS, and a driving transistor TD connected in series between the first constant voltage terminal VDD and the second constant voltage terminal VSS.
- Device EL
- the driving transistor TD is used to control the current passing through it according to the voltage of its gate;
- the light emitting device EL of the redundant pixel unit 11 has no light emitting function.
- each pixel unit 1 may be provided with a driving transistor TD and a light emitting device EL connected in series between the first constant voltage terminal VDD and the second constant voltage terminal VSS.
- the first constant voltage terminal VDD and the second constant voltage terminal VSS are used to provide a working voltage for the light emitting device EL to emit light.
- the first constant voltage terminal VDD provides a high voltage
- the second constant voltage terminal VSS provides a low voltage.
- the light emitting device EL in the redundant pixel unit 11 should not have the function of emitting light.
- the light emitting device EL is an organic light emitting diode.
- the above light-emitting device EL may specifically be in the form of an organic light-emitting diode (OLED), that is, the display substrate may be an array substrate for organic light-emitting diode display.
- OLED organic light-emitting diode
- the compensation structure 2 is connected to the first constant voltage terminal VDD of the pixel unit 1 where it is located.
- the compensation structure 2 is connected to the second constant voltage terminal VSS of the pixel unit 1 where it is located.
- the compensation structure 2 can be connected to the above first constant voltage terminal VDD or the second constant voltage terminal VSS to obtain a fixed voltage, that is, the compensation structure 2 can be connected to the first constant voltage terminal VDD or the second constant voltage terminal VSS.
- the second constant voltage terminal VSS is connected.
- the compensation structure 2 is connected to other constant voltage terminals in the pixel unit 1, it is also feasible.
- each pixel unit 1 includes a first double-gate transistor TS; the first electrode of the first double-gate transistor TS is connected to the gate of the driving transistor TD; the first double-gate transistor TS is used to transmit the data voltage to The gate of the driving transistor TD.
- the first dual gate transistor TS of each other pixel unit 1 is compensated by the compensation structure 2.
- each pixel unit 1 has at least one transistor whose one end is connected to the gate of the driving transistor TD is a double-gate transistor (first double-gate transistor TS), and the first double-gate transistor TS is used to transfer a data voltage (from The data line terminal DATA) is transmitted to the gate of the driving transistor TD to control the current in the driving transistor TD, that is, to control the display.
- first double-gate transistor TS double-gate transistor
- the above first double-gate transistor TS must be compensated by the compensation structure 2 (that is, the compensation structure 2 of the pixel unit 1 on the second side thereof) (that is, the middle portion 521 of the first double-gate transistor TS overlaps with the compensation structure 2 and Insulated from each other).
- first double-gate transistor TS directly affects the voltage of the gate of the driving transistor TD, that is, directly affects the display, if these transistors are double-gate transistors, compensation is even more necessary.
- transistors for example, the first reset transistor TR1 in the pixel unit 1 may be double-gate transistors, and these double-gate transistors may be compensated by the compensation structure 2 or not.
- the second electrode of the first double-gate transistor TS is connected to the second electrode of the driving transistor TD.
- the first double-gate transistor TS to be compensated above can be connected between the second electrode and the gate of the driving transistor TD, and these transistors are more likely to affect the display effect of the pixel unit 1, and need to be compensated for. Stabilize its state.
- each pixel unit 1 further includes a data terminal DATA, a gate line terminal GATE, a control terminal EM, a switching transistor TK, a first control transistor TC1, a second control transistor TC2, and a storage capacitor CST;
- the gate of the first control transistor TC1 is connected to the control terminal EM, the first electrode is connected to the first constant voltage terminal VDD, and the second electrode is connected to the first electrode of the driving transistor TD;
- the gate of the second control transistor TC2 is connected to the control terminal EM, the first electrode is connected to the second electrode of the driving transistor TD, and the second electrode is connected to the first electrode of the light emitting device EL;
- the second pole of the light emitting device EL is connected to the second constant voltage terminal VSS;
- the gate of the switching transistor TK is connected to the gate line terminal GATE, the first electrode is connected to the first electrode of the driving transistor TD, and the second electrode is connected to the data terminal DATA;
- the gates (two gates) of the first double-gate transistor TS are connected to the gate line terminal GATE;
- the first electrode of the storage capacitor CST is connected to the first constant voltage terminal VDD, and the second electrode is connected to the gate of the driving transistor TD.
- the above first double-gate transistor TS can be connected to the data terminal DATA through the driving transistor TD and the switching transistor TK to write a data voltage to the gate of the driving transistor TD.
- each pixel unit 1 further includes an initial signal terminal VINT, a reset terminal RESET, a first reset transistor TR1, and a second reset transistor TR2;
- the gate of the first reset transistor TR1 is connected to the reset terminal RESET, the first electrode is connected to the gate of the driving transistor TD, and the second electrode is connected to the initial signal terminal VINT;
- the gate of the second reset transistor TR2 is connected to the reset terminal RESET, the first electrode is connected to the first electrode of the light emitting device EL, and the second electrode is connected to the initial signal terminal VINT.
- the first constant voltage terminal VDD or the second constant voltage terminal VSS in 1) which is equivalent to a capacitor (the capacitor in the dashed line in FIG. 6) connected between the middle portion 521 of the first dual-gate transistor TS and the constant voltage terminal.
- the driving process may specifically include:
- Reset stage provide a turn-off signal to the gate line terminal GATE (connected to the gate line 91), provide a turn-on signal to the reset terminal RESET, and provide a turn-on signal to the control terminal EM.
- the turn-on signal refers to the signal that can turn on the transistor when it is loaded on the gate of the transistor
- the turn-off signal refers to the signal that turns the transistor off when it is loaded on the gate of the transistor.
- the transistor is a P-type transistor as an example for description, so the turn-on signal is a low voltage, and the turn-off signal is a high voltage.
- the turn-on signal is a high voltage
- the turn-off signal is a low voltage
- the gate and the second electrode of the driving transistor TD are reset to the signal of the initial signal terminal VINT (if also the initial voltage); and the first electrode of the driving transistor TD is the first constant voltage terminal High voltage signal of VDD.
- the data voltage for the pixel unit 1 is written to the gate of the driving transistor TD via the switching transistor TK, the driving transistor TD, and the first double-gate transistor TS. Therefore, the gate voltage of the driving transistor TD is the same as the data voltage A value related to the threshold voltage Vth of the driving transistor TD, and the storage capacitor CST has a high voltage at the first constant voltage terminal VDD at one end and the gate voltage of the driving transistor TD at the other end.
- Light-emitting stage provide a turn-off signal to the gate line terminal GATE, provide a turn-off signal to the reset terminal RESET, and provide a turn-on signal to the control terminal EM.
- the end (the second pole) of the storage capacitor CST connected to the gate of the driving transistor TD is in a floating state, so the two ends of the storage capacitor CST maintain the previous voltage difference, thereby eliminating the threshold voltage drift of the driving transistor TD.
- the current flowing through the driving transistor TD is accurately controlled, so that the light-emitting device EL (such as an organic light-emitting diode) continues to emit light at an intensity corresponding to the data voltage for display until the reset phase in the next frame arrives.
- each structure in the above pixel unit 1 can refer to FIG. 8.
- the two gates 51 of the double-gate transistor are located under the step structure on the upper right side of the boundary of the pixel unit 1 in the figure (the big dashed frame in the figure), and between the two gates 51
- the middle part 521 of the active region 52 of the active region has a “turned” shape, and the compensation structure 2 enters the pixel unit 1 from the right side and overlaps the middle part 521; specifically, the compensation structure 2 is connected to the pixel unit 1 through a via 89
- the lead of the first voltage terminal VDD is connected.
- the active region of each transistor can be directly provided on the substrate 8 and covered by the gate insulating layer 81.
- the gate line 91, the gate line terminal GATE, the gate of each transistor, and the first electrode of the storage capacitor CST (also the gate of the driving transistor TD) are arranged on the gate insulating layer 81 and are insulated by the first layer Layer 82 covers.
- the second pole of the storage capacitor CST and the compensation structure 2 are arranged on the first interlayer insulating layer 82 and covered by the second interlayer insulating layer 83.
- the source and drain (first electrode and second electrode) of each transistor, the data line 92, the data line terminal DATA, and the first constant voltage terminal VDD are arranged on the second interlayer insulating layer 83.
- the first constant voltage terminal VDD and the compensation structure 2 are connected through the via 89 in the second interlayer insulating layer 83; and for other structures located in different layers, if they need to be connected, they can also be connected through the corresponding insulating layer. Via connection.
- the above layout design avoids unnecessary overlap, thereby allowing the compensation structure 2 to be easily introduced into the adjacent pixel unit 1.
- the specific forms of the pixel unit 1 are various, and the number of transistors, the connection mode, etc. may be different; and the transistors of the double-gate structure among the transistors may also be different, and The double-gate transistor compensated by the compensation structure 2 may also be different.
- a display device which includes:
- the above display substrate can be combined with other devices (such as a box substrate, a housing, a driving circuit, a power supply, etc.) to form a display device with a complete display function.
- other devices such as a box substrate, a housing, a driving circuit, a power supply, etc.
- the display device further includes:
- the orthographic projection of the frame on the display substrate covers the redundant pixel units and does not overlap with other pixel units except for the redundant pixel units.
- the display device may have a frame visible on the light emitting side (display side), and the frame is a part of the housing and is arranged around the display area.
- the above redundant pixel units cannot actually display, so they can be blocked by the frame, and at the same time, the frame exposes other pixel units (conventional pixel units), so the actual display effect is not affected.
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- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
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- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Electroluminescent Light Sources (AREA)
- Control Of El Displays (AREA)
Abstract
Description
Claims (12)
- 一种显示基板,包括基底和设于基底上的多个排成阵列的像素单元,所述阵列具有相对的第一侧和第二侧;其中,每个所述像素单元包括至少一个定压端和至少一个双栅晶体管;每个所述双栅晶体管包括两个间隔设置的栅极,所述双栅晶体管的有源区位于两个栅极间的部分为中间部;除最靠近第一侧的所述像素单元外,其它每个所述像素单元还包括补偿结构;所述补偿结构与其所在像素单元的一个定压端连接,并补偿在靠近第一侧的方向上与其所在像素单元相邻的像素单元的至少一个双栅晶体管;所述补偿结构与其补偿的双栅晶体管的中间部具有交叠且绝缘;所述补偿结构和其补偿的双栅晶体管的两个栅极,相对于基底均位于该双栅晶体管的有源区的同一侧;最靠近第二侧的所述像素单元为冗余像素单元,所述冗余像素单元不用于进行显示。
- 根据权利要求1所述的显示基板,其中,每个所述像素单元还包括第一定压端、第二定压端,以及串联在所述第一定压端、第二定压端间的驱动晶体管、发光器件;所述驱动晶体管用于根据其栅极的电压控制经过其的电流;所述冗余像素单元的发光器件无发光功能。
- 根据权利要求2所述的显示基板,其中,所述发光器件为有机发光二极管。
- 根据权利要求2所述的显示基板,其中,所述补偿结构与其所在像素单元的第一定压端连接。
- 根据权利要求2所述的显示基板,其中,所述补偿结构与其所在像素单元的第二定压端连接。
- 根据权利要求2所述的显示基板,其中,每个所述像素单元包括第一双栅晶体管;所述第一双栅晶体管的第一极连接驱动晶体管的栅极;所述第一双栅晶体管用于将数据电压传输至驱动晶体管的栅极;除所述冗余像素单元外,其它每个所述像素单元的第一双栅晶体管均被补偿结构补偿。
- 根据权利要求6所述的显示基板,其中,所述第一双栅晶体管的第二极连接驱动晶体管的第二极。
- 根据权利要求7所述的显示基板,其中,每个所述像素单元还包括数据端、栅极线端、控制端、开关晶体管、第一控制晶体管、第二控制晶体管、存储电容;所述第一控制晶体管的栅极连接控制端,第一极连接第一定压端,第二极连接驱动晶体管的第一极;所述第二控制晶体管的栅极连接控制端,第一极连接驱动晶体管的第二极,第二极连接发光器件的第一极;所述发光器件的第二极连接第二定压端;所述开关晶体管的栅极连接栅极线端,第一极连接驱动晶体管的第一极,第二极连接数据端;所述第一双栅晶体管的栅极连接栅极线端;所述存储电容的第一极连接第一定压端,第二极连接驱动晶体管 的栅极。
- 根据权利要求8所述的显示基板,其中,每个所述像素单元还包括初始信号端、重置端、第一重置晶体管、第二重置晶体管;所述第一重置晶体管的栅极连接重置端,第一极连接驱动晶体管的栅极,第二极连接初始信号端;所述第二重置晶体管的栅极连接重置端,第一极连接发光器件的第一极,第二极连接初始信号端。
- 根据权利要求1所述的显示基板,其中,所述阵列中的多个像素单元排成行和列;每行所述像素单元连接一条栅极线,每列所述像素单元连接一条数据线;从所述第一侧指向第二侧的方向平行于行方向;最靠近第二侧的一列所述像素单元为冗余像素单元。
- 一种显示装置,其包括:权利要求1至10中任意一项所述的显示基板。
- 根据权利要求11所述的显示装置,其中,还包括:设于所述显示基板的出光侧的边框;所述边框在显示基板上的正投影覆盖冗余像素单元,且与除所述冗余像素单元外的其它像素单元无交叠。
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