WO2021217910A1 - 四核射频线圈电路 - Google Patents

四核射频线圈电路 Download PDF

Info

Publication number
WO2021217910A1
WO2021217910A1 PCT/CN2020/103680 CN2020103680W WO2021217910A1 WO 2021217910 A1 WO2021217910 A1 WO 2021217910A1 CN 2020103680 W CN2020103680 W CN 2020103680W WO 2021217910 A1 WO2021217910 A1 WO 2021217910A1
Authority
WO
WIPO (PCT)
Prior art keywords
capacitor
inductor
diode
coil
terminal
Prior art date
Application number
PCT/CN2020/103680
Other languages
English (en)
French (fr)
Inventor
李烨
杜凤
李楠
杨兴
陈巧燕
刘新
郑海荣
Original Assignee
深圳先进技术研究院
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳先进技术研究院 filed Critical 深圳先进技术研究院
Priority to DE212020000824.8U priority Critical patent/DE212020000824U1/de
Priority to US17/921,465 priority patent/US20230204697A1/en
Publication of WO2021217910A1 publication Critical patent/WO2021217910A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R33/00—Arrangements or instruments for measuring magnetic variables
    • G01R33/20—Arrangements or instruments for measuring magnetic variables involving magnetic resonance
    • G01R33/28—Details of apparatus provided for in groups G01R33/44 - G01R33/64
    • G01R33/32—Excitation or detection systems, e.g. using radio frequency signals
    • G01R33/36—Electrical details, e.g. matching or coupling of the coil to the receiver
    • G01R33/3628—Tuning/matching of the transmit/receive coil
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R33/00—Arrangements or instruments for measuring magnetic variables
    • G01R33/20—Arrangements or instruments for measuring magnetic variables involving magnetic resonance
    • G01R33/28—Details of apparatus provided for in groups G01R33/44 - G01R33/64
    • G01R33/32—Excitation or detection systems, e.g. using radio frequency signals
    • G01R33/36—Electrical details, e.g. matching or coupling of the coil to the receiver
    • G01R33/3628—Tuning/matching of the transmit/receive coil
    • G01R33/3635—Multi-frequency operation
    • A—HUMAN NECESSITIES
    • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
    • A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
    • A61B5/00—Measuring for diagnostic purposes; Identification of persons
    • A61B5/05—Detecting, measuring or recording for diagnosis by means of electric currents or magnetic fields; Measuring using microwaves or radio waves 
    • A61B5/055—Detecting, measuring or recording for diagnosis by means of electric currents or magnetic fields; Measuring using microwaves or radio waves  involving electronic [EMR] or nuclear [NMR] magnetic resonance, e.g. magnetic resonance imaging
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R33/00—Arrangements or instruments for measuring magnetic variables
    • G01R33/20—Arrangements or instruments for measuring magnetic variables involving magnetic resonance
    • G01R33/28—Details of apparatus provided for in groups G01R33/44 - G01R33/64
    • G01R33/32—Excitation or detection systems, e.g. using radio frequency signals
    • G01R33/34—Constructional details, e.g. resonators, specially adapted to MR
    • G01R33/341—Constructional details, e.g. resonators, specially adapted to MR comprising surface coils
    • G01R33/3415—Constructional details, e.g. resonators, specially adapted to MR comprising surface coils comprising arrays of sub-coils, i.e. phased-array coils with flexible receiver channels
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R33/00—Arrangements or instruments for measuring magnetic variables
    • G01R33/20—Arrangements or instruments for measuring magnetic variables involving magnetic resonance
    • G01R33/28—Details of apparatus provided for in groups G01R33/44 - G01R33/64
    • G01R33/32—Excitation or detection systems, e.g. using radio frequency signals
    • G01R33/36—Electrical details, e.g. matching or coupling of the coil to the receiver
    • G01R33/3642—Mutual coupling or decoupling of multiple coils, e.g. decoupling of a receive coil from a transmission coil, or intentional coupling of RF coils, e.g. for RF magnetic field amplification
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R33/00—Arrangements or instruments for measuring magnetic variables
    • G01R33/20—Arrangements or instruments for measuring magnetic variables involving magnetic resonance
    • G01R33/28—Details of apparatus provided for in groups G01R33/44 - G01R33/64
    • G01R33/32—Excitation or detection systems, e.g. using radio frequency signals
    • G01R33/36—Electrical details, e.g. matching or coupling of the coil to the receiver
    • G01R33/3642—Mutual coupling or decoupling of multiple coils, e.g. decoupling of a receive coil from a transmission coil, or intentional coupling of RF coils, e.g. for RF magnetic field amplification
    • G01R33/365—Decoupling of multiple RF coils wherein the multiple RF coils have the same function in MR, e.g. decoupling of a receive coil from another receive coil in a receive coil array, decoupling of a transmission coil from another transmission coil in a transmission coil array

Definitions

  • the embodiments of the present application relate to nuclear magnetic resonance technology, for example, to a quad-core radio frequency coil circuit.
  • hydrogen atom magnetic resonance imaging has been relatively mature, but only hydrogen atom imaging can no longer meet the needs of humans for diagnosis of various diseases. Since multi-nuclear magnetic resonance imaging technology can be used to obtain morphological and metabolic information in biological systems, it has been In addition to hydrogen-1 (1H), there are researches on nuclides such as carbon-13 (13C), fluorine-19 (19F), sodium-23 (23Na), and phosphorus-31 (31P). With the development of magnetic resonance technology, three-tuned magnetic resonance radio frequency probes or coils have been proposed to meet the needs of detecting three different magnetic resonance (MR) sensitive nuclei.
  • MR magnetic resonance
  • the related technology uses lumped element technology to demonstrate the design in a small coil, and shows the feasibility of the design in tri-frequency operation for small sample MR imaging applications.
  • the difficulty of designing, manufacturing and debugging the multi-tuned coil has been greatly increased.
  • Channel radio frequency coil system In large sample imaging applications with high magnetic fields, multi-channel quad-core radio frequency (RF) coils may encounter technical challenges, the interaction between different nuclear channels, the mutual coupling between channels, and the complexity in high-intensity electromagnetic fields The electromagnetic wave behavior, dielectric and conductive biological samples, etc.
  • the common mode differential mode method or two geometrically isolated coils can be used to achieve this.
  • Double tuning coil design The above method is usually used for single-core quadrature coil design to improve SNR, but the coil can also be used as a dual resonance mode without using a quadrature configuration.
  • one of the two coils can be a loop tuned to 1H, and the other coil can be a butterfly, dual loop, monopole antenna, or tuned microstrip transmission line tuned to the other core.
  • Two independent coil loops can also be nested and combined to form a dual resonant unit; a dual-core resonant coil unit sharing one coil loop can be realized by inserting a resonant network at the coil port.
  • Most multi-nuclear magnetic resonance experiments are performed by separately acquiring images of single nuclei, and then registering the images acquired from each nucleus. This is not only time-consuming, but also because of the different coil settings and image resolution for image acquisition by each nucleus, it is difficult to successfully complete image registration.
  • One solution is to use multiple tuning coil arrays to simultaneously detect multi-core signals. However, the design of this type of coil is more complicated, and the interaction and crosstalk between each individually tuned coil element must be suppressed.
  • the present application provides a quad-core radio frequency coil circuit to realize multi-channel, multi-frequency, high-uniformity radio frequency excitation and high-sensitivity signal acquisition.
  • the quad-core radio frequency coil circuit includes:
  • a coil module configured to receive a nuclear magnetic test signal and generate an induction signal according to the nuclear magnetic test signal;
  • a front-end module is connected to the coil module, and is configured to generate the nuclear magnetic test signal and collect the induction signal.
  • the coil module includes a first coil array and a second coil array, and the center positions of the first coil array and the second coil array coincide.
  • the first coil array includes a first sub-coil array and a second sub-coil array
  • the first sub-coil array includes a plurality of first coil units
  • the plurality of first coil units are based on a first preset
  • the second sub-coil array includes a plurality of second coil units
  • the plurality of second coil units are superimposed and arranged based on a second preset phase difference
  • the second coil array includes a plurality of third coil units.
  • the coil unit, the plurality of third coil units are arranged in superposition based on a third preset phase difference.
  • the first coil unit includes: a first interface circuit and a first detuning circuit, the first detuning circuit is connected to the first interface circuit, and the first interface circuit is connected to the front end Module.
  • the first interface circuit includes: an input terminal IN1, an input terminal IN2, a capacitor C1, a capacitor C2, and an inductor L1.
  • the input terminal IN1 is connected to the first end of the capacitor C1, and the The second terminal is connected to the first terminal of the capacitor C2, the second terminal of the capacitor C2 is connected to the first terminal of the inductor L1, and the second terminal of the inductor L1 is connected to the first terminal of the capacitor C2.
  • the input terminal IN2 is connected to the second terminal of the capacitor C1.
  • the first detuning circuit includes: an inductor L2, an inductor L3, an inductor L4, an inductor L5, a capacitor C3, a capacitor C4, a capacitor C5, a diode D1, a diode D2, and a diode D3.
  • the terminal is connected to the first terminal of the capacitor C3, the second terminal of the inductor L2 is connected to the cathode of the diode D1, the anode of the diode D1 is connected to the second terminal of the capacitor C3, and the capacitor C4
  • the second end of the diode D2 is connected to the first end of the capacitor C3, the anode of the diode D2 is connected to the second end of the capacitor C4, and the cathode of the diode D2 is connected to the second end of the inductor L3, so
  • the first end of the inductor L3 is connected to the first end of the capacitor C4, the second end of the capacitor C5 is connected to the first end of the capacitor C4, and the anode of the diode D3 is connected to the first end of the capacitor C5.
  • the cathode of the diode D3 is connected to the second end of the inductor L4, the first end of the inductor L4 is connected to the first end of the capacitor C5, and the first end of the inductor L5 is connected to The second end of the capacitor C5 and the second end of the inductor L5 are connected to the first end of the capacitor C4; or, the first end of the inductor L2 is connected to the first end of the capacitor C3, so The second end of the inductor L2 is connected to the cathode of the diode D1, the anode of the diode D1 is connected to the second end of the capacitor C3, and the second end of the capacitor C4 is connected to the second end of the capacitor C3.
  • the anode of the diode D2 is connected to the first end of the capacitor C4, the cathode of the diode D2 is connected to the second end of the inductor L3, and the first end of the inductor L3 is connected to the capacitor C4
  • the anode of the diode D3 is connected to the second end of the capacitor C5, the cathode of the diode D3 is connected to the second end of the inductor L4, and the first end of the inductor L4 is connected to the second end of the inductor L4.
  • the first terminal of the capacitor C5, the first terminal of the capacitive inductor L5 is connected to the first terminal of the capacitor C5, and the second terminal of the inductor L5 is connected to the first terminal of the capacitor C4.
  • the second coil unit includes: a second interface circuit and a second detuning circuit, the second detuning circuit is connected to the second interface circuit, and the second interface circuit is connected to the front end Module.
  • the second interface circuit includes: an input terminal IN1, an input terminal IN2, a capacitor C6, a capacitor C7, and an inductor L6, the input terminal IN1 is connected to the first end of the capacitor C6, and the The second terminal is connected to the first terminal of the capacitor C7, the second terminal of the capacitor C7 is connected to the first terminal of the inductor L6, and the second terminal of the inductor L6 is connected to the first terminal of the capacitor C7.
  • the input terminal IN2 is connected to the second terminal of the capacitor C6.
  • the second detuning circuit includes: an inductor L7, an inductor L8, an inductor L9, an inductor L10, a capacitor C8, a capacitor C9, a capacitor C10, a diode D4, a diode D5, and a diode D6;
  • the first terminal is connected to the first terminal of the capacitor C8, the second terminal of the inductor L7 is connected to the cathode of the diode D4, and the anode of the diode D4 is connected to the second terminal of the capacitor C8.
  • the second end of the capacitor C9 is connected to the first end of the capacitor C8, the anode of the diode D5 is connected to the second end of the capacitor C9, and the cathode of the diode D5 is connected to the second end of the inductor L8 ,
  • the first end of the inductor L8 is connected to the first end of the capacitor C9, the anode of the diode D6 is connected to the second end of the capacitor C10, and the cathode of the diode D6 is connected to the first end of the inductor L9
  • the first end of the inductor L9 is connected to the first end of the capacitor C10, the first end of the inductor L10 is connected to the second end of the capacitor C10, and the second end of the inductor L10 Connected to the first terminal of the capacitor C9; or, the first terminal of the inductor L7 is connected to the first terminal of the capacitor C8, and the second terminal of the inductor L7 is connected to the catho
  • the cathode of the diode D5 is connected to the second terminal of the inductor L8, the first terminal of the inductor L8 is connected to the second terminal of the capacitor C9, and the anode of the diode D6 is connected to the capacitor C10
  • the second terminal of the diode D6 is connected to the second terminal of the inductor L9
  • the first terminal of the inductor L9 is connected to the first terminal of the capacitor C10
  • the first terminal of the capacitive inductor L10 It is connected to the first end of the capacitor C10
  • the second end of the inductor L10 is connected to the first end of the capacitor C9.
  • the third coil unit includes: a third interface circuit and a third detuning circuit, the third detuning circuit is connected to the third interface circuit, and the third interface circuit is connected to the front end Module.
  • the third interface circuit includes: input terminal IN1, input terminal IN2, capacitor C11, capacitor C12, capacitor C13, capacitor C14, capacitor C15, variable capacitor B1, variable capacitor B2, inductor L11, and inductor L12 And inductor L13, the input terminal IN1 is connected to the first terminal of the capacitor C11, the second terminal of the capacitor C11 is connected to the first terminal of the capacitor C12, and the first terminal of the inductor L13 is connected to the first terminal of the capacitor C12.
  • the second end of the capacitor C12, the second end of the inductor L13 is connected to the first end of the capacitor C11, the first end of the capacitor C13 is connected to the second end of the capacitor C12, and the capacitor C13
  • the second end of the capacitor C14 is connected to the first end of the capacitor C14, the second end of the capacitor C14 is connected to the first end of the capacitor C15, and the second end of the capacitor C15 is connected to the input terminal IN2
  • the first end of the inductor L12 is connected to the second end of the capacitor C11, the second end of the inductor L12 is connected to the second end of the capacitor C15, and the first end of the inductor L11 is connected to the capacitor.
  • the first end of C14, the second end of the inductor L11 is connected to the second end of the capacitor C15, the first end of the variable capacitor B1 is connected to the first end of the capacitor C13, the variable capacitor The second terminal of B1 is connected to the second terminal of the capacitor C13, the first terminal of the variable capacitor B2 is connected to the first terminal of the capacitor C12, and the second terminal of the variable capacitor B2 is connected to the capacitor C15 The second end.
  • the third detuning circuit includes: a capacitor C16, a capacitor C17, a capacitor C18, a capacitor C19, an inductor L14, an inductor L15, an inductor L16, an inductor L17, a diode D7, a diode D8, and a diode D9; wherein, the The first end of the inductor L16 is connected to the first end of the capacitor C16, the second end of the inductor L16 is connected to the cathode of the diode D7, and the anode of the diode D7 is connected to the second end of the capacitor C16.
  • the second end of the capacitor C17 is connected to the first end of the capacitor C16, the first end of the capacitor C17 is connected to the second end of the capacitor C18, and the anode of the diode D8 is connected to the capacitor
  • the second end of C17, the cathode of the diode D8 is connected to the second end of the inductor L14, the first end of the inductor L14 is connected to the first end of the capacitor C18, and the anode of the diode D9 is connected to The second end of the capacitor C19, the cathode of the diode D9 is connected to the second end of the inductor L15, the first end of the inductor L15 is connected to the first end of the capacitor C19, and the The first terminal is connected to the first terminal of the capacitor C18, and the second terminal of the inductor L17 is connected to the second terminal of the capacitor C19; or, the first terminal of the inductor L16 is connected to the capacitor C16.
  • the second end of the inductor L16 is connected to the cathode of the diode D7, the anode of the diode D7 is connected to the second end of the capacitor C16, and the second end of the capacitor C18 is connected to the The second end of the capacitor C16, the first end of the capacitor C17 is connected to the first end of the capacitor C18, the anode of the diode D8 is connected to the second end of the capacitor C17, and the cathode of the diode D8 is connected To the second end of the inductor L14, the first end of the inductor L14 is connected to the second end of the capacitor C18, the anode of the diode D9 is connected to the second end of the capacitor C19, and the diode D9
  • the negative pole of is connected to the second end of the inductor L15, the first end of the inductor L15 is connected to the first end of the capacitor C19, and the first end of the inductor L17 is connected to the first end of the
  • the front-end module includes: a power division module and a signal drive module, the power division module is connected to the signal drive module, the signal drive module is connected to the coil module, and the power division module is configured to The nuclear magnetic test signal is split into multiple test signals, and the signal driving module is configured to input the multiple test signals into the coil module.
  • FIG. 1 is a module connection diagram of a quad-core radio frequency coil circuit provided by Embodiment 1 of the application;
  • FIG. 2 is a top view of the structure of the quad-core radio frequency coil circuit in the first embodiment of the application;
  • FIG. 3 is a circuit diagram of the first sub-coil array in the first embodiment of the application.
  • Fig. 5 is a circuit diagram of the coil Na2 in the first embodiment of the application.
  • Fig. 6 is a circuit diagram of the coil Na3 in the first embodiment of the application.
  • Fig. 7 is a circuit diagram of the coil Na4 in the first embodiment of the application.
  • Fig. 9 is a circuit diagram of the coil P1 in the first embodiment of the application.
  • Fig. 10 is a circuit diagram of the coil P2 in the first embodiment of the application.
  • FIG. 11 is a circuit diagram of the coil P3 in the first embodiment of the application.
  • Fig. 12 is a circuit diagram of the coil P4 in the first embodiment of the application.
  • FIG. 13 is a schematic diagram of the arrangement of the first coil array in the first embodiment of the application.
  • 16 is a circuit diagram of the coil H/F2 in the first embodiment of the application.
  • Fig. 17 is a circuit diagram of the coil H/F3 in the first embodiment of the application.
  • 19 is a circuit diagram of the front-end module in the second embodiment of the application.
  • 20 is a circuit diagram of a quad-core radio frequency coil circuit in the second embodiment of the application.
  • first”, “second”, etc. may be used herein to describe various directions, actions, steps or elements, etc., but these directions, actions, steps or elements are not limited by these terms. These terms are only used to distinguish a first direction, action, step or element from another direction, action, step or element.
  • the first coil array may be referred to as the second coil array
  • the second coil array may be referred to as the first coil array. Both the first coil array and the second coil array are coil arrays, but they are not the same coil array.
  • the terms “first”, “second”, etc. cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined with “first” and “second” may explicitly or implicitly include one or more of these features.
  • “plurality” means at least two, such as two, three, etc., unless specifically defined otherwise.
  • Fig. 1 is a module connection diagram of a quad-core radio frequency coil circuit provided in the first embodiment of the application. This embodiment is suitable for the case of using multiple radionuclide signals for nuclear magnetic resonance.
  • a quad-core radio frequency coil provided in this embodiment The circuit includes: coil module 1 and front-end module 2.
  • the coil module 1 is configured to receive the nuclear magnetic test signal and generate an induction signal according to the nuclear magnetic test signal.
  • the nuclear magnetic test signal is generated by a signal generator and other instruments for nuclear magnetic resonance imaging. Common nuclides are 1H (hydrogen), 13C (carbon), 19F (fluorine), 23Na (sodium) and 31P ( Phosphorus) and so on, the quad-core radio frequency coil circuit provided in this embodiment takes four nuclides 1H, 19F, 23Na, and 31P as examples for illustration.
  • the induction signal is the induction signal fed back by the user according to the nuclear magnetic test signal.
  • the coil module 1 collects the induction signal fed back by the user and can be transmitted to an instrument such as an oscilloscope for display.
  • the coil module 1 includes a first coil array 11 and a second coil array 12, and the center positions of the first coil array 11 and the second coil array 12 coincide.
  • Figure 2 is a top view of the structure of the quad-core radio frequency coil circuit in this embodiment.
  • the first coil array 11 and the second coil array 12 are designed with a double-layer nested structure.
  • the first coil array 11 includes a first sub-coil array and The second sub-coil array, the first sub-coil array includes 4 Na coils, the second sub-coil array includes 4 P coils, 4 Na coils form a circular structure, and 4 P coils form a circular structure, And the circular structure surrounded by 4 Na coils has the same radius and the same circle center as the circular structure surrounded by 4 P coils; the second coil array 12 includes 4 H/F coils and 4 H/F coils.
  • the coil also forms a circular structure, and the center of the circular structure coincides with the center of the circular structure surrounded by 4 Na coils and the center of the circular structure surrounded by 4 P coils.
  • the center line of the P coil in the plane of the vertical P coil (ignoring the arc of the coil) and the center line of the H/F coil in the plane of the vertical H/F coil coincide with each other, for example, coincide with the axis Z1 passing through the center of the circle.
  • the center line Z2 of the Na coil perpendicular to the plane of the Na coil (ignoring the coil radian) and the center line Z3 of the H/F coil perpendicular to the plane of the H/F coil (ignoring the coil radian) are different by 45°.
  • Na coil is a coil whose frequency is tuned to 23Na
  • P coil is a coil whose frequency is tuned to 31P
  • H/F coil is a coil whose frequency is tuned to 1H and 19F.
  • FIG. 3 is a circuit diagram of the first sub-coil array 11a.
  • the first sub-coil array 11a is illustrated by taking 4 Na coils as an example, and the first sub-coil array 11a includes a plurality of first coils.
  • Units coil Na1, coil Na2, coil Na3, and coil Na4
  • a plurality of first coil units are superimposed and arranged based on a first preset phase difference.
  • the coil Na1, the coil Na2, the coil Na3 and the coil Na4 are all Na coils.
  • the wires X2 and X3 of the coil Na1 and the wires X5 and X8 of the coil Na2 enclose the overlapping area M1 of area A1, and the wires X6 and X7 of the coil Na2 are connected with each other.
  • the wires X9 and X12 of the coil Na3 enclose the overlap area M2 of area A2, the wires X10 and X11 of the coil Na3 and the wires X13 and X16 of the coil Na4 enclose the overlap area M3 of the area A3, by dividing the first sub-coil
  • the multiple first coil units in the array 11a are superimposed and arranged to achieve the effect of decoupling adjacent coil channels and reduce the interference between the Na coils.
  • the coil Na1 in the first coil unit includes: a first interface circuit 111A and a first detuning circuit 112A.
  • the first detuning circuit 112A is connected to the first interface circuit 111A, and the first interface circuit 111A is connected to the front-end module 2.
  • the wire X1, the wire X2, the wire X3 and the wire X4 of the coil Na1 form a rectangular and convex structure.
  • the wire X1, the wire X3, and the wire X4 are L-shaped wires.
  • the wire X2 includes a Z-shaped wire and an L-shaped wire, Z A convex structure is formed between the L-shaped wire and the L-shaped wire to connect the inductor L5A, the wire X1 and the wire X4 are connected with the secondary detuning circuit composed of the inductor L2A, the diode D1A, and the capacitor C3A.
  • a secondary detuning circuit composed of inductance L3A, diode D2A and capacitor C4A is connected between the wire X2 and wire X3, and a secondary detuning circuit composed of inductor L4A, diode D3A and capacitor C5A is connected between wire X4 and wire X3.
  • the first interface circuit 111A is connected therebetween.
  • FIG. 4 is a circuit diagram of the coil Na1.
  • the first interface circuit 111A includes: an input terminal IN1A, an input terminal IN2A, a capacitor C1A, a capacitor C2A, and an inductor L1A.
  • the input terminal IN1A is connected to the first end of the capacitor C1A and the second end of the capacitor C1A Connect to the first end of the capacitor C2A, the second end of the capacitor C2A to the first end of the inductor L1A, the second end of the inductor L1A to the first end of the capacitor C2A, and the input terminal IN2A to the second end of the capacitor C1A .
  • the first detuning circuit 112A includes: an inductor L2A, an inductor L3A, an inductor L4A, an inductor L5A, a capacitor C3A, a capacitor C4A, a capacitor C5A, a diode D1A, a diode D2A, and a diode D3A.
  • the first end of the inductor L2A is connected to the first terminal of the capacitor C3A.
  • the second end of the inductor L2A is connected to the cathode of the diode D1A, the anode of the diode D1A is connected to the second end of the capacitor C3A, the second end of the capacitor C4A is connected to the first end of the capacitor C3A, and the anode of the diode D2A is connected to The second end of the capacitor C4A, the cathode of the diode D2A is connected to the second end of the inductor L3A, the first end of the inductor L3A is connected to the first end of the capacitor C4A, the anode of the diode D3A is connected to the second end of the capacitor C5A, and the diode D3A
  • the negative pole of the inductor is connected to the second end of the inductor L4A, the first end of the inductor L4A is connected to the first end of the capacitor C5A, the first end of the inductor L5A is connected to the second end of
  • Figure 5 is a circuit diagram of the coil Na2.
  • the wire X5, the wire X6, the wire X7 and the wire X8 of the coil Na2 form a rectangular and convex structure.
  • the wires X5, X7, and X8 are L-shaped wires.
  • the wire X6 includes a Z-shaped wire and an L-shaped wire.
  • a raised structure is formed between the Z-shaped wire and the L-shaped wire to connect the inductor L5B, and the wire X5 and the wire X8 are connected with an inductor L2B, a diode D1B, and a capacitor C3B.
  • the secondary detuning circuit composed of inductor L3B, diode D2B and capacitor C4B is connected between wire X5 and wire X6, and the inductor L4B, diode D3B and capacitor C5B are connected between wire X6 and wire X7.
  • the first interface circuit 111B is connected between the wire X8 and the wire X7.
  • the first interface circuit 111B includes: an input terminal IN1B, an input terminal IN2B, a capacitor C1B, a capacitor C2B, and an inductor L1B.
  • the input terminal IN1B is connected to the first terminal of the capacitor C1B, and the second terminal of the capacitor C1B is connected to the first terminal of the capacitor C2B.
  • the second end of the capacitor C2B is connected to the first end of the inductor L1B, the second end of the inductor L1B is connected to the first end of the capacitor C2B, and the input terminal IN2B is connected to the second end of the capacitor C1B.
  • the first detuning circuit 112B includes: an inductor L2B, an inductor L3B, an inductor L4B, an inductor L5B, a capacitor C3B, a capacitor C4B, a capacitor C5B, a diode D1B, a diode D2B, and a diode D3B.
  • the first end of the inductor L2B is connected to the first terminal of the capacitor C3B.
  • the second end of the inductor L2B is connected to the cathode of the diode D1B, the anode of the diode D1B is connected to the second end of the capacitor C3B, the second end of the capacitor C4B is connected to the first end of the capacitor C3B, and the anode of the diode D2B is connected to The second end of the capacitor C4B, the cathode of the diode D2B is connected to the second end of the inductor L3B, the first end of the inductor L3B is connected to the first end of the capacitor C4B, the anode of the diode D3B is connected to the second end of the capacitor C5B, and the diode D3B
  • the negative terminal of the inductor is connected to the second terminal of the inductor L4B, the first terminal of the inductor L4B is connected to the first terminal of the capacitor C5B, the first terminal of the inductor L5B is connected to the second terminal of
  • Figure 6 is a circuit diagram of the coil Na3.
  • the wire X9, the wire X10, the wire X11 and the wire X12 of the coil Na3 form a rectangular and convex structure.
  • the wires X10, X11, and X12 are L-shaped wires.
  • the wire X9 includes a Z-shaped wire and an L-shaped wire.
  • a raised structure is formed between the Z-shaped wire and the L-shaped wire to connect the inductor L5C, and the wire X10 and the wire X11 are connected with an inductor L2C, a diode D1C, and a capacitor C3C.
  • the secondary detuning circuit composed of inductor L3C, diode D2C and capacitor C4C is connected between wire X9 and wire X10, and the inductor L4C, diode D3C and capacitor C5C are connected between wire X9 and wire X12
  • the first interface circuit 111C is connected between the wire X11 and the wire X12.
  • the inductance L5A of the coil Na1 and the inductance L5C of the coil Na3 are arranged adjacent to each other corresponding to each other, and are used for decoupling between the coil Na1 and the coil Na3.
  • the first interface circuit 111C includes: an input terminal IN1C, an input terminal IN2C, a capacitor C1C, a capacitor C2C, and an inductor L1C.
  • the input terminal IN1C is connected to the first terminal of the capacitor C1C, and the second terminal of the capacitor C1C is connected to the first terminal of the capacitor C2C.
  • the second end of the capacitor C2C is connected to the first end of the inductor L1C, the second end of the inductor L1C is connected to the first end of the capacitor C2C, and the input terminal IN2C is connected to the second end of the capacitor C1C.
  • the first detuning circuit 112C includes: an inductor L2C, an inductor L3C, an inductor L4C, an inductor L5C, a capacitor C3C, a capacitor C4C, a capacitor C5C, a diode D1C, a diode D2C, and a diode D3C.
  • the first end of the inductor L2C is connected to the first terminal of the capacitor C3C.
  • the second end of the inductor L2C is connected to the cathode of the diode D1C
  • the anode of the diode D1C is connected to the second end of the capacitor C3C
  • the second end of the capacitor C4C is connected to the second end of the capacitor C3C
  • the anode of the diode D2C is connected to The first end of the capacitor C4C
  • the cathode of the diode D2C is connected to the second end of the inductor L3C
  • the first end of the inductor L3C is connected to the second end of the capacitor C4C
  • the anode of the diode D3C is connected to the second end of the capacitor C5C
  • the diode D3C is connected to the negative pole of the inductor
  • Figure 7 is a circuit diagram of the coil Na4.
  • the wire X13, the wire X14, the wire X15 and the wire X16 of the coil Na4 form a rectangular and convex structure.
  • the wires X14, X15, and X16 are L-shaped wires.
  • the wire X13 includes a Z-shaped wire and an L-shaped wire.
  • a raised structure is formed between the Z-shaped wire and the L-shaped wire to connect the inductor L5D, and the wire X14 and the wire X15 are connected with an inductor L2D, a diode D1D, and a capacitor C3D.
  • the secondary detuning circuit composed of inductor L3D, diode D2D and capacitor C4D is connected between wire X13 and wire X14, and the inductor L4D, diode D3D and capacitor C5D are connected between wire X13 and wire X16.
  • the first interface circuit 111D is connected between the wire X15 and the wire X16.
  • the inductance L5B of the coil Na2 and the inductance L5D of the coil Na4 are arranged adjacent to each other corresponding to each other, and are used for decoupling between the coil Na2 and the coil Na4.
  • the first interface circuit 111D includes: an input terminal IN1D, an input terminal IN2D, a capacitor C1D, a capacitor C2D, and an inductor L1D.
  • the input terminal IN1D is connected to the first terminal of the capacitor C1D
  • the second terminal of the capacitor C1D is connected to the first terminal of the capacitor C2D.
  • the second end of the capacitor C2D is connected to the first end of the inductor L1D
  • the second end of the inductor L1D is connected to the first end of the capacitor C2D
  • the input terminal IN2D is connected to the second end of the capacitor C1D.
  • the first detuning circuit 112D includes: an inductor L2D, an inductor L3D, an inductor L4D, an inductor L5D, a capacitor C3D, a capacitor C4D, a capacitor C5D, a diode D1D, a diode D2D, and a diode D3D.
  • the first end of the inductor L2D is connected to the first terminal of the capacitor C3D.
  • the second end of the inductor L2D is connected to the cathode of the diode D1D
  • the anode of the diode D1D is connected to the second end of the capacitor C3D
  • the second end of the capacitor C4D is connected to the second end of the capacitor C3D
  • the anode of the diode D2D is connected to The first end of the capacitor C4D
  • the cathode of the diode D2D is connected to the second end of the inductor L3D
  • the first end of the inductor L3D is connected to the second end of the capacitor C4D
  • the anode of the diode D3D is connected to the second end of the capacitor C5D
  • the diode D3D is connected to the first end of the inductor L4D
  • the first end of the inductor L4D is connected to the first end of the capacitor C5D
  • the first end of the inductor L5D is connected to the first end of
  • the second sub-coil array 11b includes a plurality of second coil units (coil P1, coil P2, coil P3, and coil P4), and the plurality of second coil units are superimposed and arranged based on a second preset phase difference.
  • Coil P1, coil P2, coil P3, and coil P4 are all P coils.
  • the wires X18 and X19 of the coil P1 and the wires X21 and X24 of the coil P2 enclose an overlapping area M4 with an area of A4, and the wires X22 and X23 of the coil P2 and the wires X25 and X28 of the coil P3 enclose an overlapping area of A5 M5, the wires X26 and X27 of the coil P3 and the wires X29 and X32 of the coil P4 enclose an overlapping area M6 with an area of A6.
  • the coil P1 in the second coil unit includes: a second interface circuit 113A and a second detuning circuit 114A.
  • the second detuning circuit 114A is connected to the second interface circuit 113A, and the second interface circuit 113A is connected to the front-end module 2.
  • the second interface circuit 113A includes: an input terminal IN1A, an input terminal IN2A, a capacitor C6A, a capacitor C7A, and an inductor L6A.
  • the input terminal IN1A is connected to the first end of the capacitor C6A, and the second end of the capacitor C6A is connected to the first end of the capacitor C7A.
  • the second detuning circuit 114A includes: an inductor L7A, an inductor L8A, an inductor L9A, an inductor L10A, a capacitor C8A, a capacitor C9A, a capacitor C10A, a diode D4A, a diode D5A, and a diode D6A.
  • the first end of the inductor L7A is connected to the capacitor The first end of C8A, the second end of inductor L7A is connected to the cathode of diode D4A, the anode of diode D4A is connected to the second end of capacitor C8A, the second end of capacitor C9A is connected to the first end of capacitor C8A, and the second end of diode D5A
  • the anode is connected to the second end of the capacitor C9A
  • the cathode of the diode D5A is connected to the second end of the inductor L8A
  • the first end of the inductor L8A is connected to the first end of the capacitor C9A
  • the anode of the diode D6A is connected to the second end of the capacitor C10A
  • the cathode of diode D6A is connected to the second end of inductor L9A, the first end of inductor L9A is connected to the first end of capacitor C10A, the first
  • the coil P2 in the second coil unit includes: a second interface circuit 113B and a second detuning circuit 114B.
  • the second detuning circuit 114B is connected to the second interface circuit 113B, and the second interface circuit 113B is connected to the front-end module 2.
  • the second interface circuit 113B includes: an input terminal IN1B, an input terminal IN2B, a capacitor C6B, a capacitor C7B, and an inductor L6B.
  • the input terminal IN1B is connected to the first terminal of the capacitor C6B, and the second terminal of the capacitor C6B is connected to the first terminal of the capacitor C7B.
  • the second end of the capacitor C7B is connected to the first end of the inductor L6B, the second end of the inductor L6B is connected to the first end of the capacitor C7B, and the input terminal IN2B is connected to the second end of the capacitor C6B.
  • the second detuning circuit 114B includes: an inductor L7B, an inductor L8B, an inductor L9B, an inductor L10B, a capacitor C8B, a capacitor C9B, a capacitor C10B, a diode D4B, a diode D5B, and a diode D6B.
  • the first end of the inductor L7B is connected to the first terminal of the capacitor C8B.
  • the second end of the inductor L7B is connected to the cathode of the diode D4B, the anode of the diode D4 B is connected to the second end of the capacitor C8 B, the second end of the capacitor C9 B is connected to the second end of the capacitor C8B, and the second end of the diode D5B
  • the anode is connected to the first end of the capacitor C9B
  • the cathode of the diode D5B is connected to the second end of the inductor L8B
  • the first end of the inductor L8B is connected to the second end of the capacitor C9B
  • the anode of the diode D6B is connected to the second end of the capacitor C10B
  • the cathode of the diode D6B is connected to the second end of the inductor L9B
  • the first end of the inductor L9B is connected to the first end of the capacitor C10B
  • the first end of the capacitor L10B is connected to the
  • the coil P3 in the second coil unit includes a second interface circuit 113C and a second detuning circuit 114C.
  • the second detuning circuit 114C is connected to the second interface circuit 113C, and the second interface circuit 113C is connected to the front-end module 2.
  • the second interface circuit 113C includes: an input terminal IN1C, an input terminal IN2C, a capacitor C6C, a capacitor C7C, and an inductor L6C.
  • the input terminal IN1C is connected to the first terminal of the capacitor C6C, and the second terminal of the capacitor C6C is connected to the first terminal of the capacitor C7C.
  • the second detuning circuit 114C includes: an inductor L7C, an inductor L8C, an inductor L9C, an inductor L10C, a capacitor C8C, a capacitor C9C, a capacitor C10C, a diode D4C, a diode D5C, and a diode D6C.
  • the first end of the inductor L7C is connected to The first end of the capacitor C8C and the second end of the inductor L7C are connected to the cathode of the diode D4C, the anode of the diode D4C is connected to the second end of the capacitor C8C, the second end of the capacitor C9C is connected to the second end of the capacitor C8C, and the diode D5C
  • the anode of the diode D5C is connected to the first end of the capacitor C9C
  • the cathode of the diode D5C is connected to the second end of the inductor L8C
  • the first end of the inductor L8C is connected to the second end of the capacitor C9C
  • the anode of the diode D6C is connected to the second end of the capacitor C10C.
  • the cathode of the diode D6C is connected to the second end of the inductor L9C, the first end of the inductor L9C is connected to the first end of the capacitor C10C, the first end of the inductor L10C is connected to the first end of the capacitor C10C, and the second end of the inductor L10C The terminal is connected to the first terminal of the capacitor C9C.
  • the coil P4 in the second coil unit includes a second interface circuit 113D and a second detuning circuit 114D.
  • the second detuning circuit 114D is connected to the second interface circuit 113D, and the second interface circuit 113D is connected to the front-end module 2.
  • the second interface circuit 113D includes: an input terminal IN1D, an input terminal IN2D, a capacitor C6D, a capacitor C7D, and an inductor L6D.
  • the input terminal IN1D is connected to the first terminal of the capacitor C6D, and the second terminal of the capacitor C6D is connected to the first terminal of the capacitor C7D ,
  • the second end of the capacitor C7D is connected to the first end of the inductor L6D, the second end of the inductor L6D is connected to the first end of the capacitor C7D, and the input terminal IN2D is connected to the second end of the capacitor C6D.
  • the second detuning circuit 114D includes: an inductor L7D, an inductor L8D, an inductor L9D, an inductor L10D, a capacitor C8D, a capacitor C9D, a capacitor C10D, a diode D4D, a diode D5D, and a diode D6D.
  • the first end of the inductor L7D is connected to the first terminal of the capacitor C8D.
  • the second end of the inductor L7D is connected to the cathode of the diode D4D
  • the anode of the diode D4 D is connected to the second end of the capacitor C8 D
  • the second end of the capacitor C9 D is connected to the second end of the capacitor C8D
  • the second end of the diode D5D The anode is connected to the first end of the capacitor C9D
  • the cathode of the diode D5D is connected to the second end of the inductor L8D
  • the first end of the inductor L8D is connected to the second end of the capacitor C9D
  • the anode of the diode D6D is connected to the second end of the capacitor C10D
  • the cathode of the diode D6D is connected to the second end of the inductor L9D
  • the first end of the inductor L9D is connected to the first end of the capacitor C10D
  • the first end of the capacitor L10D is connected to the
  • first sub-coil unit 11a and the second sub-coil unit 11b are similar, and will not be repeated here.
  • the first coil array 11 includes 4 Na coils and 4 P coils.
  • FIG. 13 is a schematic diagram of the arrangement of the first coil array 11 in Embodiment 1 of the application.
  • the 4 Na coils (coils Na1, coil Na2, coil Na3, and coil Na4) are decoupling between non-adjacent coils through the inductance of the rectangular outer convex part.
  • the 4 P coils (coil P1, coil P2, coil P3, and coil P4) also pass through the rectangular outer
  • the inductance of the protruding part realizes the decoupling of non-adjacent coils, and the decoupling between adjacent coils, such as the coil Na1 and the coil Na2, is achieved through the overlapping area.
  • the nuclear magnetic test signal is input to the first interface circuit 111 through the input terminal IN1 and the input terminal IN2 of the first interface circuit 111, and the working state of the Na coil is controlled by the first detuning circuit 112 to allow Na imaging
  • the nuclear magnetic test signal is input to the second interface circuit 113 through the input terminal IN1 and the input terminal IN2 of the second interface circuit 113, and the working state of the P coil is controlled by the second detuning circuit 114 to allow P imaging.
  • the value of the element in each coil can be adjusted according to actual conditions, which is not limited in this embodiment.
  • FIG. 14 is a circuit diagram of the second coil array 12.
  • the H/F coil can transmit radio frequency signals of nuclide H and nuclide F.
  • four H/F coils are taken as an example for description.
  • the second coil array 12 includes a plurality of third coil units (coil H/F 1, coil H/F2, coil H/F3, and coil H/F4), and the plurality of third coil units are superimposed and arranged based on the third preset phase difference , Coil H/F1, coil H/F2, coil H/F3, and coil H/F 4 are H/F coils.
  • the wires X34 and X35 of coil H/F1 and the wires X37 and X40 of coil H/F2 form an area It is the overlap area M7 of A7, the wires X38 and X39 of the coil H/F2 and the wires X41 and X44 of the coil H/F3 enclose the overlap area M8 of the area A8, and the wires X42 and X43 of the coil H/F3 and the coil H/
  • the wires X45 and X48 of F4 enclose an overlapping area M9 with an area of A9.
  • the coil H/F1 in the third coil unit includes a third interface circuit 121A and a third detuning circuit 122A.
  • the third detuning circuit 122A is connected to the third interface circuit 121A, and the third interface circuit 121A is connected to the front-end module 2.
  • Figure 15 is a circuit diagram of the coil H/F1 in this embodiment.
  • the wire X33, the wire X34, the wire X35 and the wire X36 of the coil H/F1 form a rectangular and convex structure, and the wire X33, the wire X35,
  • the wire X36 is an L-shaped wire, and the wire X34 includes a Z-shaped wire and an L-shaped wire.
  • a convex structure is formed between the Z-shaped wire and the L-shaped wire to connect the inductor L17A.
  • the wire X33 and the wire X36 are connected with the inductor L16A,
  • the secondary detuning circuit composed of diode D7A and capacitor C16A, the secondary detuning circuit composed of inductor L14A, diode D8A, capacitor C17A and capacitor C18A is connected between wire X33 and wire X34, and wire X34 and wire X35 are connected
  • a secondary detuning circuit composed of an inductor L15A, a diode D9A and a capacitor C19A, a third interface circuit 121A is connected between the wire X36 and the wire X35.
  • the third interface circuit 121A includes: input terminal IN1A, input terminal IN2A, capacitor C11A, capacitor C12A, capacitor C13A, capacitor C14A, capacitor C15A, variable capacitor B1A, variable capacitor B2A, inductor L11A, inductor L12A, and inductor L13A, input
  • the terminal IN1A is connected to the first terminal of the capacitor C11A
  • the second terminal of the capacitor C11A is connected to the first terminal of the capacitor C12A
  • the first terminal of the inductor L13A is connected to the second terminal of the capacitor C12A
  • the second terminal of the inductor L13A is connected to the capacitor
  • the first end of C11A, the first end of capacitor C13A is connected to the second end of capacitor C12A, the second end of capacitor C13A is connected to the first end of capacitor C14A, and the second end of capacitor C14A is connected to the first end of capacitor C15A
  • the second end of the capacitor C15A is connected to the input terminal IN
  • the third detuning circuit 122A includes: a capacitor C16A, a capacitor C17A, a capacitor C18A, a capacitor C19A, an inductor L14A, an inductor L15A, an inductor L16A, an inductor L17A, a diode D7A, a diode D8A, and a diode D9A.
  • the first end of the inductor L16A is connected to the capacitor The first end of C17A, the second end of inductor L16A is connected to the cathode of diode D7A, the anode of diode D7A is connected to the second end of capacitor C16A, the second end of capacitor C17A is connected to the first end of capacitor C16A, and the second end of capacitor C17A
  • the first end is connected to the second end of the capacitor C18A
  • the anode of the diode D8A is connected to the second end of the capacitor C17A
  • the cathode of the diode D8A is connected to the second end of the inductor L14A
  • the first end of the inductor L14A is connected to the first end of the capacitor C18A.
  • the anode of the diode D9A is connected to the second end of the capacitor C19A
  • the cathode of the diode D9A is connected to the second end of the inductor L15A
  • the first end of the inductor L15A is connected to the first end of the capacitor C19A
  • the first end of the inductor L17A Connect to the first end of the capacitor C18A, and the second end of the inductor L17A to the second end of the capacitor C19A.
  • Figure 16 is a circuit diagram of the coil H/F2 in this embodiment.
  • the wire X37, the wire X38, the wire X39 and the wire X40 of the coil H/F2 form a rectangular and convex structure, the wire X37 and the wire X39
  • the wire X40 is an L-shaped wire
  • the wire X38 includes a Z-shaped wire and an L-shaped wire.
  • a convex structure is formed between the Z-shaped wire and the L-shaped wire to connect the inductor L17B, and the inductor L16B is connected between the wire X37 and the wire X40.
  • the secondary detuning circuit composed of diode D7B and capacitor C16B, the secondary detuning circuit composed of inductor L14B, diode D8B, capacitor C17B and capacitor C18B is connected between wire X37 and wire X38, and wire 38 and wire X39 are connected
  • a secondary detuning circuit composed of an inductor L15B, a diode D9B and a capacitor C19B is used, and a third interface circuit 121B is connected between the wire X39 and the wire X40.
  • the third interface circuit 121B includes: input terminal IN1B, input terminal IN2B, capacitor C11B, capacitor C12B, capacitor C13B, capacitor C14B, capacitor C15B, variable capacitor B1B, variable capacitor B2B, inductor L11B, inductor L12B and inductor L13B, input
  • the terminal IN1B is connected to the first terminal of the capacitor C11B
  • the second terminal of the capacitor C11B is connected to the first terminal of the capacitor C12B
  • the first terminal of the inductor L13B is connected to the second terminal of the capacitor C12B
  • the second terminal of the inductor L13B is connected to the capacitor
  • the first end of C12B, the first end of capacitor C13B is connected to the second end of capacitor C12B, the second end of capacitor C13B is connected to the first end of capacitor C14B, and the second end of capacitor C14B is connected to the first end of capacitor C15B
  • the second end of the capacitor C15B is connected to the input terminal IN2
  • the third detuning circuit 122B includes: a capacitor C16B, a capacitor C17B, a capacitor C18B, a capacitor C19B, an inductor L14B, an inductor L10B, an inductor L16B, an inductor L17B, a diode D7B, a diode D8B, and a diode D9B.
  • the first end of the inductor L16B is connected to the capacitor The first end of C16B, the second end of inductor L16B is connected to the cathode of diode D7B, the anode of diode D7B is connected to the second end of capacitor C16B, the second end of capacitor C17B is connected to the first end of capacitor C16B, and the second end of capacitor C17B
  • the first end is connected to the second end of the capacitor C18B
  • the anode of the diode D8B is connected to the second end of the capacitor C17B
  • the cathode of the diode D8B is connected to the second end of the inductor L14B
  • the first end of the inductor L14B is connected to the first end of the capacitor C18B.
  • the anode of the diode D9B is connected to the second end of the capacitor C19B
  • the cathode of the diode D11B is connected to the second end of the inductor L15B
  • the first end of the inductor L15B is connected to the first end of the capacitor C19B
  • the first end of the inductor L17B Connect to the first end of the capacitor C18B, and the second end of the inductor L17B to the second end of the capacitor C19B.
  • Figure 17 is a circuit diagram of the coil H/F3 in this embodiment.
  • the wire X41, the wire X42, the wire X43 and the wire X44 of the coil H/F3 enclose a rectangular and convex structure, the wire X42, the wire X43
  • the wire X44 is an L-shaped wire
  • the wire X41 includes a Z-shaped wire and an L-shaped wire.
  • a convex structure is formed between the Z-shaped wire and the L-shaped wire to connect the inductor L17C, and the inductor L16C is connected between the wire X42 and the wire X43.
  • the secondary detuning circuit composed of diode D7C and capacitor C16C, the secondary detuning circuit composed of inductor L14C, diode D8C, capacitor C17C and capacitor C18C is connected between wire X41 and wire X42, and wire X41 and wire X44 are connected
  • a secondary detuning circuit composed of an inductor L15C, a diode D11C and a capacitor C19C is used, and a second interface circuit 121C is connected between the wire X43 and the wire X44.
  • the inductance L17A of the coil H/F1 and the inductance L17C of the coil H/F3 are arranged adjacent to each other, and are used for decoupling between the coil H/F1 and the coil H/F3. Decoupling is achieved by adjusting the coincidence area of the inductance coil between the inductance L17A and the inductance L17C.
  • the third interface circuit 121C includes: input terminal IN1C, input terminal IN2C, capacitor C11C, capacitor C12C, capacitor C13C, capacitor C14C, capacitor C15C, variable capacitor B1C, variable capacitor B2C, inductor L11C, inductor L12C, and inductor L13C, input
  • the terminal IN1C is connected to the first terminal of the capacitor C11C
  • the second terminal of the capacitor C11C is connected to the first terminal of the capacitor C12C
  • the first terminal of the inductor L13C is connected to the second terminal of the capacitor C12C
  • the second terminal of the inductor L13C is connected to the capacitor
  • the first end of C11C, the first end of capacitor C13C is connected to the second end of capacitor C12C
  • the second end of capacitor C13C is connected to the first end of capacitor C14C
  • the second end of capacitor C14C is connected to the first end of capacitor C15C.
  • the second end of the capacitor C15C is connected to the input terminal IN2C
  • the first end of the inductor L12C is connected to the second end of the capacitor C11C
  • the second end of the inductor L12C is connected to the second end of the capacitor C15C
  • the first end of the inductor L11C is connected to The first end of the capacitor C14C
  • the second end of the inductor L11C are connected to the second end of the capacitor C15C
  • the first end of the variable capacitor B1C is connected to the first end of the capacitor C13C
  • the second end of the variable capacitor B1C is connected to the second end of the capacitor C13C.
  • the third detuning circuit 122C includes: a capacitor C16C, a capacitor C17C, a capacitor C18C, a capacitor C19C, an inductor L14C, an inductor L15C, an inductor L16C, an inductor L17C, a diode D7C, a diode D8C, and a diode D9C.
  • the first end of the inductor L16C is connected to the capacitor The first end of C16C, the second end of inductor L16C is connected to the cathode of diode D7C, the anode of diode D7C is connected to the second end of capacitor C16C, the second end of capacitor C18C is connected to the second end of capacitor C16C, and the second end of capacitor C17C
  • the first end is connected to the first end of the capacitor C18C
  • the anode of the diode D8C is connected to the second end of the capacitor C17C
  • the cathode of the diode D8C is connected to the second end of the inductor L14C
  • the first end of the inductor L14C is connected to the first end of the capacitor C18C.
  • the anode of diode D9C is connected to the second end of capacitor C19C
  • the cathode of diode D9C is connected to the second end of inductor L15C
  • the first end of inductor L15C is connected to the first end of capacitor C19C
  • the first end of inductor L17C It is connected to the second end of the capacitor C17C
  • the second end of the inductor L17C is connected to the first end of the capacitor C19C.
  • FIG 18 is a circuit diagram of the coil H/F4 in this embodiment.
  • the wire X45, wire X46, wire X47 and the wire X48 of the coil H/F4 are enclosed in a rectangular and convex structure, and the wire X46 and the wire X47
  • the wire X48 is an L-shaped wire
  • the wire X45 includes a Z-shaped wire and an L-shaped wire.
  • a convex structure is formed between the Z-shaped wire and the L-shaped wire to connect the inductor L17D, and the inductor L16D is connected between the wire X46 and the wire X47.
  • a secondary detuning circuit composed of an inductor L15D, a diode D9D and a capacitor C19D is used, and a second interface circuit 121D is connected between the wire X47 and the wire X48.
  • the inductance L17B of the coil H/F2 and the inductance L17D of the coil H/F4 are arranged adjacent to each other corresponding to each other, and are used for decoupling between the coil H/F2 and the coil H/F4. Decoupling is achieved by adjusting the coincidence area of the inductance coils between the inductance L17B and the inductance L17D.
  • the third interface circuit 121D includes: input terminal IN1D, input terminal IN2D, capacitor C11D, capacitor C12D, capacitor C13D, capacitor C14D, capacitor C15D, variable capacitor B1D, variable capacitor B2D, inductor L11D, inductor L12D and inductor L13D, input
  • the terminal IN1D is connected to the first terminal of the capacitor C11D
  • the second terminal of the capacitor C11D is connected to the first terminal of the capacitor C12D
  • the first terminal of the inductor L13D is connected to the second terminal of the capacitor C12D
  • the second terminal of the inductor L13D is connected to the capacitor
  • the first end of C11D, the first end of capacitor C13D is connected to the second end of capacitor C12D, the second end of capacitor C13D is connected to the first end of capacitor C14D, and the second end of capacitor C14D is connected to the first end of capacitor C15D
  • the second end of the capacitor C15D is connected to the input terminal IN2
  • the third detuning circuit 122D includes: a capacitor C16D, a capacitor C17D, a capacitor C18D, a capacitor C19D, an inductor L14D, an inductor L15D, an inductor L16D, an inductor L17D, a diode D7D, a diode D8D, and a diode D9D.
  • the first end of the inductor L16D is connected to the capacitor The first end of C16D, the second end of inductor L16D is connected to the cathode of diode D7D, the anode of diode D7D is connected to the second end of capacitor C16D, the second end of capacitor C18D is connected to the second end of capacitor C16D, and the second end of capacitor C17D
  • the first end is connected to the first end of the capacitor C18D
  • the anode of the diode D8D is connected to the second end of the capacitor C17D
  • the cathode of the diode D8D is connected to the second end of the inductor L14D
  • the first end of the inductor L14D is connected to the first end of the capacitor C18D.
  • the anode of the diode D9D is connected to the second end of the capacitor C19D
  • the cathode of the diode D9D is connected to the second end of the inductor L15D
  • the first end of the inductor L15D is connected to the first end of the capacitor C19D
  • the first end of the inductor L17D It is connected to the second end of the capacitor C17D
  • the second end of the inductor L17D is connected to the first end of the capacitor C19D.
  • the nuclear magnetic test signal is input to the third interface circuit 121 through the input terminal IN1 and the input terminal IN2 of the third interface circuit 121, and the working state of the H/F coil is controlled by the third detuning circuit 122 to reduce Residual interference and shielding effects caused by copper components in other array loops.
  • the third detuning circuit 122 By designing multiple independent detuning circuits to control the working state of multiple nuclide coils, reduce the interference between the nuclides of the inner and outer coils.
  • the Na array and the H/F double-tuned array are detuned to reduce the difference between the P and H/F/N arrays. Electromagnetic interference between. And to decouple the P and H/F/Na arrays, three active detuning circuits are inserted in each loop of the array to reduce residual interference and shielding effects caused by copper components in other array loops. In this embodiment, the value of the element in each coil can be adjusted according to actual conditions, which is not limited in this embodiment.
  • the front-end module 2 is connected to the coil module 1, and is configured to generate nuclear magnetic test signals and collect induction signals.
  • the front-end module 2 is set to be connected to an external radio frequency signal generator.
  • an external radio frequency signal generator By inputting a nuclear magnetic test signal and using, for example, a quadrature coupler, the nuclear magnetic test signal is phase-shifted, and the nuclear magnetic test signal is split into a plurality of different phases.
  • the radio frequency signal can transmit multiple radionuclide signals at the same time or at different times for the effect of nuclear magnetic resonance imaging.
  • This embodiment discloses a quad-core radio frequency coil circuit, including: a coil module configured to receive a nuclear magnetic test signal and generate an induction signal according to the nuclear magnetic test signal; a front-end module, the front-end module and the coil The module is connected and configured to generate the nuclear magnetic test signal and collect the induction signal.
  • the quad-core radio frequency coil circuit disclosed in the embodiments of the present application is designed through a double-layer nested structure combination design. Based on the high coordination with the multi-frequency and multi-channel electronic and timing control system, it can transmit multiple types at the same time or at different times.
  • the nuclear magnetic resonance imaging of the nuclide signal solves the problem of interaction between different nuclides and electromagnetic interference, and realizes multi-channel multi-frequency high-uniformity radio-frequency excitation and high-sensitivity signal acquisition.
  • FIG. 19 is a circuit diagram of the front-end module in the second embodiment.
  • the front-end module 2 includes a power division module 21 and a signal driving module 22.
  • the power dividing module 21 is connected to the signal driving module 22, and the power dividing module 21 is configured to split the nuclear magnetic test signal into multiple test signals.
  • the power divider module 21 includes three 1:2 power dividers, namely, a power divider 211, a power divider 212, and a power divider 213.
  • the input terminal of the power divider module 21 is set to be connected to an external signal generator.
  • the high-power output signal input from the outside is divided into 4 signals by three 1:2 power dividers, and each signal is input to a different coil unit in the coil module 1.
  • the power division module 21 is configured to coordinate the adjustment of the amplitude and phase of the excitation sources of multiple channels, separate 4 channels of signals, and finally realize the amplitude change and phase modulation of the excitation sources of the multiple channels.
  • the signal driving module 22 is connected to the coil module 1, and the signal driving module 22 is configured to input multiple test signals into the coil module 1.
  • each signal drive module 22 is connected to the four signals generated by the power dividing module 21, and the coaxial cable of each coil is connected with three different frequency radio frequency traps (radio frequency trap 221, radio frequency trap 221, 222 and RF trap 223), the radio frequency trap corresponding to the working frequency of the coil is connected at a position close to the coil direction, and the other two are connected to the radio frequency trap at the working frequency of the coil, and the test signal is input to the coil module 1 through the output terminal 1.
  • the weak magnetic resonance voltage signal received from the coil is amplified by the amplifier 224, the signal is divided into two channels by the bridge 225, and transmitted to the spectrometer through the hospital bed to complete the image reconstruction and display the MRI result.
  • FIG. 20 is a circuit diagram of a quad-core radio frequency coil circuit in this embodiment.
  • the first sub-coil array 11a is connected to 4 signal driving modules 22A, 22B, 22C, and 22D, and 4 signal driving modules 22A, 22B, 22C and 22D are connected to the power dividing module 21E, and the power dividing module 21E is connected to the external signal input terminal.
  • the second coil array 12 is connected to four signal driving modules 22F, 22G, 22H, and 22I.
  • the four signal driving modules 22F, 22G, 22H, and 22I are connected to the power dividing module 21J, and the power dividing module 21J is connected to the external signal input terminal.
  • the signal input terminal is divided into a plurality of signals with different phase differences by inputting a preset nuclear magnetic signal through the power division module and input to the first sub-coil array 11a and the second coil array 12, and the signal is input to the external display through the detected feedback signal In the equipment, you can observe the NMR test results.
  • the first sub-coil array 11a and the second coil array may not be connected to the same signal input terminal, which can be selected according to actual application conditions.
  • connection relationship between the second sub-coil array and the signal driving module is similar to that of the first sub-coil array, and will not be repeated here.
  • This embodiment discloses a quad-core radio frequency coil circuit, including: a coil module configured to receive a nuclear magnetic test signal and generate an induction signal according to the nuclear magnetic test signal; a front-end module, the front-end module and the coil The module is connected and configured to generate the nuclear magnetic test signal and collect the induction signal.
  • the quad-core radio frequency coil circuit disclosed in the embodiments of the present application is designed through a double-layer nested structure combination design. Based on the high coordination with the multi-frequency and multi-channel electronic and timing control system, it can transmit multiple types at the same time or at different times.
  • the nuclear magnetic resonance imaging of the nuclide signal solves the problem of interaction between different nuclides and electromagnetic interference, and realizes multi-channel multi-frequency high-uniformity radio-frequency excitation and high-sensitivity signal acquisition.

Abstract

一种四核射频线圈电路，包括：线圈模块（1），线圈模块（1）设置为接收核磁测试信号并根据核磁测试信号生成感应信号；前端模块（2），前端模块（2）与线圈模块（1）连接，设置为产生核磁测试信号并采集感应信号。

Description

四核射频线圈电路
本申请要求在2020年04月27日提交中国专利局、申请号为202010346493.X的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及核磁共振技术，例如涉及一种四核射频线圈电路。
背景技术
相关技术中氢原子磁共振成像已经比较成熟，但是只对氢原子成像已经不能满足人类对多种疾病的诊断的需求，由于多核磁共振成像技术可用于获得生物系统中的形态和代谢信息，已经得到迅速的发展，除了氢-1(1H)之外，还有碳-13(13C)、氟-19(19F)、钠-23(23Na)、磷-31(31P)等核素的研究。随着磁共振技术的发展，已经提出了三调谐磁共振射频探针或线圈，以满足检测三个不同的磁共振(Magnetic Resonance，MR)敏感核的需要。相关技术中使用集总元件技术在小型线圈中展示了该设计，并显示了该设计在小样本MR成像应用的三频操作中的可行性。但由于多调谐线圈的结构复杂，多调谐线圈的设计、制作和调试的难度都大大增加，相关技术中还未有在高场和超高场中实现四核素信号的同步激发和采集的多通道射频线圈系统。在高磁场的大样本成像应用中，多通道四核射频(Radio Frequency，RF)线圈可能会遇到技术挑战，不同核通道之间的相互作用，通道间的相互耦合以及在高强度电磁场中复杂的电磁波行为、电介质和导电生物样品等等会严重降低线圈的传输效率以及接收灵敏度。在射频技术中，为了在激发信号的时候有一个均匀的激发，在接收信号的时候有一个高灵敏度的接收场，可通过改变不同通道激励源的相位，实现多核素多通道线圈的正交激发，产生圆极化的发射场。在接收模式下形成了高灵敏度的接收场,才能具有足够的覆盖范围以提升弱核素的信噪比(Signal-to-Noise Ratio，SNR)。
在多种配置的用于观察来自质子以外的核的信号(例如19F和31P)的双核RF线圈中，可以使用共模差模方法或使用两个几何隔离的线圈(B1场彼此垂直)来实现双调谐线圈设计。上述方法通常用于单核正交线圈设计以改善SNR，但是在不使用正交配置的情况下，该线圈也可以用作双谐振模式。例如，两个线圈中的一个线圈可以是调谐到1H的环路，另一个线圈可以是调谐到另一个核的蝶形、双环路、单极天线或调谐的微带传输线。也可使用两个独立线圈回路嵌套组合形成双谐振单元；通过在线圈端口处插入谐振网络实现共用一个线圈回 路的双核谐振线圈单元。大多数多核磁共振实验都是通过分别进行单核的图像采集，然后配准从每个核采集的图像来进行的。这不仅费时，而且由于每个核进行图像采集的线圈设置和图像分辨率不同，所以很难成功地完成图像配准。一种解决方案是使用多重调谐线圈阵列同时检测多核信号。然而，这种类型的线圈的设计比较复杂，必须抑制每个单独调谐的线圈元件之间的相互作用和串扰。
发明内容
本申请提供一种四核射频线圈电路，以实现多通道多频率高均匀性的射频激发和高灵敏度的信号采集，该四核射频线圈电路包括：
线圈模块，所述线圈模块设置为接收核磁测试信号并根据所述核磁测试信号生成感应信号；
前端模块，所述前端模块与所述线圈模块连接，设置为产生所述核磁测试信号并采集所述感应信号。
可选的，所述线圈模块包括第一线圈阵列和第二线圈阵列，所述第一线圈阵列与所述第二线圈阵列中心位置重合。
可选的，所述第一线圈阵列包括第一子线圈阵列和第二子线圈阵列，所述第一子线圈阵列包括多个第一线圈单元，所述多个第一线圈单元基于第一预设相位差叠加排列，所述第二子线圈阵列包括多个第二线圈单元，所述多个第二线圈单元基于第二预设相位差叠加排列，所述第二线圈阵列包括多个第三线圈单元，所述多个第三线圈单元基于第三预设相位差叠加排列。
可选的，所述第一线圈单元包括：第一接口电路和第一失谐电路，所述第一失谐电路与所述第一接口电路连接，所述第一接口电路连接到所述前端模块。
可选的，所述第一接口电路包括：输入端IN1、输入端IN2、电容C1、电容C2和电感L1，所述输入端IN1连接到所述电容C1的第一端，所述电容C1的第二端连接到所述电容C2的第一端，所述电容C2的第二端连接到所述电感L1的第一端，所述电感L1的第二端连接到所述电容C2的第一端，所述输入端IN2连接到所述电容C1的第二端。
可选的，所述第一失谐电路包括：电感L2、电感L3、电感L4、电感L5、电容C3、电容C4、电容C5、二极管D1、二极管D2和二极管D3，所述电感L2的第一端连接到所述电容C3的第一端，所述电感L2的第二端连接到所述二极管D1的负极，所述二极管D1的正极连接到所述电容C3的第二端，所述电容C4的第二端连接到所述电容C3的第一端，所述二极管D2的正极连接到所 述电容C4的第二端，所述二极管D2的负极连接到所述电感L3的第二端，所述电感L3的第一端连接到所述电容C4的第一端，所述电容C5的第二端连接到所述电容C4的第一端，所述二极管D3的正极连接到所述电容C5的第二端，所述二极管D3的负极连接到所述电感L4的第二端，所述电感L4的第一端连接到所述电容C5的第一端，所述电感L5的第一端连接到所述电容C5的第二端，所述电感L5的第二端连接到所述电容C4的第一端；或者，所述电感L2的第一端连接到所述电容C3的第一端，所述电感L2的第二端连接到所述二极管D1的负极，所述二极管D1的正极连接到所述电容C3的第二端，所述电容C4的第二端连接到所述电容C3的第二端，所述二极管D2的正极连接到所述电容C4的第一端，所述二极管D2的负极连接到所述电感L3的第二端，所述电感L3的第一端连接到所述电容C4的第二端，所述二极管D3的正极连接到所述电容C5的第二端，所述二极管D3的负极连接到所述电感L4的第二端，所述电感L4的第一端连接到所述电容C5的第一端，所述电容感L5的第一端连接到所述电容C5的第一端，所述电感L5的第二端连接到所述电容C4的第一端。
可选的，所述第二线圈单元包括：第二接口电路和第二失谐电路，所述第二失谐电路与所述第二接口电路连接，所述第二接口电路连接到所述前端模块。
可选的，所述第二接口电路包括：输入端IN1、输入端IN2、电容C6、电容C7和电感L6，所述输入端IN1连接到所述电容C6的第一端，所述电容C6的第二端连接到所述电容C7的第一端，所述电容C7的第二端连接到所述电感L6的第一端，所述电感L6的第二端连接到所述电容C7的第一端，所述输入端IN2连接到所述电容C6的第二端。
可选的，所述第二失谐电路包括：电感L7、电感L8、电感L9、电感L10、电容C8、电容C9、电容C10、二极管D4、二极管D5和二极管D6；其中，所述电感L7的第一端连接到所述电容C8的第一端，所述电感L7的第二端连接到所述二极管D4的负极，所述二极管D4的正极连接到所述电容C8的第二端，所述电容C9的第二端连接到所述电容C8的第一端，所述二极管D5的正极连接到所述电容C9的第二端，所述二极管D5的负极连接到所述电感L8的第二端，所述电感L8的第一端连接到所述电容C9的第一端，所述二极管D6的正极连接到所述电容C10的第二端，所述二极管D6的负极连接到所述电感L9的第二端，所述电感L9的第一端连接到所述电容C10的第一端，所述电感L10的第一端连接到所述电容C10的第二端，所述电感L10的第二端连接到所述电容C9的第一端；或者，所述电感L7的第一端连接到所述电容C8的第一端，所述电感L7的第二端连接到所述二极管D4的负极，所述二极管D4的正极连接到所述电容C8的第二端，所述电容C9的第二端连接到所述电容C8的第二端，所述二极管D5的正极连接到所述电容C9的第一端，所述二极管D5的负 极连接到所述电感L8的第二端，所述电感L8的第一端连接到所述电容C9的第二端，所述二极管D6的正极连接到所述电容C10的第二端，所述二极管D6的负极连接到所述电感L9的第二端，所述电感L9的第一端连接到所述电容C10的第一端，所述电容感L10的第一端连接到所述电容C10的第一端，所述电感L10的第二端连接到所述电容C9的第一端。
可选的，所述第三线圈单元包括：第三接口电路和第三失谐电路，所述第三失谐电路与所述第三接口电路连接，所述第三接口电路连接到所述前端模块。
可选的，所述第三接口电路包括：输入端IN1、输入端IN2、电容C11、电容C12、电容C13、电容C14、电容C15、可变电容B1、可变电容B2、电感L11、电感L12和电感L13，所述输入端IN1连接到所述电容C11的第一端，所述电容C11的第二端连接到所述电容C12的第一端，所述电感L13的第一端连接到所述电容C12的第二端，所述电感L13的第二端连接到所述电容C11的第一端，所述电容C13的第一端连接到所述电容C12的第二端，所述电容C13的第二端连接到所述电容C14的第一端，所述电容C14的第二端连接到所述电容C15的第一端，所述电容C15的第二端连接到所述输入端IN2，所述电感L12的第一端连接所述电容C11的第二端，所述电感L12的第二端连接到所述电容C15的第二端，所述电感L11的第一端连接到所述电容C14的第一端，所述电感L11的第二端连接到所述电容C15的第二端，所述可变电容B1的第一端连接所述电容C13的第一端，所述可变电容B1的第二端连接所述电容C13的第二端，所述可变电容B2的第一端连接所述电容C12的第一端，所述可变电容B2的第二端连接所述电容C15的第二端。
可选的，所述第三失谐电路包括：电容C16、电容C17、电容C18、电容C19、电感L14、电感L15、电感L16、电感L17、二极管D7、二极管D8和二极管D9；其中，所述电感L16的第一端连接到所述电容C16的第一端，所述电感L16的第二端连接到所述二极管D7的负极，所述二极管D7的正极连接到所述电容C16的第二端，所述电容C17的第二端连接到所述电容C16的第一端，所述电容C17的第一端连接到所述电容C18的第二端，所述二极管D8的正极连接到所述电容C17的第二端，所述二极管D8的负极连接到所述电感L14的第二端，所述电感L14的第一端连接到所述电容C18的第一端，所述二极管D9的正极连接到所述电容C19的第二端，所述二极管D9的负极连接到所述电感L15的第二端，所述电感L15的第一端连接到所述电容C19的第一端，所述电感L17的第一端连接到所述电容C18的第一端，所述电感L17的第二端连接到所述电容C19的第二端；或者，所述电感L16的第一端连接到所述电容C16的第一端，所述电感L16的第二端连接到所述二极管D7的负极，所述二极管D7的正极连接到所述电容C16的第二端，所述电容C18的第二端连接到所述电容 C16的第二端，所述电容C17的第一端连接到所述电容C18的第一端，所述二极管D8的正极连接到所述电容C17的第二端，所述二极管D8的负极连接到所述电感L14的第二端，所述电感L14的第一端连接到所述电容C18的第二端，所述二极管D9的正极连接到所述电容C19的第二端，所述二极管D9的负极连接到所述电感L15的第二端，所述电感L15的第一端连接到所述电容C19的第一端，所述电感L17的第一端连接到所述电容C17的第一端，所述电感L17的第二端连接到所述电容C19的第二端。
可选的，所述前端模块包括：功分模块和信号驱动模块，所述功分模块与信号驱动模块连接，所述信号驱动模块与所述线圈模块连接，所述功分模块设置为将所述核磁测试信号拆分为多路测试信号，所述信号驱动模块设置为将所述多路测试信号输入到所述线圈模块中。
附图说明
图1为本申请实施例一提供的一种四核射频线圈电路的模块连接图；
图2为本申请实施例一中四核射频线圈电路的结构俯视图；
图3为本申请实施例一中第一子线圈阵列的电路图；
图4为本申请实施例一中为线圈Na1的电路图；
图5为本申请实施例一中为线圈Na2的电路图；
图6为本申请实施例一中为线圈Na3的电路图；
图7为本申请实施例一中为线圈Na4的电路图；
图8为本申请实施例一中第二子线圈阵列的电路图；
图9为本申请实施例一中为线圈P1的电路图；
图10为本申请实施例一中为线圈P2的电路图；
图11为本申请实施例一中为线圈P3的电路图；
图12为本申请实施例一中为线圈P4的电路图；
图13为本申请实施例一中第一线圈阵列的排列示意图；
图14为本申请实施例一中第二线圈阵列的电路图；
图15为本申请实施例一中为线圈H/F1的电路图；
图16为本申请实施例一中为线圈H/F2的电路图；
图17为本申请实施例一中为线圈H/F3的电路图；
图18为本申请实施例一中为线圈H/F4的电路图；
图19为本申请实施例二中前端模块的电路图；
图20为本申请实施例二中一种四核射频线圈电路的电路图。
具体实施方式
下面结合附图和实施例对本申请进行说明。此处所描述的实施例仅仅用于解释本申请，而非对本申请的限定。附图中仅示出了与本申请相关的部分而非全部结构。
在讨论示例性实施例之前应当提到的是，一些示例性实施例被描述成作为流程图描绘的处理或方法。虽然流程图将多个步骤描述成顺序的处理，但是其中的许多步骤可以被并行地、并发地或者同时实施。此外，多个步骤的顺序可以被重新安排。当其操作完成时处理可以被终止，但是还可以具有未包括在附图中的附加步骤。处理可以对应于方法、函数、规程、子例程、子程序等等。
此外，术语“第一”、“第二”等可在本文中用于描述多种方向、动作、步骤或元件等，但这些方向、动作、步骤或元件不受这些术语限制。这些术语仅用于将第一个方向、动作、步骤或元件与另一个方向、动作、步骤或元件区分。举例来说，在不脱离本申请的范围的情况下，可以将第一线圈阵列称为第二线圈阵列，且类似地，可将第二线圈阵列称为第一线圈阵列。第一线圈阵列和第二线圈阵列两者都是线圈阵列，但其不是同一线圈阵列。术语“第一”、“第二”等而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，“多个”的含义是至少两个，例如两个，三个等，除非另有明确的限定。
实施例一
图1为本申请实施例一提供的一种四核射频线圈电路的模块连接图，本实施例适用于使用多种核素信号进行核磁共振的情况，本实施例提供的一种四核射频线圈电路包括：线圈模块1和前端模块2。
线圈模块1设置为接收核磁测试信号并根据核磁测试信号生成感应信号。在本实施中，核磁测试信号由信号产生器等仪器产生，用于进行核磁共振成像，常见的核素有1H(氢)、13C(碳)、19F(氟)、23Na(钠)和31P(磷)等等，在本实施例中提供的四核射频线圈电路以1H、19F、23Na和31P四种核素为例进行说明。感应信号为用户根据核磁测试信号反馈的感应信号，线圈模块1收集到用户反馈的感应信号后可以传输到如示波器等仪器中进行显像。
参阅图2，线圈模块1包括第一线圈阵列11和第二线圈阵列12，第一线圈阵列11与第二线圈阵列12的中心位置重合。图2为本实施例中四核射频线圈电路的结构俯视图，第一线圈阵列11和第二线圈阵列12采用双层嵌套式结构组合设计，第一线圈阵列11包括了第一子线圈阵列和第二子线圈阵列，第一子线圈阵列包括4个Na线圈，第二子线圈阵列包括4个P线圈，4个Na线圈围成一个圆形结构，4个P线圈围成一个圆形结构，且4个Na线圈围成的圆形结构与4个P线圈围城的圆形结构的横截面的半径相同且圆心重合；第二线圈阵列12包括了4个H/F线圈，4个H/F线圈也围成了一个圆形结构，并且该圆形结构的圆心与4个Na线圈围成的圆形结构的圆心和4个P线圈围成的圆形结构的圆心重合。4个Na线圈中相邻的两个Na线圈部分重叠；4个P线圈中相邻的两个P线圈部分重叠；4个H/F线圈中相邻的两个H/F线圈部分重叠。垂直P线圈所在平面的(忽略线圈弧度)P线圈的中心线与垂直H/F线圈所在平面的H/F线圈的中心线相互重合，例如和穿过圆心的轴Z1重合。垂直Na线圈所在平面(忽略线圈弧度)的Na线圈的中心线Z2与垂直H/F线圈所在平面(忽略线圈弧度)的H/F线圈的中心线Z3相差45°。通过设置Na线圈的中心线Z2的位置相对H/F线圈的中心线Z3的位置偏移45°从而解决了内外层线圈阵列互相干扰的问题。
Na线圈为频率调谐到23Na的线圈，P线圈为频率调谐到31P的线圈，H/F线圈为频率调谐到1H以及19F的线圈。
参阅图3，图3为第一子线圈阵列11a的电路图，在本实施例中，第一子线圈阵列11a以4个Na线圈为例进行说明，第一子线圈阵列11a包括多个第一线圈单元(线圈Na1、线圈Na2、线圈Na3和线圈Na4)，多个第一线圈单元基于第一预设相位差叠加排列。线圈Na1、线圈Na2、线圈Na3和线圈Na4均为Na线圈，线圈Na1的导线X2和X3与线圈Na2的导线X5和X8围成了面积为A1的重叠区域M1，线圈Na2的导线X6和X7与线圈Na3的导线X9和X12围成了面积为A2的重叠区域M2，线圈Na3的导线X10和X11和线圈Na4的导线X13和X16围成了面积为A3的重叠区域M3，通过将第一子线圈阵列11a中的多个第一线圈单元叠加排列，实现了相邻线圈通道去耦的效果，减少了Na线圈之间的干扰。
参阅图4，第一线圈单元中线圈Na1包括：第一接口电路111A和第一失谐电路112A，第一失谐电路112A与第一接口电路111A连接，第一接口电路111A连接到前端模块2。线圈Na1的导线X1、导线X2、导线X3和到导线X4围成了一个矩形加凸起结构，导线X1、导线X3、导线X4为L型导线，导线X2包括Z型导线和L型导线，Z型导线和L型导线之间组成了凸起结构用于连接电感L5A，导线X1与导线X4之间连接了电感L2A、二极管D1A和电容C3A组成的次级失谐电路，导线X1与导线X2之间连接了电感L3A、二极管D2A和 电容C4A组成的次级失谐电路，导线X2与导线X3之间连接了电感L4A、二极管D3A和电容C5A组成的次级失谐电路，导线X4与导线X3之间连接了第一接口电路111A。图4为线圈Na1的电路图，第一接口电路111A包括：输入端IN1A、输入端IN2A、电容C1A、电容C2A和电感L1A，输入端IN1A连接到电容C1A的第一端，电容C1A的第二端连接到电容C2A的第一端，电容C2A的第二端连接到电感L1A的第一端，电感L1A的第二端连接到电容C2A的第一端，输入端IN2A连接到电容C1A的第二端。第一失谐电路112A包括：电感L2A、电感L3A、电感L4A、电感L5A、电容C3A、电容C4A、电容C5A、二极管D1A、二极管D2A和二极管D3A，电感L2A的第一端连接到电容C3A的第一端，电感L2A的第二端连接到二极管D1A的负极，二极管D1A的正极连接到电容C3A的第二端，电容C4A的第二端连接到电容C3A的第一端，二极管D2A的正极连接到电容C4A的第二端，二极管D2A的负极连接到电感L3A的第二端，电感L3A的第一端连接到电容C4A的第一端，二极管D3A的正极连接到电容C5A的第二端，二极管D3A的负极连接到电感L4A的第二端，电感L4A的第一端连接到电容C5A的第一端，电感L5A的第一端连接到电容C5A的第二端，电感L5A的第二端连接到电容C4A的第一端。
参阅图5，图5为线圈Na2的电路图，线圈Na2的导线X5、导线X6、导线X7和到导线X8围成了一个矩形加凸起结构，导线X5、导线X7、导线X8为L型导线，导线X6包括Z型导线和L型导线，Z型导线和L型导线之间组成了凸起结构用于连接电感L5B，导线X5与导线X8之间连接了电感L2B、二极管D1B和电容C3B组成的次级失谐电路，导线X5与导线X6之间连接了电感L3B、二极管D2B和电容C4B组成的次级失谐电路，导线X6与导线X7之间连接了电感L4B、二极管D3B和电容C5B组成的次级失谐电路，导线X8与导线X7之间连接了第一接口电路111B。第一接口电路111B包括：输入端IN1B、输入端IN2B、电容C1B、电容C2B和电感L1B，输入端IN1B连接到电容C1B的第一端，电容C1B的第二端连接到电容C2B的第一端，电容C2B的第二端连接到电感L1B的第一端，电感L1B的第二端连接到电容C2B的第一端，输入端IN2B连接到电容C1B的第二端。第一失谐电路112B包括：电感L2B、电感L3B、电感L4B、电感L5B、电容C3B、电容C4B、电容C5B、二极管D1B、二极管D2B和二极管D3B，电感L2B的第一端连接到电容C3B的第一端，电感L2B的第二端连接到二极管D1B的负极，二极管D1B的正极连接到电容C3B的第二端，电容C4B的第二端连接到电容C3B的第一端，二极管D2B的正极连接到电容C4B的第二端，二极管D2B的负极连接到电感L3B的第二端，电感L3B的第一端连接到电容C4B的第一端，二极管D3B的正极连接到电容C5B的第二端，二极管D3B的负极连接到电感L4B的第二端，电感L4B的第一端 连接到电容C5B的第一端，电感L5B的第一端连接到电容C5B的第二端，电感L5B的第二端连接到电容C4B的第一端。
参阅图6，图6为线圈Na3的电路图，线圈Na3的导线X9、导线X10、导线X11和到导线X12围成了一个矩形加凸起结构，导线X10、导线X11、导线X12为L型导线，导线X9包括Z型导线和L型导线，Z型导线和L型导线之间组成了凸起结构用于连接电感L5C，导线X10与导线X11之间连接了电感L2C、二极管D1C和电容C3C组成的次级失谐电路，导线X9与导线X10之间连接了电感L3C、二极管D2C和电容C4C组成的次级失谐电路，导线X9与导线X12之间连接了电感L4C、二极管D3C和电容C5C组成的次级失谐电路，导线X11与导线X12之间连接了第一接口电路111C。本实施例线圈Na1的电感L5A和线圈Na3的电感L5C相互邻近对应设置，用于线圈Na1和线圈Na3之间的去耦。通过适应调整电感L5A与电感L5C之间的电感线圈重合面积实现去耦。第一接口电路111C包括：输入端IN1C、输入端IN2C、电容C1C、电容C2C和电感L1C，输入端IN1C连接到电容C1C的第一端，电容C1C的第二端连接到电容C2C的第一端，电容C2C的第二端连接到电感L1C的第一端，电感L1C的第二端连接到电容C2C的第一端，输入端IN2C连接到电容C1C的第二端。第一失谐电路112C包括：电感L2C、电感L3C、电感L4C、电感L5C、电容C3C、电容C4C、电容C5C、二极管D1C、二极管D2C和二极管D3C，电感L2C的第一端连接到电容C3C的第一端，电感L2C的第二端连接到二极管D1C的负极，二极管D1C的正极连接到电容C3C的第二端，电容C4C的第二端连接到电容C3C的第二端，二极管D2C的正极连接到电容C4C的第一端，二极管D2C的负极连接到电感L3C的第二端，电感L3C的第一端连接到电容C4C的第二端，二极管D3C的正极连接到电容C5C的第二端，二极管D3C的负极连接到电感L4C的第二端，电感L4C的第一端连接到电容C5C的第一端，电感L5C的第一端连接到电容C5C的第一端，电感L5C的第二端连接到电容C4C的第一端。
参阅图7，图7为线圈Na4的电路图，线圈Na4的导线X13、导线X14、导线X15和到导线X16围成了一个矩形加凸起结构，导线X14、导线X15、导线X16为L型导线，导线X13包括Z型导线和L型导线，Z型导线和L型导线之间组成了凸起结构用于连接电感L5D，导线X14与导线X15之间连接了电感L2D、二极管D1D和电容C3D组成的次级失谐电路，导线X13与导线X14之间连接了电感L3D、二极管D2D和电容C4D组成的次级失谐电路，导线X13与导线X16之间连接了电感L4D、二极管D3D和电容C5D组成的次级失谐电路，导线X15与导线X16之间连接了第一接口电路111D。本实施例线圈Na2的电感L5B和线圈Na4的电感L5D相互邻近对应设置，用于线圈Na2和线圈Na4之间的去耦。通过适应调整电感L5B与电感L5D之间的电感线圈重合面积 实现去耦。第一接口电路111D包括：输入端IN1D、输入端IN2D、电容C1D、电容C2D和电感L1D，输入端IN1D连接到电容C1D的第一端，电容C1D的第二端连接到电容C2D的第一端，电容C2D的第二端连接到电感L1D的第一端，电感L1D的第二端连接到电容C2D的第一端，输入端IN2D连接到电容C1D的第二端。第一失谐电路112D包括：电感L2D、电感L3D、电感L4D、电感L5D、电容C3D、电容C4D、电容C5D、二极管D1D、二极管D2D和二极管D3D，电感L2D的第一端连接到电容C3D的第一端，电感L2D的第二端连接到二极管D1D的负极，二极管D1D的正极连接到电容C3D的第二端，电容C4D的第二端连接到电容C3D的第二端，二极管D2D的正极连接到电容C4D的第一端，二极管D2D的负极连接到电感L3D的第二端，电感L3D的第一端连接到电容C4D的第二端，二极管D3D的正极连接到电容C5D的第二端，二极管D3D的负极连接到电感L4D的第二端，电感L4D的第一端连接到电容C5D的第一端，电感L5D的第一端连接到电容C5D的第一端，电感L5D的第二端连接到电容C4D的第一端。
参阅图8，图8为本申请实施例一中第二子线圈阵列的电路图。第二子线圈阵列11b包括多个第二线圈单元(线圈P1、线圈P2、线圈P3和线圈P4)，多个第二线圈单元基于第二预设相位差叠加排列。线圈P1、线圈P2、线圈P3和线圈P4均为P线圈。线圈P1的导线X18和X19与线圈P2的导线X21和X24围成了面积为A4的重叠区域M4，线圈P2的导线X22和X23与线圈P3的导线X25和X28围成了面积为A5的重叠区域M5，线圈P3的导线X26和X27和线圈P4的导线X29和X32围成了面积为A6的重叠区域M6，通过将第二子线圈阵列11b中的多个第二线圈单元叠加排列，实现了相邻线圈通道去耦的效果，减少了P线圈之间的干扰。
参阅图9，第二线圈单元中线圈P1包括：第二接口电路113A和第二失谐电路114A，第二失谐电路114A与第二接口电路113A连接，第二接口电路113A连接到前端模块2。第二接口电路113A包括：输入端IN1A、输入端IN2A、电容C6A、电容C7A和电感L6A，输入端IN1A连接到电容C6A的第一端，电容C6A的第二端连接到电容C7A的第一端，电容C7A的第二端连接到电感L6A的第一端，电感L6A的第二端连接到电容C7A的第一端，输入端IN2A连接到电容C6A的第二端。第二失谐电路114A包括：电感L7A、电感L8A、电感L9A、电感L10A、电容C8 A、电容C9A、电容C10A、二极管D4A、二极管D5 A和二极管D6 A，电感L7A的第一端连接到电容C8A的第一端，电感L7A的第二端连接到二极管D4A的负极，二极管D4A的正极连接到电容C8A的第二端，电容C9A的第二端连接到电容C8A的第一端，二极管D5A的正极连接到电容C9A的第二端，二极管D5A的负极连接到电感L8A的第二端，电感L8A的第 一端连接到电容C9A的第一端，二极管D6A的正极连接到电容C10A的第二端，二极管D6A的负极连接到电感L9A的第二端，电感L9A的第一端连接到电容C10A的第一端，电感L10A的第一端连接到电容C10A的第二端，电感L10A的第二端连接到电容C9A的第一端。
参阅图10，第二线圈单元中线圈P2包括：第二接口电路113B和第二失谐电路114B，第二失谐电路114B与第二接口电路113B连接，第二接口电路113B连接到前端模块2。第二接口电路113B包括：输入端IN1B、输入端IN2B、电容C6B、电容C7B和电感L6B，输入端IN1B连接到电容C6B的第一端，电容C6B的第二端连接到电容C7B的第一端，电容C7B的第二端连接到电感L6B的第一端，电感L6B的第二端连接到电容C7B的第一端，输入端IN2B连接到电容C6B的第二端。第二失谐电路114B包括：电感L7B、电感L8B、电感L9B、电感L10B、电容C8B、电容C9B、电容C10B、二极管D4B、二极管D5B和二极管D6B，电感L7B的第一端连接到电容C8B的第一端，电感L7B的第二端连接到二极管D4B的负极，二极管D4 B的正极连接到电容C8 B的第二端，电容C9 B的第二端连接到电容C8B的第二端，二极管D5B的正极连接到电容C9B的第一端，二极管D5B的负极连接到电感L8B的第二端，电感L8B的第一端连接到电容C9B的第二端，二极管D6B的正极连接到电容C10B的第二端，二极管D6B的负极连接到电感L9B的第二端，电感L9B的第一端连接到电容C10B的第一端，电容感L10B的第一端连接到电容C10B的第一端，电感L10B的第二端连接到电容C9B的第一端。
参阅图11，第二线圈单元中线圈P3包括第二接口电路113C和第二失谐电路114C，第二失谐电路114C与第二接口电路113C连接，第二接口电路113C连接到前端模块2。第二接口电路113C包括：输入端IN1C、输入端IN2C、电容C6C、电容C7C和电感L6C，输入端IN1C连接到电容C6C的第一端，电容C6C的第二端连接到电容C7C的第一端，电容C7C的第二端连接到电感L6C的第一端，电感L6C的第二端连接到电容C7C的第一端，输入端IN2C连接到电容C6C的第二端。第二失谐电路114C包括：电感L7C、电感L8C、电感L9C、电感L10C、电容C8 C、电容C9 C、电容C10C、二极管D4C、二极管D5 C和二极管D6 C，电感L7C的第一端连接到电容C8C的第一端，电感L7C的第二端连接到二极管D4C的负极，二极管D4C的正极连接到电容C8C的第二端，电容C9C的第二端连接到电容C8C的第二端，二极管D5C的正极连接到电容C9C的第一端，二极管D5C的负极连接到电感L8C的第二端，电感L8C的第一端连接到电容C9C的第二端，二极管D6C的正极连接到电容C10C的第二端，二极管D6C的负极连接到电感L9C的第二端，电感L9C的第一端连接到电容C10C的第一端，电感L10C的第一端连接到电容C10C的第一端，电感L10C 的第二端连接到电容C9C的第一端。
参阅图12，第二线圈单元中线圈P4包括第二接口电路113D和第二失谐电路114D，第二失谐电路114D与第二接口电路113D连接，第二接口电路113D连接到前端模块2。第二接口电路113D包括：输入端IN1D、输入端IN2D、电容C6D、电容C7D和电感L6D，输入端IN1D连接到电容C6D的第一端，电容C6D的第二端连接到电容C7D的第一端，电容C7D的第二端连接到电感L6D的第一端，电感L6D的第二端连接到电容C7D的第一端，输入端IN2D连接到电容C6D的第二端。第二失谐电路114D包括：电感L7D、电感L8D、电感L9D、电感L10D、电容C8D、电容C9D、电容C10D、二极管D4D、二极管D5D和二极管D6D，电感L7D的第一端连接到电容C8D的第一端，电感L7D的第二端连接到二极管D4D的负极，二极管D4 D的正极连接到电容C8 D的第二端，电容C9 D的第二端连接到电容C8D的第二端，二极管D5D的正极连接到电容C9D的第一端，二极管D5D的负极连接到电感L8D的第二端，电感L8D的第一端连接到电容C9D的第二端，二极管D6D的正极连接到电容C10D的第二端，二极管D6D的负极连接到电感L9D的第二端，电感L9D的第一端连接到电容C10D的第一端，电容感L10D的第一端连接到电容C10D的第一端，电感L10D的第二端连接到电容C9D的第一端。
第一子线圈单元11a与第二子线圈单元11b的结构和原理类似，此处不再赘述。
在本实施例中，第一线圈阵列11包括4个Na线圈和4个P线圈，参阅图13，图13为本申请实施例一中第一线圈阵列11的排列示意图，4个Na线圈(线圈Na1、线圈Na2、线圈Na3、线圈Na4)之间通过矩形外凸起部分的电感实现不相邻线圈去耦，4个P线圈(线圈P1、线圈P2、线圈P3、线圈P4)也通过矩形外凸起部分的电感实现不相邻线圈去耦，相邻线圈例如线圈Na1和线圈Na2之间通过重叠面积实现去耦。
在本实施例中，核磁测试信号通过第一接口电路111的输入端IN1和输入端IN2输入到第一接口电路111中，通过第一失谐电路112控制Na线圈的工作状态，允许进行Na成像；核磁测试信号通过第二接口电路113的输入端IN1和输入端IN2输入到第二接口电路113中，通过第二失谐电路114控制P线圈的工作状态，允许进行P成像。。在本实施例中，每个线圈中的元件的数值可以根据实际情况进行调整，在本实施例中不做限定。
参阅图14，图14为第二线圈阵列12的电路图，在本实施例中，H/F线圈可以传输核素H和核素F的射频信号，。在本实施例中，以4个H/F线圈为例进行说明。第二线圈阵列12包括多个第三线圈单元(线圈H/F 1、线圈H/F2、 线圈H/F3和线圈H/F4)，多个第三线圈单元基于第三预设相位差叠加排列，线圈H/F1、线圈H/F2、线圈H/F3和线圈H/F 4为H/F线圈，线圈H/F1的导线X34和X35与线圈H/F2的导线X37和X40围成了面积为A7的重叠区域M7，线圈H/F2的导线X38和X39与线圈H/F3的导线X41和X44围成了面积为A8的重叠区域M8，线圈H/F3的导线X42和X43和线圈H/F4的导线X45和X48围成了面积为A9的重叠区域M9，通过将第二线圈阵列12中的多个第三线圈单元叠加排列，实现了相邻线圈通道去耦的效果。
第三线圈单元中线圈H/F1包括：第三接口电路121A和第三失谐电路122A，第三失谐电路122A与第三接口电路121A连接，第三接口电路121A连接到前端模块2。参阅图15，图15为本实施例中线圈H/F1的电路图，线圈H/F1的导线X33、导线X34、导线X35和导线X36围成了一个矩形加凸起结构，导线X33、导线X35、导线X36为L型导线，导线X34包括Z型导线和L型导线，Z型导线和L型导线之间组成了凸起结构用于连接电感L17A，导线X33与导线X36之间连接了电感L16A、二极管D7A和电容C16A组成的次级失谐电路，导线X33与导线X34之间连接了电感L14A、二极管D8A、电容C17A和电容C18A组成的次级失谐电路，导线X34与导线X35之间连接了电感L15A、二极管D9A和电容C19A组成的次级失谐电路，导线X36与导线X35之间连接了第三接口电路121A。第三接口电路121A包括：输入端IN1A、输入端IN2A、电容C11A、电容C12A、电容C13A、电容C14A、电容C15A、可变电容B1A、可变电容B2A、电感L11A、电感L12A和电感L13A，输入端IN1A连接到电容C11A的第一端，电容C11A的第二端连接到电容C12A的第一端，电感L13A的第一端连接到电容C12A的第二端，电感L13A的第二端连接到电容C11A的第一端，电容C13A的第一端连接到电容C12A的第二端，电容C13A的第二端连接到电容C14A的第一端，电容C14A的第二端连接到电容C15A的第一端，电容C15A的第二端连接到输入端IN2A，电感L12A的第一端连接电容C11A的第二端，电感L12A的第二端连接到电容C15A的第二端，电感L11A的第一端连接到电容C14A的第一端，电感L11A的第二端连接到电容C15A的第二端，可变电容B1A的第一端连接电容C8A的第一端，可变电容B1A的第二端连接电容C8A的第二端，可变电容B2A的第一端连接电容C12A的第一端，可变电容B2A的第二端连接电容C15A的第二端。第三失谐电路122A包括：电容C16A、电容C17A、电容C18A、电容C19A、电感L14A、电感L15A、电感L16A、电感L17A、二极管D7A、二极管D8A和二极管D9A，电感L16A的第一端连接到电容C17A的第一端，电感L16A的第二端连接到二极管D7A的负极，二极管D7A的正极连接到电容C16A的第二端，电容C17A的第二端连接到电容C16A的第一端，电容C17A的第一端连接到电容C18A的第二端，二极管D8A的正极连接到电 容C17A的第二端，二极管D8A的负极连接到电感L14A的第二端，电感L14A的第一端连接到电容C18A的第一端，二极管D9A的正极连接到电容C19A的第二端，二极管D9A的负极连接到电感L15A的第二端，电感L15A的第一端连接到电容C19A的第一端，电感L17A的第一端连接到电容C18A的第一端，电感L17A的第二端连接到电容C19A的第二端。
参阅图16，图16为本实施例中线圈H/F2的电路图，线圈H/F2的导线X37、导线X38、导线X39和到导线X40围成了一个矩形加凸起结构，导线X37、导线X39、导线X40为L型导线，导线X38包括Z型导线和L型导线，Z型导线和L型导线之间组成了凸起结构用于连接电感L17B，导线X37与导线X40之间连接了电感L16B、二极管D7B和电容C16B组成的次级失谐电路，导线X37与导线X38之间连接了电感L14B、二极管D8B、电容C17B和电容C18B组成的次级失谐电路，导线38与导线X39之间连接了电感L15B、二极管D9B和电容C19B组成的次级失谐电路，导线X39与导线X40之间连接了第三接口电路121B。第三接口电路121B包括：输入端IN1B、输入端IN2B、电容C11B、电容C12B、电容C13B、电容C14B、电容C15B、可变电容B1B、可变电容B2B、电感L11B、电感L12B和电感L13B，输入端IN1B连接到电容C11B的第一端，电容C11B的第二端连接到电容C12B的第一端，电感L13B的第一端连接到电容C12B的第二端，电感L13B的第二端连接到电容C12B的第一端，电容C13B的第一端连接到电容C12B的第二端，电容C13B的第二端连接到电容C14B的第一端，电容C14B的第二端连接到电容C15B的第一端，电容C15B的第二端连接到输入端IN2B，电感L12B的第一端连接电容C11B的第二端，电感L12B的第二端连接到电容C15B的第二端，电感L11B的第一端连接到电容C14B的第一端，电感L11B的第二端连接到电容C15B的第二端，可变电容B1B的第一端连接电容C13B的第一端，可变电容B1B的第二端连接电容C13B的第二端，可变电容B2B的第一端连接电容C12B的第一端，可变电容B2B的第二端连接电容C15B的第二端。第三失谐电路122B包括：电容C16B、电容C17B、电容C18B、电容C19B、电感L14B、电感L10B、电感L16B、电感L17B、二极管D7B、二极管D8B和二极管D9B，电感L16B的第一端连接到电容C16B的第一端，电感L16B的第二端连接到二极管D7B的负极，二极管D7B的正极连接到电容C16B的第二端，电容C17B的第二端连接到电容C16B的第一端，电容C17B的第一端连接到电容C18B的第二端，二极管D8B的正极连接到电容C17B的第二端，二极管D8B的负极连接到电感L14B的第二端，电感L14B的第一端连接到电容C18B的第一端，二极管D9B的正极连接到电容C19B的第二端，二极管D11B的负极连接到电感L15B的第二端，电感L15B的第一端连接到电容C19B的第一端，电感L17B的第一端连接到电容C18B的第一端，电感L17B 的第二端连接到电容C19B的第二端。
参阅图17，图17为本实施例中线圈H/F3的电路图，线圈H/F3的导线X41、导线X42、导线X43和到导线X44围成了一个矩形加凸起结构，导线X42、导线X43、导线X44为L型导线，导线X41包括Z型导线和L型导线，Z型导线和L型导线之间组成了凸起结构用于连接电感L17C，导线X42与导线X43之间连接了电感L16C、二极管D7C和电容C16C组成的次级失谐电路，导线X41与导线X42之间连接了电感L14C、二极管D8C、电容C17C和电容C18C组成的次级失谐电路，导线X41与导线X44之间连接了电感L15C、二极管D11C和电容C19C组成的次级失谐电路，导线X43与导线X44之间连接了第二接口电路121C。本实施例线圈H/F1的电感L17A和线圈H/F3的电感L17C相互邻近对应设置，用于线圈H/F1和线圈H/F3之间的去耦。通过适应调整电感L17A合电感L17C之间的电感线圈重合面积实现去耦。第三接口电路121C包括：输入端IN1C、输入端IN2C、电容C11C、电容C12C、电容C13C、电容C14C、电容C15C、可变电容B1C、可变电容B2C、电感L11C、电感L12C和电感L13C，输入端IN1C连接到电容C11C的第一端，电容C11C的第二端连接到电容C12C的第一端，电感L13C的第一端连接到电容C12C的第二端，电感L13C的第二端连接到电容C11C的第一端，电容C13C的第一端连接到电容C12C的第二端，电容C13C的第二端连接到电容C14C的第一端，电容C14C的第二端连接到电容C15C的第一端，电容C15C的第二端连接到输入端IN2C，电感L12C的第一端连接电容C11C的第二端，电感L12C的第二端连接到电容C15C的第二端，电感L11C的第一端连接到电容C14C的第一端，电感L11C的第二端连接到电容C15C的第二端，可变电容B1C的第一端连接电容C13C的第一端，可变电容B1C的第二端连接电容C13C的第二端，可变电容B2C的第一端连接电容C12C的第一端，可变电容B2C的第二端连接电容C15C的第二端。第三失谐电路122C包括：电容C16C、电容C17C、电容C18C、电容C19C、电感L14C、电感L15C、电感L16C、电感L17C、二极管D7C、二极管D8C和二极管D9C，电感L16C的第一端连接到电容C16C的第一端，电感L16C的第二端连接到二极管D7C的负极，二极管D7C的正极连接到电容C16C的第二端，电容C18C的第二端连接到电容C16C的第二端，电容C17C的第一端连接到电容C18C的第一端，二极管D8C的正极连接到电容C17C的第二端，二极管D8C的负极连接到电感L14C的第二端，电感L14C的第一端连接到电容C18C的第二端，二极管D9C的正极连接到电容C19C的第二端，二极管D9C的负极连接到电感L15C的第二端，电感L15C的第一端连接到电容C19C的第一端，电感L17C的第一端连接到电容C17C的第二端，电感L17C的第二端连接到电容C19C的第一端。
参阅图18，图18为本实施例中线圈H/F4的电路图，线圈H/F4的导线X45、导线X46、导线X47和到导线X48围成了一个矩形加凸起结构，导线X46、导线X47、导线X48为L型导线，导线X45包括Z型导线和L型导线，Z型导线和L型导线之间组成了凸起结构用于连接电感L17D，导线X46与导线X47之间连接了电感L16D、二极管D7D和电容C16D组成的次级失谐电路，导线X45与导线X46之间连接了电感L14D、二极管D8D、电容C17D和电容C18D组成的次级失谐电路，导线X45与导线X48之间连接了电感L15D、二极管D9D和电容C19D组成的次级失谐电路，导线X47与导线X48之间连接了第二接口电路121D。本实施例线圈H/F2的电感L17B和线圈H/F4的电感L17D相互邻近对应设置，用于线圈H/F2和线圈H/F4之间的去耦。通过适应调整电感L17B合电感L17D之间的电感线圈重合面积实现去耦。第三接口电路121D包括：输入端IN1D、输入端IN2D、电容C11D、电容C12D、电容C13D、电容C14D、电容C15D、可变电容B1D、可变电容B2D、电感L11D、电感L12D和电感L13D，输入端IN1D连接到电容C11D的第一端，电容C11D的第二端连接到电容C12D的第一端，电感L13D的第一端连接到电容C12D的第二端，电感L13D的第二端连接到电容C11D的第一端，电容C13D的第一端连接到电容C12D的第二端，电容C13D的第二端连接到电容C14D的第一端，电容C14D的第二端连接到电容C15D的第一端，电容C15D的第二端连接到输入端IN2D，电感L12D的第一端连接电容C11D的第二端，电感L12D的第二端连接到电容C15D的第二端，电感L11D的第一端连接到电容C14D的第一端，电感L11D的第二端连接到电容C15D的第二端，可变电容B1D的第一端连接电容C13D的第一端，可变电容B1D的第二端连接电容C13D的第二端，可变电容B2D的第一端连接电容C12D的第一端，可变电容B2D的第二端连接电容C15D的第二端。第三失谐电路122D包括：电容C16D、电容C17D、电容C18D、电容C19D、电感L14D、电感L15D、电感L16D、电感L17D、二极管D7D、二极管D8D和二极管D9D，电感L16D的第一端连接到电容C16D的第一端，电感L16D的第二端连接到二极管D7D的负极，二极管D7D的正极连接到电容C16D的第二端，电容C18D的第二端连接到电容C16D的第二端，电容C17D的第一端连接到电容C18D的第一端，二极管D8D的正极连接到电容C17D的第二端，二极管D8D的负极连接到电感L14D的第二端，电感L14D的第一端连接到电容C18D的第二端，二极管D9D的正极连接到电容C19D的第二端，二极管D9D的负极连接到电感L15D的第二端，电感L15D的第一端连接到电容C19D的第一端，电感L17D的第一端连接到电容C17D的第二端，电感L17D的第二端连接到电容C19D的第一端。
在本实施例中，核磁测试信号通过第三接口电路121的输入端IN1和输入 端IN2输入到第三接口电路121中，通过第三失谐电路122控制H/F线圈的工作状态，以减少由其他阵列环路中的铜成分引起的残留干扰和屏蔽效应。通过设计多个独立失谐电路分别控制多个核素线圈的工作状态，降低内外层线圈核素间的干扰，当Na阵列(第一子线圈阵列)和H/F双调谐阵列(第二线圈阵列)同时工作时，使P阵列(第二子线圈阵列)失谐，当P阵列工作时，使Na阵列和H/F双调谐阵列失谐，以减小P和H/F/N阵列之间的电磁干扰。并且为了解耦P和H/F/Na阵列，在阵列的每个环路中插入三个有源失谐电路，以减少由其他阵列环路中的铜成分引起的残留干扰和屏蔽效应。在本实施例中，每个线圈中的元件的数值可以根据实际情况进行调整，在本实施例中不做限定。
前端模块2与线圈模块1连接，设置为产生核磁测试信号并采集感应信号。
在本实施例中，前端模块2设置为连接外部射频信号发生器，通过输入核磁测试信号并使用例如正交耦合器将核磁测试信号进行相位偏差，将核磁测试信号拆分为多个相位不同的射频信号，可以同时或者不同时发射多种核素信号进行核磁共振成像的效果。
本实施例公开了一种四核射频线圈电路，包括：线圈模块，所述线圈模块设置为接收核磁测试信号并根据所述核磁测试信号生成感应信号；前端模块，所述前端模块与所述线圈模块连接，设置为产生所述核磁测试信号并采集所述感应信号。本申请实施例公开的一种四核射频线圈电路，通过双层嵌套式结构组合设计，在与多频多通道电子与时序控制系统的高度配合的基础上，可以同时或者不同时发射多种核素信号进行核磁共振成像，解决了不同核素间相互作用以及电磁干扰的问题，实现多通道多频率高均匀性的射频激发和高灵敏度的信号采集。
实施例二
本实施例是在实施例一的基础上对前端模块的结构进行说明，图19为本实施例二中前端模块的电路图，前端模块2包括：功分模块21和信号驱动模块22。
功分模块21与信号驱动模块22连接，功分模块21设置为将核磁测试信号拆分为多路测试信号。
在本实施例中，功分模块21包括三个1:2功分器，分别为功分器211、功分器212和功分器213，功分模块21输入端设置为连接外部信号发生器，将外部输入的高功率输出信号由三个1：2功分器分为4路信号，每1路信号对应输入到线圈模块1中的不同线圈单元。功分模块21设置为配合实现多个通道激励源的幅值和相位调控，分离出4路信号，最终实现多个通道激励源幅值改变和 相位调制。
信号驱动模块22与线圈模块1连接，信号驱动模块22设置为将多路测试信号输入到线圈模块1中。
在本实施例中，通过4个信号驱动模块22连接到功分模块21产生的4路信号上，每个线圈的同轴电缆上都连接有三个不同频率的射频陷(射频陷221、射频陷222和射频陷223)，对应于线圈工作频率的射频陷连接在靠近线圈方向的位置，另两个连接在线圈工作频率的射频陷之后，将测试信号通过输出端1输入到线圈模块1中，从线圈接收到的微弱磁共振电压信号经过放大器224放大，经电桥225将信号分成两路，经过病床传输至谱仪，完成图像重建，显示核磁共振成像结果。
参阅图20，图20为本实施例中一种四核射频线圈电路的电路图，第一子线圈阵列11a连接4个信号驱动模块22A、22B、22C和22D，4个信号驱动模块22A、22B、22C和22D与功分模块21E连接，功分模块21E连接到外部信号输入端。第二线圈阵列12连接4个信号驱动模块22F、22G、22H和22I，4个信号驱动模块22F、22G、22H和22I与功分模块21J连接，功分模块21J连接到外部信号输入端。信号输入端通过输入预设核磁信号通过功分模块分为多个不同相位差的信号输入到第一子线圈阵列11a和第二线圈阵列12中，通过检测到的反馈信号将信号输入到外部显示设备中，即可观察核磁检测结果。在替代实施例中，第一子线圈阵列11a与第二线圈阵列也可以不连接同一信号输入端，可根据实际应用情况进行选择。
第二子线圈阵列与信号驱动模块的连接关系，与第一子线圈阵列类似，此处不再赘述。
本实施例公开了一种四核射频线圈电路，包括：线圈模块，所述线圈模块设置为接收核磁测试信号并根据所述核磁测试信号生成感应信号；前端模块，所述前端模块与所述线圈模块连接，设置为产生所述核磁测试信号并采集所述感应信号。本申请实施例公开的一种四核射频线圈电路，通过双层嵌套式结构组合设计，在与多频多通道电子与时序控制系统的高度配合的基础上，可以同时或者不同时发射多种核素信号进行核磁共振成像，解决了不同核素间相互作用以及电磁干扰的问题，实现多通道多频率高均匀性的射频激发和高灵敏度的信号采集。

Claims (13)

  1. 一种四核射频线圈电路，包括：
    线圈模块，所述线圈模块设置为接收核磁测试信号并根据所述核磁测试信号生成感应信号；
    前端模块，所述前端模块与所述线圈模块连接，设置为产生所述核磁测试信号并采集所述感应信号。
  2. 根据权利要求1中所述的四核射频线圈电路，其中，所述线圈模块包括第一线圈阵列和第二线圈阵列，所述第一线圈阵列与所述第二线圈中心位置重合。
  3. 根据权利要求2中所述的四核射频线圈电路，其中，所述第一线圈阵列包括第一子线圈阵列和第二子线圈阵列，所述第一子线圈阵列包括多个第一线圈单元，所述多个第一线圈单元基于第一预设相位差叠加排列，所述第二子线圈阵列包括多个第二线圈单元，所述多个第二线圈单元基于第二预设相位差叠加排列，所述第二线圈阵列包括多个第三线圈单元，所述多个第三线圈单元基于第三预设相位差叠加排列。
  4. 根据权利要求3中所述的四核射频线圈电路，其中，所述第一线圈单元包括：第一接口电路和第一失谐电路，所述第一失谐电路与所述第一接口电路连接，所述第一接口电路连接到所述前端模块。
  5. 根据权利要求4中所述的四核射频线圈电路，其中，所述第一接口电路包括：输入端IN1、输入端IN2、电容C1、电容C2和电感L1，所述输入端IN1连接到所述电容C1的第一端，所述电容C1的第二端连接到所述电容C2的第一端，所述电容C2的第二端连接到所述电感L1的第一端，所述电感L1的第二端连接到所述电容C2的第一端，所述输入端IN2连接到所述电容C1的第二端。
  6. 根据权利要求4中所述的四核射频线圈电路，其中，所述第一失谐电路包括：电感L2、电感L3、电感L4、电感L5、电容C3、电容C4、电容C5、二极管D1、二极管D2和二极管D3；
    其中，所述电感L2的第一端连接到所述电容C3的第一端，所述电感L2的第二端连接到所述二极管D1的负极，所述二极管D1的正极连接到所述电容C3的第二端，所述电容C4的第二端连接到所述电容C3的第一端，所述二极管D2的正极连接到所述电容C4的第二端，所述二极管D2的负极连接到所述电感L3的第二端，所述电感L3的第一端连接到所述电容C4的第一端，所述二极管D3的正极连接到所述电容C5的第二端，所述二极管D3的负极连接到所述电感L4的第二端，所述电感L4的第一端连接到所述电容C5的第一端，所述电感L5的第一端连接到所述电容C5的第二端，所述电感L5的第二端连接到所述电 容C4的第一端；或者，所述电感L2的第一端连接到所述电容C3的第一端，所述电感L2的第二端连接到所述二极管D1的负极，所述二极管D1的正极连接到所述电容C3的第二端，所述电容C4的第二端连接到所述电容C3的第二端，所述二极管D2的正极连接到所述电容C4的第一端，所述二极管D2的负极连接到所述电感L3的第二端，所述电感L3的第一端连接到所述电容C4的第二端，所述二极管D3的正极连接到所述电容C5的第二端，所述二极管D3的负极连接到所述电感L4的第二端，所述电感L4的第一端连接到所述电容C5的第一端，所述电容感L5的第一端连接到所述电容C5的第一端，所述电感L5的第二端连接到所述电容C4的第一端。
  7. 根据权利要求3中所述的四核射频线圈电路，其中，所述第二线圈单元包括：第二接口电路和第二失谐电路，所述第二失谐电路与所述第二接口电路连接，所述第二接口电路连接到所述前端模块。
  8. 根据权利要求7所述的四核射频线圈电路，其中，所述第二接口电路包括：输入端IN1、输入端IN2、电容C6、电容C7和电感L6，所述输入端IN1连接到所述电容C6的第一端，所述电容C6的第二端连接到所述电容C7的第一端，所述电容C7的第二端连接到所述电感L6的第一端，所述电感L6的第二端连接到所述电容C7的第一端，所述输入端IN2连接到所述电容C6的第二端。
  9. 根据权利要求7所述的四核射频线圈电路，其中，所述第二失谐电路包括：电感L7、电感L8、电感L9、电感L10、电容C8、电容C9、电容C10、二极管D4、二极管D5和二极管D6；
    其中，所述电感L7的第一端连接到所述电容C8的第一端，所述电感L7的第二端连接到所述二极管D4的负极，所述二极管D4的正极连接到所述电容C8的第二端，所述电容C9的第二端连接到所述电容C8的第一端，所述二极管D5的正极连接到所述电容C9的第二端，所述二极管D5的负极连接到所述电感L8的第二端，所述电感L8的第一端连接到所述电容C9的第一端，所述二极管D6的正极连接到所述电容C10的第二端，所述二极管D6的负极连接到所述电感L9的第二端，所述电感L9的第一端连接到所述电容C10的第一端，所述电感L10的第一端连接到所述电容C10的第二端，所述电感L10的第二端连接到所述电容C9的第一端；或者，所述电感L7的第一端连接到所述电容C8的第一端，所述电感L7的第二端连接到所述二极管D4的负极，所述二极管D4的正极连接到所述电容C8的第二端，所述电容C9的第二端连接到所述电容C8的第二端，所述二极管D5的正极连接到所述电容C9的第一端，所述二极管D5的负极连接到所述电感L8的第二端，所述电感L8的第一端连接到所述电容C9的第二端，所述二极管D6的正极连接到所述电容C10的第二端，所述二极管 D6的负极连接到所述电感L9的第二端，所述电感L9的第一端连接到所述电容C10的第一端，所述电容感L10的第一端连接到所述电容C10的第一端，所述电感L10的第二端连接到所述电容C9的第一端。
  10. 根据权利要求3中所述的四核射频线圈电路，其中，所述第三线圈单元包括：第三接口电路和第三失谐电路，所述第三失谐电路与所述第三接口电路连接，所述第二接口电路连接到所述前端模块
  11. 根据权利要求10中所述的四核射频线圈电路，其中，所述第三接口电路包括：输入端IN1、输入端IN2、电容C11、电容C12、电容C13、电容C14、电容C15、可变电容B1、可变电容B2、电感L11、电感L12和电感L13，所述输入端IN1连接到所述电容C11的第一端，所述电容C11的第二端连接到所述电容C12的第一端，所述电感L13的第一端连接到所述电容C12的第二端，所述电感L13的第二端连接到所述电容C11的第一端，所述电容C13的第一端连接到所述电容C12的第二端，所述电容C13的第二端连接到所述电容C14的第一端，所述电容C14的第二端连接到所述电容C15的第一端，所述电容C1015第二端连接到所述输入端IN2，所述电感12的第一端连接所述电容C11的第二端，所述电感L12的第二端连接到所述电容C15的第二端，所述电感L11的第一端连接到所述电容C14的第一端，所述电感L11的第二端连接到所述电容C15的第二端，所述可变电容B1的第一端连接所述电容C13的第一端，所述可变电容B1的第二端连接所述电容C13的第二端，所述可变电容B2的第一端连接所述电容C12的第一端，所述可变电容B2的第二端连接所述电容C15的第二端。
  12. 根据权利要求10中所述的四核射频线圈电路，其中，所述第三失谐电路包括：电容C16、电容C17、电容C18、电容C19、电感L14、电感L15、电感L16、电感L17、二极管D7、二极管D8和二极管D9；
    其中，所述电感L16的第一端连接到所述电容C16的第一端，所述电感L16的第二端连接到所述二极管D7的负极，所述二极管D7的正极连接到所述电容C16的第二端，所述电容C17的第二端连接到所述电容C16的第一端，所述电容C17的第一端连接到所述电容C18的第二端，所述二极管D8的正极连接到所述电容C17的第二端，所述二极管D8的负极连接到所述电感L14的第二端，所述电感L14的第一端连接到所述电容C18的第一端，所述二极管D9的正极连接到所述电容C19的第二端，所述二极管D9的负极连接到所述电感L15的第二端，所述电感L15的第一端连接到所述电容C19的第一端，所述电感L17的第一端连接到所述电容C18的第一端，所述电感L17的第二端连接到所述电容C19的第二端；或者，所述电感L16的第一端连接到所述电容C16的第一端，所述电感L16的第二端连接到所述二极管D7的负极，所述二极管D7的正极连 接到所述电容C16的第二端，所述电容C18的第二端连接到所述电容C16的第二端，所述电容C17的第一端连接到所述电容C18的第一端，所述二极管D8的正极连接到所述电容C17的第二端，所述二极管D8的负极连接到所述电感L14的第二端，所述电感L14的第一端连接到所述电容C18的第二端，所述二极管D9的正极连接到所述电容C19的第二端，所述二极管D9的负极连接到所述电感L15的第二端，所述电感L15的第一端连接到所述电容C19的第一端，所述电感L17的第一端连接到所述电容C17的第二端，所述电感L17的第二端连接到所述电容C19的第一端。
  13. 根据权利要求1中所述的四核射频线圈电路，其中，所述前端模块包括：功分模块和信号驱动模块，所述功分模块与信号驱动模块连接，所述信号驱动模块与所述线圈模块连接，所述功分模块设置为将所述核磁测试信号拆分为多路测试信号，所述信号驱动模块设置为将所述多路测试信号输入到所述线圈模块中。
PCT/CN2020/103680 2020-04-27 2020-07-23 四核射频线圈电路 WO2021217910A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
DE212020000824.8U DE212020000824U1 (de) 2020-04-27 2020-07-23 Quad-Core-Hochfrequenzspulenschaltung
US17/921,465 US20230204697A1 (en) 2020-04-27 2020-07-23 Quad-core radio-frequency coil circuit

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202010346493.X 2020-04-27
CN202010346493.XA CN111426997A (zh) 2020-04-27 2020-04-27 四核射频线圈电路

Publications (1)

Publication Number Publication Date
WO2021217910A1 true WO2021217910A1 (zh) 2021-11-04

Family

ID=71551925

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/103680 WO2021217910A1 (zh) 2020-04-27 2020-07-23 四核射频线圈电路

Country Status (4)

Country Link
US (1) US20230204697A1 (zh)
CN (1) CN111426997A (zh)
DE (1) DE212020000824U1 (zh)
WO (1) WO2021217910A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114137458A (zh) * 2021-11-23 2022-03-04 深圳先进技术研究院 一种双核射频线圈系统

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111426997A (zh) * 2020-04-27 2020-07-17 深圳先进技术研究院 四核射频线圈电路
CN113608155B (zh) * 2021-08-23 2022-09-27 深圳先进技术研究院 磁共振多核射频线圈装置及控制方法、磁共振成像系统
WO2023028785A1 (zh) * 2021-08-30 2023-03-09 深圳先进技术研究院 多核射频接收线圈结构、多核射频接收装置及设备
CN117054940B (zh) * 2023-08-15 2024-03-26 浙江大学 一种用于磁共振成像的多核检测线圈组件

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1420363A (zh) * 1996-06-27 2003-05-28 皇家菲利浦电子有限公司 用于磁共振成像装置的射频线圈系统
CN101427150A (zh) * 2006-04-24 2009-05-06 皇家飞利浦电子股份有限公司 多元件rf线圈的简单去耦，还能够实现去谐和匹配功能
CN102762997A (zh) * 2010-02-22 2012-10-31 皇家飞利浦电子股份有限公司 用于涉及并行mri的多核mr图像重构的rf天线装置和方法
CN105759230A (zh) * 2016-02-25 2016-07-13 哈尔滨医科大学 一种多核磁共振成像用四频射频表面线圈
US9606204B2 (en) * 2011-12-12 2017-03-28 Shenzhen Institutes Of Advanced Technology Chinese Academy Of Sciences Magnetic resonance multi-core array radio frequency device and magnetic resonance signal receiving method
CN107329100A (zh) * 2017-07-07 2017-11-07 哈尔滨医科大学 一种多核素多频共振同步成像系统
CN107526049A (zh) * 2017-09-13 2017-12-29 中国科学院生物物理研究所 一种用于超高场的多核代谢成像双频头线圈
CN107561464A (zh) * 2017-07-17 2018-01-09 上海联影医疗科技有限公司 磁共振射频线圈和磁共振系统
CN108680882A (zh) * 2018-06-28 2018-10-19 深圳先进技术研究院 一种双核射频线圈装置和双核射频阵列线圈装置
CN111426997A (zh) * 2020-04-27 2020-07-17 深圳先进技术研究院 四核射频线圈电路

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1420363A (zh) * 1996-06-27 2003-05-28 皇家菲利浦电子有限公司 用于磁共振成像装置的射频线圈系统
CN101427150A (zh) * 2006-04-24 2009-05-06 皇家飞利浦电子股份有限公司 多元件rf线圈的简单去耦，还能够实现去谐和匹配功能
CN102762997A (zh) * 2010-02-22 2012-10-31 皇家飞利浦电子股份有限公司 用于涉及并行mri的多核mr图像重构的rf天线装置和方法
US9606204B2 (en) * 2011-12-12 2017-03-28 Shenzhen Institutes Of Advanced Technology Chinese Academy Of Sciences Magnetic resonance multi-core array radio frequency device and magnetic resonance signal receiving method
CN105759230A (zh) * 2016-02-25 2016-07-13 哈尔滨医科大学 一种多核磁共振成像用四频射频表面线圈
CN107329100A (zh) * 2017-07-07 2017-11-07 哈尔滨医科大学 一种多核素多频共振同步成像系统
CN107561464A (zh) * 2017-07-17 2018-01-09 上海联影医疗科技有限公司 磁共振射频线圈和磁共振系统
CN107526049A (zh) * 2017-09-13 2017-12-29 中国科学院生物物理研究所 一种用于超高场的多核代谢成像双频头线圈
CN108680882A (zh) * 2018-06-28 2018-10-19 深圳先进技术研究院 一种双核射频线圈装置和双核射频阵列线圈装置
CN111426997A (zh) * 2020-04-27 2020-07-17 深圳先进技术研究院 四核射频线圈电路

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114137458A (zh) * 2021-11-23 2022-03-04 深圳先进技术研究院 一种双核射频线圈系统
CN114137458B (zh) * 2021-11-23 2022-08-12 深圳先进技术研究院 一种双核射频线圈系统
WO2023092700A1 (zh) * 2021-11-23 2023-06-01 深圳先进技术研究院 双核射频线圈系统

Also Published As

Publication number Publication date
US20230204697A1 (en) 2023-06-29
CN111426997A (zh) 2020-07-17
DE212020000824U1 (de) 2023-01-30

Similar Documents

Publication Publication Date Title
WO2021217910A1 (zh) 四核射频线圈电路
US7898255B2 (en) Inspection apparatus using magnetic resonance and nuclear magnetic resonance signal receiver coil
JP3817585B2 (ja) 磁気共鳴撮像システム
JP3779384B2 (ja) 磁気共鳴撮像装置
JP2009534098A (ja) 磁気共鳴撮像及び分光システム用ｒｆコイルアセンブリ
JP3957327B2 (ja) Ｎｍｒ用の直角位相だ円形バード・ケージ・コイル
JPS63111846A (ja) Ｎｍｒ装置
US20150369886A1 (en) System and method for decoupling magnetic resonance imaging radio frequency coils with a modular magnetic wall
US20150355297A1 (en) System and method for decoupling magentic resonance imaging radio frequency coils with a modular magnetic wall
WO2023024229A1 (zh) 磁共振多核射频线圈装置及控制方法、磁共振成像系统
JP2009542295A (ja) オンボード・デジタル受信回路を有する無線周波数面コイル
WO2014088941A1 (en) System and method for improved radio-frequency detection or b0 field shimming in magnetic resonance imaging
RU2524447C2 (ru) Устройства и кабельное соединение для использования в многорезонансной системе магнитного резонанса
JP2002345780A (ja) マトリクス正則化を用いたｍｒｉ画像品質改善法
CN105849576A (zh) 降低用于mri 成像和核成像的组合式组件中的干扰
JP3157157B2 (ja) 多重共鳴ｎｍｒコイル
CN107110925A (zh) 用于体线圈导体中的集成拾波器环的系统和方法
CN212433380U (zh) 四核射频线圈电路
US20130076353A1 (en) Recording of calibration data for a magnetic resonance system
WO2023092700A1 (zh) 双核射频线圈系统
WO2021097940A1 (zh) 多通道射频线圈装置及核磁共振成像系统
JP3197262B2 (ja) 磁気共鳴映像装置
US10197646B2 (en) Decoupling of parallel transmission arrays in magnetic resonance imaging
CN115856736A (zh) 一种磁共振双核成像系统及其异形鸟笼线圈装置
US8378681B2 (en) Multiple-frequency RF trap and MRI system

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20932947

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 20932947

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 20/04/2023)