WO2021217413A1 - Substrat d'affichage et dispositif d'affichage - Google Patents

Substrat d'affichage et dispositif d'affichage Download PDF

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Publication number
WO2021217413A1
WO2021217413A1 PCT/CN2020/087477 CN2020087477W WO2021217413A1 WO 2021217413 A1 WO2021217413 A1 WO 2021217413A1 CN 2020087477 W CN2020087477 W CN 2020087477W WO 2021217413 A1 WO2021217413 A1 WO 2021217413A1
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WIPO (PCT)
Prior art keywords
sub
pixel
light
electrode
transistor
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PCT/CN2020/087477
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English (en)
Chinese (zh)
Inventor
冯雪欢
李永谦
Original Assignee
京东方科技集团股份有限公司
合肥京东方卓印科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 京东方科技集团股份有限公司, 合肥京东方卓印科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2020/087477 priority Critical patent/WO2021217413A1/fr
Priority to CN202080000618.1A priority patent/CN113939865B/zh
Publication of WO2021217413A1 publication Critical patent/WO2021217413A1/fr

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00

Definitions

  • the embodiment of the present disclosure relates to a display substrate and a display device.
  • a pixel array of a liquid crystal display panel or an Organic Light Emitting Diode (OLED) display panel usually includes multiple rows of gate lines and multiple columns of data lines interlaced with the gate lines.
  • a GOA Gate driver On Array including multiple cascaded shift register units can be used to provide on-off voltage signals (scanning signals) for multiple rows of gate lines of the pixel array, so as to control the sequential opening of the multiple rows of gate lines.
  • the data lines provide data signals to the pixel units of the corresponding rows in the pixel array, so as to form the gray voltages required by each gray level of the displayed image in each pixel unit, and then display a frame of image. It is widely used to integrate GOAs of multiple cascaded shift register units generally on the short side of the display panel.
  • At least one embodiment of the present disclosure provides a display substrate, which includes a base substrate, a plurality of sub-pixel units, and a gate driving circuit.
  • the base substrate includes a display area, the display area includes a plurality of sub-display areas arranged in an array, the plurality of sub-display areas include a plurality of first sub-display areas and are located at least in a first direction.
  • each of the multiple sub-pixel units includes a light-emitting element and a sub-pixel drive circuit for driving the light-emitting element to emit light
  • the plurality of sub-pixel units include a plurality of first sub-pixel units and a plurality of second sub-pixel units, and the light-emitting elements of the plurality of first sub-pixel units are located in the plurality of first sub-display regions in a one-to-one correspondence , And the light-emitting elements of the plurality of second sub-pixel units are located in the plurality of second sub-display regions in one-to-one correspondence;
  • the gate driving circuit is at least partially located in the plurality of second sub-display regions, and the gate The driving circuit is configured to output the gate scanning signals for driving the plurality of sub-pixel units row by row.
  • the orthographic projection on the base substrate and the orthographic projection of the gate driving circuit on the base substrate at least partially overlap.
  • the light-emitting element of each of the plurality of sub-pixel units includes a light-emitting area and a first electrode at least partially located in the light-emitting area of the light-emitting element
  • the display substrate It further includes a pixel defining layer, the pixel defining layer is disposed on a side of the sub-pixel driving circuit of the plurality of sub-pixel units away from the base substrate, the pixel defining layer includes a plurality of openings, the plurality of openings One-to-one correspondence among the multiple light-emitting elements located in the multiple sub-pixel units, each of the multiple openings is configured to expose the first electrode to form a light-emitting area of the light-emitting element, and each light-emitting element The distance between each point of the first electrode in the corresponding position in the light-emitting area of each light-emitting element and the base substrate is equal.
  • the orthographic projection of the light-emitting regions of the light-emitting elements of the plurality of second sub-pixel units on the base substrate and the gate driving circuit are on the base substrate.
  • the orthographic projections on the base substrate at least partially overlap.
  • the light-emitting regions of the light-emitting elements of the plurality of sub-pixel units arranged in a row in the first direction are arranged at equal intervals.
  • the sub-pixel driving circuit of each second sub-pixel unit of the plurality of second sub-pixel units is at least partially located in contact with the light-emitting circuit of the second sub-pixel unit.
  • the first sub-display area adjacent to the second sub-display area where the element is located is located.
  • the sub-pixel driving circuits of the plurality of sub-pixel units are located in the plurality of first sub-display regions.
  • the orthographic projection of at least part of the light-emitting elements in the plurality of first sub-display regions on the base substrate and at least two of the first sub-pixels The orthographic projections of the sub-pixel driving circuits of the unit on the base substrate at least partially overlap.
  • the plurality of sub-pixel units are arranged in N rows
  • the gate driving circuit includes N cascaded shift register units
  • the n-th stage shift register The unit is connected to the sub-pixel driving circuit of the plurality of sub-pixel units in the nth row
  • the n-th stage shift register unit is located in the plurality of second sub-display areas in the nth row, 1 ⁇ n ⁇ N, and N is greater than or equal to An integer of 2.
  • the first electrode is provided on the sub-pixel driving circuit of the plurality of sub-pixel units and the gate driving circuit on a side away from the base substrate, And the first electrode is connected with the sub-pixel driving circuit.
  • each of the plurality of sub-pixel units further includes a first via hole
  • the first electrode of the light-emitting element includes a main body part and extends from the main body part. At least part of the main body part is located in the light-emitting area of the light-emitting element, and the lead part is connected to the sub-pixel driving circuit through the first via hole.
  • the lead portion of the first electrode of the light-emitting element of the second sub-pixel unit extends from the second sub-display area where the light-emitting element of the second sub-pixel unit is located. It extends into the adjacent first sub-display area, and is connected to the sub-pixel driving circuit of the second sub-pixel unit in the first sub-display area through the first via hole.
  • the plurality of sub-pixel units further include a first power supply line, and the first power supply line extends in a second direction different from the first direction and is provided Between the sub-pixel driving circuits of the plurality of first sub-pixel units, the orthographic projection of the first power line on the base substrate and the first electrodes of the light-emitting elements of the plurality of sub-pixel units are located at the The orthographic projections on the base substrate at least partially overlap, the light-emitting element of each of the plurality of sub-pixel units further includes a second electrode disposed on a side of the first electrode away from the base substrate, and the multiple The second electrode of the light-emitting element of at least one first sub-pixel unit of the first sub-pixel unit is connected to the first power line through a second via hole, and the first light-emitting element of the at least one first sub-pixel unit
  • the lead part of the electrode surrounds the second via hole and passes through a side of the second via hole away
  • the second via hole and the light-emitting area of the light-emitting element of the first sub-pixel unit corresponding to the second via hole are along the second direction.
  • the distance between is greater than the distance along the second direction between the first via hole and the light-emitting area of the light-emitting element of the first sub-pixel unit.
  • the sub-pixel driving circuit of each of the plurality of sub-pixel units includes a data writing circuit, a driving circuit, a charge storage circuit, and a sensing circuit. Is connected to the first node and the second node, and is configured to control the driving current flowing through the light-emitting element under the control of the level of the first node; the data writing circuit and the first node Connected and configured to receive the gate scan signal as a scan drive signal, and write a data signal to the first node in response to the scan drive signal; the charge storage circuit is connected to the first node and the The second node is connected and is configured to store the written data signal and the reference voltage signal; the sensing circuit is connected to the second node and is configured to receive the gate scan signal as a sensing drive signal , And in response to the sensing driving signal, writing the reference voltage signal to the driving circuit or reading a sensing voltage signal from the driving circuit; the light-emitting element and the second no
  • the plurality of sub-pixel units further includes a plurality of data lines extending along the second direction, and the plurality of data lines and each column of the plurality of sub-pixel units
  • the pixel units are connected in one-to-one correspondence, and the orthographic projections of the plurality of data lines on the base substrate and the orthographic projections of the first electrodes of the light-emitting elements of the plurality of sub-pixel units on the base substrate at least partially overlap
  • the display substrate further includes a plurality of gate lines extending along the first direction, the plurality of gate lines are connected to the gate driving circuit and each row of sub-pixel units, and the plurality of gate lines include a first gate line.
  • the output terminal of the shift register unit is connected to output the gate scan signal output from the output terminal of the M-th row of shift register unit to the drive circuit of the sub-pixel drive circuit of the M-th row of sub-pixel units as a scan drive Signal and the sensing circuit output to the sub-pixel drive circuit of the sub-pixel unit in the M-1th row as the sensing drive signal, the second gate line and the sub-pixel of the sub-pixel unit in the M-th row
  • the sensing circuit of the driving circuit, the driving circuit of the sub-pixel driving circuit of the sub-pixel unit of the M+1th row, and the output terminal of the M+1th shift register unit are connected to connect the M+1th row
  • the gate scan signal output from the output terminal of the shift register unit is output to the drive circuit of the sub-pixel
  • the data writing circuit includes a data writing transistor
  • the driving circuit includes a driving transistor
  • the sensing circuit includes a sensing transistor
  • the charge storage circuit Including a storage capacitor
  • the active layer of the data writing transistor extends along the first direction and is located between the first gate line and the second gate line
  • the active layer of the driving transistor and the The active layer of the sensing transistor extends along the second direction and is located on the side of the data writing transistor close to the second gate line
  • the storage capacitor is located on the active layer of the data writing transistor
  • the area surrounded by the active layer of the driving transistor and the active layer of the sensing transistor, and the orthographic projection of the data line connected to the data writing circuit on the base substrate are located on the sensing transistor
  • the active layer is away from the side of the driving transistor.
  • the gate of the data writing transistor is connected to the first gate line to receive the scan driving signal, and the first electrode of the data writing transistor Connected to the data line to receive data signals, the first electrode of the storage capacitor and the gate electrode of the data writing transistor are arranged in the same layer, and the first electrode of the storage capacitor includes a first protrusion and a second protrusion.
  • the first convex portion faces the data writing transistor
  • the second convex portion faces the driving transistor and extends along the second direction
  • the first convex portion is not in the same layer as the data
  • the second pole of the writing transistor is connected
  • the second protrusion serves as the gate of the driving transistor
  • the gate of the sensing transistor is connected to the second gate line and formed integrally
  • the The orthographic projection of the first pole and the second pole on the base substrate are located on both sides of the orthographic projection of the second grid line on the base substrate along the second direction, and the first pass
  • the hole exposes the first electrode of the sensing transistor of the sub-pixel driving circuit, and the lead portion of the first electrode is connected to the first electrode of the sensing transistor through the first via hole.
  • the plurality of sub-pixel units further include a second power line connected to the sub-pixel driving circuit and a sensing signal line connected to the sub-pixel driving circuit
  • the second power line is located between the second sub-display area and the first sub-display area where the sub-pixel driving circuit of the second sub-pixel unit is located
  • the sensing signal line is connected to the first power line Adjacently arranged and located between the first power line and the driving transistor
  • the second electrode of the storage capacitor partially overlaps the first electrode of the storage capacitor
  • the second pole is located on the side of the second gate line close to the storage capacitor, and the second pole of the storage capacitor, the first pole of the driving transistor, and the first pole of the sensing transistor are located in a continuous
  • the second electrode of the driving transistor is connected to the second power line
  • the second electrode of the sensing transistor is connected to the sensing signal line to receive the sensing drive Signal.
  • the display substrate further includes a first transfer electrode extending along the second direction and a first connection trace extending along the first direction, the The second electrode of the driving transistor is connected to the first end of the first transfer electrode, and the second end of the first transfer electrode is connected to the first connection trace that is not in the same layer.
  • the first connection The wiring is connected to the first power line that is not in the same layer, and the first transfer electrode and the second gate line overlap in a direction perpendicular to the base substrate.
  • the display substrate further includes a second transfer electrode extending along the second direction, a second connection trace extending along the first direction, and
  • the second electrode of the sensing transistor is connected to the first end of the second transfer electrode, and the second end of the second transfer electrode is connected to the second connection trace that is not in the same layer.
  • the connection wires are connected to the sensing signal wires that are not in the same layer, and the second transfer electrode and the first connection wires overlap in a direction perpendicular to the base substrate.
  • At least one embodiment of the present disclosure further provides a display device, including the display substrate described in any one of the above.
  • FIG. 1A is a schematic diagram of a display substrate
  • Figure 1B is a circuit diagram of a shift register unit
  • FIG. 1C is a signal timing diagram of the shift register unit shown in FIG. 1B during operation;
  • FIG. 2A is a schematic diagram of a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 2B is a schematic diagram of the distribution of sub-pixel driving circuits and gate driving circuits of sub-pixel units of the display substrate shown in FIG. 2A;
  • FIG. 2C is a schematic diagram of the distribution of the display area of the display substrate shown in FIG. 2A;
  • FIG. 3A is a schematic diagram of the layout of the display substrate shown in FIG. 2A;
  • 3B is a schematic diagram of the layout of light-emitting elements of sub-pixel units of the display substrate of FIG. 3A;
  • 3C is a schematic diagram of the layout of the first electrode of the light-emitting element shown in FIG. 3A;
  • FIG. 4 is a schematic cross-sectional view of a part of the structure of FIG. 3A;
  • 5A is a circuit diagram of a sub-pixel driving circuit of a sub-pixel unit provided by at least one embodiment of the present disclosure
  • 5B is a schematic diagram of the connection between the sub-pixel driving circuit of the sub-pixel unit and the register unit provided by at least one embodiment of the present disclosure
  • FIG. 6 is a layout diagram of a sub-pixel driving circuit of a sub-pixel unit provided by at least one embodiment of the present disclosure
  • FIG. 7A is a plan view of a semiconductor layer of a sub-pixel unit provided by at least one embodiment of the present disclosure
  • 7B is a plan view of the first conductive layer of the sub-pixel unit provided by at least one embodiment of the present disclosure
  • 7C is a plan view of the first conductive layer of the sub-pixel unit provided by at least one embodiment of the present disclosure
  • FIG. 8A is a layout diagram of a part of the structure of a shift register unit provided by at least one embodiment of the present disclosure
  • 8B is a layout diagram of another part of the structure of the shift register unit provided by at least one embodiment of the present disclosure.
  • FIG. 8C is a layout diagram of another part of the structure of the shift register unit provided by at least one embodiment of the present disclosure.
  • FIG. 9 is a schematic diagram of a display device provided by at least one embodiment of the present disclosure.
  • the display panel may be a liquid crystal display (LCD) panel or an organic light emitting diode (OLED) display panel.
  • LCD liquid crystal display
  • OLED organic light emitting diode
  • a GOA including multiple cascaded shift register units is usually integrated on the short side of the display panel. Therefore, when splicing technology is used to form a large display screen, seamless sub-displays cannot be realized. Docking, thereby affecting the display quality of the display.
  • GOA can be solved by transferring the GOA from the peripheral area of the display panel to the pixel array area, for example, vacating multiple areas between the pixel openings (ie, light-emitting areas) of the pixel array of the display panel, and setting the GOA In the multiple areas of the pixel array area, the area of the peripheral area is thereby reduced to realize seamless docking of the various sub-display screens.
  • this design scheme has many defects, which will be described in detail below in conjunction with FIG. 1A.
  • FIG. 1A is a schematic diagram of a display substrate.
  • the display substrate 01 includes a base substrate 010, a data drive chip IC, a plurality of data lines 0D1-0DN (N is an integer greater than 1), and a plurality of gate lines 0G1-0GM (M is an integer greater than 1. ).
  • the base substrate 010 includes a display area 011 and a peripheral area 012.
  • the peripheral area 012 is located on one side of the display area 011.
  • the data driving chip IC is located in the peripheral area 012.
  • the display area 011 includes multiple sub-display areas 013, multiple GOA circuit areas 014, and multiple wiring areas 015.
  • each sub-display area is provided with a sub-pixel unit 016 (including a sub-pixel unit driving circuit and a light-emitting element), and multiple sub-display areas 013 are arranged in multiple columns and multiple rows in the X and Y directions, that is, multiple sub-pixel units. Arranged in an array in the X and Y directions.
  • the plurality of GOA circuit regions 014 includes a gate driving circuit 017, and the gate driving circuit 017 includes a plurality of cascaded shift register units.
  • Each of the plurality of sub-display areas 013 includes a sub-pixel unit 016.
  • Each of the plurality of cascaded shift register units is distributed in the GOA circuit area 014 in a row to provide gate scan signals to the sub-pixel units 016 in the row.
  • the multiple wiring areas 015 include multiple signal lines (for example, clock signal lines) and multiple power lines.
  • the data driving chip IC is configured to provide a data signal to the sub-pixel unit 016.
  • the data lines OD1-0DN connected to the data driving chip IC pass through the display area 011 along the X direction (for example, the vertical direction in the figure) to provide data signals for the sub-pixel units 016 of each column respectively.
  • Fig. 1B is a circuit diagram of a shift register unit
  • Fig. 1C is a signal timing diagram of the shift register unit shown in Fig. 1B during operation.
  • the working process of the shift register unit 017 will be briefly introduced below in conjunction with FIG. 1B and FIG. 1C.
  • FIG. 1B shows the circuit structure of one stage of the shift register unit 170 of the gate driving circuit 017.
  • the shift register unit 170 includes nine transistors (a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor).
  • the gate of the first transistor T1 is connected to the input terminal STU, the first electrode of the first transistor T1 is connected to the second voltage terminal VDD (for example, to maintain the input DC high-level signal), and the second electrode of the first transistor T1 is connected to Pull up the node PU connection.
  • the gate of the second transistor T2 is connected to the reset terminal STD, the first electrode of the second transistor T2 is connected to the pull-up node PU, and the second electrode of the second transistor T2 is connected to the first voltage terminal VGL (for example, the input DC low voltage Level signal) connected to receive the first voltage.
  • VGL for example, the input DC low voltage Level signal
  • the gate of the third transistor T3 is connected to the pull-up node PU, the first electrode of the third transistor T3 is connected to the first clock signal terminal CLK to receive the first clock signal, and the second electrode of the third transistor T3 is connected to the output terminal. GOUT connection.
  • the gate of the fourth transistor T4 is connected to the pull-down node PD, the first electrode of the fourth transistor T4 is connected to the output terminal GOUT, and the second electrode of the fourth transistor T4 is connected to the first voltage terminal VGL to receive the first voltage.
  • the gate of the fifth transistor T5 is connected to the pull-up node PU, the first electrode of the fifth transistor T5 is connected to the pull-down node PD, and the second electrode of the fifth transistor T5 is connected to the first voltage terminal VGL to receive the first voltage. .
  • the gate of the sixth transistor T6 is connected to the pull-down node PD, the first electrode of the sixth transistor T6 is connected to the pull-up node PU, and the second electrode of the sixth transistor T6 is connected to the first voltage terminal VGL to receive the first voltage .
  • the gate of the seventh transistor T7 is connected to the first electrode and both are connected to the second clock signal terminal CLKB, and the second electrode of the seventh transistor T7 is connected to the pull-down node PD.
  • the gate of the eighth transistor T8 is connected to the output terminal GOUT, the first electrode of the eighth transistor T8 is connected to the pull-down node PD, and the second electrode of the eighth transistor T8 is connected to the first voltage terminal VGL to receive the first voltage.
  • the gate of the ninth transistor T9 is connected to the initialization terminal TRST to receive the power-on initialization signal
  • the first pole of the ninth transistor T9 is connected to the pull-up node PU to reset the pull-up node PU
  • the first pole of the ninth transistor T9 is connected to the pull-up node PU.
  • the two poles are connected to the first voltage terminal VGL to receive the first voltage.
  • the first pole of the first capacitor C1 is connected to the pull-up node PU, and the second pole of the first capacitor C1 is connected to the output terminal GOUT.
  • the first pole of the second capacitor C2 is connected to the pull-down node PD, and the second pole of the second capacitor C2 is connected to the first voltage terminal VGL.
  • the first voltage terminal VGL in the embodiment of the present disclosure keeps the input DC low level signal
  • this DC low level is referred to as the first voltage
  • the second voltage terminal VDD for example, keeps the input DC high level.
  • the DC high level is called the second voltage, for example, the second voltage is greater than the first voltage.
  • the transistors used above can all be thin film transistors or field effect transistors or other switching devices with the same characteristics.
  • thin film transistors are used as an example for description.
  • the active layer (channel region) of the transistor is made of semiconductor materials, for example, Polysilicon (such as low temperature polysilicon or high temperature polysilicon), amorphous silicon, indium gallium tin oxide (IGZO), etc., while the gate, source, drain, etc. are made of metal materials, such as metal aluminum or aluminum alloy.
  • the source and drain of the transistor used here can be symmetrical in structure, so the source and drain of the transistor can be structurally indistinguishable.
  • the electrode of the capacitor may be a metal electrode or one of the electrodes may be a semiconductor material (for example, doped polysilicon).
  • the above-mentioned transistors are all described with N-type transistors as an example, that is, each transistor is turned on when the gate is connected to a high level (conduction level), and is turned off when the gate is connected to a low level (cut-off level).
  • the first electrode may be the drain
  • the second electrode may be the source.
  • the present disclosure includes but is not limited to this.
  • one or more transistors in the shift register unit provided by the embodiments of the present disclosure can also be P-type transistors.
  • the first electrode can be the source and the second electrode can be the drain.
  • the polarity of each pole of a certain type of transistor can be connected according to the polarity of each pole of the corresponding transistor in the embodiment of the present disclosure.
  • all the transistors used in the shift register unit can be a signal timing diagram of the shift register unit 170 shown in FIG. 1B when the shift register unit 170 shown in FIG. 1C is working.
  • the working principle of the shift register unit shown in FIG. 1B will be described below in conjunction with the signal timing shown in FIG. 1C.
  • the working principle of the shift register unit 170 is described, and the working principles of the other stages of the shift register unit 170 (except for the first stage of shift register unit) are similar to this, and will not be repeated.
  • the working principle of the first-stage register unit is different from the shift register unit 170 in that: the input end of the first-stage register unit is connected to the trigger signal line GSTV, and the input end of the shift register unit 170 is connected to the previous-stage shift register The output terminal of the unit.
  • the shift register unit 170 performs the following operations.
  • the initialization terminal TRST inputs a high level. Since the initialization terminal TRST inputs a high level, the ninth transistor T9 is turned on, so that the pull-up node PU and the first voltage terminal VGL are electrically connected, and the potential of the pull-up node PU is pulled down to a low level. The third transistor T3 is turned off due to the low level of the pull-up node PU. Therefore, even if the first clock signal terminal CLK inputs a high level at this stage, the output terminal GOUT cannot output this high level. It should be noted that the potential of the pull-down node PD at this stage is uncertain, and FIG. 1C only schematically shows the potential of the pull-down node PD in the first stage t1. In addition, at this stage, other transistors are also kept in the off state, so I will not repeat them.
  • the first clock signal terminal CLK inputs a low level
  • the second clock signal terminal CLKB inputs a high level
  • the input terminal STU inputs a high level. Since the input terminal STU inputs a high level, the first transistor T1 is turned on, so that the high level input from the second voltage terminal VDD charges the first capacitor C1, and the potential of the pull-up node PU is pulled up to the first high level .
  • the seventh transistor T7 Since the second clock signal terminal CLKB inputs a high level, the seventh transistor T7 is turned on, and the high level input from the second clock signal terminal CKLB charges the pull-down node PD. Since the potential of the pull-up node PU is at the first high level, the fifth transistor T5 is turned on, so that the pull-down node PD and the first voltage terminal VGL are electrically connected.
  • the first voltage terminal VGL can be set to keep the input DC low level signal.
  • the seventh transistor T7 and the fifth transistor T5 can be configured (for example, the size ratio, threshold voltage, etc.) of the seventh transistor T7 and the fifth transistor T5 are turned on, the node is pulled down The potential of the PD is pulled down to a lower level, which will not turn on the sixth transistor T6 and the fourth transistor T4. It should be noted that the potential level of the signal timing diagram shown in FIG. 2 is only schematic, and does not represent the true potential value.
  • the pull-up node PU is at the first high level and the third transistor T3 is turned on, at this time the first clock signal terminal CLK inputs a low level, so at this stage, the output terminal GOUT outputs the low level signal.
  • the first clock signal terminal CLK inputs a high level
  • the second clock signal terminal CLKB inputs a low level
  • the input terminal STU inputs a low level. Since the input terminal STU inputs a low level, the first transistor T1 is turned off, and the pull-up node PU maintains the first high level of the previous stage, so that the third transistor T3 remains on. Because the first clock signal terminal CLK is in this stage The input is high, so the output terminal GOUT outputs the high level signal.
  • the level of the pull-up node PU is further pulled up to reach the second high level, so that the third transistor T3 is turned on more fully. Since the potential of the pull-up node PU is at a high level, the fifth transistor T5 continues to conduct, so that the pull-down node PD is electrically connected to the first voltage terminal VGL. At this time, the seventh transistor T7 is low due to the input of the second clock signal terminal CLKB. Therefore, compared with the first stage, the potential of the pull-down node PD is pulled down to a lower low level in this stage. Since the potential of the pull-down node PD is at a low level, the sixth transistor T6 and the fourth transistor T4 remain in the off state, so that the shift register unit will not affect the normal output of the shift signal.
  • the first clock signal terminal CLK inputs a low level
  • the second clock signal terminal CLKB inputs a high level
  • the input terminal STU continues to input a low level
  • the reset terminal STD inputs a high level. Since the reset terminal STD inputs a high level, the second transistor T2 is turned on, and the potential of the pull-up node PU is pulled down to the low level input by the first voltage terminal VGL (for example, keeping the input DC low level signal), so that the third transistor T3 ends.
  • the seventh transistor T7 Since the second clock signal terminal CLKB inputs a high level, the seventh transistor T7 is turned on, and the high level input from the second clock signal terminal CLKB charges the pull-down node PD.
  • the fifth transistor T5 is turned off, the discharge path of the pull-down node PD is cut off, and the pull-down node PD is charged to a high level, thereby making the sixth transistor T6 and the fourth transistor T4 conduct Pull down the potentials of the pull-up node PU and the output terminal GOUT to the low level input by the first voltage terminal VGL, which eliminates the possible occurrence of the output terminal GOUT and the pull-up node PU of the shift register unit in the non-output stage. noise.
  • the pull-up node PU and the pull-down node PD have a mutual restriction relationship. For example, when the potential of the pull-up node PU is high, the potential of the pull-down node PD will be pulled down to a low level; for example, when the potential of the pull-down node PD is high, the potential of the pull-up node PU will be pulled down to a low level. Level.
  • the potential of the pull-up node PU directly affects the output of the shift register unit. In the non-output stage, the potential of the pull-up node PU should be kept stable at a low level, otherwise the shift register unit may be affected within one frame. Cause multiple output. In the non-output stage, if the potential of the pull-down node PD fails to maintain a high level, the potential of the pull-up node PU may drift, thereby affecting the normal output of the shift register unit 170.
  • the gate lines 0G1-0GM (M is an integer greater than 1) connected to the shift register unit 170 of the gate driving circuit 017 pass through the display area 011 along the Y direction (for example, the horizontal direction in the figure), so that The sub-pixel unit 016 provides gate scan signals and the like.
  • the sub-pixel driving circuit of each sub-pixel unit may include pixel circuits with circuit structures such as 7T1C, 8T2C, 4T1C, or 3T1C in the art. It works under the control of scanning signals and the like to drive the light-emitting elements to emit light so as to realize operations such as display.
  • the light-emitting element may be, for example, an organic light-emitting diode (OLED) or a quantum dot light-emitting diode (QLED).
  • the wiring area 015 and the GOA circuit area 014 are located between the plurality of sub-display areas 013.
  • the wiring area 015, the multiple sub-display areas 013, and the GOA circuit area 014 are arranged at intervals. Since some space needs to be left in the display area 011 for the GOA circuit area 014 and the wiring area 015, the space of the sub-display area 013 is compressed, and the space area between the wiring area 105 and the GOA circuit area 014 is compressed.
  • the area is not equal, so the spacing between the multiple sub-display areas 013 in each row is not equal, that is, the arrangement in the Y direction is not evenly spaced, for example, the sub-pixels in 6 adjacent sub-display areas 013 on a row
  • the unit 016 is a repeating unit, and the sub-display area where the 6 repeating units are located is not arranged at equal intervals.
  • the light-emitting area 018 of the light-emitting element of the sub-pixel unit 016 is located in the sub-display area 013. Therefore, the light-emitting area 018 of the light-emitting element of the sub-pixel unit 016 is arranged in the same manner as the sub-display area 013. That is, the light-emitting regions 018 of the light-emitting elements of the sub-pixel unit 016 are arranged at unequal intervals in the Y direction (that is, on a row).
  • the light-emitting area refers to the opening area of the light-emitting element of the sub-pixel unit 016, the light-emitting layer of the light-emitting element is located in the opening area, and the light-emitting layer may emit red light, blue light, or green light, for example.
  • the sub-display area 013 leaves space for the gate driving circuit 017 and other wirings, the space occupied by the light-emitting element is reduced, thereby reducing the area of the opening area of the light-emitting element, thereby The aperture ratio of the display substrate is greatly reduced.
  • the display panel is usually selected as a top-emission type.
  • the light-emitting layer of the light-emitting element of the sub-pixel unit 016 is usually prepared by a printing process. Since the current printing process can only print the light-emitting area of each sub-pixel unit in each sub-display area in equal proportion, and because the multiple sub-display areas 013 of each repeating unit are arranged at unequal intervals, the light-emitting area in each sub-display area 013
  • the light-emitting area 018 of the element needs to be printed separately according to its location, so that each repeating unit of the display substrate 01 shown in FIG. Each light-emitting element is printed to the printing area, which will greatly increase the printing time and reduce the printing efficiency.
  • At least one embodiment of the present disclosure provides a display substrate including a base substrate, a plurality of sub-pixel units, and a gate driving circuit.
  • the base substrate includes a display area, the display area includes a plurality of sub-display areas arranged in an array, and the plurality of sub-display areas includes a plurality of first sub-display areas and a plurality of sub-display areas located between the plurality of first sub-display areas at least in the first direction.
  • At least one embodiment of the present disclosure also provides a display device corresponding to the above-mentioned display substrate.
  • the gate driving circuit is arranged in the display area, and the orthographic projection of the light-emitting elements of the plurality of second sub-pixel units on the base substrate and the gate driving circuit are on the base substrate.
  • the orthographic projections overlap at least partially so that the light-emitting elements can be covered on the gate drive circuit, that is, to avoid reducing the space occupied by the light-emitting elements and reserve for the gate drive circuit to affect the aperture ratio of the display substrate, so that the aperture ratio of the display substrate can be Improve the aperture ratio of the display substrate.
  • FIG. 2A is a schematic diagram of a display substrate provided by at least one embodiment of the present disclosure
  • FIG. 2B is a schematic diagram of the distribution of sub-pixel driving circuits and gate driving circuits of sub-pixel units of the display substrate shown in FIG. 2A
  • FIG. 2C is FIG. 2A
  • the schematic diagram of the distribution of the display area of the display substrate is shown. That is to say, FIG. 2A is a stacked structure diagram of FIG. 2B and FIG. 2C.
  • the display substrate 1 includes a base substrate 10, a plurality of gate lines G1-GK (K is an integer greater than 1) arranged in a first direction Y, and a plurality of gate lines G1-GK arranged in a second direction X.
  • the base substrate 10 includes a display area 11 and a peripheral area 12.
  • the display area 11 is an effective display area, and a pixel array or the like can be arranged in this area.
  • the base substrate 10 may be made of, for example, glass, plastic, quartz or other suitable materials, which are not limited in the embodiments of the present disclosure.
  • the display area 11 includes a plurality of sub-display areas 13 arranged in an array, and the plurality of sub-display areas 13 include a plurality of first sub-display areas 14 and are located at least in the first direction Y.
  • the following takes the sub-pixel unit in each of the 6 columns of the sub-display area 13 arranged along the first direction Y as a repeating unit as an example.
  • each repeating unit may also include 9 columns, 12 columns, etc. With fewer columns, the embodiment of the present disclosure does not limit this.
  • one column of second sub display areas 15 is provided between every 5 columns of the plurality of first sub display areas 14.
  • the first to fifth columns are the first sub-display area 14, and the sixth column is the second sub-display area 15.
  • first sub-display area 14 and the second sub-display area 15 may also be arranged in other ways.
  • one of the first to fifth columns is set as the second sub-display area 15 to The 6 columns are arranged along the first direction Y in one cycle.
  • the embodiments of the present disclosure are not limited thereto.
  • the display substrate 1 further includes a plurality of sub-pixel units 16.
  • a plurality of sub-pixel units 16 are located in the display area 11.
  • Each of the plurality of sub-pixel units 16 includes a light-emitting element 161 and a sub-pixel driving circuit 160 for driving the light-emitting element 161 to emit light.
  • each sub-pixel driving circuit 160 may include pixel circuits with circuit structures such as 7T1C, 8T2C, 4T1C, or 3T1C in the art.
  • the embodiments of the present disclosure are introduced by taking a pixel circuit including a 3T1C circuit structure as an example. The disclosed embodiment does not limit this.
  • the light-emitting elements 161 are located in the sub-display area 13 in a one-to-one correspondence, and the rectangles arranged in the array shown in FIGS. 2A and 2C indicate the positions of the light-emitting elements 161 and the sub-display area 13.
  • the sub-pixel driving circuit 160 is represented by a white dashed rectangular frame in FIGS. 2A and 2B, arranged in multiple columns in the second direction X, and the sub-pixel driving circuit 160 is located in the first sub-display area 14 and does not occupy the first sub-display area 14. The position of the two sub-display area 15.
  • the light-emitting element 161 of the sub-pixel unit 16 is located in the sub-display area 13 (that is, the light-emitting element 161 is located in the first sub-display area 14 and the second sub-display area 15 at the same time), and the arrangement of the light-emitting elements 161 is the same as that of the sub-display area. 13 are the same, arranged in an array.
  • the sub-pixel drive circuit 160 of the sub-pixel unit 16 is only located in the first sub-display area 14.
  • the sub-pixel drive circuit 160 is compressed so that it occupies less space than the light-emitting element 161 of the sub-pixel unit 16, forming a sub-pixel drive circuit 160 and the light emitting element 161 are arranged in a staggered arrangement.
  • the plurality of sub-pixel units 16 includes a plurality of first sub-pixel units 163 and a plurality of second sub-pixel units 164.
  • the light-emitting elements 161 of the plurality of first sub-pixel units 163 are located in the plurality of first sub-display areas 14 in one-to-one correspondence
  • the light-emitting elements 161 of the plurality of second sub-pixel units 164 are located in the plurality of second sub-display regions in one-to-one correspondence.
  • the light-emitting element 161 of the first sub-pixel unit 163 is located in the first sub-display area 14, for example, the light-emitting element 161 corresponding to the light-emitting element 161 located in the first to fifth columns in FIG. 2A (counting from the leftmost side in the figure)
  • the pixel unit 16 is the first sub-pixel unit 163.
  • the sub-pixel unit 16 corresponding to the light-emitting element 161 located in the sixth column (counting from the leftmost side in the figure) in FIG. 2A is the second sub-pixel unit 164. In this way, the cycle is performed with 6 columns as a cycle, that is, the sub-pixel units 16 in 6 columns are used as a repeating unit.
  • the first sub-pixel unit 163 and the plurality of second sub-pixel units 164 are all located in the first sub-display area 14.
  • the light-emitting element 161 of the second sub-pixel unit 164 is located in the second sub-display area 15 and the sub-pixel driving circuit 1602 thereof is located in the first sub-display area 14.
  • the first to sixth columns in FIG. 2B are provided with sub-pixel driving circuits 160
  • the seventh column is provided with gate driving circuits 17, corresponding to the first to seventh columns in FIG. 2B, in FIG. 2C
  • the first to sixth rows of light-emitting elements 161 are arranged in, the number of columns in FIG. 2B is greater than the number of columns in FIG. 2C.
  • the display substrate 1 further includes a gate driving circuit 17, and the gate driving circuit 17 includes a plurality of cascaded shift register units 170.
  • the shift register unit 170 may be the shift register unit shown in FIG. 1B, of course, it may also be a shift register unit with a circuit structure with more or less transistors and capacitors in the art, as long as it can output the gate The polar scan signal is sufficient, and the embodiment of the present disclosure does not limit this.
  • the gate driving circuit 17 is at least partially located in the plurality of second sub-display regions 15, and the gate driving circuit 17 is configured to output the gate scanning signals for driving the plurality of sub-pixel units 16 to work row by row.
  • the gate driving circuit 17 is interspersed between the sub-pixel driving circuits 160 of the plurality of sub-pixel units 16, and does not occupy the space of the frame of the display substrate 1, that is, does not occupy the peripheral area of the display substrate, which is beneficial to realize the display substrate 1. Borderless design.
  • the orthographic projection of the light-emitting elements 161 of the plurality of second sub-pixel units 164 on the base substrate 10 and the orthographic projection of the gate drive circuit 17 on the base substrate 10 at least partially overlap .
  • the light-emitting element 161 is located on the side of the gate drive circuit 17 away from the base substrate 10, so that the gate drive circuit 17 drives the sub-pixels inserted into the display area 11.
  • the circuit 160 does not occupy the space of the light emitting element 161 at the same time, so as to avoid affecting the aperture ratio of the display substrate.
  • the 6 sub-pixel driving circuits 160 are compressed to leave an area for inserting the gate driving circuit 17 between each of the 6 sub-pixel driving circuits 160, so that the 6 sub-pixel driving circuits 160 and one
  • the area corresponding to the second sub-display area 15 where the gate driving circuit 17 is inserted is repeatedly arranged in the first direction Y for one period.
  • the embodiments of the present disclosure are not limited to the above arrangement.
  • the area occupied by the sub-pixel driving circuit 160 may be compressed from the two sides of the display substrate 1 to the middle (for example, 6 sub-pixel driving circuits 160 constitute a group of Compressed), in a row of sub-pixel units, when the number of regions between the sub-pixel driving circuits 160 (for example, between every 6 sub-pixel driving circuits 160) can be inserted into the first-stage shift register unit of the gate driving circuit 17
  • the remaining sub-pixel drive circuits 160 can also be uncompressed, as long as the first level shift register unit can be set in It may be located between the sub-pixel driving circuits 160 in a row.
  • the display substrate if there is a difference in the structure of the multiple sub-pixel driving circuits 160 located in a row, it will increase the difficulty in preparing the display substrate.
  • the sub-pixel driving circuit 160 of the multi-sub-pixel unit 16 is located in the first sub-display area 14, the sub-pixel driving circuit 160 is compressed, so that it occupies less space than the sub-pixel unit 16.
  • the light-emitting element 161 forms a staggered arrangement of the sub-pixel driving circuit 160 and the light-emitting element 161.
  • the part of the light-emitting element 161 of the second sub-pixel unit 164 is located on the side of the gate driving circuit 17 away from the base substrate, so that the gate
  • the driving circuit 17 is arranged to be inserted between the sub-pixel driving circuits 160 without occupying the space of the light-emitting element 161, thereby satisfying the display substrate 1 to achieve frameless display without affecting the arrangement of the light-emitting element 161, thereby improving the display substrate.
  • the opening rate is arranged to be inserted between the sub-pixel driving circuits 160 without occupying the space of the light-emitting element 161, thereby satisfying the display substrate 1 to achieve frameless display without affecting the arrangement of the light-emitting element 161, thereby improving the display substrate.
  • the light-emitting element 161 (rectangular area in FIG. 2C) of each of the plurality of sub-pixel units 16 includes a light-emitting area 162 (represented by an ellipse extending in the second direction X).
  • the orthographic projection of the light-emitting area 162 of the light-emitting element 161 of the plurality of second sub-pixel units 164 on the base substrate 10 and the orthographic projection of the gate driving circuit 17 on the base substrate 10 at least partially overlap .
  • the light-emitting area 162 of the light-emitting element 161 of the plurality of second sub-pixel units 164 is located in the second sub-display area 15, and the sub-pixel driving circuits of the plurality of second sub-pixel units 164 are located in the first sub-display area 14, and the gate drive The circuit 17 is also located in the second sub-display area 15.
  • the light-emitting regions 162 of the light-emitting elements 161 of the plurality of second sub-pixel units 164 are located on the side away from the gate driving circuit 17, thereby ensuring a high aperture ratio of the display substrate.
  • the light-emitting regions 162 of the light-emitting elements 161 of the plurality of sub-pixel units 16 arranged in a row in the first direction Y are arranged at equal intervals, so that all the light-emitting elements can be completed by one printing process.
  • the preparation of 161 improves the printing efficiency, saves the preparation process, improves the production efficiency of the display substrate 1, and saves the preparation cost.
  • the light-emitting element 161 may be, for example, an organic light-emitting diode (OLED) or a quantum dot light-emitting diode (QLED).
  • OLED organic light-emitting diode
  • QLED quantum dot light-emitting diode
  • the display substrate 1 further includes a plurality of gate lines G1-GK (K is an integer greater than 1) arranged in a first direction Y and a plurality of gate lines G1-GK arranged in a second direction X.
  • the peripheral area 12 includes a data driving chip IC.
  • the data driving chip IC is configured to provide data signals to the sub-pixel driving circuit 160.
  • the data D1-DL connected to the data driving chip IC passes through the display area 11 along the second direction X (for example, the vertical direction in the figure) to provide data signals for the sub-pixel driving circuits 160 of each column, respectively.
  • the gate lines G1-GK connected to the gate driving circuit 17 pass through the display area 11 along the first direction Y (for example, the horizontal direction in the figure) to provide the sub-pixel driving circuit 160 with gate scanning signals.
  • the sub-pixel driving circuit 160 of the sub-pixel unit 16 operates under the control of the data signal transmitted through the data line and the gate scanning signal transmitted through the gate line to drive the light-emitting element 161 to emit light to achieve display and other operations.
  • the sub-pixel driving circuit 1602 of each of the plurality of second sub-pixel units 164 (for example, located in the sixth column from the left in FIG. 2B) is at least partially In the first sub-display area 14 adjacent to the second sub-display area 15 where the light-emitting elements 161 of the two sub-pixel units 164 are located.
  • the first sub-display area 14 of the column includes the sub-pixel driving circuit 1602 of the second sub-pixel unit 164, so that when the sub-pixel driving circuit 1602 of the second sub-pixel unit 164 is connected to the light-emitting element 161 in the second sub-display area 15
  • the required traces are shorter, which reduces the wiring complexity of the display substrate.
  • the number of columns in FIGS. 2A and 2C is based on the arrangement of the light-emitting elements 161 as an example, and the number of columns in FIG. 2B is based on the arrangement of the sub-pixel drive circuit 160 and the gate drive circuit 17 as an example. . In the case of the arrangement of 6 light-emitting elements 161 in FIG.
  • the number of columns in FIG. 2B is 6 sub-pixel driving circuits 160 and every 6 sub-pixel driving circuits 1601 are provided with gate driving
  • the drive of the circuit 17 is a repeating unit.
  • 2A and 2C take the second sub-display area 15 in the sixth column as an example for description.
  • the first sub-display area 14 in the first column adjacent to the second sub-display area 15 where the light-emitting elements 161 in the second column are located includes the sub-pixel driving circuit 1602 of the second sub-pixel unit 164.
  • the orthographic projection of at least part of the light-emitting elements 161 in the plurality of first sub-display regions 14 on the base substrate 10 and the sub-pixel drive circuits of at least two first sub-pixel units 163 The orthographic projections of 1601 (for example, located in the first to fifth columns in FIG. 2B) on the base substrate 10 at least partially overlap.
  • the sub-pixel drive circuit 160 of the sub-pixel unit 16 is located in the first sub-display area 14, the sub-pixel drive circuit 160 is compressed so that it occupies less space than the light-emitting element 161 of the sub-pixel unit 16, forming a sub-pixel drive circuit 160 and the light-emitting element 161 are arranged in a staggered arrangement, the orthographic projection of the light-emitting element 161 located in the first sub-display area 14 in the first column to the fourth column on the base substrate 10 is the same as that of the two first sub-pixel units.
  • the orthographic projection of the sub-pixel driving circuit 1601 of 163 on the base substrate 10 partially overlaps.
  • a plurality of sub-pixel units 16 are arranged in N rows, and the gate driving circuit 17 includes N cascade-connected shift register units 170.
  • the sub-pixel driving circuit 160 of the pixel unit 16 is connected, and the n-th stage shift register unit 170 is located in the plurality of second sub-display regions 15 in the n-th row. 1 ⁇ n ⁇ N, N is an integer greater than or equal to 2.
  • the n-th stage shift register unit 170 is interspersedly arranged in the plurality of second sub-display areas 15 in the n-th row, that is, the plurality of second sub-display areas 15 correspond to the plurality of sub-pixel driving circuits 160. Space.
  • the shift register unit 170 of the gate driving circuit 17 can be, for example, a 9T2C circuit as shown in FIG.
  • the shift register unit 170 may also include a plurality of signal lines and power supply lines.
  • the shift register unit 170 can also be a shift register unit with a circuit structure with more or less transistors and capacitors in the art, as long as it can output a gate scan signal, and the embodiment of the present disclosure does not do this. limit.
  • the transistors, capacitors, signal lines, and power lines of the n-th stage shift register unit 170 are arranged in the plurality of second sub-display areas 15 in the n-th row to form a complete shift register unit 170, thereby realizing
  • the gate driving circuit 17 functions as a shift register unit of one stage.
  • the n-th stage shift register unit 170 is connected to the sub-pixel driving circuit 160 of the n-th row of the plurality of sub-pixel units 16 through gate lines to provide gate scan signals. Inserting the gate driving circuit 17 in the display area 11 can realize the frameless display of the display substrate 1 and provide a better display effect.
  • FIG. 3A is a schematic diagram of the layout of the display substrate shown in FIG. 2A.
  • the orthographic projection of the part of the light-emitting element 161 of the sub-pixel unit 16 (for example, five light-emitting elements 161 from the left in FIG. 3A) on the base substrate 10 and the sub-pixel drive of the sub-pixel unit 16
  • the orthographic projection of the circuit 160 on the base substrate partially overlaps.
  • the light-emitting element 161 of the sub-pixel unit 16 is located on a side of the sub-pixel driving circuit of the sub-pixel unit 16 away from the base substrate 10.
  • the sub-pixel driving circuit 160 is connected to the light-emitting element 161 to drive the light-emitting element 161 to emit light.
  • the first sub-pixel unit 163 of the sub-pixel unit 16 includes a light-emitting element 161 and a sub-pixel driving circuit 1601
  • the second sub-pixel unit 164 of the sub-pixel unit 16 includes a light-emitting element 161 and a sub-pixel driving circuit 1602.
  • the sub-pixel driving circuit 1601 of the first sub-pixel unit 163 and the sub-pixel driving circuit 1602 of the second sub-pixel unit 164 are arranged in a row in the first direction Y with unequal intervals, so that the second sub-pixel unit 164 A space is reserved on one side of the sub-pixel driving circuit 1602 for the gate driving circuit 17, and a space is reserved between the sub-pixel driving circuits 1601 of the first sub-pixel unit 163 for other power lines or signal lines.
  • five sub-pixel driving circuits 1601 of the first sub-pixel unit 163 and one sub-pixel driving circuit 1602 of the second sub-pixel unit 164 are arranged in a first direction Y as a cycle, where Three adjacent sub-pixel drive circuits 160 (in FIG. 3A, in the first direction Y, the first three sub-pixel drive circuits 1601 from the left) and three adjacent sub-pixel drive circuits 160 (in FIG. 3A, in the first direction) In one direction Y, the other two sub-pixel driving circuits 1601 and the sub-pixel driving circuit 1602 have a larger interval, which is greater than the interval between three adjacent sub-pixel driving circuits 160. It should be noted that what is shown in FIG.
  • 3A is only an example of the arrangement of the sub-pixel driving circuits 160, and the interval between the sub-pixel driving circuits 160 can be adjusted according to the needs of the circuit arrangement. As a result, the space occupied by the sub-pixel driving circuits 160 of the plurality of sub-pixel units 16 is reduced, so as to leave space for the gate driving circuit 17.
  • FIG. 3A only exemplarily shows a layout diagram of six sub-pixel units 16 arranged in one row in a row in the display substrate 1, and the structure of other parts will not be repeated.
  • the light-emitting regions 162 of the light-emitting elements 161 of the six sub-pixel units 16 are arranged at equal intervals in the first direction Y, which can improve the aperture ratio of the display substrate 1 while realizing the frameless design of the display substrate 1.
  • the sub-pixel driving circuit 160 may adopt a pixel circuit having a 3T1C circuit structure in the art.
  • the sub-pixel driving circuit 160 includes a data writing transistor T21, a driving transistor T23, a sensing transistor T22, and a storage capacitor C21.
  • the sub-pixel driving circuit 160 may also adopt pixel circuits with other circuit structures, such as 4T2C, 8T2C, etc. The embodiments of the present disclosure are not limited thereto.
  • FIG. 3B is a schematic diagram of the layout of the light-emitting elements of the sub-pixel units of the display substrate of FIG. 3A;
  • FIG. 3C is a schematic diagram of the layout of the first electrode of the light-emitting element shown in FIG. 3A.
  • the light-emitting element 161 of each of the plurality of sub-pixel units 16 includes a first electrode 1611 at least partially located in the light-emitting region 162 of the light-emitting element 161.
  • the first electrode 1611 is arranged on a side of the sub-pixel driving circuit 160 and the gate driving circuit 17 of the plurality of sub-pixel units 161 away from the base substrate 10, and the first electrode 1611 is connected to the sub-pixel driving circuit 160.
  • the first electrode 1611 is provided in a one-to-one correspondence with the area where the light-emitting element 161 is located, and the light-emitting area 162 is located in the first electrode 1611.
  • 3C shows six first electrodes 1611, which are arranged at equal intervals in the first direction Y to increase the aperture ratio of the display substrate 1 and realize the preparation of the light-emitting element 161 in one printing process.
  • the six first electrodes 1611 are used as a repeating period in the first direction Y, the shape of each of the six first electrodes 1611 away from the light-emitting area 162 is slightly different, which will be described in detail later.
  • each of the plurality of sub-pixel units 16 further includes a first via 1614.
  • the first electrode 1611 of the light-emitting element 161 includes a main body portion 1621 and a lead portion 1622 extending from the main body portion 1621 away from the light-emitting area 162.
  • a portion of the main body portion 1621 is located in the light-emitting area 162 of the light-emitting element 161, for example, the light-emitting area 162 of the light-emitting element 161 is located in the main body portion 1621.
  • the area of the main body portion 1621 is greater than or equal to the area of the light-emitting region 162.
  • the lead portion 1622 is connected to the sub-pixel driving circuit 160 through the first via 1614.
  • the lead portion 1622 extends to the position where the first via 1614 is located, so as to be connected to the sub-pixel driving circuit 160 through the first via 1614.
  • the first via hole 1614 may expose the source or drain of the sensing transistor or the driving transistor of the sub-pixel driving circuit 160.
  • the size range of the first via 1614 may be 7-9 microns.
  • the size of the first via 1614 is selected to be about 8 microns. It should be noted that "about” means that it can fluctuate within a range of, for example, ⁇ 15% or ⁇ 5% of the value it takes.
  • the size of the first via 1614 is selected by the manufacturing process of the display substrate, and the embodiment of the present disclosure is not limited thereto.
  • the five first electrodes 1611 in the first display area 14 of the six first electrodes 1611 in FIG. 3C are the light emission of the first sub-pixel unit 163.
  • the first electrode 1611 of the element 161, and the other first electrode 1611 in the second display area 15 is the first electrode 1611 of the light-emitting element 161 of the second sub-pixel unit 164.
  • the main body portion 1621 of the six first electrodes 1611 The shape and structure are the same, and they are all rectangular.
  • the first electrode 1611 of the light-emitting element 161 of the first sub-pixel unit 163 located on the second left in the first direction Y, and its lead portion 1622 is from the main body portion 1621 away from the light-emitting area 162 on the left side in FIG.
  • the lead portion 1622 extends to the area between the first electrode 1611 of the first first sub-pixel unit 163 close to the first and the first electrode 1611 of the second first sub-pixel unit 163.
  • the direction of the first electrode 1611 of the two first sub-pixel units 163 extends to the lower side of the first electrode 1611 of the second first sub-pixel unit 163 away from the light-emitting area 162 in FIG. 3C.
  • the first electrode 1611 of the light-emitting element 161 of the fourth first sub-pixel unit 163 from the left in the first direction Y, and its lead portion 1622 is located on the left side of FIG. , The length of the lead portion 1622 is relatively short.
  • the lead portion 1622 of the first electrode 1611 of the light-emitting element 161 of the second sub-pixel unit 164 extends from the second sub-display area 15 where the light-emitting element 161 of the second sub-pixel unit 164 is located.
  • the sub-pixel driving circuit 1602 (shown in FIG. 3A) of the second sub-pixel unit 164 located in the first sub-display area 14 through the first via 1614 Show) connection For example, in FIG.
  • the first electrode 1611 located on the far right in the first direction Y is the first electrode 1611 of the light-emitting element 161 of the second sub-pixel unit 164, and its lead portion 1622 is located on the left in the first direction Y.
  • the first electrode 1611 of the light-emitting element 161 of the fifth first sub-pixel unit 163 extends.
  • the respective points of the first electrode 1611 of each light-emitting element 161 in the light-emitting area 162 of each light-emitting element 161 have the same distance from the base substrate 10.
  • the light-emitting area 162 is located in the main body portion 1621 of the first electrode 1611
  • the first via 1614 is located on the side of the main body portion 1621 of the first electrode 1611 away from the light-emitting area 162 (for example, below the main body portion 1621 in FIG. 3C).
  • the first via 1614 is connected to the lead portion 1611 of the first electrode 1611, so that the respective points of the corresponding positions of each first electrode 1611 in the light-emitting area 162 are equal to the distance of the base substrate 10 in the second direction X .
  • the main body portion 1621 of each first electrode 1611 located in the light-emitting area 162 has the same height relative to the base substrate 10 and can be regarded as being located on the same plane.
  • six points corresponding to the first electrode 1611 are taken, such as point XY1, point XY2, point XY3, point XY4, point XY5, and point XY6, namely, point XY1-point XY6.
  • the position pairs in the first electrode 1611 where they are located correspond to each other.
  • the point XY1, the point XY2, the point XY3, the point XY4, the point XY5, and the point XY6 are the same distance from the base substrate 10 in the second direction X. It should be noted that the corresponding position of each first electrode 1611 is not limited to the point XY1-point XY6 shown in FIG. 3C, and the corresponding position of each first electrode 1611 may be any point.
  • the six first vias 1614 are located on the same horizontal line in the first direction Y to reduce the complexity of the circuit arrangement of the display substrate.
  • FIG. 6 is a layout diagram of a sub-pixel driving circuit of a sub-pixel unit provided by at least one embodiment of the present disclosure.
  • the plurality of sub-pixel units 16 further includes a first power line ELVSS.
  • the first power line ELVSS extends along the second direction X and is provided in the sub-pixel driving circuit of the plurality of first sub-pixel units 163.
  • the orthographic projection of the first power line ELVSS on the base substrate 10 and the orthographic projection of the first electrodes 1611 of the light-emitting elements 161 of the plurality of sub-pixel units 16 on the base substrate 10 at least partially overlap. For example, in FIG.
  • the light-emitting element 161 of each of the plurality of sub-pixel units 16 further includes a second electrode 1612 (shown in FIG. 4) disposed on the side of the first electrode 1611 away from the base substrate.
  • the included angle between the first direction Y and the second direction X involved in the present disclosure is between 70° and 90°, and includes 70° and 90°.
  • the included angle between the first direction Y and the second direction X is 70°, 90°, 80°, etc., which can be set according to actual conditions, and the embodiment of the present disclosure does not limit this.
  • the included angle between the first direction Y and the second direction X may also be 75°, 85°, and so on.
  • the second electrode 1612 of the light-emitting element 161 of the at least one first sub-pixel unit 163 is connected to the first power line ELVSS through the second via 1615.
  • the first power line ELVSS provides a light emitting control signal to the light emitting element 161.
  • the second electrode 1612 of the light-emitting element 161 of the first sub-pixel unit 163 located third from the left in the first direction Y in FIG. 3B is connected to the first power line ELVSS through the second via 1615.
  • the size range of the second via 1615 may be 9-12 microns.
  • the size of the second via 1615 is selected to be about 10 or 11 microns. It should be noted that "about” means that it can fluctuate within a range of, for example, ⁇ 15% or ⁇ 5% of the value it takes.
  • the size of the second via 1615 is selected by the manufacturing process of the display substrate, and the size of the second via 1615 needs to be no larger than the width of the first power line ELVSS.
  • the embodiments of the present disclosure are not limited thereto.
  • the lead portion 1622 of the first electrode 1611 of the light-emitting element 161 of at least one first sub-pixel unit 163 surrounds the second via 1615 and passes through the second via 1615.
  • the lead portion 1622 of the first electrode 1611 of the light-emitting element 161 of the first sub-pixel unit 163 located third from the left in the first direction Y in FIG. (Except for the side of the second via 1615 facing the main body portion 1621).
  • the lead portions 1622 respectively include two sections of leads along the second direction X located on both sides of the second via 1615 (the left and right sides in FIG. 3C), and the edge located on the side of the second via 1615 away from the light-emitting area 162.
  • the light emitting elements 161 can be arranged at equal intervals to increase the aperture ratio of the display substrate.
  • the second via 1615 and the first sub-pixel unit 163 corresponding to the second via 1615 (the third first sub-pixel unit 163 from the left in the first direction Y in FIG. 3B)
  • the distance d2 of the light-emitting area 162 of the light-emitting element 161 along the second direction X is greater than the first via 1614 and the first sub-pixel unit 163 (the third first sub-pixel unit 163 from the left in the first direction Y in FIG. 3B ) Is the distance d1 of the light-emitting area 162 of the light-emitting element 161 along the second direction X.
  • the distance d2 is the distance from the midline of the second via 1615 to the midline of the light-emitting area 162 along the second direction X
  • the distance d1 is the distance from the midline of the first via 1614 to the midline of the light-emitting area 162 along the second direction X the distance.
  • the width of the lead portion 1622 is appropriate.
  • the width of the lead portion 1622 is not less than 4 microns, for example, 4 mm.
  • the display substrate 1 includes a light-shielding layer 102 disposed on a base substrate 10 to block external light irradiation, and a blocking layer 101 disposed on the side of the light-shielding layer 102 away from the base substrate 10 and on the base substrate.
  • the barrier layer 101 can provide a flat surface for forming the gate driving circuit, and can prevent the impurities that may exist in the base substrate 10 from diffusing into the sub-pixel driving circuit or the gate driving circuit to adversely affect the performance of the display substrate.
  • the material of the light shielding layer 102 may be made of metallic materials or non-metallic materials.
  • metallic materials include silver, aluminum, chromium, copper, molybdenum, titanium, aluminum-neodymium alloy, copper-molybdenum alloy, molybdenum-tantalum alloy, and molybdenum-neodymium alloy. Or any combination of them.
  • the material of the barrier layer 101 may include inorganic insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride, or other suitable materials.
  • the display substrate 1 further includes an active layer 103, a gate insulating layer 106, a gate 104, an interlayer insulating layer 107, and a source-drain layer 1053 (for example, including a source electrode 1051 and a drain electrode 1052).
  • the active layer 103 is located on the side of the barrier layer 101 away from the base substrate 10
  • the gate insulating layer 106 is located on the side of the active layer 103 away from the base substrate 10
  • the gate 104 is located on the side of the gate insulating layer 106 away from the base substrate 10.
  • the interlayer insulating layer 107 is located on the side of the gate 104, the active layer 103, and the barrier layer 101 away from the base substrate 10, and the interlayer insulating layer 107 includes two via holes to respectively leak out the source regions 1031 and 1031 of the active layer. Drain region 1032.
  • the source electrode 1051 and the drain electrode 1052 are located in the source-drain electrode layer 1053 and are respectively connected to the source region 1031 and the drain region 1032 of the active layer through the via holes of the interlayer insulating layer 107.
  • the active layer 103, the gate 104, the source 1051 and the drain 1052 together form a transistor, which may be the sensing transistor T22 of the sub-pixel driving circuit 160 in FIG. 3A.
  • the light-shielding layer 102 when the light-shielding layer 102 is disposed under the thin film transistors of the sub-pixels (that is, the orthographic projection of the light-shielding layer 102 on the base substrate 10 overlaps with the orthographic projection of the active layer 103 on the base substrate 1), the light-shielding layer 102 It can also prevent the transistor from being irradiated by external light to generate photo-generated carriers and cause leakage current.
  • cross-sectional structure of other transistors of the sub-pixel driving circuit 160 such as the data writing transistor T21 and the driving transistor T23, and the cross-sectional structure of the sensing transistor T22 may be the same, and will not be repeated here.
  • the material of the active layer 103 may include oxide semiconductor, organic semiconductor or amorphous silicon, polysilicon, etc.
  • the oxide semiconductor includes a metal oxide semiconductor (for example, indium gallium zinc oxide (IGZO)), and the polysilicon includes low-temperature polysilicon or High-temperature polysilicon, etc., which are not limited in the embodiments of the present disclosure.
  • IGZO indium gallium zinc oxide
  • the above-mentioned source region 1031 and drain region 1032 may be regions doped with n-type impurities or p-type impurities, which is not limited in the embodiments of the present disclosure.
  • one or more materials of the gate insulating layer 106 and the interlayer insulating layer 107 may include inorganic insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride, or other suitable materials.
  • the material of the gate 104 may include a metal material or an alloy material, such as a metal single-layer or multi-layer structure formed by molybdenum, aluminum, and titanium.
  • the multi-layer structure is a multi-metal laminated layer (such as titanium, aluminum and titanium) Three-layer metal stack (Ti/Al/Ti)).
  • the material of the source electrode 1051 and the drain electrode 1052 (or the source/drain electrode layer 1053) may include a metal material or an alloy material, such as a metal single-layer or multi-layer structure formed of molybdenum, aluminum, and titanium.
  • the multi-layer structure is Multi-metal laminates (such as titanium, aluminum and titanium three-layer metal laminates (Ti/Al/Ti)).
  • the embodiments of the present disclosure do not specifically limit the material of each functional layer.
  • the display substrate 1 further includes a passivation layer 108, a planarization layer 109, a pixel defining layer 1011, a light emitting element 161, and an encapsulation layer 1012.
  • the passivation layer 108 is located on the side of the source and drain electrode layer 1053 away from the base substrate 10, and the passivation layer 108 can protect the source electrode 1051 and the drain electrode 1052 of the sub-pixel driving circuit from being corroded by water vapor.
  • the planarization layer 109 is located on the side of the passivation layer 108 away from the base substrate 10 to provide a planarized surface.
  • a first via 1614 is formed in the planarization layer 109 and the passivation layer 108, and the first via 1614 exposes the source and drain electrode layer 1053.
  • the light emitting element 161 is connected to the source and drain electrode layer 1053 through the first via hole 1614.
  • the material of the passivation layer 108 may include an organic insulating material or an inorganic insulating material, for example, silicon nitride material. Due to its high dielectric constant and good hydrophobic function, it can well protect the sub-pixel drive. The circuit is not corroded by water vapor.
  • the material of the planarization layer 109 may include inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, etc., and may also include polyimide, polyphthalimide, polyphthalamide, acrylic resin, and benzocyclobutene. Or organic insulating materials such as phenolic resin, which are not limited in the embodiments of the present disclosure.
  • the light-emitting element 161 is disposed on the side of the planarization layer 109 away from the base substrate 10.
  • the light-emitting element 161 includes a first electrode 1611, a second electrode 1612, and an electrode located between the first electrode 1611 and the second electrode. Luminescent layer.
  • the first electrode 1611 of the light-emitting element 161 is connected to the source and drain electrode layer 1053 through the planarization layer 109 and the first via hole 1614 in the passivation layer 108, that is, is connected to the sub-pixel driving circuit 160.
  • a pixel defining layer 1011 is formed on a side of the first electrode 1611 away from the base substrate 10, and the pixel defining layer 1011 includes a plurality of openings to define a plurality of pixel units.
  • the opening corresponds to the light-emitting area 162.
  • Each of the plurality of openings exposes the first electrode 1611, and the light-emitting layer 1613 is disposed in the plurality of openings (ie, the light-emitting region 162) of the pixel defining layer 1011.
  • the second electrode 1612 may be disposed in a part or the entire display area 11, for example, so that it may be formed on the entire surface during the manufacturing process.
  • the first electrode 1611 may include a reflective layer
  • the second electrode 1612 may include a transparent layer or a semi-transparent layer.
  • the first electrode 1611 can reflect the light emitted from the light-emitting layer 1613, and this part of the light is emitted into the external environment through the second electrode 1612, so that the light emission rate can be improved.
  • the second electrode 1612 includes a semi-transmissive layer, some of the light reflected by the first electrode 1611 is reflected again by the second electrode 1612, so the first electrode 1611 and the second electrode 1612 form a resonance structure, so that light emission efficiency can be improved.
  • the material of the first electrode 1611 may include at least one transparent conductive oxide material, including indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and the like.
  • the first electrode 261 may include a metal having high reflectivity as a reflective layer, such as silver (Ag).
  • the light-emitting layer 1613 may include small molecular organic materials or polymer molecular organic materials, which may be fluorescent light-emitting materials or phosphorescent light-emitting materials, which can emit red light, green light, blue light, or white light; and, as required
  • the light-emitting layer may further include functional layers such as an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer.
  • the light-emitting layer may include quantum dot materials, for example, silicon quantum dots, germanium quantum dots, cadmium sulfide quantum dots, cadmium selenide quantum dots, cadmium telluride quantum dots, zinc selenide quantum dots, lead sulfide quantum dots, selenium Lead quantum dots, indium phosphide quantum dots and indium arsenide quantum dots, etc.
  • the particle size of the quantum dots is 2-20nm.
  • the second electrode 1612 may include various conductive materials.
  • the second electrode 1612 may include metal materials such as lithium (Li), aluminum (Al), magnesium (Mg), and silver (Ag).
  • the material of the pixel defining layer 1011 may include organic insulating materials such as polyimide, polyphthalimide, polyphthalamide, acrylic resin, benzocyclobutene, or phenolic resin, or inorganic materials such as silicon oxide and silicon nitride.
  • organic insulating materials such as polyimide, polyphthalimide, polyphthalamide, acrylic resin, benzocyclobutene, or phenolic resin, or inorganic materials such as silicon oxide and silicon nitride.
  • the insulating material is not limited in the embodiment of the present disclosure.
  • the encapsulation layer 1012 is provided on the side of the light-emitting element 161 away from the base substrate 10.
  • the encapsulation layer 1012 seals the light emitting element 161, so that the deterioration of the light emitting element 161 caused by moisture and/or oxygen included in the environment can be reduced or prevented.
  • the encapsulation layer 1012 may be a single-layer structure or a composite layer structure, and the composite layer structure includes a stacked structure of an inorganic layer and an organic layer.
  • the encapsulation layer 1012 includes at least one encapsulation sublayer.
  • the encapsulation layer 1012 may include a first inorganic encapsulation layer, a first organic encapsulation layer, and a second inorganic encapsulation layer that are sequentially arranged.
  • the material of the encapsulation layer 1012 may include insulating materials such as silicon nitride, silicon oxide, silicon oxynitride, and polymer resin.
  • Inorganic materials such as silicon nitride, silicon oxide, and silicon oxynitride have high density and can prevent the intrusion of water and oxygen;
  • the material of the organic encapsulation layer can be a polymer material containing a desiccant or a polymer material that can block water vapor, etc.
  • polymer resins are used to flatten the surface of the display substrate, and can relieve the stress of the first inorganic encapsulation layer and the second inorganic encapsulation layer, and can also include water-absorbing materials such as desiccant to absorb water intruding into the interior, Oxygen and other substances.
  • FIG. 5A is a circuit diagram of a sub-pixel driving circuit of a sub-pixel unit provided by at least one embodiment of the present disclosure.
  • the sub-pixel driving circuit 160 of each of the plurality of sub-pixel units 16 includes a data writing circuit 1603, a driving circuit 1604, a charge storage circuit 1606, and a sensing circuit 1605.
  • the driving circuit 1604 is connected to the first node G and the second node S, and is configured to control the driving current flowing through the light-emitting element OLED (for example, the light-emitting element 161) under the control of the level of the first node G.
  • the data writing circuit 1603 is connected to the first node G and is configured to receive a gate scan signal (for example, provided by the gate driving circuit) as a scan driving signal, and write the data signal to the first node G in response to the scan driving signal .
  • the charge storage circuit 1606 is connected to the first node G and the second node S, and is configured to store the written data signal and the reference voltage signal.
  • the sensing circuit 1605 is connected to the second node S and is configured to connect the gate scan signal as a sensing driving signal, and in response to the sensing driving signal, write a reference voltage signal to the driving circuit 1604 or read the sensing voltage from the driving circuit 1604 Signal.
  • the light emitting element OLED and the second node S are connected to the first power supply line ELVSS, and are configured to emit light under the driving of a driving current.
  • the data writing circuit 1603 is implemented as a data writing transistor T21
  • the drive circuit 1604 is implemented as a drive transistor T23
  • the charge storage circuit 1606 is implemented as a storage capacitor C21
  • the sensing circuit 1605 is implemented as a sensing transistor. T22. That is, the multiple gate lines G1-GK in FIG. 2A and FIG. 2B include the first gate line G1 and the second gate line G2.
  • the sub-pixel unit 16 further includes a plurality of second power supply lines ELVDD and sensing signal lines SENSE.
  • the first pole of the data writing transistor T21 is connected to one of the multiple data lines DATA (ie, the multiple data lines D1-DL in FIG. 2A and FIG. 2B) so as to receive a data signal, and the second pole of the data writing transistor T21 It is connected to the first node G (that is, connected to the gate of the driving transistor T23).
  • the gate G211 of the data writing transistor T21 is connected to the first gate line G1 (that is, the gate line connected to the output terminal of the shift register unit) among the plurality of gate lines so as to receive the scan driving signal.
  • the first electrode of the driving transistor T23 is connected to a second power supply line ELVDD and is configured to receive the first driving voltage.
  • the second electrode of the driving transistor T23 is connected to the second node S (that is, connected to the first electrode of the sensing transistor T2). connect).
  • the gate G221 of the sensing transistor T22 is configured to receive a sensing driving signal, for example, the gate G221 of the sensing transistor T22 and the second gate line G2 of the plurality of gate lines (that is, the gate line G2 located in a different row from the sensing transistor T22)
  • the output terminal of the shift register unit is connected to the gate line) so as to receive the sensing driving signal.
  • the first pole of the sensing transistor T2 is connected to the second node S, and the second pole of the sensing transistor T2 is connected to a sensing signal line SENSE, and is configured to receive a reference voltage signal or output a sensing voltage signal.
  • the first electrode of the OLED is connected to the second node S, that is, connected to the first electrode of the driving transistor T23 and the first electrode of the sensing transistor T22, so as to receive the driving current of the driving transistor T23; the second electrode of the OLED is configured as It is connected to the first power line ELVSS to receive the second driving voltage.
  • the second electrode of the OLED is configured to be grounded, and the second driving voltage is 0V at this time.
  • the first driving voltage is a high-level voltage (for example, 5V, 10V or other suitable voltage)
  • the second driving voltage is a low-level voltage (for example, 0V, -5V, -10V or other suitable voltage).
  • the above-mentioned transistors are all described with N-type transistors as an example, that is, each transistor is turned on when the gate is connected to a high level (conduction level), and is turned off when the gate is connected to a low level (cut-off level).
  • the first electrode may be the drain
  • the second electrode may be the source.
  • the present disclosure includes but is not limited to this.
  • one or more transistors in the shift register unit provided by the embodiments of the present disclosure can also be P-type transistors.
  • the first electrode can be the source and the second electrode can be the drain.
  • the polarity of each pole of a certain type of transistor can be connected according to the polarity of each pole of the corresponding transistor in the embodiment of the present disclosure.
  • a plurality of data lines DATA extend along the second direction X, and the plurality of data lines DATA are connected in a one-to-one correspondence with the sub-pixel driving circuits 160 of each column of sub-pixel units 16 in the plurality of sub-pixel units 16.
  • the orthographic projection of the data line DATA on the base substrate 10 and the orthographic projection of the first electrodes 1611 (shown in FIG. 3C) of the light-emitting elements 161 of the plurality of sub-pixel units 16 on the base substrate 10 at least partially overlap.
  • FIG. 5B is a schematic diagram of the connection between the sub-pixel driving circuit of the sub-pixel unit and the register unit provided by at least one embodiment of the present disclosure.
  • the first gate line G1 and the data writing circuit 1603 of the sub-pixel driving circuit 160 of the sub-pixel unit 16 in the M-th row, and the sensing of the sub-pixel driving circuit 160 of the sub-pixel unit 16 in the M-1th row are The circuit 1605 is connected to the output end of the shift register unit 170 in the Mth row to output the gate scan signal output from the output end of the shift register unit 170 in the Mth row to the sub-pixel driving circuit 160 of the sub-pixel unit 16 in the Mth row.
  • the data writing circuit 1603 is used as a scanning drive signal, and the sensing circuit 1605 output to the sub-pixel drive circuit 160 of the sub-pixel unit 16 in the M-1th row is used as a sensing drive signal.
  • the second gate line G2 is connected to the sensing circuit 1605 of the sub-pixel driving circuit 160 of the M-th row of sub-pixel units 16, the data writing circuit 1603 of the sub-pixel driving circuit 160 of the M+1-th row of sub-pixel units 16, and the M+th row.
  • the output terminal of the shift register unit 170 is connected to output the gate scan signal output from the output terminal of the shift register unit 170 in the M+1 th row to the sub-pixel driving circuit 160 of the sub-pixel unit 16 in the M+1 th row.
  • the data writing circuit 1603 serves as a scan driving signal
  • the sensing circuit 1605 output to the sub-pixel driving circuit 160 of the M-th row of sub-pixel units 16 serves as a sensing driving signal.
  • 1 ⁇ M ⁇ N, M is an odd number greater than 1.
  • FIG. 7A is a plan view of the semiconductor layer 1030 of the sub-pixel unit provided by at least one embodiment of the present disclosure
  • FIG. 7B is a plan view of the first conductive layer 1040 of the sub-pixel unit provided by at least one embodiment of the present disclosure
  • An embodiment provides a plan view of the first conductive layer 1050 of the sub-pixel unit. That is, after superimposing FIGS. 7A, 7B, and 7C, FIG. 6 can be obtained.
  • the structure of the sub-pixel unit driving circuit 160 of the sub-pixel unit is described below in conjunction with FIGS. 4, 6, 7A, 7B, and 7C. Detailed introduction. It should be noted that the structure of one sub-pixel unit driving circuit 160 in FIG. 6, FIG. 7A, FIG. 7B, and FIG. No longer.
  • the active layer A21 of the data writing transistor T21 extends along the first direction Y and is located between the first gate line G1 and the second gate line G2, and the active layer A23 of the driving transistor T23 And the active layer A22 of the sensing transistor T22 extends along the second direction X and is located on the side of the data writing transistor T21 close to the second gate line G2.
  • the active layer A23 of the driving transistor T23 and the active layer A22 of the sensing transistor T22 are arranged side by side.
  • the storage capacitor C21 is located in the area surrounded by the active layer A21 of the data writing transistor T21, the active layer A23 of the driving transistor T23, and the active layer A22 of the sensing transistor T22, and the data line DATA connected to the data writing circuit 1603
  • the orthographic projection on the base substrate 10 is located on the side of the active layer A22 of the sensing transistor T22 away from the driving transistor T23.
  • the active layer A21 of the data writing transistor T21, the active layer A23 of the driving transistor T23, and the active layer A22 of the sensing transistor T22 are located in the semiconductor layer 1030. For example, in FIG.
  • each sub-pixel driving circuit 160 is connected to a data line DATA, and the data line DATA is located on the side of the active layer A22 of the sensing transistor T22 away from the driving transistor T23.
  • the transistors and capacitors of the sub-pixel unit 160 are mainly located in the area defined by the plurality of data lines DATA, the first gate line G1, the second gate line G2, the first power line ELVSS, and the second power line ELVDD.
  • the above arrangement of the sub-pixel units 160 can reduce the number of connecting wires or switching electrodes, and reduce the space occupied by the sub-pixel units 160.
  • the active layer A21 of the data writing transistor T21 may not be parallel to the first direction Y.
  • the active layer A21 of the data writing transistor T21 intersects the second direction Y at a certain angle.
  • the crossing angle is less than or equal to 20°.
  • the active layer A23 of the driving transistor T23 and the active layer A22 of the sensing transistor T22 may not be parallel to the second direction X, for example, the active layer A23 of the driving transistor T23 and the active layer A22 of the sensing transistor T22 and the second direction X intersects at a certain angle.
  • the crossing angle is less than or equal to 20°.
  • the active layer A21 of the data writing transistor T21 includes a source region S1, a drain region D1, and a channel region P1.
  • the data writing transistor T21 further includes a gate G21, the gate G21 is located in the first conductive layer 1040, and the gate G21 is connected to the first gate line G1 and is integrally formed.
  • the orthographic projection of the channel region P1 on the base substrate partially overlaps the orthographic projection of the gate G21 on the base substrate.
  • the material of the semiconductor layer 1030 may include oxide semiconductor, organic semiconductor or amorphous silicon, polysilicon, etc.
  • the oxide semiconductor includes a metal oxide semiconductor (such as indium gallium zinc oxide (IGZO)), and the polysilicon includes low-temperature polysilicon or high-temperature polysilicon.
  • IGZO indium gallium zinc oxide
  • Polysilicon and the like are not limited in the embodiments of the present disclosure.
  • the aforementioned source region and drain region may be regions doped with n-type impurities or p-type impurities, which is not limited in the embodiments of the present disclosure.
  • the semiconductor layer 1030 is disposed on the side of the barrier layer 101 away from the base substrate 10.
  • the first conductive layer 1040 is disposed on the side of the gate insulating layer 106 away from the base substrate 10 to be insulated from the first conductive layer 1040.
  • the first conductive layer 1030 may include the first electrode CE1 of the storage capacitor C21, the gate G23 of the driving transistor T23, and the gate G22 of the sensing transistor T22, and are connected to various wires (for example, the first connection wires L1 and The second connection trace L2).
  • the first electrode CE1 is substantially in the shape of a “concave” shape along the second direction X, and the opening is located on the long side of the first electrode CE11 that is close to the driving transistor T23 along the second direction X.
  • the material of the first conductive layer 1040 may include a metal material or an alloy material, such as a metal single-layer or multi-layer structure formed by molybdenum, aluminum, titanium, etc.
  • the multi-layer structure is a multi-metal laminated layer (such as titanium, aluminum And titanium three-layer metal stack (Ti/Al/Ti)).
  • the first electrode CE1 of the storage capacitor C21 includes a first convex portion CE11 and a second convex portion CE12, the first convex portion CE11 faces the data writing transistor T21, and the second convex portion CE12 faces
  • the driving transistor T23 extends along the second direction Y, and the first protrusion CE12 is connected to the second electrode SD12 of the data writing transistor T21 not in the same layer through a via hole.
  • the second electrode SD12 of the data writing transistor T21 is located on the second conductive layer 1050.
  • the second conductive layer 1050 is located on the side of the interlayer insulating layer 107 away from the base substrate 10 to be insulated from the first conductive layer 1040.
  • the first convex portion CE12 is connected to the second electrode SD12 of the data writing transistor T21 not in the same layer through a via hole passing through the interlayer insulating layer 107.
  • the second protrusion CE12 serves as the gate G23 of the driving transistor T23, that is, the gate G23 of the driving transistor T23 and the first electrode CE1 of the storage capacitor C21 are integrally formed to save space and reduce wiring. set up.
  • the gate G22 of the sensing transistor T22 is connected to the second gate line G2 and is integrally formed to save space and reduce wiring arrangement.
  • the orthographic projection of the first electrode SD21 and the second electrode SD22 of the sensing transistor T22 on the base substrate is located along the second direction Y of the orthographic projection of the second gate line G2 on the base substrate.
  • the orthographic projection of the active layer A22 of the sensing transistor T22 on the base substrate partially overlaps the orthographic projection of the second gate line G2 on the base substrate, that is, the sensing transistor T22 and the The second gate line G2 crosses.
  • the first electrode SD11 of the data writing transistor T21 is connected to the data line DATA and formed integrally.
  • the first electrode SD31 and the second electrode SD32 of the driving transistor T23 are located on the side of the second gate line G2 close to the storage capacitor C21.
  • the first electrode SD21 of the sensing transistor T22 and the first electrode SD31 of the driving transistor T23 are connected to the second electrode CE2 of the storage capacitor C21 and are located in a continuous first source-drain electrode layer and formed integrally. As a result, space is saved and wiring settings are reduced.
  • the second electrode SD12 of the writing transistor T21 is connected to the source region S1 of the active layer A21 through a via hole penetrating the interlayer insulating layer 107.
  • the second pole CE2 of the storage capacitor C21 is approximately in an inverted "L" shape.
  • the second pole CE2 of the storage capacitor C21 partially overlaps the first pole CE1 of the storage capacitor C21.
  • An interlayer insulating layer 107 is provided between the second pole CE2 of the storage capacitor C21 and the first pole CE1 of the storage capacitor C21.
  • the first via hole 1614 exposes the first electrode SD21 of the sensing transistor T22 of the sub-pixel driving circuit 160, and the lead portion 1622 (shown in FIG. 3C) of the first electrode 1611 passes through the first electrode SD21 of the sensing transistor T22 of the sub-pixel driving circuit 160.
  • the via 1611 is connected to the first electrode SD21 of the sensing transistor T22.
  • the material of the second conductive layer 1050 may include a metal material or an alloy material, such as a metal single-layer or multi-layer structure formed by molybdenum, aluminum, titanium, etc.
  • the multi-layer structure is a multi-metal laminated layer (such as titanium, aluminum And titanium three-layer metal stack (Ti/Al/Ti)).
  • the second power supply line ELVDD is located in the first sub-display area 14 (shown in FIG. 2C) and the first sub-pixel driving circuit 1602 (shown in FIG. 2B) of the second sub-pixel unit 164. Between display areas 13 (shown in Figure 2C).
  • the sensing signal line SENSE is arranged adjacent to the first power line ELVSS, and is located between the first power line ELVSS and the driving transistor T23.
  • the display substrate further includes a first transfer electrode E1 (located in the second conductive layer 1050) extending along the second direction X and a first connection trace L1 extending along the first direction Y (Located in the first conductive layer 1040).
  • the second electrode SD23 of the driving transistor T23 is connected to the first terminal of the first switching electrode E1, and the second terminal E12 of the first switching electrode E1 is connected to the first connection line L1 not in the same layer.
  • the second end E12 of the first transfer electrode E1 is connected to the first connection trace L1 through a via hole passing through the interlayer insulating layer 107.
  • the position of the first terminal of the first transfer electrode E1 can be regarded as the same as the position of the second electrode SD23 of the driving transistor T23, for example, it is integrally formed, which is not labeled in the figure.
  • the first connection trace L1 is connected to the first power line ELVSS (located in the second conductive layer 1050) that is not in the same layer through a via GH1 (shown in FIG. 6).
  • the via hole GH1 penetrates the interlayer insulating layer 107.
  • the first transfer electrode E1 and the second gate line G2 overlap in a direction perpendicular to the base substrate. As a result, the complexity of wiring is reduced, and wiring space is saved.
  • the first transfer electrode E1 may not be parallel to the second direction X, for example, the first transfer electrode E1 intersects the second direction X at a certain angle.
  • the crossing angle is less than or equal to 20°.
  • the first connection trace L1 may not be parallel to the first direction Y, for example, the first connection trace L1 intersects the first direction Y at a certain angle.
  • the crossing angle is less than or equal to 20°.
  • the display substrate further includes a second transfer electrode E2 (located in the second conductive layer 1050) extending along the second direction X and a second connection trace L2 extending along the first direction Y (Located in the first conductive layer 1040).
  • the second electrode SD22 of the sensing transistor T22 is connected to the first end of the second switching electrode E2.
  • the position of the first end of the second transfer electrode E2 can be regarded as the same as the position of the second electrode SD22 of the sensing transistor T22, for example, it is integrally formed, which is not labeled in the figure.
  • the second end E22 of the second transfer electrode E2 is connected to the second connection trace L2 not in the same layer through a via GH2 (shown in FIG. 6).
  • the via hole GH2 penetrates the interlayer insulating layer 107.
  • the second connection trace L2 is connected to the sensing signal line SENSE (located on the second conductive layer 1050) that is not in the same layer.
  • the second transfer electrode E2 overlaps the first connection trace L1 in a direction perpendicular to the base substrate. As a result, the complexity of wiring is reduced, and wiring space is saved.
  • the second transfer electrode E2 may not be parallel to the second direction X, for example, the second transfer electrode E2 intersects the second direction X at a certain angle.
  • the crossing angle is less than or equal to 20°.
  • the second connection trace L2 may not be parallel to the first direction Y, for example, the second connection trace L2 intersects the first direction Y at a certain angle.
  • the crossing angle is less than or equal to 20°.
  • each of the plurality of shift register units 170 includes nine transistors (first transistor-ninth transistor) and two capacitors (first capacitor and second capacitor).
  • Each of the plurality of shift register units 170 is arranged in the second sub-display area 15 located in one row (as shown in FIG. 2B).
  • 8A is a layout diagram of a part of the structure of the shift register unit 170 provided by at least one embodiment of the present disclosure
  • FIG. 8B is a layout diagram of another part of the structure of the shift register unit 170 provided by at least one embodiment of the present disclosure
  • FIG. 8C This is a layout diagram of another part of the structure of the shift register unit 170 provided in at least one embodiment of the present disclosure.
  • a layout diagram of a part of the structure of the shift register unit 170 will be introduced in conjunction with FIG. 8A, FIG. 8B, and FIG. 8C.
  • the first capacitor C1 of the shift register unit 170 is arranged in an area on one side of the six sub-pixel driving circuits 160 (for example, on the right side of the first direction Y in FIG. 8A) (ie, in FIG. 2C)
  • a second sub-display area 15) of the first capacitor C1 the first pole of the first capacitor C1 is connected to the pull-up node PU, and the second pole of the first capacitor C1 is connected to the first gate line G1 to output the gate scan signal to the
  • the first capacitor C1 is located in the sub-pixel driving circuit 160 in the same row.
  • the pull-up node PU may be a signal line extending along the first direction Y, and may be connected to multiple transistors of the shift register unit 170 in a row.
  • the pull-up node PU may also be connected to the second electrode of the first transistor T1 and the gate of the fifth transistor T5 located in the other second sub-display area 15.
  • the pull-up node PU connected to the second pole of the first transistor T1 and the first pole of the second transistor T2 is provided on one side of the six sub-pixel driving circuits 160 (for example, the left side along the first direction Y in FIG. 8B, That is, in the area close to the sub-pixel driving circuit 1602 in the figure (ie, a second sub-display area 15 in FIG.
  • the second voltage terminal VDD connected to the first pole of the first transistor T1 for example, keeping the input DC high Level signal
  • the first voltage terminal VGL connected to the second pole of the second transistor T2 for example, input of a DC low-level signal
  • the power supply line GSTV are arranged in the area on the other side of the six sub-pixel driving circuits 160 (i.e., Another second sub-display area 15 in FIG. 2C).
  • the input terminal of the first stage shift register unit 170 of the gate driving circuit 17 is connected to the trigger signal line GSTV
  • the input terminal of the shift register unit 104 is connected to the output terminal of the previous stage shift register unit.
  • the second voltage terminal VDD of the shift register unit 170 of the gate drive circuit 17 located in other rows are connected to a power supply extending in the second direction X.
  • Line to provide a high-level signal to the multi-stage shift register unit 170 For example, the first voltage terminal VGL of the shift register unit in FIG. 8B and the high first voltage terminal VGL of the shift register unit 170 of the gate drive circuit 17 located in other rows are connected to another line extending in the second direction X.
  • the third transistor T3 of the shift register unit 170 is provided in the area between the two sub-pixel driving circuits 160 (for example, between the sub-pixel driving circuit 1601 and the sub-pixel driving circuit 1602) (that is, the one in FIG. 2C).
  • the gate of the third transistor T3 is connected to the pull-up node PU, the first electrode of the third transistor T3 is connected to the first clock signal terminal CLK, and the second electrode of the third transistor T3 is connected to the first gate line G1 to connect the gate
  • the polar scanning signal is output to the sub-pixel driving circuit 160 located in the same row as the first capacitor C1.
  • the layout of other transistors or capacitors of the shift register unit 170 on the display substrate can be designed with reference to the layout diagrams shown in FIG. 8A, FIG. 8B, and FIG. 8C.
  • the layout of the first capacitor C1, the first transistor T1, the second transistor T2, the second transistor T3, etc. of the shift register unit 170 is just an example in FIGS. 8A, 8B, and 8C, and it can also be used Layout in other ways, as long as all the transistors and capacitors of the first-stage shift register unit 170 of the gate drive circuit are interspersed in the second sub-display area (area between the sub-pixel drive circuits 160) in a row.
  • the embodiments of the present disclosure do not limit the layout structure of the gate driving circuit.
  • the distance between the orthographic projections on the base substrate 10 is generally 1.5 microns, for example, the gate of the transistor in the first conductive layer 1040 exceeds its corresponding active on the semiconductor layer 1030 (shown in FIG. 7A).
  • the layer e.g., the channel region
  • the orthographic projection of the first gate G21 of the first transistor T21 on the base substrate 10 extends beyond the groove of the active layer A21 of the first transistor T21 in the first direction X.
  • the track area P1 is on both sides of the orthographic projection on the base substrate 10, for example, 2 microns or more, which is not limited in the embodiment of the present disclosure.
  • the source or drain of the transistor of the sub-pixel driving circuit is connected to the via hole of the active layer, as well as the transfer electrode and the connection trace via (for example, connecting the first transfer electrode and the first transfer electrode).
  • the size of the via GH1) connecting the traces is 3.0-3.5 microns
  • the width of each trace of the second conductive layer 1050 (shown in FIG. 7C) that covers the via is 4-5 microns.
  • the width of each trace of the first conductive layer 1040 (shown in FIG. 7B) is 4 to 5 microns.
  • the source or drain corresponding to the via hole of the data writing transistor T21 and the driving transistor T23 is 1 micrometer above and below the via hole, for example, 4.0-4.5 micrometers.
  • the thickness of the first conductive layer 1040 is 2000-300 angstroms and the thickness of the second conductive layer 1050 is 5000-8000 angstroms, which is not limited in the embodiments of the present disclosure.
  • the spacing between the multiple data lines DATA, the first power line ELVSS, and the sensing signal lines located in the second conductive layer 1050 is more than 3 microns.
  • FIG. 9 is a schematic diagram of a display device provided by at least one embodiment of the present disclosure.
  • the display device 2 includes a display substrate 1 provided by any embodiment of the present disclosure, for example, the display substrate 1 shown in FIG. 2A.
  • the display device 2 can be any product or component with a display function, such as an OLED panel, an OLED TV, a QLED panel, a QLED TV, a mobile phone, a tablet computer, a notebook computer, a digital photo frame, a navigator, and the like.
  • the display device 2 may also include other components, such as a data driving circuit, a timing controller, etc., which are not limited in the embodiment of the present disclosure.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

L'invention concerne un substrat d'affichage et un dispositif d'affichage. Le substrat d'affichage comprend un substrat de base, de multiples unités de sous-pixel et un circuit d'attaque de grille. Le substrat de base comprend une région d'affichage, la région d'affichage comprend de multiples sous-régions d'affichage agencées dans un réseau, les multiples sous-régions d'affichage comprennent de multiples premières sous-régions d'affichage et de multiples secondes sous-régions d'affichage; les multiples unités de sous-pixel comprennent de multiples premières unités de sous-pixel et de multiples secondes unités de sous-pixel, les éléments électroluminescents des multiples premières unités de sous-pixel sont situés dans les multiples premières sous-régions d'affichage selon une correspondance biunivoque, et les éléments électroluminescents des multiples secondes unités de sous-pixel sont situés dans les multiples secondes sous-régions d'affichage selon une correspondance biunivoque; le circuit d'attaque de grille est au moins partiellement situé dans les multiples secondes sous-régions d'affichage, et la projection orthographique des éléments électroluminescents des multiples secondes unités de sous-pixel sur le substrat de base chevauche au moins partiellement la projection orthographique du circuit d'attaque de grille sur le substrat de base. Le substrat d'affichage peut augmenter le rapport d'ouverture du dispositif d'affichage.
PCT/CN2020/087477 2020-04-28 2020-04-28 Substrat d'affichage et dispositif d'affichage WO2021217413A1 (fr)

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CN202080000618.1A CN113939865B (zh) 2020-04-28 2020-04-28 显示基板以及显示装置

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CN114843327A (zh) * 2022-04-26 2022-08-02 武汉华星光电半导体显示技术有限公司 显示面板以及显示装置
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WO2024021001A1 (fr) * 2022-07-29 2024-02-01 京东方科技集团股份有限公司 Substrat d'affichage et son procédé de fabrication, et dispositif d'affichage
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CN114843327A (zh) * 2022-04-26 2022-08-02 武汉华星光电半导体显示技术有限公司 显示面板以及显示装置
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