WO2021215105A1 - 固体撮像素子 - Google Patents

固体撮像素子 Download PDF

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Publication number
WO2021215105A1
WO2021215105A1 PCT/JP2021/006785 JP2021006785W WO2021215105A1 WO 2021215105 A1 WO2021215105 A1 WO 2021215105A1 JP 2021006785 W JP2021006785 W JP 2021006785W WO 2021215105 A1 WO2021215105 A1 WO 2021215105A1
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WO
WIPO (PCT)
Prior art keywords
stage
reset
level
transistor
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2021/006785
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English (en)
French (fr)
Japanese (ja)
Inventor
ルォンフォン 朝倉
喜昭 稲田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Semiconductor Solutions Corp
Original Assignee
Sony Semiconductor Solutions Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to JP2022516866A priority Critical patent/JP7668266B2/ja
Priority to KR1020247040465A priority patent/KR20250004111A/ko
Priority to CN202411670371.0A priority patent/CN119629501A/zh
Priority to EP25172976.0A priority patent/EP4580208A3/en
Priority to CN202180028744.2A priority patent/CN115398885B/zh
Priority to EP21793493.4A priority patent/EP4142281B1/en
Application filed by Sony Semiconductor Solutions Corp filed Critical Sony Semiconductor Solutions Corp
Priority to DE112021002443.4T priority patent/DE112021002443T5/de
Priority to KR1020227035272A priority patent/KR20230005146A/ko
Priority to US17/995,745 priority patent/US12047701B2/en
Publication of WO2021215105A1 publication Critical patent/WO2021215105A1/ja
Anticipated expiration legal-status Critical
Priority to US18/746,479 priority patent/US12581218B2/en
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
    • H04N25/771—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/50—Control of the SSIS exposure
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H04N25/616—Noise processing, e.g. detecting, correcting, reducing or removing noise involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H04N25/65—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/78—Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/79—Arrangements of circuitry being divided between different or multiple substrates, chips or circuit boards, e.g. stacked image sensors

Definitions

  • a digital signal processing unit that adds a pair of continuous frames is further provided, and the pre-stage circuit has the first and second capacitances within the exposure period of one of the pair of frames. After having one of the elements hold the reset level, the other of the first and second capacitance elements holds the signal level, and the first and second capacitances are within the exposure period of the other of the pair of frames. After the other side of the element holds the reset level, the other side of the first and second capacitance elements may hold the signal level. This has the effect of improving the sensitivity non-uniformity.
  • an analog-digital converter that sequentially converts the output reset level and the signal level into a digital signal is further provided, and the analog-digital converter is provided on the second chip. May be done. This has the effect of facilitating the miniaturization of pixels.
  • Timing chart which shows an example of voltage control in 3rd Embodiment of this technique. It is a timing chart which shows an example of the global shutter operation of an odd number frame in 4th Embodiment of this technique. It is a timing chart which shows an example of the reading operation of an odd number frame in 4th Embodiment of this technique. It is a timing chart which shows an example of the even-numbered frame global shutter operation in 4th Embodiment of this technique. It is a timing chart which shows an example of the even-numbered frame reading operation in 4th Embodiment of this technique. It is a circuit diagram which shows one structural example of the column signal processing circuit in 5th Embodiment of this technique.
  • the vertical synchronization signal VSYNC is a signal indicating the timing of imaging, and a periodic signal of a constant frequency (60 Hz or the like) is used as the vertical synchronization signal VSYNC.
  • the image pickup device 100 records image data
  • the image data may be transmitted to the outside of the image pickup device 100.
  • an external interface for transmitting image data is further provided.
  • the image pickup apparatus 100 may further display image data.
  • a display unit is further provided.
  • the selection circuit 330 of the selected row by the above-mentioned read control controls to connect the capacitance element 321 to the subsequent node 340, to disconnect the capacitance elements 321 and 322 from the latter node 340, and to connect the capacitance element 322 to the latter node 340.
  • the control to connect to is performed in order.
  • the trailing reset transistor 341 in the selected row initializes the level of the trailing node 340.
  • the post-stage circuit 350 in the selected line reads out the reset level and the signal level in order from the capacitive elements 321 and 322 via the post-stage node 340 and outputs them to the vertical signal line 309.
  • a plurality of ADCs 261 and a digital signal processing unit 262 are arranged in the column signal processing circuit 260.
  • ADC 261 is arranged in each row. Assuming that the number of columns is I, I ADC261s are arranged.
  • the DAC 213 gradually raises the lamp signal Rmp from the timing T12 after the timing T11 to the timing T13.
  • the ADC 261 compares the lamp signal Rmp with the level Vrst'of the vertical signal line 309, and counts the count values until the comparison result is inverted. As a result, the P phase level (reset level) is read out.
  • the signal is read while the pre-stage circuit 310 is connected to the pre-stage node 320, but in this configuration, noise from the pre-stage node 320 cannot be blocked during reading.
  • the pixel 300 of the first modification of the first embodiment is different from the first embodiment in that a transistor is inserted between the pre-stage circuit 310 and the pre-stage node 320.
  • the pre-stage selection transistor 324 opens and closes the path between the pre-stage circuit 310 and the pre-stage node 320 according to the pre-stage selection signal sel from the vertical scanning circuit 211.
  • FIG. 13 is a timing chart showing an example of the global shutter operation in the first modification of the first embodiment of the present technology.
  • the timing chart of the first modification of the first embodiment is different from the first embodiment in that the vertical scanning circuit 211 further supplies the pre-stage reset signal rsta and the pre-stage selection signal sel.
  • rsta_ [n] and sel_ [n] indicate a signal to the pixel in the nth row.
  • the vertical scanning circuit 211 supplies a high-level pre-stage selection signal sel to all pixels from the timing T2 immediately before the end of exposure to the timing T5.
  • the pre-stage reset signal rsta is controlled to a low level.
  • the pre-stage selection transistor 324 shifts to the open state at the time of reading, and the pre-stage circuit 310 is separated from the pre-stage node 320.
  • the noise from the circuit 310 can be blocked.
  • the circuit in the solid-state image sensor 200 is provided on a single semiconductor chip, but in this configuration, the element may not fit in the semiconductor chip when the pixel 300 is miniaturized. There is.
  • the solid-state image sensor 200 of the second modification of the first embodiment is different from the first embodiment in that the circuits in the solid-state image sensor 200 are distributed and arranged on two semiconductor chips.
  • the upper pixel array unit 221 is arranged on the upper pixel chip 201.
  • the lower pixel array unit 222 is arranged on the lower pixel chip 202. For each pixel in the pixel array unit 220, a part thereof is arranged in the upper pixel array unit 221 and the rest is arranged in the lower pixel array unit 222.
  • the column signal processing circuit 260, the vertical scanning circuit 211, the timing control circuit 212, the DAC 213, and the load MOS circuit block 250 are arranged on the circuit chip 203. Circuits other than the column signal processing circuit 260 are omitted in the figure.
  • the upper pixel chip 201 is an example of the first chip described in the claims
  • the lower pixel chip 202 is an example of the second chip described in the claims
  • the circuit chip 203 is an example of the third chip described in the claims.
  • the reset level is sample-held within the exposure period, but in this configuration, the exposure period cannot be shorter than the sample-hold period of the reset level.
  • the solid-state image sensor 200 of the second embodiment is different from the first embodiment in that the exposure period is shortened by adding a transistor that discharges charges from the photoelectric conversion element.
  • FIG. 18 is a circuit diagram showing a configuration example of the pixel 300 according to the second embodiment of the present technology.
  • the pixel 300 of the second embodiment is different from the first embodiment in that the emission transistor 317 is further provided in the pre-stage circuit 310.
  • the PD reset and the FD reset can be performed individually. Therefore, as illustrated in the figure, the FD reset can be performed before the PD reset is released (exposure start), and the reset level can be sample-held. As a result, the exposure period can be made shorter than the sample hold period of the reset level.
  • the FD reset transistor 313 shifts to the ON state at the time of reading, and the FD 314 is fixed to the power supply voltage VDD.
  • the fluctuation amount Vft of the FD314 shifts the potentials of the front-stage node 320 and the rear-stage node 340 at the time of reading by about Vft.
  • the amount of voltage to be shifted varies from pixel to pixel due to variations in the capacitance values of the capacitance elements 321 and 322 and parasitic capacitance, which causes deterioration of PRNU.
  • the timing control circuit 212 sets the reset power supply voltage VRST to the same value as the power supply voltage VDD.
  • the timing control circuit 212 lowers the reset power supply voltage VRST to VDD-Vft. That is, during the read period, the timing control circuit 212 lowers the reset power supply voltage VRST by substantially the same amount as the fluctuation amount Vft due to the reset feedthrough.
  • the amount of voltage fluctuation between the FD 314 and the previous stage node 320 can be reduced as illustrated in the figure. As a result, it is possible to suppress variations in the capacitance elements 321 and 322 and deterioration of PRNU due to parasitic capacitance.
  • FIG. 24 is a timing chart showing an example of the global shutter operation of odd-numbered frames in the fourth embodiment.
  • the pre-stage circuit 310 in the solid-state image sensor 200 holds the reset level in the capacitive element 321 by setting the selection signal ⁇ s to a high level next to the selection signal ⁇ r, and then sets the signal level. It is held by the capacitive element 322.
  • FIG. 26 is a timing chart showing an example of even-numbered frame global shutter operation in the fourth embodiment.
  • the pre-stage circuit 310 in the solid-state image sensor 200 holds the reset level in the capacitive element 322 by setting the selection signal ⁇ r to a high level next to the selection signal ⁇ s, and then sets the signal level. It is held by the capacitive element 321.
  • FIG. 27 is a timing chart showing an example of an even-numbered frame reading operation according to the fourth embodiment of the present technology.
  • the subsequent circuit 350 in the solid-state image sensor 200 sets the selection signal ⁇ r to the high level next to the selection signal ⁇ s and reads the signal level next to the reset level.
  • the levels held by the capacitive elements 321 and 322 are opposite in the even frame and the odd frame.
  • the polarities of the PRNU are also reversed between the even-numbered frames and the odd-numbered frames.
  • the column signal processing circuit 260 in the subsequent stage obtains the averaging of odd-numbered frames and even-numbered frames.
  • PRNUs having opposite polarities can cancel each other out.
  • the column signal processing circuit 260 has obtained the difference between the reset level and the signal level for each column.
  • the charge overflows from the photoelectric conversion element 311 and the brightness is lowered, which may cause a black spot phenomenon in which the light sinks black.
  • the solid-state image sensor 200 of the fifth embodiment is different from the first embodiment in that it is determined for each pixel whether or not a black spot phenomenon has occurred.
  • the selector 281 attaches the capacitive element 282 to the non-inverting input terminal (+) of the comparator 285 with either the vertical signal line 309 of the corresponding column and the node of the predetermined reference voltage VREF according to the input side selection signal selin. It connects via.
  • the input side selection signal selin is supplied from the timing control circuit 212.
  • the selector 281 is an example of the input side selector described in the claims.
  • the output voltage Vj is input to the non-inverting input terminal (+) of the buffer amplifier 422.
  • the inverting input terminal (-) of the buffer amplifier 422 is connected to the output terminal.
  • the capacitance element 423 holds the voltage of the output terminal of the buffer amplifier 422 as V gen. This V gen is supplied to the switching unit 440.
  • the potentials of the respective pre-stage nodes at the time of global shutter operation and at the time of reading each row are aligned, and PRNU can be improved. Further, since the source follower in the previous stage is turned off when reading each line, the circuit noise of the source follower does not occur as illustrated in FIG. 38, and the value becomes 0 ( ⁇ Vrms). Of the source followers in the previous stage, the front-stage amplification transistor 315 is in the ON state.
  • the microcomputer 12051 calculates the control target value of the driving force generator, the steering mechanism, or the braking device based on the information inside and outside the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and the drive system control unit.
  • a control command can be output to 12010.
  • the microcomputer 12051 realizes ADAS (Advanced Driver Assistance System) functions including vehicle collision avoidance or impact mitigation, follow-up driving based on inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane deviation warning, and the like. It is possible to perform cooperative control for the purpose of.
  • ADAS Advanced Driver Assistance System
  • At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays.
  • the microcomputer 12051 can recognize a pedestrian by determining whether or not a pedestrian is present in the captured image of the imaging units 12101 to 12104.
  • pedestrian recognition includes, for example, a procedure for extracting feature points in an image captured by an imaging unit 12101 to 12104 as an infrared camera, and pattern matching processing for a series of feature points indicating the outline of an object to determine whether or not the pedestrian is a pedestrian. It is done by the procedure to determine.
  • a selection circuit that sequentially performs control to connect the other to the subsequent node, A post-stage reset transistor that initializes the level of the post-stage node when both the first and second capacitive elements are disconnected from the post-stage node, A solid-state imaging device including a rear-stage circuit that reads out and outputs the reset level and the signal level in order from the first and second capacitive elements via the rear-stage node.
  • a pre-stage selection transistor that opens and closes a path between the pre-stage circuit and a predetermined pre-stage node, and A pre-stage reset transistor that initializes the level of the pre-stage node is further provided.
  • the pre-stage circuit further includes a current source transistor connected to the drain of the pre-stage amplification transistor.
  • the switching unit supplies a predetermined power supply voltage as the source voltage within the exposure period, and supplies a generated voltage different from the power supply voltage as the source voltage after the end of the exposure period.
  • Solid-state image sensor (7) The above-mentioned (6), wherein the difference between the power supply voltage and the generated voltage substantially coincides with the sum of the fluctuation amount due to the reset feed-through of the first reset transistor and the gate-source voltage of the pre-stage amplification transistor.
  • the solid-state imaging device according to (19), wherein the vertical scanning circuit further controls the plurality of rows to start exposure in order.
  • the pre-stage circuit is provided on the first chip.
  • the solid-state imaging device according to any one of (1) to (20), wherein the first and second capacitive elements, the selection circuit, the latter-stage reset tragista, and the latter-stage circuit are provided on a second chip. ..
  • An analog-to-digital converter that sequentially converts the output reset level and the signal level into a digital signal is further provided.
  • the solid-state image sensor according to (21), wherein the analog-digital converter is provided on the second chip.
  • An analog-to-digital converter that sequentially converts the output reset level and the signal level into a digital signal is further provided.
  • Image sensor 110 Image sensor 120 Recording unit 130 Image control unit 200
  • Solid-state image sensor 201 Upper pixel chip 202 Lower pixel chip 203 Circuit chip 211 Vertical scanning circuit 212 Timing control circuit 213 DAC 220 Pixel array part 221 Upper pixel array part 222 Lower pixel array part 250 Load MOS circuit block 251 Load MOS transistor 260
  • Comparer 291 CDS processing unit 300 pixels 301 Effective pixel 310 Pre-circuit circuit 311 Photoelectric conversion element 312 Transfer Tragista 313 FD Reset Transistor 314 FD 315 Pre-stage amplification transistor 316 Current source transistor 317 Discharge transistor 323 Pre-stage reset transistor 324 Pre-stage selection transistor 330 Selection circuit 331, 332 Selection transistor 341 Second-stage reset transistor 350 Second-stage circuit 351 Second-stage a

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)
  • Solid State Image Pick-Up Elements (AREA)
PCT/JP2021/006785 2020-04-21 2021-02-24 固体撮像素子 Ceased WO2021215105A1 (ja)

Priority Applications (10)

Application Number Priority Date Filing Date Title
DE112021002443.4T DE112021002443T5 (de) 2020-04-21 2021-02-24 Solid-State-Bildgebungselement
KR1020247040465A KR20250004111A (ko) 2020-04-21 2021-02-24 고체 촬상 소자
CN202411670371.0A CN119629501A (zh) 2020-04-21 2021-02-24 光检测装置
EP25172976.0A EP4580208A3 (en) 2020-04-21 2021-02-24 Solid-state image capturing element
CN202180028744.2A CN115398885B (zh) 2020-04-21 2021-02-24 固态摄像元件
JP2022516866A JP7668266B2 (ja) 2020-04-21 2021-02-24 固体撮像素子
US17/995,745 US12047701B2 (en) 2020-04-21 2021-02-24 Solid-state imaging element
EP21793493.4A EP4142281B1 (en) 2020-04-21 2021-02-24 Solid-state image capturing element
KR1020227035272A KR20230005146A (ko) 2020-04-21 2021-02-24 고체 촬상 소자
US18/746,479 US12581218B2 (en) 2020-04-21 2024-06-18 Solid-state imaging element

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2020075184 2020-04-21
JP2020-075184 2020-04-21
JP2020193108 2020-11-20
JP2020-193108 2020-11-20

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US17/995,745 A-371-Of-International US12047701B2 (en) 2020-04-21 2021-02-24 Solid-state imaging element
US18/746,479 Continuation US12581218B2 (en) 2020-04-21 2024-06-18 Solid-state imaging element

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WO2021215105A1 true WO2021215105A1 (ja) 2021-10-28

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PCT/JP2021/006785 Ceased WO2021215105A1 (ja) 2020-04-21 2021-02-24 固体撮像素子

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US (2) US12047701B2 (https=)
EP (2) EP4580208A3 (https=)
JP (1) JP7668266B2 (https=)
KR (2) KR20230005146A (https=)
CN (2) CN119629501A (https=)
DE (1) DE112021002443T5 (https=)
WO (1) WO2021215105A1 (https=)

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WO2023063024A1 (ja) * 2021-10-15 2023-04-20 ソニーセミコンダクタソリューションズ株式会社 固体撮像素子、撮像装置、および、固体撮像素子の制御方法
WO2023085138A1 (ja) 2021-11-12 2023-05-19 ソニーグループ株式会社 固体撮像装置およびその駆動方法、並びに電子機器
WO2023157489A1 (ja) * 2022-02-21 2023-08-24 ソニーセミコンダクタソリューションズ株式会社 固体撮像素子、撮像装置、および、固体撮像素子の制御方法
WO2023166854A1 (ja) * 2022-03-04 2023-09-07 ソニーセミコンダクタソリューションズ株式会社 固体撮像素子、撮像装置、および、固体撮像素子の制御方法
WO2024004377A1 (ja) * 2022-06-29 2024-01-04 ソニーセミコンダクタソリューションズ株式会社 固体撮像素子、撮像装置、および、固体撮像素子の制御方法
WO2024024464A1 (ja) * 2022-07-25 2024-02-01 ソニーセミコンダクタソリューションズ株式会社 固体撮像素子、および電子機器
WO2024095630A1 (ja) * 2022-10-31 2024-05-10 ソニーセミコンダクタソリューションズ株式会社 撮像装置
WO2024203629A1 (ja) 2023-03-24 2024-10-03 ソニーセミコンダクタソリューションズ株式会社 光検出装置及び電子機器
WO2024203630A1 (ja) 2023-03-24 2024-10-03 ソニーセミコンダクタソリューションズ株式会社 光検出装置及び電子機器
WO2024203524A1 (ja) * 2023-03-24 2024-10-03 ソニーセミコンダクタソリューションズ株式会社 光検出装置及び電子機器
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