WO2021212918A1 - 一种阵列基板、显示面板及显示装置 - Google Patents

一种阵列基板、显示面板及显示装置 Download PDF

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WO2021212918A1
WO2021212918A1 PCT/CN2020/141876 CN2020141876W WO2021212918A1 WO 2021212918 A1 WO2021212918 A1 WO 2021212918A1 CN 2020141876 W CN2020141876 W CN 2020141876W WO 2021212918 A1 WO2021212918 A1 WO 2021212918A1
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chip
array substrate
row
length
chip pins
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PCT/CN2020/141876
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English (en)
French (fr)
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弋高飞
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上海创功通讯技术有限公司
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Publication of WO2021212918A1 publication Critical patent/WO2021212918A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals

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  • This application relates to the field of display technology, and in particular to an array substrate, a display panel and a display device.
  • a liquid crystal display is composed of two layers of substrates, one is a color filter substrate, and the other is an array substrate. A part of the array substrate overlaps the color filter substrate to form a display area, and the other part is a single-layer glass area. Since the higher the proportion of the display area in the entire display screen, the higher the display proportion. Therefore, how to expand the proportion of the display area under the condition of a certain area of the liquid crystal display screen is a problem that needs to be solved.
  • the present application provides an array substrate, which can effectively reduce the length of the single-layer glass area along the first direction to achieve the purpose of increasing the proportion of the display area.
  • the present application provides an array substrate, including: a single-layer glass area and a display area corresponding to the color filter substrate, the single-layer glass area and the display area are arranged along a first direction; the single-layer glass area and the display area are arranged along a first direction; There are multiple rows of chip pins along the first direction in the glass area, and each row is provided with multiple chip pins arranged in a second direction, wherein the second direction is perpendicular to the first direction and parallel to the array Substrate; In at least one row of the chip pins, the length of each chip pin along the first direction is less than its actual length.
  • the size of the chip is relatively high.
  • the array substrate provided by the present application can effectively reduce the length of the single-layer glass area along the first direction by setting the length of the chip pins in the single-layer glass area along the first direction to be less than its own length. The purpose of increasing the proportion of the display area is achieved.
  • the multiple rows of chip pins include multiple rows of output chip pins and one row of input chip pins, and in at least one row of output chip pins, each output chip pin runs along the first direction The length is smaller than its actual length, and the length of the input terminal chip pin along the first direction is smaller than its own actual length.
  • each output end chip pin is a bar shape, and at least one row of output end chip pins has an included angle greater than 0 and less than 90° with the second direction.
  • each row of the output chip pins and the second direction have an included angle greater than 0 and less than 90°, and each row of the output chip pins and the second direction The angles between the directions are the same.
  • the shape of the input terminal chip pin is a bar, and the included angle with the second direction is greater than 0 and less than 90°.
  • each output terminal chip pin in at least one row of output terminal chip pins, is an arc, and the protrusion between the output terminal chip pin and the second direction is greater than The included angle is 0 and less than 90°.
  • each row of the output end chip pins is arc
  • the protrusion of each output end chip pin has a degree greater than 0 and less than 90 degrees from the second direction.
  • the included angle between each of the output end chip pins and the second direction is the same.
  • the shape of the input end chip pin is arc, and the protrusion of each input end chip pin and the second direction have an included angle greater than 0 and less than 90° .
  • An embodiment of the present application also provides a display panel, including a color filter substrate and the array substrate described in any one of the above.
  • An embodiment of the present application also provides a display device including the above-mentioned display panel.
  • FIG. 1 is a schematic diagram of a structure of an existing array substrate
  • FIG. 2 is a schematic diagram of a structure of the array substrate in this application.
  • FIG. 3 is a schematic diagram of a structure of the array substrate in this application.
  • the chip pins 21 of the existing array substrate located in the single-layer glass area 2 are generally strip-shaped, and are placed along the direction from the display area 1 to the single-layer glass area 2, that is, each chip pin 21 is in the The length in this direction is equal to its own length. Since the size of the single-layer glass area 2 is constant, the above structure poses a challenge to increase the proportion of the display area 1.
  • the present application provides an array substrate, including: a single-layer glass area 2 and a display area 1 corresponding to the color filter substrate, and the single-layer glass area 2 and the display area 1 are arranged along a first direction; A plurality of rows of chip pins 21 are provided in the single-layer glass area 2 along the first direction, and each row is provided with a plurality of chip pins 21 arranged in a second direction, wherein the second direction is perpendicular to the first direction and parallel to Array substrate; in at least one row of chip pins 21, the length of each chip pin 21 along the first direction is less than its actual length.
  • the distance between the chip and the two ends of the single-layer glass area 2 is constant.
  • the chip pins 21 in the single-layer glass area 2 even if the length of at least one row of chip pins 21 in the multiple rows of chip pins 21 in the first direction is less than its own length, the chip can be reduced.
  • the length of the pin 21 along the first direction reduces the length of the single-layer glass area 2 along the first direction, and further increases the proportion of the display area 1.
  • the above-mentioned chip pins 21 include multiple rows of output chip pins 211 and a row of input chip pins 212, so that each output chip pin 211 in at least one row of output chip pins 211 can be arranged along the first row.
  • the length in one direction is smaller than its own length
  • the length of the input chip pin 212 along the first direction is smaller than its own length.
  • the shapes of the output chip pins 211 and the input chip pins 212 are both strip shapes, wherein at least one row of the output chip pins 211 and the second direction
  • the included angle is greater than 0 and less than 90°
  • the included angle between the input chip pin 212 and the second direction is greater than 0 and less than 90°.
  • the shape of the chip pins 21 in the above structure is similar to the existing ones, but the arrangement is at a certain angle to the second direction. According to the Pythagorean theorem, the length of each chip pin 21 in the first direction can be made smaller than The length of its own, thereby reducing the length of the single-layer glass zone 2 in the first direction.
  • each output chip pin 211 in the existing array substrate is 50mm
  • the length of a row of output chip pins 211 along the first direction is 40mm
  • a row of output chip pins 211 can save 10mm in size along the first direction.
  • the angle between each row of output chip pins 211 and the second direction is greater than 0 and less than 90°, and the angle between each row of output chip pins 211 and the second direction
  • the included angle between the two remains the same, and the included angle is the same as the included angle between the input terminal chip pin 212 and the second direction.
  • the shape of at least one row of output chip pins 211 is arc, and the protrusion of each output chip pin 211 is greater than 0 and smaller than the second direction.
  • the included angle of 90°, and the shape of the input end chip pin 212 is also arc-shaped, and the included angle between the protrusion of each input end chip pin 212 and the second direction is greater than 0 and less than 90°. Since the shapes of the output chip pins 211 and the input chip pins 212 are designed to be arcs, the length of the chip pins 21 in this embodiment along the first direction can be smaller than its own length, thereby reducing the single layer. The length of the glass zone 2 along the first direction.
  • Figure 1 and Figure 3 can be combined.
  • a row of output chip pins 211 are strip-shaped, their length is 30mm, and the length of the output chip pins 211 remains unchanged.
  • the output chip pins 211 are When designed in an arc shape, the length in the first direction can be shortened to 20 mm, so that a row of output terminal chip pins 211 can be reduced in size by 10 mm in the first direction.
  • the shapes of the output terminal chip pins 211 in more rows are designed as arcs, the size of the single-layer glass area 2 along the first direction can be saved.
  • each row of output chip pins 211 can be designed to be arc-shaped, and the angle between the protrusion of each output chip pin 211 and the second direction is the same, and each input The angle between the protrusion of the terminal chip pin 212 and the second direction is the same as the angle between the protrusion of the output chip pin 211 and the second direction.
  • each The protrusion of the chip pin 21 is 45° from the second direction.
  • the present application also provides a display panel, including a color filter substrate and the above-mentioned array substrate. Since the above-mentioned array substrate effectively reduces the length of the single-layer glass area 2, the display area 1 corresponding to the color filter substrate can be made The size of the display area is increased, thereby increasing the proportion of the display area 1 and ensuring a better display effect.
  • the present application also provides a display device including the above-mentioned display panel. Since the above-mentioned display panel improves the display effect, the display effect of the display device is also guaranteed.

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  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
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  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

本申请涉及显示技术领域，公开了一种阵列基板、显示面板及显示装置，其中，阵列基板包括：单层玻璃区和与彩膜基板对应的显示区，单层玻璃区和显示区沿第一方向排列；单层玻璃区内沿第一方向设有多排芯片管脚，每一排设有多个沿第二方向排列的芯片管脚，其中，第二方向与第一方向垂直且平行于阵列基板；至少一排芯片管脚中，各芯片管脚沿第一方向的长度小于其自身实际长度。

Description

一种阵列基板、显示面板及显示装置
交叉引用
本申请要求于2020年4月24日递交的名称为“一种阵列基板、显示面板及显示装置”、申请号为202010333113.9的中国专利申请的优先权，其通过引用被全部并入本申请。
技术领域
本申请涉及显示技术领域，特别涉及一种阵列基板、显示面板及显示装置。
背景技术
一般的，液晶显示屏由两层基板组成，一层为彩膜基板，一层为阵列基板，阵列基板的一部分与彩膜基板重合，为显示区，另一部分为单层玻璃区部分。由于显示区占整个显示屏的比例越高，则显示占比越高，因此，如何在液晶显示屏面积一定的条件下扩大显示区的占比是需要解决的问题。
发明内容
本申请提供了一种阵列基板，能够有效减小单层玻璃区沿第一方向的长度而达到提升显示区的占比的目的。
为了达到上述目的，本申请提供一种阵列基板，包括：单层玻璃区和与彩膜基板对应的显示区，所述单层玻璃区和所述显示区沿第一方向排列；所述单层玻璃区内沿第一方向设有多排芯片管脚，每一排设有多个沿第二方向排列的芯片管脚，其中，所述第二方向与第一方向垂直且平行于所述阵列基板；至少一排所述芯片管脚中，各芯片管脚沿第一方向的长度小于其自身实际长度。
上述阵列基板，由于单层玻璃区部分，芯片的尺寸占比较高，单层玻璃区内设有多排芯片管脚，通过设置其中至少一排芯片管脚的排布在沿第一方向的 长度小于其自身的长度，相比于一些情形中的每一排芯片管脚沿第一方向的长度等于其自身的长度，本申请中的技术方案能够减小单层玻璃区内芯片沿第一方向的长度，从而减小单层玻璃区沿第一方向的长度。且越多排芯片管脚沿第一方向的长度小于其自身的长度，越能够减小单层玻璃区内芯片沿第一方向的长度，从而更好地提高显示区的占比。
因此，本申请提供的阵列基板，通过设置单层玻璃区内芯片管脚的排布在沿第一方向的长度小于其自身长度，可有效减小单层玻璃区沿第一方向的长度，从而达到了提高显示区的占比的目的。
在一个实施例中，多排芯片管脚中包括多排输出端芯片管脚和一排输入端芯片管脚，至少一排输出端芯片管脚中，各输出端芯片管脚沿第一方向的长度小于其自身实际长度，且所述输入端芯片管脚沿第一方向的长度小于其自身实际长度。
在一个实施例中，各所述输出端芯片管脚的形状为条形，且至少一排输出端芯片管脚与所述第二方向之间具有大于0且小于90°的夹角。
在一个实施例中，每一排所述输出端芯片管脚与第二方向之间均具有大于0且小于90°的夹角，且每一排所述输出端芯片管脚与所述第二方向之间的夹角相同。
在一个实施例中，所述输入端芯片管脚的形状为条形，且与所述第二方向之间具有大于0且小于90°的夹角。
在一个实施例中，至少一排输出端芯片管脚中，各输出端芯片管脚的形状为弧形，且所述输出端芯片管脚的凸起部与所述第二方向之间具有大于0且小于90°的夹角。
在一个实施例中，每一排所述输出端芯片管脚的形状为弧形，每一个所述输出端芯片管脚的凸起部与所述第二方向之间具有大于0且小于90°的夹角，且每一个所述输出端芯片管脚的凸起部与所述第二方向之间的夹角相同。
在一个实施例中，所述输入端芯片管脚的形状为弧形，且各所述输入端芯 片管脚的凸起部与所述第二方向之间具有大于0且小于90°的夹角。
本申请实施例还提供一种显示面板，包括彩膜基板和上述任一项所述的阵列基板。
本申请实施例还提供一种显示装置，包括上述显示面板。
附图说明
图1为现有阵列基板的一种结构示意图；
图2为本申请中阵列基板的一种结构示意图；
图3为本申请中阵列基板的一种结构示意图。
图中：
1-显示区；2-单层玻璃区；21-芯片管脚；211-输出端芯片管脚；212-输入端芯片管脚。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
如图1所示，现有的阵列基板位于单层玻璃区2内的芯片管脚21一般呈条形，且沿显示区1到单层玻璃区2的方向放置，即各芯片管脚21在该方向的长度等于其自身的长度，由于单层玻璃区2的尺寸一定，上述结构给提升显示区1的占比带来了挑战。
请参考图2或图3，本申请提供了一种阵列基板，包括：单层玻璃区2和与彩膜基板对应的显示区1，单层玻璃区2和显示区1沿第一方向排列；单层玻璃区2内沿第一方向设有多排芯片管脚21，每一排设有多个沿第二方向排列的芯片管脚21，其中，第二方向与第一方向垂直且平行于阵列基板；至少一排 芯片管脚21中，各芯片管脚21沿第一方向的长度小于其自身实际长度。
上述阵列基板，由于单层玻璃区2内，芯片的尺寸占比较高，沿第一方向，芯片到单层玻璃区2两端的距离一定。通过改变单层玻璃区2内芯片管脚21的排布，即使得多排芯片管脚21中的至少一排芯片管脚21在沿第一方向的长度小于其自身长度，即可减小芯片管脚21沿第一方向的长度，从而减小单层玻璃区2沿第一方向的长度，进一步提高了显示区1的占比。
上述阵列基板，当越多排的芯片管脚21在排布上使得每一排的芯片管脚21在沿第一方向的长度小于其自身长度，越能够减小单层玻璃区2沿第一方向的长度，从而更好地提升显示区1的占比。
具体地，上述芯片管脚21包括多排输出端芯片管脚211和一排输入端芯片管脚212，可使得其中至少一排输出端芯片管脚211中的各输出端芯片管脚211沿第一方向的长度小于其自身长度，且输入端芯片管脚212在沿第一方向的长度小于其自身长度。通过既减小输出端芯片管脚211沿第一方向的长度，又减小输入端芯片管脚212沿第一方向的长度，可进一步地减小单层玻璃区2沿第一方向的长度。其中，作为一种可选的方案，每一排的芯片管脚21在沿第一方向的长度均小于其自身长度，可最大限度地减小单层玻璃区2沿第一方向的长度。
在一个实施例中，如图2所示，上述输出端芯片管脚211和输入端芯片管脚212的形状均为条形状，其中，至少一排输出端芯片管脚211与第二方向之间具有大于0且小于90°的夹角，且输入端芯片管脚212与第二方向之间也具有大于0且小于90°的夹角。上述结构中的芯片管脚21的形状与现有的类似，但其排列方式与第二方向之间呈一定的角度，根据勾股定理，可使得各芯片管脚21沿第一方向的长度小于其自身的长度，从而减小单层玻璃区2沿第一方向的长度。
可结合图1和图2，例如，现有阵列基板中每一个输出端芯片管脚211的长度为50mm，当使得一排的输出端芯片管脚211与第二方向呈一定夹角时， 该排输出端芯片管脚211沿第一方向的长度为40mm，则一排输出端芯片管脚211沿第一方向上可节省10mm的尺寸，当越多排芯片管脚21与第二方向之间呈一定角度排布时，可节省的空间越大。
本实施例中，上述每一排输出端芯片管脚211与第二方向之间均具有大于0且小于90°的夹角，并且可使得每一排输出端芯片管脚211与第二方向之间的夹角保持相同，且该夹角与输入端芯片管脚212与第二方向之间的夹角相同。上述结构可使得本申请实施例中的阵列基板便于生产制造的同时，还可最大限度地减小单层玻璃区2沿第一方向的长度，从而提升显示区1的占比。
在一个实施例中，如图3所示，至少一排输出端芯片管脚211的形状为弧形，且各输出端芯片管脚211的凸起部与第二方向之间具有大于0且小于90°的夹角，且输入端芯片管脚212的形状也为弧形，各输入端芯片管脚212的凸起部与第二方向之间具有大于0且小于90°的夹角。由于将输出端芯片管脚211和输入端芯片管脚212的形状设计成弧形，能够使得本实施例中的芯片管脚21沿第一方向的长度小于其自身的长度，从而减小单层玻璃区2沿第一方向的长度。
可结合图1和图3，例如，当一排输出端芯片管脚211为条形时，其自身长度为30mm，保持输出端芯片管脚211的长度不变，当该输出端芯片管脚211设计为弧形时，可将其沿第一方向上的长度缩短至20mm，由此，一排输出端芯片管脚211沿第一方向可减小10mm的尺寸。当越多排输出端芯片管脚211的形状设计为弧形，越可节省单层玻璃区2沿第一方向的尺寸。
本实施例中，可将每一排输出端芯片管脚211均设计为弧形，且每一个输出端芯片管脚211的凸起部与第二方向之间的夹角相同，且每一个输入端芯片管脚212的凸起部与第二方向之间的夹角与上述输出端芯片管脚211的凸起部与第二方向之间的夹角相同，一种方案中，可使得每一个芯片管脚21的凸起部与第二方向之间呈45°。上述结构可使得本申请实施例中的阵列基板便于生产制造的同时，还可最大限度地减小单层玻璃区2沿第一方向的长度，从而提 升显示区1的占比。
基于同一发明思路，本申请还提供一种显示面板，包括彩膜基板和上述阵列基板，由于上述阵列基板有效地减少了单层玻璃区2的长度，可使得与彩膜基板对应的显示区1的尺寸增大，从而提升了显示区1的占比，保证了更好的显示效果。
基于同一发明思路，本申请还提供一种显示装置，包括上述显示面板，由于上述显示面板提升了显示效果，也保证了显示装置的显示效果。
显然，本领域的技术人员可以对本申请实施例进行各种改动和变型而不脱离本申请的精神和范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (10)

  1. 一种阵列基板，包括：
    单层玻璃区和与彩膜基板对应的显示区，所述单层玻璃区和所述显示区沿第一方向排列；
    所述单层玻璃区内沿第一方向设有多排芯片管脚，每一排设有多个沿第二方向排列的芯片管脚，其中，所述第二方向与第一方向垂直且平行于所述阵列基板；至少一排所述芯片管脚中，各芯片管脚沿第一方向的长度小于其自身实际长度。
  2. 根据权利要求1所述的阵列基板，其中，多排芯片管脚中包括多排输出端芯片管脚和一排输入端芯片管脚，至少一排输出端芯片管脚中，各输出端芯片管脚沿第一方向的长度小于其自身实际长度，且所述输入端芯片管脚沿第一方向的长度小于其自身实际长度。
  3. 根据权利要求2所述的阵列基板，其中，各所述输出端芯片管脚的形状为条形，且至少一排输出端芯片管脚与所述第二方向之间具有大于0且小于90°的夹角。
  4. 根据权利要求3所述的阵列基板，其中，每一排所述输出端芯片管脚与第二方向之间均具有大于0且小于90°的夹角，且每一排所述输出端芯片管脚与所述第二方向之间的夹角相同。
  5. 根据权利要求3或4所述的阵列基板，其中，所述输入端芯片管脚的形状为条形，且与所述第二方向之间具有大于0且小于90°的夹角。
  6. 根据权利要求2所述的阵列基板，其中，至少一排输出端芯片管脚中，各输出端芯片管脚的形状为弧形，且所述输出端芯片管脚的凸起部与所述第二方向之间具有大于0且小于90°的夹角。
  7. 根据权利要求6所述的阵列基板，其中，每一排所述输出端芯片管脚的形状为弧形，每一个所述输出端芯片管脚的凸起部与所述第二方向之间具有大于0且小于90°的夹角，且每一个所述输出端芯片管脚的凸起部与所述第二 方向之间的夹角相同。
  8. 根据权利要求6或7所述的阵列基板，其中，所述输入端芯片管脚的形状为弧形，且各所述输入端芯片管脚的凸起部与所述第二方向之间具有大于0且小于90°的夹角。
  9. 一种显示面板，包括彩膜基板和权利要求1-8任一项所述的阵列基板。
  10. 一种显示装置，包括如权利要求9所述的显示面板。
PCT/CN2020/141876 2020-04-24 2020-12-31 一种阵列基板、显示面板及显示装置 WO2021212918A1 (zh)

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