WO2021212583A1 - Led 拼接显示面板 - Google Patents

Led 拼接显示面板 Download PDF

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Publication number
WO2021212583A1
WO2021212583A1 PCT/CN2020/090902 CN2020090902W WO2021212583A1 WO 2021212583 A1 WO2021212583 A1 WO 2021212583A1 CN 2020090902 W CN2020090902 W CN 2020090902W WO 2021212583 A1 WO2021212583 A1 WO 2021212583A1
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WO
WIPO (PCT)
Prior art keywords
fan
sub
led
out area
pixels
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PCT/CN2020/090902
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English (en)
French (fr)
Inventor
汤爱华
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深圳市华星光电半导体显示技术有限公司
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Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Priority to US16/962,054 priority Critical patent/US12014658B2/en
Publication of WO2021212583A1 publication Critical patent/WO2021212583A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/302—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements characterised by the form or geometrical disposition of the individual elements
    • G09F9/3026—Video wall, i.e. stackable semiconductor matrix display modules

Definitions

  • This application relates to the field of display technology, and in particular to an LED spliced display panel.
  • LED Light Emitting Diode
  • LED is a flat panel display, composed of small LED module panels, used to display text, image, video, video signal and other information equipment.
  • LED display The high brightness, wide viewing angle and good color reproduction ability are also better than LCD screens (liquid crystal displays).
  • LED swipe screens are generally used in airports, shopping malls, hotels, high-speed trains, subways, cinemas, exhibitions, office buildings, etc. Target customers have strong spending power and great advertising value.
  • Existing LED display screens need to be spliced according to specific lengths to make LED splicing screens.
  • LED splicing screens are moving towards a smaller size and higher resolution, which poses challenges to the size reduction of LED chips, thin film transistors and related wiring design in a single pixel space. Especially in order to achieve seamless splicing, it greatly increases the difficulty of pixel design, and greatly affects the development of LEDs in the direction of small size and high resolution.
  • the embodiment of the present application provides an LED splicing display panel, which can alleviate the space limitation of some pixels at key positions, so as to solve the existing LED splicing display panel.
  • some pixels are in the key position. Restrictions have greatly affected the technical problems of LED splicing display panels in the direction of small size and high resolution.
  • the embodiment of the present application provides an LED splicing display panel.
  • the LED splicing display panel includes at least one repeating unit, and each repeating unit includes four sub-LED display panels spliced with each other.
  • the display areas are arranged in two rows and two columns.
  • Each of the sub-LED display panels includes a display area and corresponding fan-out areas located on two adjacent sides of the display area. There are also two adjacent sub-LED display panels. Have seams and share the fan-out area;
  • each of the display areas has a plurality of sub-pixels
  • the sub-pixels include a plurality of irregular-shaped sub-pixels arranged along the edge of the display area and a plurality of non-shaped sub-pixels respectively adjacent to the irregular-shaped sub-pixels,
  • Each of the irregular-shaped sub-pixels is adjacent to the corresponding fan-out area; the display area of the irregular-shaped sub-pixel is smaller than the display area of the non-shaped sub-pixel.
  • the fan-out area includes a first fan-out area arranged along a first direction D1 and a second fan-out area arranged along a second direction D2;
  • the seams include first seams arranged along the first direction D1 and second seams arranged along the second direction D2, and the first direction D1 is perpendicular to the second direction D2.
  • the first fan-out area is provided with a plurality of data signal lines
  • the second fan-out area is provided with a plurality of scanning signal lines.
  • the sub-pixels adjacent to the fan-out area are all the special-shaped sub-pixels.
  • the data signal lines are arranged on the same side of the first seam, and the scan signal lines are arranged on the same side of the second seam.
  • the data signal lines are arranged on the same side of the first seam, and the scan signal lines are evenly arranged on two adjacent ones of the second seam. side.
  • the irregularly shaped sub-pixel includes a first irregularly-shaped sub-pixel and a second irregularly-shaped sub-pixel, and the first irregularly-shaped sub-pixel is connected to the first fan-out area and The second fan-out area is adjacent to each other, and the second irregular sub-pixel is adjacent to the first fan-out area or the second fan-out area.
  • some of the sub-pixels adjacent to the fan-out area are the irregular-shaped sub-pixels.
  • the data signal lines are misaligned arranged on the adjacent two sides of the first seam, and the scan signal lines are misaligned arranged on the second seam. Adjacent to both sides.
  • the embodiment of the present application also provides an LED splicing display panel, the LED splicing display panel includes at least one repeating unit, and each repeating unit includes four sub-LED display panels spliced with each other, and the four sub-LED display panels
  • the display areas are arranged in two rows and two columns.
  • Each of the sub-LED display panels includes a display area and corresponding fan-out areas located on two adjacent sides of the display area. Between two adjacent sub-LED display panels It also has seams and shares the fan-out area;
  • each of the display areas has a plurality of sub-pixels
  • the sub-pixels include a plurality of irregular-shaped sub-pixels arranged along the edge of the display area and a plurality of non-shaped sub-pixels respectively adjacent to the irregular-shaped sub-pixels, Each of the irregular sub-pixels is adjacent to the corresponding fan-out area.
  • the fan-out area includes a first fan-out area arranged along a first direction D1 and a second fan-out area arranged along a second direction D2;
  • the seams include first seams arranged along the first direction D1 and second seams arranged along the second direction D2, and the first direction D1 is perpendicular to the second direction D2.
  • the first fan-out area is provided with a plurality of data signal lines
  • the second fan-out area is provided with a plurality of scanning signal lines.
  • the sub-pixels adjacent to the fan-out area are all the special-shaped sub-pixels.
  • the data signal lines are arranged on the same side of the first seam, and the scan signal lines are arranged on the same side of the second seam.
  • the data signal lines are arranged on the same side of the first seam, and the scan signal lines are evenly arranged on two adjacent ones of the second seam. side.
  • the irregularly shaped sub-pixel includes a first irregularly-shaped sub-pixel and a second irregularly-shaped sub-pixel, and the first irregularly-shaped sub-pixel is connected to the first fan-out area and The second fan-out area is adjacent to each other, and the second irregular sub-pixel is adjacent to the first fan-out area or the second fan-out area.
  • some of the sub-pixels adjacent to the fan-out area are the irregular-shaped sub-pixels.
  • the data signal lines are misaligned arranged on the adjacent two sides of the first seam, and the scan signal lines are misaligned arranged on the second seam. Adjacent to both sides.
  • the LED spliced display panel provided by the embodiments of the present application has a plurality of special-shaped sub-pixels arranged at the edges of the four display areas in a repeating unit and adjacent to the corresponding fan-out areas, which effectively relieves
  • the space limitation of some pixels at key positions is further conducive to the development of LED spliced display panels towards small size and high resolution.
  • FIG. 1 is a schematic diagram of the structure of the repeating unit of the LED spliced display panel provided by the first embodiment of the application.
  • FIG. 2 is a schematic diagram of the structure of the repeating unit of the LED spliced display panel provided by the second embodiment of the application.
  • FIG. 3 is a schematic diagram of the structure of the repeating unit of the LED spliced display panel provided by the third embodiment of the application.
  • the embodiments of the present application are directed to the existing LED splicing display panels.
  • the space of some pixels at key positions is restricted, which greatly affects the development of LED splicing display panels in the direction of small size and high resolution.
  • this embodiment can solve this defect.
  • the LED splicing display panel includes at least one repeating unit 10, each repeating unit 10 includes four sub-LED display panels spliced with each other, and the display areas 11 of the four sub-LED display panels are arranged in two rows.
  • Each of the sub-LED display panels includes a display area 11 and a corresponding fan-out area 12 located on two adjacent sides of the display area 11. There are seams 13 between the two adjacent sub-LED display panels. And share the fan-out area 12.
  • the sub-pixels 111 include a plurality of irregular-shaped sub-pixels 1112 arranged at the edges of the four display regions 11 and are respectively corresponding to the irregular-shaped sub-pixels 1112.
  • the sub-pixels 111 include a plurality of adjacent non-shaped sub-pixels 1111, and each of the abnormal-shaped sub-pixels 1112 is adjacent to the corresponding fan-out area 12.
  • the display area of the abnormal-shaped sub-pixel 1112 is smaller than the display area of the non-abnormal-shaped sub-pixel 1111.
  • the fan-out area 12 includes a first fan-out area 121 arranged along the first direction D1 and a second fan-out area 122 arranged along the second direction D2;
  • the seam 13 includes The first seams 131 arranged in the first direction D1 and the second seams 132 arranged along the second direction D2, and the first direction D1 is perpendicular to the second direction D2.
  • the first fan-out area 121 is provided with a plurality of data signal lines (Data) 1211
  • the second fan-out area 122 is provided with a plurality of scanning signal lines (Gate) 1221.
  • the sub-pixels 111 adjacent to the fan-out area 12 are all the irregular-shaped sub-pixels 1112.
  • the irregularly shaped sub-pixel 1112 includes a first irregularly-shaped sub-pixel 11121 and a second irregularly-shaped sub-pixel 11122, and the first irregularly-shaped sub-pixel 11121 is respectively connected to the first fan-out area 121 and the second fan-out area 122.
  • Adjacent, the second irregular-shaped sub-pixel 11122 is adjacent to the first fan-out area 121 or the second fan-out area 122.
  • the display area of the first irregular-shaped sub-pixel 11121 is smaller than the display area of the second irregular-shaped sub-pixel 11122.
  • the data signal lines (Data) 1211 are arranged on the same side of the first seam 131, and the scan signal lines (Gate) 1221 are arranged on the same side of the second seam 132.
  • each of the sub-LED display panels further includes a base substrate, a thin film transistor layer disposed on the base substrate, and an LED light emitting layer disposed on the thin film transistor layer; the LED light emitting layer is located at the In the display area 11, the LED light-emitting layer includes a plurality of LED chips distributed in an array, and the plurality of LED chips are electrically connected to the thin film transistor layer.
  • a plurality of the special-shaped sub-pixels 1112 are arranged on the edges of the four display areas 11 in the repeating unit 10 and are adjacent to the corresponding fan-out area 12
  • the space restriction of some pixels at key positions is effectively alleviated, which is further conducive to the development of LED spliced display panels in the direction of small size and high resolution.
  • the LED splicing display panel includes at least one repeating unit 10, each repeating unit 10 includes four sub-LED display panels spliced with each other, and the display areas 11 of the four sub-LED display panels are arranged in two rows.
  • Each of the sub-LED display panels includes a display area 11 and a corresponding fan-out area 12 located on two adjacent sides of the display area 11. There are seams 13 between the two adjacent sub-LED display panels. And share the fan-out area 12.
  • the sub-pixels 111 include a plurality of irregular-shaped sub-pixels 1112 arranged at the edges of the four display regions 11 and are respectively corresponding to the irregular-shaped sub-pixels 1112.
  • the sub-pixels 111 include a plurality of adjacent non-shaped sub-pixels 1111, and each of the abnormal-shaped sub-pixels 1112 is adjacent to the corresponding fan-out area 12.
  • the display area of the abnormal-shaped sub-pixel 1112 is smaller than the display area of the non-abnormal-shaped sub-pixel 1111.
  • the fan-out area 12 includes a first fan-out area 121 arranged along the first direction D1 and a second fan-out area 122 arranged along the second direction D2;
  • the seam 13 includes The first seams 131 arranged in the first direction D1 and the second seams 132 arranged along the second direction D2, and the first direction D1 is perpendicular to the second direction D2.
  • the first fan-out area 121 is provided with a plurality of data signal lines (Data) 1211
  • the second fan-out area 122 is provided with a plurality of scanning signal lines (Gate) 1221.
  • the sub-pixels 111 adjacent to the fan-out area 12 are all the irregular-shaped sub-pixels 1112.
  • the irregularly shaped sub-pixel 1112 includes a first irregularly-shaped sub-pixel 11121 and a second irregularly-shaped sub-pixel 11122, and the first irregularly-shaped sub-pixel 11121 is respectively connected to the first fan-out area 121 and the second fan-out area 122.
  • Adjacent, the second irregular-shaped sub-pixel 11122 is adjacent to the first fan-out area 121 or the second fan-out area 122.
  • the display area of the first irregular-shaped sub-pixel 11121 is smaller than the display area of the second irregular-shaped sub-pixel 11122.
  • the data signal lines (Data) 1211 are arranged on the same side of the first seam 131, and the scan signal lines (Gate) 1221 are evenly arranged on the adjacent side of the second seam 132 On both sides.
  • each of the sub-LED display panels further includes a base substrate, a thin film transistor layer disposed on the base substrate, and an LED light emitting layer disposed on the thin film transistor layer; the LED light emitting layer is located at the In the display area 11, the LED light-emitting layer includes a plurality of LED chips distributed in an array, and the plurality of LED chips are electrically connected to the thin film transistor layer.
  • the LED spliced display panel provided by the second embodiment of the present application, on the one hand, a plurality of the special-shaped sub-pixels 1112 are arranged on the edges of the four display areas 11 in the repeating unit 10 and are connected to the corresponding fan-out areas 12
  • the scanning signal line (Gate) 1221 to a bilateral drive, the space pressure of the scanning signal line (Gate) 1221 on one side is distributed to both sides, which is similar to the first embodiment of the present application Compared with further increasing the display area of the first irregular sub-pixel 11121, the space requirement of the pixel design is further satisfied, and the LED splicing display panel is beneficial to realize the development of the LED spliced display panel in the direction of small size and high resolution.
  • the LED splicing display panel includes at least one repeating unit 10, each repeating unit 10 includes four sub-LED display panels spliced with each other, and the display areas 11 of the four sub-LED display panels are arranged in two rows.
  • Each of the sub-LED display panels includes a display area 11 and a corresponding fan-out area 12 located on two adjacent sides of the display area 11. There are seams 13 between the two adjacent sub-LED display panels. And share the fan-out area 12.
  • the sub-pixels 111 include a plurality of irregular-shaped sub-pixels 1112 arranged at the edges of the four display regions 11 and are respectively corresponding to the irregular-shaped sub-pixels 1112.
  • the sub-pixels 111 include a plurality of adjacent non-shaped sub-pixels 1111, and each of the abnormal-shaped sub-pixels 1112 is adjacent to the corresponding fan-out area 12.
  • the display area of the abnormal-shaped sub-pixel 1112 is smaller than the display area of the non-abnormal-shaped sub-pixel 1111.
  • the fan-out area 12 includes a first fan-out area 121 arranged along the first direction D1 and a second fan-out area 122 arranged along the second direction D2;
  • the seam 13 includes The first seams 131 arranged in the first direction D1 and the second seams 132 arranged along the second direction D2, and the first direction D1 is perpendicular to the second direction D2.
  • the first fan-out area 121 is provided with a plurality of data signal lines (Data) 1211
  • the second fan-out area 122 is provided with a plurality of scanning signal lines (Gate) 1221.
  • the part of the sub-pixel 111 adjacent to the fan-out area 12 is the irregular-shaped sub-pixel 1112.
  • the irregular sub-pixel 1112 is adjacent to the first fan-out area 121 or the second fan-out area 122.
  • the data signal lines (Data) 1211 are arranged in a staggered arrangement on the adjacent two sides of the first seam 131, and the scan signal lines (Gate) 1221 are arranged in a staggered arrangement on the second seam 132 On the adjacent sides.
  • each of the sub-LED display panels further includes a base substrate, a thin film transistor layer disposed on the base substrate, and an LED light emitting layer disposed on the thin film transistor layer; the LED light emitting layer is located at the In the display area 11, the LED light-emitting layer includes a plurality of LED chips distributed in an array, and the plurality of LED chips are electrically connected to the thin film transistor layer.
  • a plurality of the special-shaped sub-pixels 1112 are arranged on the edges of the four display areas 11 in the repeating unit 10 and are connected to the corresponding fan-out areas 12 Adjacent; on the other hand, by apportioning the spatial pressure of the scanning signal line (Gate) 1221 and the data signal line (Data) 1211 to both sides and staggering the distribution position of the wiring, it is the same as the second embodiment of the present application Compared with further increasing the display area of the special-shaped sub-pixel 1112 at the key position, the space requirement of pixel design is further satisfied, and the LED splicing display panel is developed to a small size and high resolution direction.
  • the LED spliced display panel provided by the embodiments of the present application has multiple special-shaped sub-pixels arranged on the edges of the four display areas in a repeating unit and adjacent to the corresponding fan-out area, which effectively relieves some
  • the space limitation of the pixel at the key position is further conducive to the development of LED spliced display panels towards small size and high resolution.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Multimedia (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
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Abstract

一种LED拼接显示面板，至少包括一个重复单元，每个所述重复单元包括四个互相拼接的子LED显示面板，每个所述子LED显示面板包括显示区及扇出区，相邻两所述子LED显示面板之间还具有拼缝并共享所述扇出区；四个所述显示区内多个子像素包括多个异形子像素以及多个非异形子像素，每一所述异形子像素与对应的所述扇出区相邻接。

Description

LED拼接显示面板 技术领域
本申请涉及显示技术领域，尤其涉及一种LED拼接显示面板。
 背景技术
目前，LED(Light Emitting Diode，LED)是显示屏是一种平板显示器，由一个个小的LED模块面板组成，用来显示文字、图像、视频、录像信号等各种信息的设备，LED显示屏的高亮度、较广的观看角度和良好的色彩还原能力也优于LCD屏（液晶显示屏），LED刷屏机一般用于机场、商场、酒店、高铁、地铁、影院、展会、写字楼等，目标客户消费能力强，具有巨大的广告价值。现有的LED显示屏在使用时需要根据具体长度进行拼接，制成LED 拼接屏。然而，LED 拼接屏正朝着尺寸更小、解析度更高的方向发展，这对单个像素空间内LED芯片的尺寸压缩、薄膜晶体管及相关走线的设计提出了挑战。尤其为了实现无缝拼接，极大地增加了像素设计的难度，很大程度影响了LED 向小尺寸、高解析方向的发展。
综上所述，现有的LED拼接显示面板，为了实现无缝拼接，导致部分像素在关键位置处的空间受限制，很大程度影响了LED拼接显示面板向小尺寸、高解析方向的发展。
 技术问题
现有的LED拼接显示面板，为了实现无缝拼接，导致部分像素在关键位置处的空间受限制，很大程度影响了LED拼接显示面板向小尺寸、高解析方向的发展。
 技术解决方案
本申请实施例提供一种LED拼接显示面板，能够缓解部分像素在关键位置处空间限制的问题，以解决现有的LED拼接显示面板，为了实现无缝拼接，导致部分像素在关键位置处的空间受限制，很大程度影响了LED拼接显示面板向小尺寸、高解析方向的发展的技术问题。
本申请实施例提供一种LED拼接显示面板，所述LED拼接显示面板至少包括一个重复单元，每个所述重复单元包括四个互相拼接的子LED显示面板，四个所述子LED显示面板的显示区排列成两行两列，每个所述子LED显示面板包括显示区及分别对应的位于所述显示区相邻两侧的扇出区，相邻两所述子LED显示面板之间还具有拼缝并共享所述扇出区；
其中，每一所述显示区内具有多个子像素，所述子像素包括沿所述显示区边缘设置的多个异形子像素以及分别与所述异形子像素相邻的多个非异形子像素，每一所述异形子像素与对应的所述扇出区相邻接；所述异形子像素的显示面积小于所述非异形子像素的显示面积。
在本申请实施例提供的LED拼接显示面板中，所述扇出区包括沿着第一方向D1排列的第一扇出区以及沿着第二方向D2排列的第二扇出区；所述拼缝包括沿着所述第一方向D1排列的第一拼缝以及沿着所述第二方向D2排列的第二拼缝，所述第一方向D1与所述第二方向D2垂直。
在本申请实施例提供的LED拼接显示面板中，所述第一扇出区设置有多条数据信号线，所述第二扇出区设置有多条扫描信号线。
在本申请实施例提供的LED拼接显示面板中，与所述扇出区相邻接的所述子像素均为所述异形子像素。
在本申请实施例提供的LED拼接显示面板中，所述数据信号线排布于所述第一拼缝的同一侧，所述扫描信号线排布于所述第二拼缝的同一侧。
在本申请实施例提供的LED拼接显示面板中，所述数据信号线排布于所述第一拼缝的同一侧，所述扫描信号线均匀排布于所述第二拼缝的相邻两侧。
在本申请实施例提供的LED拼接显示面板中，所述异形子像素包括第一异形子像素以及第二异形子像素，所述第一异形子像素分别与所述第一扇出区以及所述第二扇出区相邻接，所述第二异形子像素与所述第一扇出区或者所述第二扇出区相邻接。
在本申请实施例提供的LED拼接显示面板中，与所述扇出区相邻接的部分所述子像素为所述异形子像素。
在本申请实施例提供的LED拼接显示面板中，所述数据信号线错位排布于所述第一拼缝的相邻两侧，所述扫描信号线错位排布于所述第二拼缝的相邻两侧。
本申请实施例还提供一种LED拼接显示面板，所述LED拼接显示面板至少包括一个重复单元，每个所述重复单元包括四个互相拼接的子LED显示面板，四个所述子LED显示面板的显示区排列成两行两列，每个所述子LED显示面板包括显示区及分别对应的位于所述显示区相邻两侧的扇出区，相邻两所述子LED显示面板之间还具有拼缝并共享所述扇出区；
其中，每一所述显示区内具有多个子像素，所述子像素包括沿所述显示区边缘设置的多个异形子像素以及分别与所述异形子像素相邻的多个非异形子像素，每一所述异形子像素与对应的所述扇出区相邻接。
在本申请实施例提供的LED拼接显示面板中，所述扇出区包括沿着第一方向D1排列的第一扇出区以及沿着第二方向D2排列的第二扇出区；所述拼缝包括沿着所述第一方向D1排列的第一拼缝以及沿着所述第二方向D2排列的第二拼缝，所述第一方向D1与所述第二方向D2垂直。
在本申请实施例提供的LED拼接显示面板中，所述第一扇出区设置有多条数据信号线，所述第二扇出区设置有多条扫描信号线。
在本申请实施例提供的LED拼接显示面板中，与所述扇出区相邻接的所述子像素均为所述异形子像素。
在本申请实施例提供的LED拼接显示面板中，所述数据信号线排布于所述第一拼缝的同一侧，所述扫描信号线排布于所述第二拼缝的同一侧。
在本申请实施例提供的LED拼接显示面板中，所述数据信号线排布于所述第一拼缝的同一侧，所述扫描信号线均匀排布于所述第二拼缝的相邻两侧。
在本申请实施例提供的LED拼接显示面板中，所述异形子像素包括第一异形子像素以及第二异形子像素，所述第一异形子像素分别与所述第一扇出区以及所述第二扇出区相邻接，所述第二异形子像素与所述第一扇出区或者所述第二扇出区相邻接。
在本申请实施例提供的LED拼接显示面板中，与所述扇出区相邻接的部分所述子像素为所述异形子像素。
在本申请实施例提供的LED拼接显示面板中，所述数据信号线错位排布于所述第一拼缝的相邻两侧，所述扫描信号线错位排布于所述第二拼缝的相邻两侧。
 有益效果
相较于现有技术，本申请实施例所提供的LED拼接显示面板，通过在一个重复单元中的四个显示区边缘设置多个异形子像素并与对应的扇出区相邻接，有效缓解了部分像素在关键位置处的空间限制，进一步有利于实现LED拼接显示面板向小尺寸、高解析方向的发展。
 附图说明
图1为本申请第一实施例提供的LED拼接显示面板的重复单元的结构示意图。
图2为本申请第二实施例提供的LED拼接显示面板的重复单元的结构示意图。
图3为本申请第三实施例提供的LED拼接显示面板的重复单元的结构示意图。
 本发明的实施方式
本申请实施例针对现有的LED拼接显示面板，为了实现无缝拼接，导致部分像素在关键位置处的空间受限制，很大程度影响了LED拼接显示面板向小尺寸、高解析方向的发展的技术问题，本实施例能够解决该缺陷。
如图1所示，为本申请第一实施例提供的LED拼接显示面板的重复单元的结构示意图。其中，所述LED拼接显示面板至少包括一个重复单元10，每个所述重复单元10包括四个互相拼接的子LED显示面板，四个所述子LED显示面板的显示区11排列成两行两列，每个所述子LED显示面板包括显示区11及分别对应的位于所述显示区11相邻两侧的扇出区12，相邻两所述子LED显示面板之间还具有拼缝13并共享所述扇出区12。
具体地，四个所述显示区11内具有多个子像素111，所述子像素111包括设置在四个所述显示区11边缘的多个异形子像素1112以及分别与所述异形子像素1112相邻的多个非异形子像素1111，每一所述异形子像素1112与对应的所述扇出区12相邻接。
具体地，所述异形子像素1112的显示面积小于所述非异形子像素1111的显示面积。
具体地，所述扇出区12包括沿着第一方向D1排列的第一扇出区121以及沿着第二方向D2排列的第二扇出区122；所述拼缝13包括沿着所述第一方向D1排列的第一拼缝131以及沿着所述第二方向D2排列的第二拼缝132，所述第一方向D1与所述第二方向D2垂直。
特别地，所述第一扇出区121设置有多条数据信号线（Data）1211，所述第二扇出区122设置有多条扫描信号线(Gate)1221。
在本申请第一实施例提供的LED拼接显示面板中，与所述扇出区12相邻接的所述子像素111均为所述异形子像素1112。其中，所述异形子像素1112包括第一异形子像素11121以及第二异形子像素11122，所述第一异形子像素11121分别与所述第一扇出区121以及所述第二扇出区122相邻接，所述第二异形子像素11122与所述第一扇出区121或者所述第二扇出区122相邻接。
特别地，所述第一异形子像素11121的显示面积小于所述第二异形子像素11122的显示面积。
更进一步地，所述数据信号线（Data）1211排布于所述第一拼缝131的同一侧，所述扫描信号线(Gate)1221排布于所述第二拼缝132的同一侧。
具体地，每个所述子LED显示面板还包括衬底基板、设置在所述衬底基板上的薄膜晶体管层以及设置在所述薄膜晶体管层上的LED发光层；所述LED发光层位于所述显示区11，所述LED发光层包括多个呈阵列分布的LED芯片，多个所述LED芯片与所述薄膜晶体管层电连接。
本申请第一实施例提供的LED拼接显示面板中，通过在所述重复单元10中的四个所述显示区11边缘设置多个所述异形子像素1112并与对应的扇出区12相邻接，有效缓解了部分像素在关键位置处的空间限制，进一步有利于实现LED拼接显示面板向小尺寸、高解析方向的发展。
如图2所示，为本申请第二实施例提供的LED拼接显示面板的重复单元的结构示意图。其中，所述LED拼接显示面板至少包括一个重复单元10，每个所述重复单元10包括四个互相拼接的子LED显示面板，四个所述子LED显示面板的显示区11排列成两行两列，每个所述子LED显示面板包括显示区11及分别对应的位于所述显示区11相邻两侧的扇出区12，相邻两所述子LED显示面板之间还具有拼缝13并共享所述扇出区12。
具体地，四个所述显示区11内具有多个子像素111，所述子像素111包括设置在四个所述显示区11边缘的多个异形子像素1112以及分别与所述异形子像素1112相邻的多个非异形子像素1111，每一所述异形子像素1112与对应的所述扇出区12相邻接。
具体地，所述异形子像素1112的显示面积小于所述非异形子像素1111的显示面积。
具体地，所述扇出区12包括沿着第一方向D1排列的第一扇出区121以及沿着第二方向D2排列的第二扇出区122；所述拼缝13包括沿着所述第一方向D1排列的第一拼缝131以及沿着所述第二方向D2排列的第二拼缝132，所述第一方向D1与所述第二方向D2垂直。
特别地，所述第一扇出区121设置有多条数据信号线（Data）1211，所述第二扇出区122设置有多条扫描信号线(Gate)1221。
在本申请第二实施例提供的LED拼接显示面板中，与所述扇出区12相邻接的所述子像素111均为所述异形子像素1112。其中，所述异形子像素1112包括第一异形子像素11121以及第二异形子像素11122，所述第一异形子像素11121分别与所述第一扇出区121以及所述第二扇出区122相邻接，所述第二异形子像素11122与所述第一扇出区121或者所述第二扇出区122相邻接。
特别地，所述第一异形子像素11121的显示面积小于所述第二异形子像素11122的显示面积。
更进一步地，所述数据信号线（Data）1211排布于所述第一拼缝131的同一侧，所述扫描信号线(Gate)1221均匀排布于所述第二拼缝132的相邻两侧。
具体地，每个所述子LED显示面板还包括衬底基板、设置在所述衬底基板上的薄膜晶体管层以及设置在所述薄膜晶体管层上的LED发光层；所述LED发光层位于所述显示区11，所述LED发光层包括多个呈阵列分布的LED芯片，多个所述LED芯片与所述薄膜晶体管层电连接。
本申请第二实施例提供的LED拼接显示面板中，一方面通过在所述重复单元10中的四个所述显示区11边缘设置多个所述异形子像素1112并与对应的扇出区12相邻接；另一方面，通过将所述扫描信号线(Gate)1221改为双边驱动，使得单侧所述扫描信号线(Gate)1221的空间压力分摊到两边，与本申请第一实施例相比进一步增大了所述第一异形子像素11121的显示面积，更进一步满足了像素设计的空间需求，有利于实现LED拼接显示面板向小尺寸、高解析方向的发展。
如图3所示，为本申请第三实施例提供的LED拼接显示面板的重复单元的结构示意图。其中，所述LED拼接显示面板至少包括一个重复单元10，每个所述重复单元10包括四个互相拼接的子LED显示面板，四个所述子LED显示面板的显示区11排列成两行两列，每个所述子LED显示面板包括显示区11及分别对应的位于所述显示区11相邻两侧的扇出区12，相邻两所述子LED显示面板之间还具有拼缝13并共享所述扇出区12。
具体地，四个所述显示区11内具有多个子像素111，所述子像素111包括设置在四个所述显示区11边缘的多个异形子像素1112以及分别与所述异形子像素1112相邻的多个非异形子像素1111，每一所述异形子像素1112与对应的所述扇出区12相邻接。
具体地，所述异形子像素1112的显示面积小于所述非异形子像素1111的显示面积。
具体地，所述扇出区12包括沿着第一方向D1排列的第一扇出区121以及沿着第二方向D2排列的第二扇出区122；所述拼缝13包括沿着所述第一方向D1排列的第一拼缝131以及沿着所述第二方向D2排列的第二拼缝132，所述第一方向D1与所述第二方向D2垂直。
特别地，所述第一扇出区121设置有多条数据信号线（Data）1211，所述第二扇出区122设置有多条扫描信号线(Gate)1221。
在本申请第三实施例提供的LED拼接显示面板中，与所述扇出区12相邻接的所述子像素111部分为所述异形子像素1112。其中，所述异形子像素1112与所述第一扇出区121或者所述第二扇出区122相邻接。
更进一步地，所述数据信号线（Data）1211错位排布于所述第一拼缝131的相邻两侧，所述扫描信号线(Gate)1221错位排布于所述第二拼缝132的相邻两侧。
具体地，每个所述子LED显示面板还包括衬底基板、设置在所述衬底基板上的薄膜晶体管层以及设置在所述薄膜晶体管层上的LED发光层；所述LED发光层位于所述显示区11，所述LED发光层包括多个呈阵列分布的LED芯片，多个所述LED芯片与所述薄膜晶体管层电连接。
本申请第三实施例提供的LED拼接显示面板中，一方面通过在所述重复单元10中的四个所述显示区11边缘设置多个所述异形子像素1112并与对应的扇出区12相邻接；另一方面，通过将所述扫描信号线(Gate)1221以及所述数据信号线（Data）1211的空间压力分摊到两边并错开走线的分布位置，与本申请第二实施例相比进一步增大了关键位置处的所述异形子像素1112的显示面积，更进一步满足了像素设计的空间需求，有利于实现LED拼接显示面板向小尺寸、高解析方向的发展。
以上各个操作的具体实施可参见前面的实施例，在此不再赘述。
综上所述，本申请实施例所提供的LED拼接显示面板，通过在一个重复单元中的四个显示区边缘设置多个异形子像素并与对应的扇出区相邻接，有效缓解了部分像素在关键位置处的空间限制，进一步有利于实现LED拼接显示面板向小尺寸、高解析方向的发展。
可以理解的是，对本领域普通技术人员来说，可以根据本申请的技术方案及其发明构思加以等同替换或改变，而所有这些改变或替换都应属于本申请所附的权利要求的保护范围。

Claims (20)

  1. 一种LED拼接显示面板，其中，所述LED拼接显示面板至少包括一个重复单元，每个所述重复单元包括四个互相拼接的子LED显示面板，四个所述子LED显示面板的显示区排列成两行两列，每个所述子LED显示面板包括显示区及分别对应的位于所述显示区相邻两侧的扇出区，相邻两所述子LED显示面板之间还具有拼缝并共享所述扇出区；
    其中，四个所述显示区内具有多个子像素，所述子像素包括设置在四个所述显示区边缘的多个异形子像素以及分别与所述异形子像素相邻的多个非异形子像素，每一所述异形子像素与对应的所述扇出区相邻接；所述异形子像素的显示面积小于所述非异形子像素的显示面积。
  2. 根据权利要求1所述的LED拼接显示面板，其中，所述扇出区包括沿着第一方向D1排列的第一扇出区以及沿着第二方向D2排列的第二扇出区；所述拼缝包括沿着所述第一方向D1排列的第一拼缝以及沿着所述第二方向D2排列的第二拼缝，所述第一方向D1与所述第二方向D2垂直。
  3. 根据权利要求2所述的LED拼接显示面板，其中，所述第一扇出区设置有多条数据信号线，所述第二扇出区设置有多条扫描信号线。
  4. 根据权利要求2所述的LED拼接显示面板，其中，与所述扇出区相邻接的所述子像素均为所述异形子像素。
  5. 根据权利要求4所述的LED拼接显示面板，其中，所述数据信号线排布于所述第一拼缝的同一侧，所述扫描信号线排布于所述第二拼缝的同一侧。
  6. 根据权利要求4所述的LED拼接显示面板，其中，所述数据信号线排布于所述第一拼缝的同一侧，所述扫描信号线均匀排布于所述第二拼缝的相邻两侧。
  7. 根据权利要求5所述的LED拼接显示面板，其中，所述异形子像素包括第一异形子像素以及第二异形子像素，所述第一异形子像素分别与所述第一扇出区以及所述第二扇出区相邻接，所述第二异形子像素与所述第一扇出区或者所述第二扇出区相邻接。
  8. 根据权利要求6所述的LED拼接显示面板，其中，所述异形子像素包括第一异形子像素以及第二异形子像素，所述第一异形子像素分别与所述第一扇出区以及所述第二扇出区相邻接，所述第二异形子像素与所述第一扇出区或者所述第二扇出区相邻接。
  9. 根据权利要求2所述的LED拼接显示面板，其中，与所述扇出区相邻接的部分所述子像素为所述异形子像素。
  10. 根据权利要求9所述的LED拼接显示面板，其中，所述数据信号线错位排布于所述第一拼缝的相邻两侧，所述扫描信号线错位排布于所述第二拼缝的相邻两侧。
  11. 一种LED拼接显示面板，其中，所述LED拼接显示面板至少包括一个重复单元，每个所述重复单元包括四个互相拼接的子LED显示面板，四个所述子LED显示面板的显示区排列成两行两列，每个所述子LED显示面板包括显示区及分别对应的位于所述显示区相邻两侧的扇出区，相邻两所述子LED显示面板之间还具有拼缝并共享所述扇出区；
    其中，四个所述显示区内具有多个子像素，所述子像素包括设置在四个所述显示区边缘的多个异形子像素以及分别与所述异形子像素相邻的多个非异形子像素，每一所述异形子像素与对应的所述扇出区相邻接。
  12. 根据权利要求11所述的LED拼接显示面板，其中，所述扇出区包括沿着第一方向D1排列的第一扇出区以及沿着第二方向D2排列的第二扇出区；所述拼缝包括沿着所述第一方向D1排列的第一拼缝以及沿着所述第二方向D2排列的第二拼缝，所述第一方向D1与所述第二方向D2垂直。
  13. 根据权利要求12所述的LED拼接显示面板，其中，所述第一扇出区设置有多条数据信号线，所述第二扇出区设置有多条扫描信号线。
  14. 根据权利要求12所述的LED拼接显示面板，其中，与所述扇出区相邻接的所述子像素均为所述异形子像素。
  15. 根据权利要求14所述的LED拼接显示面板，其中，所述数据信号线排布于所述第一拼缝的同一侧，所述扫描信号线排布于所述第二拼缝的同一侧。
  16. 根据权利要求14所述的LED拼接显示面板，其中，所述数据信号线排布于所述第一拼缝的同一侧，所述扫描信号线均匀排布于所述第二拼缝的相邻两侧。
  17. 根据权利要求15所述的LED拼接显示面板，其中，所述异形子像素包括第一异形子像素以及第二异形子像素，所述第一异形子像素分别与所述第一扇出区以及所述第二扇出区相邻接，所述第二异形子像素与所述第一扇出区或者所述第二扇出区相邻接。
  18. 根据权利要求16所述的LED拼接显示面板，其中，所述异形子像素包括第一异形子像素以及第二异形子像素，所述第一异形子像素分别与所述第一扇出区以及所述第二扇出区相邻接，所述第二异形子像素与所述第一扇出区或者所述第二扇出区相邻接。
  19. 根据权利要求12所述的LED拼接显示面板，其中，与所述扇出区相邻接的部分所述子像素为所述异形子像素。
  20. 根据权利要求19所述的LED拼接显示面板，其中，所述数据信号线错位排布于所述第一拼缝的相邻两侧，所述扫描信号线错位排布于所述第二拼缝的相邻两侧。
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