WO2021212555A1 - 驱动电路及显示装置 - Google Patents

驱动电路及显示装置 Download PDF

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Publication number
WO2021212555A1
WO2021212555A1 PCT/CN2020/089392 CN2020089392W WO2021212555A1 WO 2021212555 A1 WO2021212555 A1 WO 2021212555A1 CN 2020089392 W CN2020089392 W CN 2020089392W WO 2021212555 A1 WO2021212555 A1 WO 2021212555A1
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WO
WIPO (PCT)
Prior art keywords
redundant
thin film
film transistor
driving circuit
patterned member
Prior art date
Application number
PCT/CN2020/089392
Other languages
English (en)
French (fr)
Inventor
高雅楠
彭邦银
金一坤
Original Assignee
深圳市华星光电半导体显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Priority to US16/767,769 priority Critical patent/US11443669B2/en
Publication of WO2021212555A1 publication Critical patent/WO2021212555A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0413—Details of dummy pixels or dummy lines in flat panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0876—Supplementary capacities in pixels having special driving circuits and electrodes instead of being connected to common electrode or ground; Use of additional capacitively coupled compensation electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes

Definitions

  • This application relates to the field of display technology, and in particular to a driving circuit and a display device.
  • FIG. 1 it is a schematic plan view of the connection between the pull-up unit T and the bootstrap capacitor of a conventional gate drive circuit (Gate On Array, GOA).
  • the pull-up unit T includes a plurality of thin film transistors arranged in an array and connected in series. Each thin film transistor includes a gate and a source and drain.
  • the bootstrap capacitor C includes a first electrode and a second electrode. The gates of multiple arrays of thin film transistors and the first electrodes of the bootstrap capacitors are located on the entire first metal layer M1, and the multiple arrays of thin film transistors (S, D) and the bootstrap capacitors are located on the entire first metal layer M1.
  • the second electrode 1 is located on the patterned second metal M2.
  • the second electrode 1 is a monolithic metal, the source and drain (S, D) of the thin film transistor close to the second electrode 1 and connected to the second electrode 1 There will be a problem of uneven etching, which affects the electrical performance of the pull-up unit T.
  • the purpose of the present application is to provide a driving circuit and a display device to solve the problem of uneven etching of the source and drain of the thin film transistor connected to the bootstrap capacitor in the pull-up unit in the gate driving circuit, which affects the electrical performance of the pull-up unit. problem.
  • the present application provides a driving circuit, the driving circuit includes:
  • a circuit unit the circuit unit includes a thin film transistor, and the thin film transistor includes a patterned member;
  • a capacitor connected to at least one end of the thin film transistor in the circuit unit, the capacitor including an electrode plate;
  • Redundant patterned member, the redundant patterned member, the electrode plate, and the patterned member are located on the same conductive layer, and the redundant patterned member is connected between the patterned member and the electrode plate ;
  • the preparation material of the conductive layer is selected from at least one of molybdenum, aluminum, titanium, copper, and silver.
  • the driving circuit includes a dummy thin film transistor, the dummy thin film transistor includes the redundant patterned member, the patterned member includes a source electrode and a drain, and the redundant patterned member includes a redundant patterned member.
  • the redundant source electrode and the redundant drain electrode, one end of the redundant source electrode and one end of the redundant drain electrode are connected.
  • the source and the redundant source are the same, and the drain and the redundant drain are the same.
  • the driving circuit is a gate driving circuit, and the gate driving circuit is used to output a scanning signal.
  • the circuit unit is a pull-up unit, one end of the capacitor is connected to the gate of the thin film transistor, and the other end of the capacitor is connected to the source or drain of the thin film transistor.
  • a drive circuit comprising:
  • a circuit unit the circuit unit includes a thin film transistor, and the thin film transistor includes a patterned member;
  • a capacitor connected to at least one end of the thin film transistor in the circuit unit, the capacitor including an electrode plate;
  • Redundant patterned member, the redundant patterned member, the electrode plate, and the patterned member are located on the same conductive layer, and the redundant patterned member is connected between the patterned member and the electrode plate .
  • the driving circuit includes a dummy thin film transistor, the dummy thin film transistor includes the redundant patterned member, the patterned member includes a source electrode and a drain, and the redundant patterned member includes a redundant patterned member.
  • the redundant source electrode and the redundant drain electrode, one end of the redundant source electrode and one end of the redundant drain electrode are connected.
  • the source and the redundant source are the same, and the drain and the redundant drain are the same.
  • the driving circuit is a gate driving circuit, and the gate driving circuit is used to output a scanning signal.
  • the circuit unit is a pull-up unit, one end of the capacitor is connected to the gate of the thin film transistor, and the other end of the capacitor is connected to the source or drain of the thin film transistor.
  • a display device the display device includes a drive circuit, and the drive circuit includes:
  • a circuit unit the circuit unit includes a thin film transistor, and the thin film transistor includes a patterned member;
  • a capacitor connected to at least one end of the thin film transistor in the circuit unit, the capacitor including an electrode plate;
  • Redundant patterned member, the redundant patterned member, the electrode plate, and the patterned member are located on the same conductive layer, and the redundant patterned member is connected between the patterned member and the electrode plate .
  • the driving circuit includes a dummy thin film transistor, the dummy thin film transistor includes the redundant patterning member, the patterning member includes a source electrode and a drain electrode, and the redundant patterning member includes a redundant patterning member.
  • the redundant source electrode and the redundant drain electrode, one end of the redundant source electrode and one end of the redundant drain electrode are connected.
  • the source electrode and the redundant source electrode are the same, and the drain electrode and the redundant drain electrode are the same.
  • the driving circuit is a gate driving circuit, and the gate driving circuit is used to output a scanning signal.
  • the circuit unit is a pull-up unit, one end of the capacitor is connected to the gate of the thin film transistor, and the other end of the capacitor is connected to the source or drain of the thin film transistor.
  • the present application provides a driving circuit and a display device.
  • the driving circuit includes: a circuit unit, the circuit unit includes a thin film transistor, the thin film transistor includes a patterned member; a capacitor, the capacitor is connected to at least one end of the thin film transistor in the circuit unit, and the capacitor includes An electrode plate; and a redundant patterned member, the redundant patterned member, the electrode plate and the patterned member are located on the same conductive layer, and the redundant patterned member is connected between the patterned member and the electrode plate.
  • Redundant patterning members are arranged between the patterning members constituting the thin film transistor and the electrode plates of the capacitor to avoid uneven etching of the patterning members of the thin film transistor during the patterning of the conductive layer, leading to the electrical properties of the thin film transistor of the circuit unit Affected issues.
  • FIG. 1 is a schematic plan view of a connection between a pull-up unit T and a bootstrap capacitor C of a conventional gate driving circuit;
  • FIG. 2 is a schematic diagram of a display device according to an embodiment of the application.
  • FIG. 3 is a schematic diagram of a driving circuit in the display device shown in FIG. 2;
  • FIG. 4 is a schematic plan view of the pull-up unit and the bootstrap capacitor of the gate driving circuit in FIG. 3.
  • FIG. 2 is a schematic diagram of a display device according to an embodiment of the application
  • FIG. 3 is a schematic diagram of a driving circuit in the display device shown in FIG. 2
  • FIG. 4 is a pull-up unit and a gate driving circuit in FIG. A schematic plan view of a bootstrap capacitor.
  • the display device includes a display panel 100 having a display area 100a and a non-display area 100b located at the periphery of the display area 100a.
  • the display area 100a of the display panel 100 is provided with a plurality of parallel data lines D (Dn, Dn+1, Dn+2) arranged in the row direction and a plurality of parallel scan lines S (Sn, Sn+) arranged in the column direction. 1, Sn+2), the data line D and the scan line S are perpendicular to and insulated from each other.
  • a sub-pixel is arranged between two adjacent data lines D and two adjacent scan lines S, the sub-pixels in the same row are connected to the same scan line S, the sub-pixels in the same column are connected to the same data line D, and the sub-pixels in the same column are sent
  • the color and light are the same
  • the same row of sub-pixels includes red sub-pixel R, green sub-pixel G, and blue sub-pixel B.
  • red sub-pixel R, green sub-pixel G, and blue sub-pixel B are arranged in sequence and three sub-pixels Set repeatedly in the same row as a repeating unit.
  • the non-display area 100b of the display panel 100 is provided with a driving circuit 101, and the driving circuit 101 is a gate driving circuit (Gate On Array, GOA).
  • the gate driving circuit is used to output scan signals to the scan lines S, so that a row of sub-pixels input the data signals transmitted by the data line D, and a row of sub-pixels emit light.
  • the gate drive circuit includes a multi-stage gate drive unit.
  • the gate drive circuit is described below by taking the nth stage gate drive unit outputting the scan signal G(n) as an example, and the clock signal corresponding to the gate drive circuit is Twelve clock signals CK1-CK12. It is understandable that the clock signals corresponding to the gate driving circuit may also be 4 clock signals CK1-CK4 or 8 clock signals CK1-CK8.
  • the driving circuit 101 includes a pull-up control unit 1011, a pull-up unit 1012, a pull-down unit 1013, a downstream unit 1014, a capacitor C, and a pull-down maintaining unit 1015.
  • the pull-up control unit 1011 is coupled to the pull-up node Q(n), and is configured to output a pull-up control signal to the pull-up node Q(n) according to the n-6th stage of the downstream signal ST(n-6).
  • the pull-up control unit 1011 includes a first thin film transistor T11.
  • the control terminal and the first terminal of the first thin film transistor T11 are connected to the n-6th stage downstream signal input terminal ST(n-6), and the second terminal is connected to Pull node Q(n).
  • the pull-up unit 1012 is coupled to the pull-up node Q(n), and is used for outputting the nth level scan signal according to the clock signal and the pull-up control signal.
  • the pull-up unit 1012 includes a second thin film transistor T21, the control terminal of the second thin film transistor T21 is connected to the pull-up node Q(n), the first terminal is connected to the clock signal input terminal CK, and the second terminal is connected to the nth stage scan signal The output terminal G(n).
  • the pull-down unit 1013 coupled to the pull-up node Q(n) and the pull-up unit 1012, is used to input the first DC low-level signal to the pull-up node Q(n) according to the n+8th level scan signal, and according to the The n+6 level scan signal inputs the second DC low level signal to the nth level scan signal output terminal G(n).
  • the pull-down unit 1013 includes a third thin film transistor T31 and a fourth thin film transistor T41.
  • the control terminal of the third thin film transistor T31 is connected to the n+6th stage scanning signal input terminal G (n+6), the first terminal is connected to the second DC low-level signal line VSSG, and the second terminal is connected to the nth stage scanning signal output terminal G(n).
  • the control terminal of the fourth thin film transistor T41 is connected to the n+8th level scan signal input terminal G(n+8), the first terminal is connected to the first DC low-level signal line VSSQ, and the second terminal is connected to the pull-up node Q(n ).
  • the downstream unit 1014 is coupled to the pull-up node Q(n), and is used for outputting the nth-level downstream signal according to the clock signal and the pull-up control signal.
  • the downstream unit 1014 includes a fifth thin film transistor T22, the control terminal of the fifth thin film transistor T22 is connected to the pull-up node Q(n), the first terminal is connected to the clock signal input terminal CK, and the second terminal is connected to the nth stage downstream The signal output terminal ST(n).
  • the capacitor C is coupled to the pull-up node Q(n) and the pull-up unit 1012 for raising the potential of the pull-up node Q(n).
  • one end of the capacitor C is connected to the pull-up node Q(n), and the other end is connected to the n-th scan signal output terminal G(n), that is, both ends of the capacitor C are respectively connected to the gate of the second thin film transistor T21 and the second end.
  • the coupling effect of the capacitor C causes the potential of the pull-up node Q(n) to rise.
  • the pull-down sustaining unit 1015 is coupled to the pull-up node Q(n), and is configured to maintain the potential of the pull-up node Q(n) according to the potential of the pull-up node Q(n).
  • the pull-down maintaining unit 1015 includes a first pull-down maintaining unit 10151 and a second pull-down maintaining unit 10152.
  • the first pull-down sustain unit 10151 includes a sixth thin film transistor T51, a seventh thin film transistor T52, an eighth thin film transistor T53, a ninth thin film transistor T54, a tenth thin film transistor T42, and an eleventh thin film transistor T32.
  • the control terminal and the first terminal of the sixth thin film transistor T51 are connected to the first low-frequency clock signal input terminal LC1, and the second terminal is connected to the control terminal of the eighth thin film transistor T53 and the second terminal of the seventh thin film transistor T52.
  • the control terminal of the seventh thin film transistor T52 is connected to the pull-up node Q(n), the first terminal is connected to the first DC low-level signal line VSSQ, and the second terminal is connected to the control terminal of the eighth thin film transistor T53 and the sixth thin film transistor T51 The second end.
  • the control end of the eighth thin film transistor T53 is connected to the second end of the sixth thin film transistor T51 and the second end of the seventh thin film transistor T52, the first end is connected to the first low-frequency clock signal input terminal LC1, and the second end is connected to the tenth thin film transistor
  • the control terminal of T42 and the second terminal of the ninth thin film transistor T54 is connected to the pull-up node Q(n)
  • the first terminal is connected to the first DC low-level signal line VSSQ
  • the second terminal is connected to the control terminal of the eighth thin film transistor T53 and the sixth thin film transistor T51 The second end.
  • the control end of the eighth thin film transistor T53 is connected to the second end of the sixth thin film transistor T51
  • the control end of the ninth thin film transistor T54 is connected to the pull-up node Q(n), the first end is connected to the first DC low-level signal line VSSQ, and the second end is connected to the second end of the eighth thin film transistor T53 and the tenth thin film transistor Control terminal of T42.
  • the control end of the tenth thin film transistor T42 is connected to the second end of the eighth thin film transistor T53 and the second end of the ninth thin film transistor T54, the first end is connected to the first DC low-level signal line VSSQ, and the second end is connected to the pull-up Node Q(n).
  • the control end of the eleventh thin film transistor T32 is connected to the second end of the eighth thin film transistor T53 and the second end of the ninth thin film transistor T54, the first end is connected to the second DC low-level signal line VSSG, and the second end is connected to the nth Level scanning signal output terminal G(n).
  • the second pull-down sustain unit 10152 includes a twelfth thin film transistor T61, a thirteenth thin film transistor T62, a fourteenth thin film transistor T63, a fifteenth thin film transistor T64, a sixteenth thin film transistor T43, and a seventeenth thin film transistor T33.
  • the control terminal and the first terminal of the twelfth thin film transistor T61 are connected to the second low-frequency clock signal input terminal LC2, and the second terminal is connected to the control terminal of the fourteenth thin film transistor T63 and the second terminal of the thirteenth thin film transistor T62.
  • the control end of the thirteenth thin film transistor T62 is connected to the pull-up node Q(n), the first end is connected to the first DC low-level signal line VSSQ, and the second end is connected to the control end of the fourteenth thin film transistor T63 and the twelfth The second end of the thin film transistor T61.
  • the control end of the fourteenth thin film transistor T63 is connected to the second end of the twelfth thin film transistor T61 and the second end of the thirteenth thin film transistor T62, the first end is connected to the second low frequency clock signal input terminal LC2, and the second end is connected to the second end The second terminal of the fifteenth thin film transistor T64 and the control terminal of the sixteenth thin film transistor T43.
  • the control end of the fifteenth thin film transistor T64 is connected to the pull-up node Q(n), the first end is connected to the first DC low-level signal line VSSQ, and the second end is connected to the control end of the sixteenth thin film transistor T43 and the fourteenth The second end of the thin film transistor T63.
  • the control end of the sixteenth thin film transistor T43 is connected to the second end of the fourteenth thin film transistor T63 and the second end of the fifteenth thin film transistor T64, the first end is connected to the first DC low-level signal line VSSQ, and the second end Connect the pull-up node Q(n).
  • the control end of the seventeenth thin film transistor T33 is connected to the second end of the fourteenth thin film transistor T63 and the second end of the fifteenth thin film transistor T64, the first end is connected to the second DC low-level signal line VSSG, and the second end is connected The nth level scan signal output terminal G(n).
  • the second thin film transistor T21 needs a greater driving capability.
  • a plurality of sub thin film transistors are connected in series and arrayed to form the channel width W/channel length
  • One end of the capacitor C is connected to the gate of the second thin film transistor T21, and the other end of the capacitor C is connected to the source or drain of the second thin film transistor T21.
  • the capacitor C includes a first electrode plate 201 and a second electrode plate 202.
  • the second thin film transistor T21 includes a patterned member 30.
  • the patterned member 30 includes a source 302 and a drain 301.
  • One source 302 corresponds to one drain 301, and multiple sources 302 and multiple drains 301 are arranged in an array.
  • the drain 301 is strip-shaped, and the source 302 is U-shaped.
  • the driving circuit further includes a redundant patterning member 40.
  • the first electrode plate 201 of the capacitor C, the redundant patterning member 40 and the patterning member 30 are located in the same conductive layer.
  • the preparation material of the conductive layer is selected from at least one of molybdenum, aluminum, titanium, copper, and silver.
  • the patterned member 30 of the second thin film transistor T21 needs to be etched by the traditional yellow light process, since the redundant patterned member 40 to be etched next to the patterned member 30, the yellow light process is used for photoresist The concentration of the developing solution used for development will not change, and will not cause the subsequent over-etching or under-etching of the patterned member 30.
  • the driving circuit also includes a dummy thin film transistor.
  • the dummy thin film transistor includes a redundant patterned member 40.
  • the redundant patterned member 40 includes a redundant source 402 and a redundant drain 401. One end of the redundant source 402 and the redundant One end of the remaining drain electrode 401 is connected so that the redundant patterned member 40 is equivalent to the electrode plate of the capacitor C.
  • the first electrode plate 201 is a whole piece
  • the concentration of the developer will change, resulting in the redundant patterned member 40 being unable to Etching into a designed pattern and connecting the redundant source and redundant drain can prevent the dummy thin film transistor from becoming a part of the second thin film transistor T21, and prevent the poor electrical properties of the virtual thin film crystal from causing poor electrical properties of the second thin film transistor T21.
  • designing virtual thin film transistors is more conducive to simplifying the manufacturing process.
  • the second thin film transistor T21 also includes a gate.
  • the gates of the plurality of sub thin film transistors and the second electrode plate 202 of the capacitor C are another conductive layer on the entire surface.
  • the conductive layer and the source and drain electrodes of the plurality of sub thin film transistors are located Insulate between the conductive layers.
  • the preparation material of the other conductive layer is selected from at least one of molybdenum, aluminum, titanium, copper, and silver.
  • the source 302 and the redundant source 402 are the same, the drain 301 and the redundant drain 401 are the same, that is, the shape and size of the source 302 and the redundant source 402 are the same, and the shapes and sizes of the drain 301 and the redundant drain 401 are the same.
  • the same size on the one hand, adapts to the limitation of etching accuracy, on the other hand, makes the area of the redundant patterned member 40 large enough to form the electrode plate of the capacitor C, thereby increasing the capacitance value of the capacitor C.
  • the present application also provides a driving circuit, which includes:
  • a circuit unit the circuit unit includes a thin film transistor, and the thin film transistor includes a patterned member;
  • a capacitor the capacitor is connected to at least one end of the thin film transistor in the circuit unit, the capacitor includes an electrode plate;
  • the redundant patterned member, the redundant patterned member, the electrode plate and the patterned member are located on the same conductive layer, and the redundant patterned member is connected between the patterned member and the electrode plate.
  • the driving circuit includes a dummy thin film transistor, the dummy thin film transistor includes a redundant patterned member, the patterned member includes a source electrode and a drain electrode, and the redundant patterned member includes a redundant source electrode and a redundant drain electrode. One end of the redundant source electrode and One end of the redundant drain is connected. The source and the redundant source are the same, and the drain and the redundant drain are the same.
  • the driving circuit is a gate driving circuit, and the gate driving circuit is used to output scanning signals.
  • the circuit unit is a pull-up unit, one end of the capacitor is connected to the gate of the thin film transistor, and the other end of the capacitor is connected to the source or drain of the thin film transistor.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种驱动电路（101）及显示装置，驱动电路（101）包括：电路单元，电路单元包括一个薄膜晶体管（T21），薄膜晶体管（T21）包括图案化构件（30）；电容器（C），与电路单元中的薄膜晶体管（T21）的至少一端连接，电容器（C）包括一个电极板（201）；以及冗余图案化构件（40），冗余图案化构件（40）、电极板（201）以及图案化构件（30）位于同一导电层，冗余图案化构件（40）连接于图案化构件（30）和电极板（201）之间。该电路避免了过度蚀刻或蚀刻不足的问题，保证了电路性能。

Description

驱动电路及显示装置 技术领域
本申请涉及显示技术领域，尤其涉及一种驱动电路及显示装置。
 背景技术
如图1所示，其为传统栅极驱动电路（Gate On Array，GOA）的上拉单元T以及自举电容相连的平面示意图。上拉单元T包括多个阵列排布且串接的薄膜晶体管，每个薄膜晶体管包括栅极以及源漏极，自举电容C包括第一电极和第二电极。多个阵列排布薄膜晶体管的栅极以及自举电容的第一电极位于整块的第一金属层M1上，多个阵列排布薄膜晶体管的源漏极（S，D）与自举电容的第二电极1是位于图案化第二金属M2上，由于第二电极1为整块的金属，导致靠近第二电极1且与第二电极1连接的薄膜晶体管的源漏极(S，D)会存在刻蚀不均的问题，影响上拉单元T的电性能。
因此，有必要提出一种技术方案以解决上拉单元T中与自举电容的第二电极1相连的薄膜晶体管的源漏极(S，D)蚀刻不均导致上拉单元T的电性能受影响的问题。
 技术问题
本申请的目的在于提供一种驱动电路及显示装置，以解决栅极驱动电路中上拉单元中与自举电容相连的薄膜晶体管的源漏极蚀刻不均导致上拉单元的电性能受影响的问题。
 技术解决方案
为实现上述目的，本申请提供一种驱动电路，所述驱动电路包括：
电路单元，所述电路单元包括一个薄膜晶体管，所述薄膜晶体管包括图案化构件；
一电容器，所述电容器与所述电路单元中的所述薄膜晶体管的至少一端连接，所述电容器包括一个电极板；以及
冗余图案化构件，所述冗余图案化构件、所述电极板以及所述图案化构件位于同一导电层，所述冗余图案化构件连接于所述图案化构件和所述电极板之间；
所述导电层的制备材料选自钼、铝、钛、铜以及银中的至少一种。
在上述驱动电路中，所述驱动电路包括虚拟薄膜晶体管，所述虚拟薄膜晶体管包括所述冗余图案化构件，所述图案化构件包括源极以及漏极，所述冗余图案化构件包括冗余源极以及冗余漏极，所述冗余源极的一端和所述冗余漏极的一端连接。
在上述驱动电路中，所述源极和所述冗余源极相同，所述漏极和所述冗余漏极相同。
在上述驱动电路中，所述驱动电路为栅极驱动电路，所述栅极驱动电路用于输出扫描信号。
在上述驱动电路中，所述电路单元为上拉单元，所述电容器的一端与所述薄膜晶体管的栅极连接，所述电容器的另一端与所述薄膜晶体管的源极或漏极连接。
一种驱动电路，所述驱动电路包括：
电路单元，所述电路单元包括一个薄膜晶体管，所述薄膜晶体管包括图案化构件；
一电容器，所述电容器与所述电路单元中的所述薄膜晶体管的至少一端连接，所述电容器包括一个电极板；以及
冗余图案化构件，所述冗余图案化构件、所述电极板以及所述图案化构件位于同一导电层，所述冗余图案化构件连接于所述图案化构件和所述电极板之间。
在上述驱动电路中，所述驱动电路包括虚拟薄膜晶体管，所述虚拟薄膜晶体管包括所述冗余图案化构件，所述图案化构件包括源极以及漏极，所述冗余图案化构件包括冗余源极以及冗余漏极，所述冗余源极的一端和所述冗余漏极的一端连接。
在上述驱动电路中，所述源极和所述冗余源极相同，所述漏极和所述冗余漏极相同。
在上述驱动电路中，所述驱动电路为栅极驱动电路，所述栅极驱动电路用于输出扫描信号。
在上述驱动电路中，所述电路单元为上拉单元，所述电容器的一端与所述薄膜晶体管的栅极连接，所述电容器的另一端与所述薄膜晶体管的源极或漏极连接。
一种显示装置，所述显示装置包括驱动电路，所述驱动电路包括：
电路单元，所述电路单元包括一个薄膜晶体管，所述薄膜晶体管包括图案化构件；
一电容器，所述电容器与所述电路单元中的所述薄膜晶体管的至少一端连接，所述电容器包括一个电极板；以及
冗余图案化构件，所述冗余图案化构件、所述电极板以及所述图案化构件位于同一导电层，所述冗余图案化构件连接于所述图案化构件和所述电极板之间。
在上述显示装置中，所述驱动电路包括虚拟薄膜晶体管，所述虚拟薄膜晶体管包括所述冗余图案化构件，所述图案化构件包括源极以及漏极，所述冗余图案化构件包括冗余源极以及冗余漏极，所述冗余源极的一端和所述冗余漏极的一端连接。
在上述显示装置中，所述源极和所述冗余源极相同，所述漏极和所述冗余漏极相同。
在上述显示装置中，所述驱动电路为栅极驱动电路，所述栅极驱动电路用于输出扫描信号。
在上述显示装置中，所述电路单元为上拉单元，所述电容器的一端与所述薄膜晶体管的栅极连接，所述电容器的另一端与所述薄膜晶体管的源极或漏极连接。
 有益效果
本申请提供一种驱动电路及显示装置，驱动电路包括：电路单元，电路单元包括一个薄膜晶体管，薄膜晶体管包括图案化构件；一电容器，电容器与电路单元中的薄膜晶体管的至少一端连接，电容器包括一个电极板；以及冗余图案化构件，冗余图案化构件、电极板以及图案化构件位于同一导电层，冗余图案化构件连接于图案化构件和电极板之间。通过在组成薄膜晶体管的图案化构件和电容器的电极板之间设置冗余图案化构件，以避免图案化导电层过程中薄膜晶体管的图案化构件出现蚀刻不均导致电路单元的薄膜晶体管的电性受影响的问题。
 附图说明
图1为传统栅极驱动电路的上拉单元T以及自举电容C相连的平面示意图；
图2为本申请实施例显示装置的示意图；
图3为图2所示显示装置中驱动电路的示意图；
图4为图3中栅极驱动电路的上拉单元以及自举电容器的平面示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
请参阅图2-图4，图2为本申请实施例显示装置的示意图，图3为图2所示显示装置中驱动电路的示意图，图4为图3中栅极驱动电路的上拉单元以及自举电容器的平面示意图。
显示装置包括显示面板100，显示面板100具有显示区100a和位于显示区100a外围的非显示区100b。
显示面板100的显示区100a设置有多条平行且沿行方向排列的数据线D（Dn，Dn+1，Dn+2）以及多条平行且沿列方向排列的扫描线S(Sn，Sn+1，Sn+2)，数据线D与扫描线S相互垂直且绝缘。相邻两条数据线D以及相邻两条扫描线S之间设置有一个子像素，同一行子像素与同一条扫描线S连接，同一列子像素与同一条数据线D连接，同一列子像素发出的色光相同，同一行子像素包括红色子像素R、绿色子像素G以及蓝色子像素B，同一行中，红色子像素R、绿色子像素G以及蓝色子像素B依次设置且三个子像素作为一个重复单元在同一行重复设置。
显示面板100的非显示区100b设置有驱动电路101，驱动电路101为栅极驱动电路（Gate On Array，GOA）。栅极驱动电路用于输出扫描信号至扫描线S，以使一行子像素输入数据线D传输的数据信号，一行子像素发光。
栅极驱动电路包括多级栅极驱动单元，以下以输出扫描信号G(n)的第n级栅极驱动单元为例对栅极驱动电路进行描述，且该栅极驱动电路对应的时钟信号为12个时钟信号CK1-CK12。可以理解的是，栅极驱动电路对应的时钟信号也可以为4个时钟信号CK1-CK4或8个时钟信号CK1-CK8。
驱动电路101包括上拉控制单元1011、上拉单元1012、下拉单元1013、下传单元1014、电容器C以及下拉维持单元1015。
上拉控制单元1011，耦接上拉节点Q(n)，用于根据第n-6级下传信号ST(n-6)输出上拉控制信号至上拉节点Q(n)。
具体地，上拉控制单元1011包括第一薄膜晶体管T11，第一薄膜晶体管T11的控制端以及第一端连接第n-6级下传信号输入端ST（n-6），第二端连接上拉节点Q(n)。
上拉单元1012，耦接上拉节点Q(n)，用于根据时钟信号以及上拉控制信号输出第n级扫描信号。
具体地，上拉单元1012包括第二薄膜晶体管T21，第二薄膜晶体管T21的控制端连接上拉节点Q（n），第一端连接时钟信号输入端CK，第二端连接第n级扫描信号输出端G（n）。
下拉单元1013，耦接上拉节点Q(n)以及上拉单元1012，用于根据第n+8级扫描信号将第一直流低电平信号输入至上拉节点Q(n)，且根据第n+6级扫描信号将第二直流低电平信号输入至第n级扫描信号输出端G（n）。
具体地，下拉单元1013包括第三薄膜晶体管T31以及第四薄膜晶体管T41。第三薄膜晶体管T31的控制端连接第n+6级扫描信号输入端G（n+6），第一端连接第二直流低电平信号线VSSG，第二端连接第n级扫描信号输出端G（n）。第四薄膜晶体管T41的控制端连接第n+8级扫描信号输入端G（n+8），第一端连接第一直流低电平信号线VSSQ，第二端连接上拉节点Q(n)。
下传单元1014，耦接上拉节点Q(n)，用于根据时钟信号以及上拉控制信号输出第n级下传信号。
具体地，下传单元1014包括第五薄膜晶体管T22，第五薄膜晶体管T22的控制端连接上拉节点Q(n)，第一端连接时钟信号输入端CK，第二端连接第n级下传信号输出端ST（n）。
电容器C，耦接上拉节点Q(n)和上拉单元1012，用于抬升上拉节点Q(n)的电位。
具体地，电容器C的一端连接上拉节点Q(n)，另一端连接第n级扫描信号输出端G（n），即电容器C的两端分别连接第二薄膜晶体管T21的栅极以及第二端。第n级扫描信号输出端G（n）输出的第n级扫描信号为高电平时，电容器C的耦合作用使得上拉节点Q(n)的电位抬升。
下拉维持单元1015，耦接上拉节点Q(n)，用于根据上拉节点Q(n)的电位维持上拉节点Q(n)的电位。下拉维持单元1015包括第一下拉维持单元10151和第二下拉维持单元10152。
具体地，第一下拉维持单元10151包括第六薄膜晶体管T51、第七薄膜晶体管T52、第八薄膜晶体管T53、第九薄膜晶体管T54、第十薄膜晶体管T42、第十一薄膜晶体管T32。第六薄膜晶体管T51的控制端以及第一端连接第一低频时钟信号输入端LC1，第二端连接第八薄膜晶体管T53的控制端以及第七薄膜晶体管T52的第二端。第七薄膜晶体管T52的控制端连接上拉节点Q(n)，第一端连接第一直流低电平信号线VSSQ，第二端连接第八薄膜晶体管T53的控制端以及第六薄膜晶体管T51的第二端。第八薄膜晶体管T53的控制端连接第六薄膜晶体管T51的第二端以及第七薄膜晶体管T52的第二端，第一端连接第一低频时钟信号输入端LC1，第二端连接第十薄膜晶体管T42的控制端以及第九薄膜晶体管T54的第二端。第九薄膜晶体管T54的控制端连接上拉节点Q(n)，第一端连接第一直流低电平信号线VSSQ，第二端连接第八薄膜晶体管T53的第二端以及第十薄膜晶体管T42的控制端。第十薄膜晶体管T42的控制端连接第八薄膜晶体管T53的第二端以及第九薄膜晶体管T54的第二端，第一端连接第一直流低电平信号线VSSQ，第二端连接上拉节点Q(n)。第十一薄膜晶体管T32的控制端连接第八薄膜晶体管T53的第二端以及第九薄膜晶体管T54的第二端，第一端连接第二直流低电平信号线VSSG，第二端连接第n级扫描信号输出端G（n）。
第二下拉维持单元10152包括第十二薄膜晶体管T61、第十三薄膜晶体管T62、第十四薄膜晶体管T63、第十五薄膜晶体管T64、第十六薄膜晶体管T43、第十七薄膜晶体管T33。第十二薄膜晶体管T61的控制端以及第一端连接第二低频时钟信号输入端LC2，第二端连接第十四薄膜晶体管T63的控制端以及第十三薄膜晶体管T62的第二端。第十三薄膜晶体管T62的控制端连接上拉节点Q(n)，第一端连接第一直流低电平信号线VSSQ，第二端连接第十四薄膜晶体管T63的控制端以及第十二薄膜晶体管T61的第二端。第十四薄膜晶体管T63的控制端连接第十二薄膜晶体管T61的第二端以及第十三薄膜晶体管T62的第二端，第一端连接第二低频时钟信号输入端LC2，第二端连接第十五薄膜晶体管T64的第二端以及第十六薄膜晶体管T43的控制端。第十五薄膜晶体管T64的控制端连接上拉节点Q(n)，第一端连接第一直流低电平信号线VSSQ，第二端连接第十六薄膜晶体管T43的控制端以及第十四薄膜晶体管T63的第二端。第十六薄膜晶体管T43的控制端连接第十四薄膜晶体管T63的第二端以及第十五薄膜晶体管T64的第二端，第一端连接第一直流低电平信号线VSSQ，第二端连接上拉节点Q(n)。第十七薄膜晶体管T33的控制端连接第十四薄膜晶体管T63的第二端以及第十五薄膜晶体管T64的第二端，第一端连接第二直流低电平信号线VSSG，第二端连接第n级扫描信号输出端G（n）。
对于高解析度的显示装置，第二薄膜晶体管T21需要较大的驱动能力，在第二薄膜晶体管T21的布设时，利用多个子薄膜晶体管串接且阵列的方式形成沟道宽度W/沟道长度L较大的第二薄膜晶体管T21。电容器C的一端和第二薄膜晶体管T21的栅极连接，电容器C的另一端与第二薄膜晶体管T21的源极或漏极连接。电容器C包括第一电极板201以及第二电极板202。
第二薄膜晶体管T21包括图案化构件30，图案化构件30包括源极302以及漏极301，一个源极302对应一个漏极301，多个源极302以及多个漏极301阵列排布。漏极301呈条状，源极302呈U型。驱动电路还包括冗余图案化构件40，电容器C的第一电极板201、冗余图案化构件40以及图案化构件30位于同一导电层。导电层的制备材料选自钼、铝、钛、铜以及银中的至少一种。如此，在需要传统黄光制程蚀刻出第二薄膜晶体管T21的图案化构件30时，由于图案化构件30旁待蚀刻出的是冗余图案化构件40，故黄光制程中用于对光阻进行显影的显影液的浓度不会变化，不会导致图案化构件30后续出现过度蚀刻或蚀刻不足的问题。
驱动电路还包括虚拟（dummy）薄膜晶体管，虚拟薄膜晶体管包括冗余图案化构件40，冗余图案化构件40包括冗余源极402以及冗余漏极401，冗余源极402的一端和冗余漏极401的一端连接，以使得冗余图案化构件40等效于电容器C的电极板，由于冗余图案化构件40与第一电极板201之间连接，第一电极板201为整块的导电层，在利用传统黄光制程蚀刻出冗余图案化构件40的过程中，由于待蚀刻出的是整块的导电层，显影液的浓度会变化，导致冗余图案化构件40可能无法蚀刻成设计的图案，连接冗余源极以及冗余漏极可以避免虚拟薄膜晶体管成为第二薄膜晶体管T21的一部分，避免虚拟薄膜晶体的电性不良导致第二薄膜晶体管T21的电性不良。且设计虚拟薄膜晶体管更利于简化制程。
第二薄膜晶体管T21还包括栅极，多个子薄膜晶体管的栅极以及电容器C的第二电极板202为整面的另一导电层，该导电层和多个子薄膜晶体管的源极以及漏极所在的导电层之间绝缘。另一导电层的制备材料选自钼、铝、钛、铜以及银中的至少一种。
源极302和冗余源极402相同，漏极301和冗余漏极401相同，即源极302和冗余源极402的形状和尺寸相同，漏极301和冗余漏极401的形状和尺寸相同，一方面适应蚀刻精度的限制，另一方面使得冗余图案化构件40的面积够大以形成电容器C的电极板，提高电容器C的电容值。
本申请还提供一种驱动电路，驱动电路包括：
电路单元，电路单元包括一个薄膜晶体管，薄膜晶体管包括图案化构件；
一电容器，电容器与电路单元中的薄膜晶体管的至少一端连接，电容器包括一个电极板；以及
冗余图案化构件，冗余图案化构件、电极板以及图案化构件位于同一导电层，冗余图案化构件连接于图案化构件和电极板之间。
驱动电路包括虚拟薄膜晶体管，虚拟薄膜晶体管包括冗余图案化构件，图案化构件包括源极以及漏极，冗余图案化构件包括冗余源极以及冗余漏极，冗余源极的一端和冗余漏极的一端连接。源极和冗余源极相同，漏极和冗余漏极相同。
驱动电路为栅极驱动电路，栅极驱动电路用于输出扫描信号。电路单元为上拉单元，电容器的一端与薄膜晶体管的栅极连接，电容器的另一端与薄膜晶体管的源极或漏极连接。

Claims (15)

  1. 一种驱动电路，其中，所述驱动电路包括：
    电路单元，所述电路单元包括一个薄膜晶体管，所述薄膜晶体管包括图案化构件；
    一电容器，所述电容器与所述电路单元中的所述薄膜晶体管的至少一端连接，所述电容器包括一个电极板；以及
    冗余图案化构件，所述冗余图案化构件、所述电极板以及所述图案化构件位于同一导电层，所述冗余图案化构件连接于所述图案化构件和所述电极板之间；
    所述导电层的制备材料选自钼、铝、钛、铜以及银中的至少一种。
  2. 根据权利要求1所述的驱动电路，其中，所述驱动电路包括虚拟薄膜晶体管，所述虚拟薄膜晶体管包括所述冗余图案化构件，所述图案化构件包括源极以及漏极，所述冗余图案化构件包括冗余源极以及冗余漏极，所述冗余源极的一端和所述冗余漏极的一端连接。
  3. 根据权利要求2所述的驱动电路，其中，所述源极和所述冗余源极相同，所述漏极和所述冗余漏极相同。
  4. 根据权利要求1所述的驱动电路，其中，所述驱动电路为栅极驱动电路，所述栅极驱动电路用于输出扫描信号。
  5. 根据权利要求4所述的驱动电路，其中，所述电路单元为上拉单元，所述电容器的一端与所述薄膜晶体管的栅极连接，所述电容器的另一端与所述薄膜晶体管的源极或漏极连接。
  6. 一种驱动电路，其中，所述驱动电路包括：
    电路单元，所述电路单元包括一个薄膜晶体管，所述薄膜晶体管包括图案化构件；
    一电容器，所述电容器与所述电路单元中的所述薄膜晶体管的至少一端连接，所述电容器包括一个电极板；以及
    冗余图案化构件，所述冗余图案化构件、所述电极板以及所述图案化构件位于同一导电层，所述冗余图案化构件连接于所述图案化构件和所述电极板之间。
  7. 根据权利要求6所述的驱动电路，其中，所述驱动电路包括虚拟薄膜晶体管，所述虚拟薄膜晶体管包括所述冗余图案化构件，所述图案化构件包括源极以及漏极，所述冗余图案化构件包括冗余源极以及冗余漏极，所述冗余源极的一端和所述冗余漏极的一端连接。
  8. 根据权利要求7所述的驱动电路，其中，所述源极和所述冗余源极相同，所述漏极和所述冗余漏极相同。
  9. 根据权利要求6所述的驱动电路，其中，所述驱动电路为栅极驱动电路，所述栅极驱动电路用于输出扫描信号。
  10. 根据权利要求9所述的驱动电路，其中，所述电路单元为上拉单元，所述电容器的一端与所述薄膜晶体管的栅极连接，所述电容器的另一端与所述薄膜晶体管的源极或漏极连接。
  11. 一种显示装置，其中，所述显示装置包括驱动电路，所述驱动电路包括：
    电路单元，所述电路单元包括一个薄膜晶体管，所述薄膜晶体管包括图案化构件；
    一电容器，所述电容器与所述电路单元中的所述薄膜晶体管的至少一端连接，所述电容器包括一个电极板；以及
    冗余图案化构件，所述冗余图案化构件、所述电极板以及所述图案化构件位于同一导电层，所述冗余图案化构件连接于所述图案化构件和所述电极板之间。
  12. 根据权利要求11所述的显示装置，其中，所述驱动电路包括虚拟薄膜晶体管，所述虚拟薄膜晶体管包括所述冗余图案化构件，所述图案化构件包括源极以及漏极，所述冗余图案化构件包括冗余源极以及冗余漏极，所述冗余源极的一端和所述冗余漏极的一端连接。
  13. 根据权利要求12所述的显示装置，其中，所述源极和所述冗余源极相同，所述漏极和所述冗余漏极相同。
  14. 根据权利要求11所述的显示装置，其中，所述驱动电路为栅极驱动电路，所述栅极驱动电路用于输出扫描信号。
  15. 根据权利要求14所述的显示装置，其中，所述电路单元为上拉单元，所述电容器的一端与所述薄膜晶体管的栅极连接，所述电容器的另一端与所述薄膜晶体管的源极或漏极连接。
PCT/CN2020/089392 2020-04-23 2020-05-09 驱动电路及显示装置 WO2021212555A1 (zh)

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