WO2021208855A1 - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

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Publication number
WO2021208855A1
WO2021208855A1 PCT/CN2021/086620 CN2021086620W WO2021208855A1 WO 2021208855 A1 WO2021208855 A1 WO 2021208855A1 CN 2021086620 W CN2021086620 W CN 2021086620W WO 2021208855 A1 WO2021208855 A1 WO 2021208855A1
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hole
forming
layer
semiconductor structure
semiconductor substrate
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French (fr)
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张志伟
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to US17/599,413 priority Critical patent/US11581219B2/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/73—Etching of wafers, substrates or parts of devices using masks for insulating materials
    • H—ELECTRICITY
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/60—Wet etching
    • H10P50/64—Wet etching of semiconductor materials
    • H10P50/642—Chemical etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0245—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising use of blind vias during the manufacture
    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0249—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias wherein the through-semiconductor via protrudes from backsides of the chips, wafers or substrates during the manufacture
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/041—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being discontinuous
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/072—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising air gaps
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
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    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/43—Layouts of interconnections
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    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/46—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts comprising air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/481—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes on the rear surfaces of the wafers or substrates
    • H—ELECTRICITY
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/089—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning
    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H10W72/01908—Manufacture or treatment of bond pads using permanent auxiliary members, e.g. using alignment marks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/934—Cross-sectional shape, i.e. in side view

Definitions

  • This application relates to the field of semiconductor packaging manufacturing processes, and in particular to a semiconductor structure and a method of forming the same.
  • the purpose of the present application is to provide a semiconductor structure and a method of forming the same, which can improve the performance and reliability of the semiconductor structure after packaging.
  • this application provides a method for forming a semiconductor structure, which includes the following steps:
  • the surface of the semiconductor substrate has an exposed conductive structure
  • Etching is performed to form a hole in the bottom of the concave hole.
  • forming an adhesion layer on the surface of the concave hole further includes: along the direction from the side wall of the concave hole to the bottom of the concave hole, the thickness of the adhesion layer gradually decreases until the concave hole is exposed. The sidewall of the hole.
  • the height of the side wall exposing the concave hole is 1-5 micrometers.
  • the step of forming the hole further includes: using an isotropic etching process to form the hole by etching the exposed sidewall of the concave hole, and the holes are continuously arranged around the bottom of the concave hole Inside.
  • the shape of the cross section of the hole is a circle or an ellipse; the size of the hole is 1 to 5 microns.
  • the size of the concave holes is 5-30 microns.
  • the material of the adhesion layer includes: tantalum, tantalum nitride or a combination thereof.
  • a seed layer is deposited on the surface of the adhesion layer.
  • the method further includes: forming a barrier layer on the surface of the hole.
  • the thickness of the barrier layer is 80-120 nanometers.
  • a metal layer is filled into the recessed hole.
  • the technical solution of the present application also provides a semiconductor structure, including:
  • a semiconductor substrate, the surface of the semiconductor substrate has an exposed conductive structure
  • a recessed hole located in the passivation layer, and one end of the conductive structure is exposed at the bottom of the recessed hole;
  • the hole is located at the bottom of the concave hole
  • the metal layer is filled in the concave hole.
  • a barrier layer is deposited on the surface inside the hole.
  • the holes are continuously arranged in the circumference of the bottom of the concave hole.
  • the advantage of the present application is that compared with some through silicon via packaging technologies, the present application mainly improves the structure process of the semiconductor metal contact hole.
  • the hole between the metal layer and the passivation layer is used as the thermal expansion of the metal during heterogeneous bonding.
  • the performance and reliability of the semiconductor structure after packaging are improved.
  • 1 to 9 are schematic diagrams of structures obtained by sequentially implementing each step of the semiconductor structure and its forming method in an embodiment of this application;
  • 10A and 10B are top cross-sectional views of the semiconductor structure in an embodiment of the application.
  • 100 semiconductor substrate; 200: conductive structure; 101: passivation layer; w: cavity; 102: adhesion layer; 201: hole; 103: barrier layer; 300: metal layer.
  • Step one is to provide a semiconductor substrate, the surface of the semiconductor substrate has an exposed conductive structure.
  • the formation of the exposed conductive structure on the surface of the semiconductor substrate may be as follows:
  • a semiconductor substrate 100 is provided.
  • the semiconductor substrate 100 has a conductive structure 200 therein.
  • One end of the conductive structure 200 is located on the second surface of the semiconductor substrate 100, and the other end of the conductive structure 200 Built in the first surface of the semiconductor substrate 100.
  • the semiconductor substrate 100 is a wafer
  • the first surface is the crystal back of the wafer
  • the second surface is the crystal plane of the wafer.
  • a portion of the semiconductor substrate layer on the first surface is removed by a grinding process, exposing the conductive structure 200, which is exposed on the first surface of the semiconductor substrate 100, thereby forming a The semiconductor substrate 100 with the exposed conductive structure 200 is described.
  • the semiconductor substrate 100 may include, but is not limited to, a single crystal silicon substrate, a polycrystalline silicon substrate, a gallium nitride substrate, or a sapphire substrate.
  • the semiconductor substrate 100 is a single crystal substrate or a polycrystalline silicon substrate. In the case of a crystalline substrate, it may also be an intrinsic silicon substrate or a doped silicon substrate, and further, it may be an N-type polycrystalline silicon substrate or a P-type polycrystalline silicon substrate.
  • the exposed conductive structure 200 passes through the surface of the semiconductor substrate 100; the exposed conductive structure 200 can be, but is not limited to, tungsten, copper and other related integrated circuit conductive materials. Further, there is a silicon oxide or silicon nitride isolation layer on the sidewall of the conductive structure 200 to prevent the conductive material copper from diffusing into the semiconductor substrate.
  • Step two please refer to FIG. 3 for forming a passivation layer 101 on the surface of the semiconductor substrate 100 and the exposed conductive structure 200.
  • the passivation layer 101 is deposited on the surface of the semiconductor substrate 100 and the exposed conductive structure 200 through a deposition process.
  • the thin film deposition process there are two main deposition methods: chemical vapor deposition, in which one or several substances are activated in a certain way, and a chemical reaction occurs on the surface of the substrate to deposit the required solid film Growth technology.
  • Physical vapor deposition the use of a certain physical process to achieve the transfer of substances, that is, the transfer of atoms or molecules to the surface of the silicon substrate, and deposited into a thin film technology.
  • spin-coating and electroplating techniques for depositing thin films.
  • the specific deposition method of the passivation layer 101 may be various.
  • a chemical vapor deposition method is used to deposit a passivation layer 101 with a predetermined thickness distribution on the surface of the semiconductor substrate 100.
  • the control means of controlling the flow rate of the introduced airflow, controlling the flow rate of the introduced airflow, controlling the deposition time or controlling the deposition temperature can be used separately. By improving the control accuracy of the airflow and temperature, it can ensure that all atoms are arranged neatly during deposition to form a single unit.
  • the crystal layer finally obtains a passivation layer 101 with a uniform thickness on the surface of the semiconductor substrate 100 and the exposed conductive structure 200.
  • the material of the passivation layer 101 may include, but is not limited to, silicon dioxide, silicon nitride, silicon oxynitride and other related integrated circuit insulating materials.
  • Step three please refer to FIG. 4 for etching the surface of the passivation layer 101 to form a recessed hole w, and the bottom of the recessed hole w exposes one end of the conductive structure 200.
  • the method further includes: forming a patterned first mask layer (not shown) on the surface of the passivation layer 101.
  • the first mask layer patterns are arranged at intervals.
  • the passivation layer 101 is etched according to the pattern on the first mask layer that is arranged at intervals, and the pattern of the first mask layer is transferred to the passivation layer 101.
  • the size of the recessed hole is 5-30 microns, that is, the depth of the recessed hole is 5-30 microns, such as 10 microns, 15 microns, 20 microns or 25 microns.
  • the shape of the concave holes can be round, square or other irregular shapes. Those skilled in the art can understand that in the packaging process, the through-silicon via process needs to connect the semiconductor substrate, the conductive structure, and the through holes to meet other subsequent process steps.
  • Step 4 referring to FIG. 5, an adhesion layer 102 is formed on the surface of the concave hole w.
  • the adhesion layer 102 is deposited on the surface of the etched recessed hole w through a sputtering process.
  • the adhesion layer 102 covers part of the sidewall of the concave hole, and covers the bottom of the concave hole and the surface of the passivation layer 101 away from the bottom of the concave hole.
  • the thickness of the adhesion layer 102 gradually decreases until the sidewall of the recessed hole is exposed. Since the sputtering process will lead to poor vertical coverage, the most difficult area to cover is the corner of the recessed hole.
  • the sidewall of the recessed hole can be deposited to form an inverted triangle-shaped adhesion layer 102, and no adhesion layer 102 is deposited on the sidewall of the recessed hole near the bottom.
  • the height of the lower sidewall of the cavity not covered by the adhesion layer 102 is 1-5 microns, for example, 2 microns or 4 microns.
  • the material of the adhesion layer 102 includes: tantalum, tantalum nitride or a combination thereof.
  • the thickness of the adhesion layer 102 is 35-45 nanometers, for example, 40 nanometers.
  • the adhesion layer 102 formed by the deposition can make the later seed layer more uniformly and densely deposited on the substrate.
  • a seed layer (not shown) may be deposited on the surface of the adhesion layer 102.
  • the material of the seed layer is copper seed.
  • the thickness of the seed layer is 80-120 nanometers, for example, 100 nanometers.
  • the seed layer may not be deposited first, and the metal adhesion layer may be formed before the subsequent electroplating of the metal layer.
  • Step 5 referring to FIG. 6, etching is performed to form a hole 201 in the bottom of the concave hole.
  • an isotropic etching process may be used to form the holes 201 by etching the sidewalls that expose the concave holes, and the holes 201 are continuously arranged around the bottom of the concave holes.
  • a hole 201 can be formed in the corner of the original cavity where the adhesion layer 102 is not deposited.
  • the top cross-sectional view (FIG. 10A/FIG. 10B) shows that the bottom of the concave hole w is surrounded by a hole 201, and the continuous hole 201 can be defined as ring-shaped surrounding the bottom of the concave hole. Since wet etching is isotropic, the shape of the cross-section of the hole 201 is a circle or an ellipse, or other approximate circular shapes. The size of the holes is 1 to 5 microns. Further, in other embodiments, the hole 201 may also be formed by a chemical dry etching process.
  • the chemical dry etching utilizes the chemically active radicals in the plasma to chemically react with the material to be etched, so as to achieve the purpose of etching. Since the core of the etching is still a chemical reaction (but it does not involve the gas state of the solution), the etching effect is somewhat similar to that of wet etching and has better selectivity.
  • the present application compared with some through silicon via packaging technologies, mainly improves the structure process of the semiconductor metal contact hole, that is, a circle of holes is formed at the outer edge under the metal layer.
  • the hole between the metal layer and the passivation layer is used as a buffer during the thermal expansion of the metal to control the stability of the back-side through hole exposure device in the chemical mechanical process, thereby also enhancing the ability of wafer bonding.
  • the performance and reliability of the semiconductor structure after packaging are improved.
  • the present application can avoid the risk of particles getting stuck in the hole in the later chemical mechanical polishing process.
  • Step 6 please refer to FIG. 7 to form a barrier layer 103 on the surface of the hole 201.
  • a barrier layer 103 is deposited on the surface of the adhesion layer 102 in the cavity w and the cavity 201 after etching through a vapor deposition process.
  • the vapor deposition process has the characteristics of good coverage, and a relatively uniform barrier layer 103 can be formed on the surface of the adhesion layer 102 in the hole 201.
  • other suitable processes can also be used to form the barrier layer 103.
  • the material of the barrier layer 103 is an insulating material such as silicon nitride.
  • the thickness of the barrier layer 103 is 80-120 nanometers, for example, 100 nanometers.
  • the barrier layer 103 on the sidewall and bottom of the cavity w is removed by a dry etching process, and the barrier layer 103 in the hole is retained, so that only the barrier layer 103 on the inner surface of the hole 201 is formed. Because the dry etching process has good anisotropic etching characteristics, during the etching process, the etching gas only etches the barrier layer 103 in the depth direction, and does not penetrate the hole 201, thereby ensuring The barrier layer 103 in the hole can be retained. In this embodiment, the barrier layer 103 can prevent the metal from being diffused into the passivation layer 101 at high temperature through the hole 201 when the metal layer 300 is subsequently deposited, thereby forming a parasitic capacitance.
  • Step 7 please refer to FIG. 8 for filling the metal layer 300 into the recessed hole w.
  • electroplating technology is used to fill the recessed holes with copper.
  • the material of the metal layer 300 may be, but not limited to, tungsten, copper, aluminum and other related integrated circuit conductive materials.
  • a seed layer (not shown) may be sputtered on the surface of the adhesion layer 102, and then an electroplating process may be performed. During the electroplating process, since there is no seed layer in the hole 201, no electroplated metal is formed in the hole 201.
  • FIG. 9 for polishing the excess metal layer 300 and the adhesion layer 102 on the upper surface of the passivation layer 101 by using the chemical mechanical polishing technology.
  • the embodiment of the present application also provides a semiconductor structure, please refer to FIG. 9.
  • the semiconductor device includes: a semiconductor substrate 100, a conductive structure 200, a passivation layer 101, a cavity w, an adhesion layer 102, a hole 201, and a metal layer 300.
  • the surface of the semiconductor substrate 100 has an exposed conductive structure 200.
  • the exposed conductive structure 200 passes through the surface of the semiconductor substrate 100; the exposed conductive structure 200 can be, but is not limited to, tungsten, copper and other related integrated circuit conductive materials. Further, there is a silicon oxide or silicon nitride isolation layer on the sidewall of the conductive structure 200 to prevent the conductive material copper from diffusing into the semiconductor substrate.
  • the semiconductor substrate 100 may include, but is not limited to, a single crystal silicon substrate, a polycrystalline silicon substrate, a gallium nitride substrate or a sapphire substrate.
  • the semiconductor substrate 100 when the semiconductor substrate 100 is a single crystal substrate or a polycrystalline substrate, It may be an intrinsic silicon substrate or a doped silicon substrate, and further, it may be an N-type polysilicon substrate or a P-type polysilicon substrate.
  • the passivation layer 101 is deposited on the surface of the semiconductor substrate 100 and the exposed conductive structure 200.
  • the material of the passivation layer 101 may include, but is not limited to, silicon dioxide, silicon nitride, silicon oxynitride and other related integrated circuit insulating materials.
  • the concave hole w is located in the passivation layer 101, and the bottom of the concave hole w exposes one end of the conductive structure 200.
  • the size of the recessed hole is 5-30 microns, that is, the depth of the recessed hole is 5-30 microns, for example, 10 microns, 15 microns, 20 microns or 25 microns.
  • the shape of the concave holes can be round, square or other irregular shapes. Those skilled in the art can understand that in the packaging process, the through-silicon via process needs to connect the semiconductor substrate, the conductive structure, and the through holes to meet other subsequent process steps.
  • the adhesion layer 102 is deposited on the surface of the concave hole w.
  • the adhesion layer 102 is deposited on the surface of the etched cavity w through a sputtering process.
  • the adhesion layer 102 covers part of the sidewall of the concave hole, and covers the bottom of the concave hole and the surface of the passivation layer 101 away from the bottom of the concave hole.
  • the thickness of the adhesion layer 102 gradually decreases until the sidewall of the concave hole is exposed. Since the sputtering process will lead to poor vertical coverage, the most difficult area to cover is the corner of the recessed hole.
  • an inverted triangle-shaped adhesion layer 102 can be deposited on the sidewall of the recessed hole, and no adhesion layer 102 is deposited on the bottom sidewall of the recessed hole near the bottom.
  • the height of the lower sidewall of the cavity not covered by the adhesion layer 102 is 1-5 micrometers, for example, 2 micrometers or 4 micrometers.
  • the material of the adhesion layer 102 includes: tantalum, tantalum nitride or a combination thereof.
  • the thickness of the adhesion layer is 35-45 nanometers, for example, 40 nanometers.
  • a seed layer (not shown) can be deposited on the surface of the adhesion layer; the material of the seed layer is a copper seed.
  • the thickness of the seed layer is 80-120 nanometers, for example, 100 nanometers.
  • a hole 201 is formed at the bottom of the concave hole.
  • the holes 201 are continuously arranged in the circumference of the bottom of the concave hole.
  • An isotropic etching process is used to etch the exposed sidewalls of the recesses to form the holes 201 around the bottom of the recesses, and the holes 201 are continuously arranged in the circumference of the bottom of the recesses .
  • a hole 201 can be formed in the corner of the original cavity where the adhesion layer 102 is not deposited. From the top cross-sectional view (FIG. 10A/FIG.
  • the bottom of the concave hole w is surrounded by a hole 201, and the continuous hole 201 can be defined as a ring surrounding the bottom of the concave hole. Since wet etching is isotropic, the shape of the cross-section of the hole 201 is a circle or an ellipse, or other approximate circular shapes. The size of the holes is 1-5 microns.
  • the barrier layer 103 is deposited on the surface of the hole 201.
  • a barrier layer 103 is deposited on the surface of the recessed hole w and the hole 201 through a vapor deposition process, and then a dry etching process is used to remove the barrier layer 103 on the sidewall and bottom of the recessed hole w, leaving the hole 201
  • the material of the barrier layer 103 is an insulating material such as silicon nitride.
  • the thickness of the barrier layer 103 is 80-120 nanometers, for example, 100 nanometers.
  • the barrier layer 103 can prevent the metal from diffusing into the passivation layer at high temperature through the hole 201 when the metal layer 300 is subsequently deposited, thereby forming a parasitic capacitance. At the same time, it can also prevent the thermal expansion of the metal from buffering to the hole 201 during bonding, and then drilling into the passivation layer 101. Therefore, by forming the barrier layer 103 in the hole 201, the yield of the semiconductor structure in the semiconductor manufacturing process can be improved.
  • the metal layer 300 is filled in the recessed hole. Electroplating ECP technology is used to fill metal copper in the recessed holes.
  • the material of the metal layer 300 may be, but not limited to, tungsten, copper, aluminum and other related integrated circuit conductive materials.
  • the present application compared with some through silicon via packaging technologies, mainly improves the structure process of the semiconductor metal contact hole, that is, a circle of holes is formed at the outer edge under the metal layer.
  • the hole between the metal layer and the passivation layer is used as a buffer during the thermal expansion of the metal to control the stability of the back-side through hole exposure device in the chemical mechanical process, thereby also enhancing the ability of wafer bonding.
  • the performance and reliability of the semiconductor structure after packaging are improved.
  • the present application can avoid the risk of particles getting stuck in the hole in the later chemical mechanical polishing process.

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
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Abstract

该申请涉及半导体封装制程领域，公开了一种半导体结构及其形成方法。该形成方法包括：提供半导体衬底，所述半导体衬底表面具有显露的导电结构；在所述半导体衬底和所述显露的导电结构的表面形成钝化层；刻蚀所述钝化层以形成凹孔，所述凹孔的底部暴露出所述导电结构的一端；在所述凹孔表面形成黏附层；进行刻蚀，以形成所述凹孔底部内的孔洞。本申请改进金属层接触面的结构工艺，将金属层与钝化层凹孔底部孔洞作为金属热膨胀时的缓冲，来控制化学机械工艺中背面通孔显露装置的稳定性，从而使得封装后半导体结构的性能改善、可靠性增强。

Description

半导体结构及其形成方法
相关申请引用说明
本申请要求于2020年04月16日递交的中国专利申请号202010299490.5，申请名为“半导体结构及其形成方法”的优先权，其全部内容以引用的形式附录于此。
技术领域
本申请涉及半导体封装制程领域，具体涉及一种半导体结构及其形成方法。
背景技术
随着半导体集成电路器件特征尺寸的不断缩小，对半导体封装制程技术的要求也在不断提高。硅通孔封装技术是通过在芯片和芯片之间制作垂直导通，实现芯片和芯片之间互连，该技术能够使芯片在三维方向堆叠的密度最大，外形尺寸最小，并且大大改善了芯片速度和低功耗的性能。
在硅通孔封装技术的制造流程中，涉及到晶圆异键合制成，其需要控制金属层接触面的深度在1至5纳米，对工艺技术要求极高，非常难控制。当金属层深度过深，金属之间会出现断路，无法接通；当金属层深度过浅，金属层由键合面挤压，造成键合分离或是与邻近的金属层短路。因此，如何控制化学机械工艺中背面通孔显露装置的稳定性，避免当化学机械平坦化时，出现金属层深度过深的断路问题以及金属层深度过浅的短路问题是目前亟待解决的技术问题。
发明内容
本申请的目的在于提供一种半导体结构及其形成方法，能够使得封装后半导体结构的性能改善、可靠性增强。
为解决上述技术问题，本申请中提供了一种半导体结构的形成方法，包括如下步骤：
提供半导体衬底，所述半导体衬底表面具有显露的导电结构；
在所述半导体衬底和所述显露的导电结构的表面形成钝化层；
刻蚀所述钝化层以形成凹孔，所述凹孔的底部暴露出所述导电结构的一端；
在所述凹孔表面形成黏附层；
进行刻蚀，以形成所述凹孔底部内的孔洞。
可选的，在所述凹孔表面形成黏附层还包括：沿着所述凹孔的侧壁至所述凹孔底部的方向，所述黏附层的厚度逐渐减小，直至暴露出所述凹孔的侧壁。
可选的，所述暴露出凹孔的侧壁的高度为1-5微米。
可选的，形成所述孔洞的步骤进一步包括：采用各向同性刻蚀工艺，通过刻蚀所述暴露出凹孔侧壁形成所述孔洞，所述孔洞连续排布于所述凹孔底部四周内。
可选的，所述孔洞的横截面的形状为圆形或者椭圆形；所述孔洞的尺寸为1至5微米。
可选的，所述凹孔的尺寸为5-30微米。
可选的，所述黏附层的材料包括：钽、氮化钽或其组合。
可选的，在黏附层表面沉积种子层。
可选的，在形成所述凹孔底部内的孔洞后，还包括：形成一阻挡层于所述孔洞内的表面。
可选的，所述阻挡层厚度为80-120纳米。
可选的，填充金属层至所述凹孔内。
相应的，本申请的的技术方案还提供一种半导体结构，包括：
半导体衬底，所述半导体衬底表面具有显露的导电结构；
钝化层，沉积于所述半导体衬底和所述显露的导电结构的表面；
凹孔，位于所述钝化层内，所述凹孔的底部暴露出所述导电结构的一端；
黏附层，沉积于所述凹孔表面；
孔洞，位于所述凹孔底部；
金属层，填充于所述凹孔内。
可选的，阻挡层，沉积于所述孔洞内的表面。
可选的，所述孔洞连续排布于所述凹孔底部四周内。
本申请的优点在于，相较于一些硅通孔封装技术，本申请主要改进了半导体金属接触孔的结构工艺，将金属层与钝化层凹孔之间的孔洞作为异质键合时金属热膨胀时的缓冲，来控制化学机械工艺中背面通孔显露结构的稳定性，进而也增强了晶圆键合的能力。从而使得封装后半导体结构的性能改善、可靠性增强。
附图说明
图1至图9为本申请的一种实施例中的半导体结构及其形成方法依次实施各步骤所得到结构示意图；
图10A和图10B为本申请的一种实施例中的半导体结构俯视剖面图。
附图标记：
100：半导体衬底；200：导电结构；101：钝化层；w：凹孔；102：黏附层；201：孔洞；103：阻挡层；300：金属层。
具体实施方式
为了更清楚地说明本申请实施例的技术方案，下面将对本申请实施例中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
步骤一，提供半导体衬底，所述半导体衬底表面具有显露的导电结构。
在本实施例中，所述半导体衬底表面具有显露的导电结构的形成方式可以为：
请参阅图1，提供一半导体衬底100，所述半导体衬底100内具有一导电结构200，所述导电结构200的一端位于半导体衬底100的第二表面，所述导电结构200的另一端内置于所述半导体衬底100的第一表面。在一实施例中，所述半导体衬底100为晶圆，所述第一表面为所述晶圆的晶背，所述第二表面为所述晶圆的晶面。请参阅图2，通过研磨工艺，去除部分第一表面的所述半导体衬底层，暴露出所述导电结构200，所述导电结构200显露于所述半导体衬底100的第一表面，从而形成所述具有显露的导电结构200的半导体衬底100。
提供半导体衬底100，所述半导体衬底100可以包括但不限于单晶硅衬底、多晶硅衬底、氮化镓衬底或蓝宝石衬底，另外，半导体衬底100为单晶衬底或多晶衬底时，还可以是本征硅衬底或者是掺杂硅衬底，进一步，可以为N型多晶硅衬底或P型多晶硅衬底。
所述显露的导电结构200穿过所述半导体衬底100的表面；所述显露的导电结构200可以但不限于是钨、铜等相关集成电路导电材料。进一步的，在所述导电结构200的侧壁有氧化硅或氮化硅隔离层，用于防止导电材料铜扩散到 半导体衬底中。
步骤二，请参阅图3为在所述半导体衬底100和所述显露的导电结构200的表面形成钝化层101。
具体地说，通过沉积工艺在所述半导体衬底100表面和所述显露的导电结构200的表面沉积钝化层101。在薄膜沉积工艺中，主要的沉积方式有两种：化学气相沉积，将一种或数种物质的气体，以某种方式激活后，在衬底表面发生化学反应，并沉积出所需固体薄膜的生长技术。物理气相沉积，利用某种物理过程实现物质的转移，即将原子或分子转移到硅衬底表面，并沉积成薄膜的技术。沉积薄膜的技术还有旋涂法、电镀法等。本实施例中，钝化层101的具体沉积方式可以是多样的。例如，采用化学气相沉积的方式，在半导体衬底100的表面，沉积预设厚度分布的钝化层101。进一步的，可以单独运用控制导入气流的流速、控制导入气流的流量、控制沉积时长或控制沉积温度的控制手段，通过提高对气流和温度的控制精度，可以确保所有原子沉积时排列整齐，形成单晶层，最终在半导体衬底100及显露的导电结构200的表面得到一层厚度均匀的钝化层101。
常用的沉积材料有二氧化硅、氮化硅等隔离互连层的绝缘材料。因此，钝化层101的材料可以包括但不限于二氧化硅、氮化硅、氮氧化硅等相关集成电路绝缘材料。
步骤三，请参阅图4为刻蚀所述钝化层101表面以形成凹孔w，所述凹孔w的底部暴露出所述导电结构200的一端。
具体地说，在刻蚀钝化层101的步骤之前还包括：在钝化层101表面形成图形化的第一掩膜层(未示出)。所述第一掩膜层图形间隔排列。根据第一掩膜层上设计为间隔排列的图案，刻蚀钝化层101，将第一掩膜层图形转移到了钝化层101上。
进一步的，所述凹孔的尺寸为5-30微米，即所述凹孔的深度为5-30微米，例如10微米，15微米，20微米或25微米。所述凹孔的形状可以为圆形，方形或其他不规则形状。本领域技术人员可以理解，在封装工艺中，其中硅通孔工艺需要将半导体衬底、导电结构、通孔相连通，以满足后续其他工艺步骤。
步骤四，请参阅图5，在所述凹孔w表面形成黏附层102。
具体地说，通过溅镀工艺在上述刻蚀后凹孔w的表面沉积黏附层102。所述黏附层102覆盖所述凹孔的部分侧壁，且覆盖所述凹孔的底部及所述钝化层101远离所述凹孔底部的表面。在一实施例中，沿着所述凹孔的侧壁至所述凹孔底部的方向，所述黏附层102的厚度逐渐减小，直至暴露出所述凹孔的侧壁。由于溅镀工艺会导致垂直面覆盖率不佳，最不容易覆盖的地方是凹孔的角落。在本实施例中，通过控制沉积速度，可以使所述凹孔的侧壁沉积形成倒三角状的黏附层102，所述凹孔的侧壁靠近底部的位置均没有沉积黏附层102。其中凹孔下侧壁未被黏附层102覆盖的高度为1-5微米，例如2微米或4微米。同时，所述黏附层102的材料包括：钽、氮化钽或其组合。所述黏附层102的厚度为35-45纳米，例如为40纳米。因此，通过控制溅镀工艺形成所述黏附层102，可以控制所述凹孔下侧壁未被黏附层覆盖的高度尺寸，从而控制后期形成的孔洞201的尺寸。且沉积形成的黏附层102能使后期种子层更均匀致密的沉积在衬底上。
进一步的，在另一实施例中，可以在黏附层102表面沉积种子层(未示出)。所述种子层的材料为铜种子。所述种子层的厚度为80-120纳米，例如为100纳米。为了更便于后续工艺中填充金属层，可以提前准备在本步骤中形成铜种子层。同时，在本实施例的步骤中也可以先不用沉积种子层，而在后续电镀金属层之前形成金属黏附层。
步骤五，请参阅图6，进行刻蚀，以形成所述凹孔底部内的孔洞201。
在一实施例中，可采用各向同性刻蚀工艺，通过刻蚀所述暴露出凹孔的侧壁形成所述孔洞201，所述孔洞201连续排布于所述凹孔底部四周内。
具体地说，通过湿法刻蚀，可以使原先凹孔内未被沉积黏附层102的角落形成孔洞201。在本实施例中，俯视剖面图(图10A/图10B)可以看到凹孔w的底部四周环绕着孔洞201，孔洞201连续起来可以定义为环状包围在凹孔底部。由于湿法蚀刻是各向同性，因此，孔洞201的横截面的形状为圆形或者椭圆形，或其他近似圆形的形状。所述孔洞的尺寸为1至5微米。进一步的，在其它实施例中，也可以采用化学干法刻蚀工艺形成所述孔洞201。化学干法刻蚀利用等离子体中的化学活性原子团与被刻蚀材料发生化学反应，从而实现刻蚀目的。由于刻蚀的核心还是化学反应(只是不涉及溶液的气体状态)，因此， 刻蚀的效果和湿法刻蚀有些相近，具有较好的选择性。
因此，本实施例相较于一些硅通孔封装技术，本申请主要改进了半导体金属接触孔的结构工艺，即在金属层下面外缘形成一圈孔洞。金属层与钝化层凹孔之间的孔洞作为金属热膨胀时的缓冲，来控制化学机械工艺中背面通孔显露装置的稳定性，进而也增强了晶圆键合的能力。从而使得封装后半导体结构的性能改善、可靠性增强。同时，相比于在金属层上端形成孔洞，本申请能避免在后期化学机械抛光工艺中颗粒物卡在孔洞的风险。
步骤六，请参阅图7，形成一阻挡层103于所述孔洞201内的表面。
具体地说，通过气相沉积工艺，在刻蚀后所述凹孔w和所述孔洞201内黏附层102的表面沉积一阻挡层103。利用气相沉积工艺具有很好的覆盖率的特征，可以在所述孔洞201内的黏附层102表面形成一层比较均匀的阻挡层103。在其他实施例中，也可以采用其他合适的工艺形成所述阻挡层103。所述阻挡层103的材料为氮化硅等绝缘材料。所述阻挡层103的厚度为80-120纳米，例如为100纳米。通过干法刻蚀工艺去除所述凹孔w侧壁及底部的阻挡层103，保留孔洞内的阻挡层103，从而只形成孔洞201内表面的阻挡层103。干法刻蚀工艺由于具有良好的各相异性蚀刻特点，因此，刻蚀过程中，刻蚀气体只在纵深方向对所述阻挡层103进行刻蚀，而不会钻进孔洞201内，从而保证孔洞内的阻挡层103能被保留下来。在本实施例中，所述阻挡层103可以防止后续沉积金属层300时，通过所述孔洞201，金属高温扩散至钝化层101内，从而形成寄生电容。同时，也可以防止在键合时，金属热膨胀缓冲至所述孔洞201，进而钻进所述钝化层101内。因此，通过在孔洞201内形成一层阻挡层103，可以提升半导体制造工艺中半导体结构的良品率。
步骤七，请参阅图8为填充金属层300至所述凹孔w内。
具体地说，采用电镀技术在凹孔中填充金属铜。所述金属层300的材料可以为但不限于钨、铜、铝等相关集成电路导电材料。在另一实施例中，采用电镀技术沉积金属层300之前，可以溅镀一层种子层(未示出)于所述黏附层102表面，然后进行电镀工艺。在电镀工艺中，由于孔洞201内没有种子层，所以在所述孔洞201内不会有电镀金属形成。同时，请参阅图9为采用化学机械抛光技术磨平钝化层101上表面多余的金属层300和黏附层102。
本申请的实施例还提供一种半导体结构，请参考图9。
所述半导体器件包括：半导体衬底100，导电结构200，钝化层101，凹孔w，黏附层102，孔洞201，金属层300。
所述半导体衬底100表面具有显露的导电结构200。所述显露的导电结构200穿过所述半导体衬底100的表面；所述显露的导电结构200可以但不限于是钨、铜等相关集成电路导电材料。进一步的，在所述导电结构200的侧壁有氧化硅或氮化硅隔离层，用于防止导电材料铜扩散到半导体衬底中。
所述半导体衬底100可以包括但不限于单晶硅衬底、多晶硅衬底、氮化镓衬底或蓝宝石衬底，另外，半导体衬底100为单晶衬底或多晶衬底时，还可以是本征硅衬底或者是掺杂硅衬底，进一步，可以为N型多晶硅衬底或P型多晶硅衬底。
所述钝化层101沉积于所述半导体衬底100和所述显露的导电结构200表面。所述钝化层101的材料可以包括但不限于二氧化硅、氮化硅、氮氧化硅等相关集成电路绝缘材料。
所述凹孔w位于所述钝化层101内，所述凹孔w的底部暴露出所述导电结构200的一端。所述凹孔的尺寸为5-30微米，即所述凹孔的深度为5-30微米，例如10微米，15微米，20微米或25微米。所述凹孔的形状可以为圆形，方形或其他不规则形状。本领域技术人员可以理解，在封装工艺中，其中硅通孔工艺需要将半导体衬底、导电结构、通孔相连通，以满足后续其他工艺步骤。
所述黏附层102沉积于所述凹孔w表面。通过溅镀工艺在上述刻蚀后凹孔w的表面沉积黏附层102。所述黏附层102覆盖所述凹孔的部分侧壁，且覆盖所述凹孔的底部及所述钝化层101远离所述凹孔底部的表面。沿着所述凹孔的侧壁至所述凹孔底部的方向，所述黏附层102的厚度逐渐减小，直至暴露出所述凹孔的侧壁。由于溅镀工艺会导致垂直面覆盖率不佳，最不容易覆盖的地方是凹孔的角落。因此，在本实施例中，通过控制沉积速度，可以使所述凹孔的侧壁沉积有倒三角状的黏附层102，所述凹孔底侧壁靠近底部四周均没有沉积黏附层102。其中，凹孔下侧壁未被黏附层102覆盖的高度为1-5微米，例如2微米或4微米。同时，所述黏附层102的材料包括：钽、氮化钽或其组合。所述黏附层的厚度为35-45纳米，例如为40纳米。
进一步的，可以在黏附层表面沉积种子层(未示出)；所述种子层的材料为铜种子。所述种子层的厚度为80-120纳米，例如为100纳米。
进一步的，形成孔洞201于所述凹孔的底部。所述孔洞201连续排布于所述凹孔底部四周内。采用各向同性刻蚀工艺，通过刻蚀所述暴露的凹孔侧壁，以在所述凹孔底部四周内形成所述孔洞201，所述孔洞201连续排布于所述凹孔底部四周内。具体地说，通过湿法刻蚀，可以使原先凹孔内未被沉积黏附层102的角落形成孔洞201。俯视剖面图(图10A/图10B)可以看到凹孔w的底部四周环绕着孔洞201，孔洞201连续起来可以定义为环状包围在凹孔底部。由于湿法蚀刻是各向同性，因此，孔洞201的横截面的形状为圆形或者椭圆形，或其他近似圆形的形状。所述孔洞的尺寸为1-5微米。
进一步的，所述阻挡层103沉积于所述孔洞201内的表面。通过气相沉积工艺，在所述凹孔w和所述孔洞201表面沉积一阻挡层103，而后利用干法刻蚀工艺去除所述凹孔w侧壁和底部的阻挡层103，保留所述孔洞201内钝化层表面的阻挡层103。所述阻挡层103的材料为氮化硅等绝缘材料。所述阻挡层103的厚度为80-120纳米，例如为100纳米。在本实施例中，所述阻挡层103可以防止后续沉积金属层300时，通过所述孔洞201，金属高温扩散至钝化层内，从而形成寄生电容。同时，也可以防止在键合时，金属热膨胀缓冲至所述孔洞201，进而钻进所述钝化层101内。因此，通过在孔洞201内形成以层阻挡层103，可以提升半导体制造工艺中半导体结构的良品率。
进一步的，所述金属层300填充于所述凹孔内。采用电镀ECP技术在凹孔中填充金属铜。所述金属层300的材料可以为但不限于钨、铜、铝等相关集成电路导电材料。
因此，本实施例相较于一些硅通孔封装技术，本申请主要改进了半导体金属接触孔的结构工艺，即在金属层下面外缘形成一圈孔洞。利用金属层与钝化层凹孔之间的孔洞作为金属热膨胀时的缓冲，来控制化学机械工艺中背面通孔显露装置的稳定性，进而也增强了晶圆键合的能力。从而使得封装后半导体结构的性能改善、可靠性增强。同时，相比于在金属层上端形成孔洞，本申请能避免在后期化学机械抛光工艺中颗粒物卡在孔洞的风险。
以上所述仅是本申请的优选实施例，应当指出，对于本技术领域的普通技 术人员，在不脱离本申请原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本申请的保护范围。

Claims (14)

  1. 一种半导体结构的形成方法，其中，包括：
    提供半导体衬底，所述半导体衬底表面具有显露的导电结构；
    在所述半导体衬底和所述显露的导电结构的表面形成钝化层；
    刻蚀所述钝化层以形成凹孔，所述凹孔的底部暴露出所述导电结构的一端；
    在所述凹孔表面形成黏附层；
    进行刻蚀，以形成所述凹孔底部内的孔洞。
  2. 根据权利要求1所述的半导体结构的形成方法，其中，在所述凹孔表面形成黏附层还包括：沿着所述凹孔的侧壁至所述凹孔底部的方向，所述黏附层的厚度逐渐减小，直至暴露出所述凹孔的侧壁。
  3. 根据权利要求2所述的半导体结构的形成方法，其中，所述暴露出凹孔的侧壁的高度为1-5微米。
  4. 根据权利要求2所述的半导体结构的形成方法，其中，形成所述孔洞的步骤进一步包括：采用各向同性刻蚀工艺，通过刻蚀所述暴露出凹孔的侧壁形成所述孔洞，所述孔洞连续排布于所述凹孔底部四周内。
  5. 根据权利要求1所述的半导体结构的形成方法，其中，还包括：所述孔洞的横截面的形状为圆形或者椭圆形；所述孔洞的尺寸为1至5微米。
  6. 根据权利要求1所述的半导体结构的形成方法，其中，所述凹孔的尺寸为5-30微米。
  7. 根据权利要求1所述的半导体结构的形成方法，其中，所述黏附层的材料包括：钽、氮化钽或其组合。
  8. 根据权利要求1所述的半导体结构的形成方法，其中，在所述黏附层表面沉积种子层。
  9. 根据权利要求1所述的半导体结构的形成方法，其中，在形成所述凹孔底部内的孔洞后，还包括：形成一阻挡层于所述孔洞内的表面。
  10. 根据权利要求9所述的半导体结构的形成方法，其中，所述阻挡层厚度为80-120纳米。
  11. 根据权利要求1所述的半导体结构的形成方法，其中，还包括：填充金属层至所述凹孔内。
  12. 一种半导体结构，其中，包括：
    半导体衬底，所述半导体衬底表面具有显露的导电结构；
    钝化层，沉积于所述半导体衬底和所述显露的导电结构的表面；
    凹孔，位于所述钝化层内，所述凹孔的底部暴露出所述导电结构的一端；
    黏附层，沉积于所述凹孔表面；
    孔洞，位于所述凹孔底部；
    金属层，填充于所述凹孔内。
  13. 根据权利要求12所述的半导体结构，其中，还包括：阻挡层，沉积于所述孔洞内的表面。
  14. 根据权利要求12所述的半导体结构，其中，所述孔洞连续排布于所述凹孔底部四周内。
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