WO2021203887A1 - 半导体器件及其制备方法 - Google Patents

半导体器件及其制备方法 Download PDF

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Publication number
WO2021203887A1
WO2021203887A1 PCT/CN2021/079567 CN2021079567W WO2021203887A1 WO 2021203887 A1 WO2021203887 A1 WO 2021203887A1 CN 2021079567 W CN2021079567 W CN 2021079567W WO 2021203887 A1 WO2021203887 A1 WO 2021203887A1
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Prior art keywords
dummy
protective layer
opening
layer
semiconductor device
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Application number
PCT/CN2021/079567
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English (en)
French (fr)
Inventor
范增焰
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长鑫存储技术有限公司
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Priority to US17/430,856 priority Critical patent/US20230054495A1/en
Publication of WO2021203887A1 publication Critical patent/WO2021203887A1/zh

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Definitions

  • This application relates to the field of semiconductor packaging, in particular to a semiconductor device and a method for manufacturing the semiconductor device.
  • the dummy bumps are specially formed on the protective layer by the existing process.
  • the dummy bumps are generally formed on the surface of the protective layer because they have no electrical connection function.
  • the materials of the protective layer and the dummy bumps are different, such as dummy bumps.
  • the basis of the bump and the protective layer is the bond between metal and polymer material, the bonding force is not very strong, it is easier to cause the problem of dummy bumps falling off, and because the bonding force between the dummy bumps and the polymer material is poor , It is also prone to breakage, resulting in a weak structure of the semiconductor device.
  • the present application provides a semiconductor device, the structure of the semiconductor device is stable, and the dummy bumps are not easy to fall off.
  • the semiconductor device includes a semiconductor substrate; a passivation layer provided on the upper surface of the semiconductor substrate; a protective layer provided on the upper surface of the passivation layer ,
  • the protective layer is provided with a dummy opening; a dummy bump, and the dummy bump is partially located in the dummy opening and closely attached to the protective layer.
  • the dummy bump is at least partially located in the dummy opening and closely attached to the protective layer, which not only can increase the contact area between the dummy bump and the protective layer to improve the bonding
  • the dummy bumps can also be fixed through the dummy openings, which enhances the strength of the fixed connection between the dummy bumps and the protective layer, improves the bonding strength between the dummy bumps and the protective layer, and reduces the risk of the dummy bumps falling off.
  • it further includes: at least one conductive bump, a conductive pad is provided on the semiconductor substrate, the passivation layer partially covers the conductive pad, and the conductive bump passes through the conductive pad.
  • the protection layer and the passivation layer are connected to the conductive pad.
  • the dummy bumps are electroplated and formed.
  • a blocking groove communicating with the dummy opening is formed in the protective layer, the dummy bump is provided with a blocking portion, and the blocking portion is located in the blocking groove.
  • the blocking groove is formed by recessing a part of the side wall forming the dummy opening in a direction away from the dummy opening.
  • the blocking groove is formed as an annular groove extending along the circumferential direction of the dummy opening.
  • the dummy opening penetrates the protective layer in an up-and-down direction, and the blocking groove is formed at the lower end of the dummy opening and extends to the lower surface of the protective layer.
  • the dummy opening penetrates the protective layer, and the upper surface of the dummy opening has a first width, and the first width is smaller than the maximum width of the dummy opening.
  • the protective layer further covers the exposed side surface of the passivation layer and partially covers the conductive pad.
  • the semiconductor device further includes: a seed layer formed on the bottom of the dummy opening by sputtering and located between the dummy bump and the passivation layer.
  • This application also proposes a method for manufacturing a semiconductor device, which can be used to prepare the semiconductor device of the above-mentioned embodiments.
  • the method for manufacturing a semiconductor device includes the following steps: providing a semiconductor substrate with a passivation layer formed on the upper surface of the semiconductor substrate; forming a protective layer on the passivation layer; Exposure and development are performed to remove part of the protective layer to form dummy openings; a mask layer is formed on the protective layer, and the area of the mask corresponding to the dummy openings is exposed and developed to form a connection with the dummy openings. Electroplating openings; forming dummy bumps in the electroplating openings and the dummy openings, and removing the mask layer to expose the dummy bumps.
  • the protective layer after removing part of the protective layer to form the dummy opening, before the protective layer forms the mask layer, perform the following steps: sputtering on the upper surface of the protective layer and the bottom of the dummy opening A seed layer is formed, and after removing the mask layer to expose the dummy bumps, the following steps are performed: removing the seed layer formed on the upper surface of the protective layer.
  • the exposing and developing the protective layer, and removing part of the protective layer to form the dummy openings includes: using direct light exposure to form the dummy openings, using increased side light exposure to form the blocking grooves, the The blocking groove communicates with the dummy opening.
  • the exposing and developing the protective layer to remove part of the protective layer to form a dummy opening includes: exposing the protective layer by using a preset mask, the preset mask including The first area portion and the second area portion, the light transmittance of the second area portion is greater than the light transmittance of the first area portion; the protective layer corresponding to the first area portion is removed to form a dummy opening; The bottom of the protective layer corresponding to the second area portion forms a blocking groove, and the blocking groove communicates with the dummy opening.
  • forming a dummy bump in the electroplating opening and the dummy opening further includes: forming a blocking portion of the dummy bump in the blocking groove.
  • FIG. 1 is a schematic structural diagram of a semiconductor device according to an embodiment of the present application.
  • FIG. 2-11 is a partial cross-sectional view of each step of the method of manufacturing a semiconductor device according to an embodiment of the present application, wherein FIG. 3 is a partial structure of the protective layer in the method of manufacturing a semiconductor device according to an embodiment of the present application. 4 is a cross-sectional view of a part of the structure for exposing and developing the protective layer in a method of manufacturing a semiconductor device according to another embodiment of the present application;
  • FIG. 12 is a schematic structural diagram of a semiconductor device according to another embodiment of the invention.
  • FIG. 13 is a schematic structural diagram of a semiconductor device according to another embodiment of the invention.
  • FIG. 14 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present application.
  • FIG. 15 is a flowchart of a manufacturing method of a semiconductor device according to another embodiment of the present application.
  • the semiconductor device 100 may include a semiconductor substrate 1, a passivation layer 11, a protective layer 2 and dummy bumps 3.
  • the passivation layer 11 is provided on the upper surface of the semiconductor substrate 1. Specifically, as shown in FIGS. 1 to 11, the passivation layer 11 is formed on the semiconductor substrate 1 and covers the semiconductor substrate 1.
  • the protective layer 2 is provided on the upper surface of the passivation layer 11 and covers the upper surface of the passivation layer 11.
  • the protective layer 2 is formed with dummy openings 21, wherein the dummy bumps 3 can be used to connect and support other components;
  • the part of the bump 3 is located in the dummy opening 21 and closely adheres to the protective layer 2, that is, the part of the dummy bump 3 extends into the protective layer 2 through the dummy opening 21 and the side walls of the dummy opening 21 are tightly connected.
  • the lower end of the dummy bump 3 is located in the dummy opening 21 and connected to the side wall of the dummy opening 21.
  • the dummy bumps 3 are only provided on the upper surface of the protective layer 2.
  • the dummy bumps 3 and the protective layer 2 are connected by the bonding force of metal and polymer materials.
  • the dummy bumps The block 3 is at least partially located in the dummy opening 21 and the side walls of the dummy opening 21 are tightly connected, which not only can increase the contact area between the dummy bump 3 and the protective layer 2 to improve the bonding force, but also can fix the dummy bump 3 through the dummy opening 21 Enhance the fixed connection strength between the dummy bump 3 and the protective layer 2, increase the bonding strength between the dummy bump 3 and the protective layer 2, and reduce the risk of the dummy bump 3 falling off.
  • the semiconductor device 100 further includes at least one conductive bump 6.
  • a conductive pad 12 may be provided on the semiconductor substrate 1, and the conductive pad 12 is formed above the semiconductor substrate 1.
  • the conductive pad 12 is a metal pad, for example, an aluminum pad or an aluminum copper pad, or other metal materials.
  • the semiconductor substrate 1 may be a bulk silicon substrate or a silicon-on-insulator substrate, and other semiconductor materials may also be used, for example, a glass substrate or a ceramic substrate, etc., which is not specifically limited in this application.
  • the passivation layer 11 partially covers the conductive pad 12. Specifically, as shown in FIGS. 1 to 11, the passivation layer 11 is formed with an opening to expose the conductive pad 12, and a part of the passivation layer 11 may cover the conductive pad 12 The edge part.
  • the passivation layer 11 can be made of one or more of silicon oxide and silicon nitride.
  • the passivation layer 11 can be a single-layer silicon oxide layer or a passivation layer.
  • the chemical layer 11 can also be formed by stacking a silicon nitride layer and a silicon nitride layer.
  • the protective layer 2 is provided with an opening and exposes the conductive pad 12, wherein the protective layer 2 can cover the exposed side surface of the passivation layer 11 and partially cover the conductive pad 12, as shown in FIG. 1, the protective layer 2 and the passivation layer 11
  • An opening suitable for the conductive bump 6 to pass through and exposing the conductive pad 12 is formed therein, and a part of the opening formed by the protective layer 2 covers the edge of the conductive pad 12.
  • the protective layer 2 may cover the upper surface of the passivation layer 11, and the edge side of the protective layer 2 where the opening is formed is flush with the edge side of the passivation layer 11 where the opening is formed.
  • the protective layer 2 can be formed of photoresist.
  • the protective layer 2 can be formed of a negative photoresist or a positive photoresist.
  • the protective layer 2 can be formed of polyimide.
  • the PI layer may also be a polybenzoxazole (PBO) layer, benzocyclobutene (BCB) or formed of other suitable polymers.
  • PBO polybenzoxazole
  • BCB benzocyclobutene
  • a photoresist may be coated on the upper surface of the passivation layer 11 to form the protective layer 2, and an opening may be formed through a process such as exposure, development, and etching by photolithography to expose the conductive pad 12.
  • conductive bumps 6 and dummy bumps 3 there may be one or more conductive bumps 6 and dummy bumps 3, preferably, there may be a plurality of conductive bumps 6 and dummy bumps 3 respectively, wherein the conductive bumps 6 can be used for electrical connection with other components, and the plurality of conductive bumps 6 and dummy bumps 3
  • the conductive bumps 6 are arranged at intervals, and each conductive bump 6 passes through the opening of the protective layer 2 and the opening of the passivation layer 11 in turn to connect to the conductive pad 12.
  • a plurality of dummy bumps 3 are arranged at intervals.
  • the dummy bumps 3 can be used to connect and support other components, and do not have the function of being electrically connected to other components.
  • the dummy bumps 3 can be set at The location where the stress is concentrated when the semiconductor device 100 is connected to other components is beneficial to the connection and combination of the semiconductor device 100 and other components to improve the structural performance of the combined device.
  • the dummy bump 3 is formed by electroplating.
  • the dummy bump 3 is formed in the dummy opening 21 through an electroplating process, so that the dummy bump 3 and the protective layer 2 are more closely connected, and the dummy bump 3 and the protective layer 2 can be more closely connected.
  • the stability of the connection of the protective layer 2 is also conducive to the formation of the dummy bump 3.
  • the dummy opening 21 can be formed by exposure and development on the protective layer 2 by photolithography, and the mask layer 7 can be formed by applying glue on the protective layer 2, and then formed and dummy on the mask layer 7 by the exposure and development process again.
  • the opening 21 corresponds to the connected electroplating opening 71.
  • Dummy bumps 3 are formed by electroplating materials in the electroplating openings 71 and the dummy openings 21. After the electroplating process, the dummy bumps 3 are exposed to expose the dummy bumps 3 to form the semiconductor device 100.
  • conductive bumps 6 and dummy bumps 3 are usually formed at the same time by one-step electroplating. Due to the high horizontal position formed by dummy bumps 6, the height difference between conductive bumps 6 and dummy bumps 3 is relatively large. When connecting with other components, it will be unbalanced, and by forming the blocking portion 31, the height difference between the conductive bump 6 and the dummy bump 3 can also be reduced.
  • a blocking groove 22 communicating with the dummy opening 21 is formed in the protective layer 2
  • the dummy bump 3 is provided with a blocking portion 31, and the blocking portion 31 is located in the blocking groove 22
  • the dummy bump 3 can be fixed in the up and down direction, which enhances the up-and-down bonding force between the dummy bump 3 and the protective layer 2, and prevents the dummy bump 3 from protecting Layer 2 is detached.
  • the intensity and direction of the light source can be adjusted to form the blocking groove 22 in the protective layer 2, and the dummy bump 3 is formed by electroplating. In the process, an electroplating process is used to form the blocking portion 31 in the blocking groove 22.
  • the blocking groove 22 may be formed by recessing a part of the side wall forming the dummy opening 21 in a direction away from the dummy opening 21. Specifically, the blocking groove 22 is formed in the dummy opening 21. The side of the opening 21 is communicated with the side of the dummy opening 21, the side of the dummy bump 3 is provided with a blocking portion 31 corresponding to the blocking groove 22, and the blocking portion 31 is formed in the blocking groove 22 by electroplating. Inside, through the cooperation of the blocking groove 22 and the blocking portion 31, the dummy bump 3 can be fixed in the up and down direction to prevent the dummy bump 3 from being detached from the protective layer 2.
  • the blocking groove 22 may be an annular groove extending in the circumferential direction of the dummy opening 21, and the blocking portion 31 is formed in an annular shape matching the structure of the annular groove, so that the annular blocking groove 22 and the blocking portion 31 can further The bonding strength of the protective layer 2 and the dummy bump 3 is improved to further prevent the dummy bump 3 from falling off.
  • the dummy opening 21 penetrates the protective layer 2 in the up and down direction, so that the dummy bump 3 can expose the protective layer 2 to be connected to other components, and can further strengthen the dummy bump.
  • 3 formed in the dummy opening 21 can also enhance the fixing strength of the dummy bump 3.
  • the blocking groove 22 can be formed by adding side light, where the side light is emitted when the side light contacts the passivation layer 11 at the bottom of the protective layer 2, causing the protective layer 2 to correspond to The part where the blocking groove 22 is formed is removed after being irradiated with light and developed, which is beneficial to controlling the light source to form the blocking groove 22 during the photolithography process.
  • the method of forming the blocking groove 22 is not limited to this.
  • the blocking groove 22 is formed at the lower end of the dummy opening 21 and extends to the lower surface of the protective layer 2, that is, the lower end of the blocking groove 22 extends to the upper surface of the passivation layer 11, so that the blocking portion 31 is formed in the blocking groove 22 Inside, the blocking portion 31 is located below the protective layer 2, and the protective layer 2 can prevent the dummy bump 3 from falling off.
  • the dummy opening 21 penetrates the protective layer 2, and the upper surface of the dummy opening 21 has a first width, and the first width is smaller than the maximum width of the dummy opening 21, that is, the dummy opening 21
  • the width of the vertical section of the opening 21 in the vertical direction is different.
  • the width of the upper surface of the dummy opening 21 in the vertical section is the first width, wherein the position of the dummy opening 21 having the largest width is lower than the upper surface of the dummy opening 21, thus the dummy
  • the opening 21 can be formed with a narrow top and a wide bottom structure, thereby preventing the dummy bump 3 from falling off the dummy opening 21.
  • the dummy opening 21 may be formed in a truncated cone shape, the vertical cross section of the dummy opening 21 in the vertical direction is formed in a trapezoid shape, and the width of the dummy opening 21 gradually increases from the top to the bottom.
  • the protective layer 2 also covers the exposed side surfaces of the passivation layer 11 and partially covers the conductive pad 12. In other examples of the present application, the protective layer 2 may cover the upper surface of the passivation layer 11 and It is flush with the side surface of the passivation layer 11 where the conductive pad 12 is exposed.
  • the semiconductor device 100 may further include a seed layer 4.
  • the seed layer 4 is formed at the bottom of the dummy opening 21 by sputtering, and as shown in FIG. 11, the seed layer 4 in the semiconductor device 100 is finally formed.
  • the bottom of the dummy bump 3 can be at least partially connected to the passivation layer 11 through the seed layer 4, and the bottom of the dummy bump 3 can be further enhanced through the seed layer 4
  • the bonding strength with the passivation layer 11 reduces the risk of falling off.
  • the present application also proposes a method for manufacturing the semiconductor device 100, and the method for manufacturing a semiconductor according to an embodiment of the present application can be used to manufacture the semiconductor device 100 of the above-mentioned embodiment.
  • the manufacturing method of the semiconductor device 100 may include the following steps:
  • a semiconductor substrate 1 is provided.
  • a passivation layer 11 is formed on the upper surface of the semiconductor substrate 1, wherein the upper surface of the semiconductor substrate 1 is also provided with a conductive pad 12, and the passivation layer 11 is provided above the conductive pad 12 and A part of the passivation layer 11 covers the edge of the conductive pad 12, an opening is formed on the passivation layer 11 to expose the conductive pad 12, and the conductive bump 6 is connected to the conductive pad 12 through the passivation layer 11.
  • a protective layer 2 is formed on the passivation layer 11.
  • photoresist can be coated on the upper surface of the passivation layer 11 to form the protective layer 2, for example, a photoresist spin coater can be used
  • a photoresist is coated on the passivation layer 11.
  • the photoresist can be a positive photoresist, for example, it can be a polyimide photoresist, which has outstanding heat resistance, good mechanical properties, and insulation. Resistance and corrosion resistance, polyimide photoresist is coated on the passivation layer 11, which can play the role of insulation, corrosion resistance, stress buffering and planarization.
  • the PI (polyimide) layer itself has The protective function and stress buffering function of the product greatly improve the structural reliability of the product, and can also protect the surface of the chip from stress damage, and make the surface of the chip more flat, which is beneficial to improve the uniformity and bonding force of the subsequent electroplating process.
  • the protective layer 2 can also be a negative photoresist, and different masks 5 can be used for the patterning process according to different photoresists.
  • S3 Expose and develop the protective layer 2 to remove part of the protective layer 2 to form the dummy opening 21.
  • the protective layer 2 can be exposed and developed to remove the protective layer 2 corresponding to the region where the dummy opening 21 is formed to form Dummy opening 21.
  • a mask 5 can be arranged above the protective layer 2, and the protective layer 2 is exposed through the mask 5, and the photoresist is dissolved by a developer to remove the protective layer 2. A portion of the dummy opening 21 is formed, so that the dummy opening 21 can be formed in the protective layer 2.
  • the dummy opening 21 can extend in the up and down direction and penetrate through the protective layer 2. As shown in FIG. That is, the light is irradiated vertically in the vertical direction, and after development, a dummy opening 21 extending in the vertical direction can be formed in the protective layer 2.
  • a dummy bump 3 can be formed in the dummy opening 21, and the dummy bump 3 is partially located in the protective layer 2 through the dummy opening 21, so that the dummy bump 3 can be fixed by the protective layer 2 to prevent the dummy bump 3 from falling off.
  • a blocking groove 22 may also be formed in the protective layer 2, and the blocking groove 22 is in communication with the dummy opening 21, the dummy bump 3 is formed in the blocking groove 22 and the dummy opening 21, and the dummy bump 3 is blocking A blocking portion 31 is provided in the groove 22. Therefore, the dummy bump 3 can be fixed in the up and down direction by the cooperation of the blocking portion 31 and the blocking groove 22 to further prevent the dummy bump 3 from falling off.
  • a positive photolithography method may be used Perform exposure and development.
  • direct light exposure is used to form the dummy opening 21
  • side light exposure is used to form the blocking groove 22. That is, during the exposure process, the direction of light source (such as UV lamp) can be adjusted to make the development.
  • the irradiation light may include direct light (light along the up and down direction as shown in FIG. 3) and side light.
  • the side light is reflected when it contacts the bottom passivation layer 11, thereby making the protection
  • the part of the bottom of the layer 2 where the blocking groove 22 is formed is irradiated with light, so that after development, the part of the protective layer 2 that forms the dummy opening 21 and the blocking groove 22 is emptied by the developer to remove the glue, thereby forming the dummy opening 21 and blocking ⁇ 22.
  • a negative photolithography method in the step of performing exposure and development of the protective layer 2 and removing part of the protective layer 2 to form the dummy opening 21, a negative photolithography method can be used.
  • the light transmittance of the mask 5 used in the engraving is different, and the light transmittance of the area corresponding to the position where the dummy opening 21 is formed on the mask 5 and the area corresponding to the position where the blocking groove 22 is formed on the mask 5 is different.
  • Ground including: using a preset mask 5 to expose the protective layer 2.
  • the preset mask 5 includes a first area portion 51 and a second area portion 52, and the transmittance of the second area portion 52 is greater than that of the second area.
  • the protective layer 2 corresponding to the first area portion 51 is removed to form a dummy opening 21, and the bottom of the protective layer 2 corresponding to the second area portion 52 is removed to form a blocking groove 22.
  • the opening 21 communicates.
  • the first area portion 51 corresponds to the position where the dummy opening 21 is formed
  • the second area portion 52 corresponds to the position where the blocking groove 22 is formed.
  • the light transmittance of the second area portion 52 is greater than that of the first area.
  • the light transmittance of a region 51 is such that during the exposure process, the intensity of the light reaching the position where the dummy opening 21 is formed and the position where the blocking groove 22 is formed is different, and the light is irradiated on the protective layer 2 through the second region 52 In this way, the intensity of the light on the part of the protective layer 2 forming the blocking groove 22 is weaker than that of the protective layer 2 not covered by the mask 5, so that the light reaching the part of the protective layer 2 where the blocking groove 22 is formed It is not sufficient for cross-linking, so after development, the protective layer 2 is hollowed out at the positions where the dummy opening 21 and the blocking groove 22 are formed.
  • the mask 5 used in the negative photolithography method can be designed using mesh technology, and the second region portion
  • a mask layer 7 is formed on the protective layer 2, and the area corresponding to the mask layer 7 and the dummy opening 21 is exposed and developed to form an electroplating opening 71 communicating with the dummy opening 21; specifically as As shown in Figures 7-9, after the dummy opening 21 is formed in the protective layer 2, glue is applied again to form a mask layer 7 on the upper surface of the protective layer 2.
  • the mask layer 7 covers the upper surface of the protective layer 2 and covers the dummy
  • the opening 21 is then exposed and developed again to form an electroplating opening 71 in the mask layer 7.
  • the electroplating opening 71 is formed above the dummy opening 21 and corresponds to the dummy opening 21.
  • the cross section is the same, so that the plating opening 71 and the dummy opening 21 are correspondingly communicated in the up-down direction.
  • Dummy bumps 3 are formed in the electroplating opening 71 and the dummy opening 21; as shown in FIG. 9, specifically, the electroplating opening 71 and the dummy opening 21 may be electroplated with materials to form the electroplating opening 71 and the dummy opening 21 Dummy bump 3 with matching shape.
  • a copper material may be electroplated in the electroplating opening 71 and the dummy opening 21 to form a copper pillar 72
  • a tin material may be electroplated on the copper pillar 72 to form a solder joint 73.
  • the copper pillar 72 and the solder joint 73 together constitute a dummy bump 3.
  • blocking grooves 22 can be formed on the side of the dummy opening 21.
  • blocking portions 31 can be formed in the blocking grooves 22.
  • the blocking portions 31 are formed as part of the dummy bumps 3.
  • the combination of the dummy bump 3 and the protective layer 2 can further improve the combination strength and prevent falling off.
  • S6 Remove the mask layer 7 to expose the dummy bump 3; specifically, after the electroplating process is completed, the mask layer 7 used to define the electroplating position above the protective layer 2 is removed by a de-handing process through a glue removing solution, so that the dummy bumps Part 3 of the block is exposed to facilitate connection with other components. Further, after the de-glueing process, the solder joint 73 of the dummy bump 3 can be reflowed, so that the structure of the dummy bump 3 is more stable, or the solder joint 73 of the dummy bump 3 can be reflowed before the removal. Glue process.
  • the following steps are performed: S31: on the upper surface of the protective layer 2 And the bottom of the dummy opening 21 by sputtering to form a seed layer 4, as shown in FIGS. 10-11, after removing the mask layer to expose the dummy bumps, the following steps are performed: S7: removing the upper surface of the protective layer 2 The formation of the seed layer4. As shown in FIG. 6, a seed layer 4 is formed at the bottom of the dummy opening 21. The seed layer 4 is located between the dummy bump 3 and the passivation layer 11.
  • the gap between the dummy bump 3 and the passivation layer 11 can be strengthened. Connection strength.
  • an etching method may be used to remove the seed layer 4, for example, dry etching or wet etching may be used.

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Abstract

提供一种半导体器件及其制备方法。半导体器件包括：半导体衬底（1）；钝化层（11），设在半导体衬底（1）的上表面；保护层（2），设在钝化层（11）的上表面，保护层（2）设有虚设开口（21），虚设开口（21）上表面具有第一宽度且该第一宽度小于虚设开口（21）的最大宽度；具有阻断部（31）的虚设凸块（3），部分位于虚设开口（21）内且与保护层（2）紧密贴合。阻断部（31）能够固定虚设凸块（3），防止虚设凸块（3）脱落。

Description

半导体器件及其制备方法
相关申请引用说明
本申请要求于2020年04月10日递交的中国专利申请号202010279566.8，申请名为“半导体器件及其制备方法”的优先权，其全部内容以引用的形式附录于此。
技术领域
本申请涉及半导体封装领域，具体涉及一种半导体器件以及半导体器件的制备方法。
背景技术
相关技术的半导体封装领域中，尤其是涉及铜柱凸块(Copper pillar bump)在倒装封装(Flip chip)技术领域的应用，在倒装封装工艺之前通常会在待封装芯片的保护层上形成虚设凸块(dummy bump)。其中虚设凸块通过现有工艺特别成型在保护层上，相关技术中虚设凸块由于不具有电连接作用，一般形成在保护层的表面，但由于保护层与虚设凸块的材料不同，比如虚设凸块与保护层的基础为金属与高分子材料之间的结合，结合力不是很强，比较容易出现虚设凸块脱落的问题，而且由于虚设凸块与高分子材料之间的结合力较差，也容易发生断裂，导致半导体器件的结构不牢固。
发明内容
为解决上述技术问题，本申请提供了一种半导体器件，所述半导体器件的结构稳定，虚设凸块不易脱落。
根据本申请实施例的半导体器件包括半导体衬底；钝化层，所述钝化层设在所述半导体衬底的上表面；保护层，所述保护层设在所述钝化层的上表面，所述保护层设有虚设开口；虚设凸块，所述虚设凸块部分位于所述虚设开口内且与所述保护层紧密贴合。
根据本申请实施例的半导体器件，通过在保护层内形成虚设开口，虚设凸块至少部分位于虚设开口内且与保护层紧密贴合，不仅可以增加虚设凸块与保护层的接触面积以提高结合力，而且通过虚设开口也可固定虚设凸块，增强虚设凸块与保护层之间固定连接强度，提高虚设凸块与保护层之间的结合强度， 降低虚设凸块脱落的风险。
根据本申请的一些实施例，还包括：至少一个导电凸块，所述半导体衬底上设有导电焊盘，所述钝化层部分覆盖所述导电焊盘，所述导电凸块穿过所述保护层和所述钝化层与所述导电焊盘连接。
根据本申请的一些实施例，所述虚设凸块电镀成型。
根据本申请的一些实施例，所述保护层内形成有与所述虚设开口相通的阻断槽，所述虚设凸块设有阻断部，所述阻断部位于所述阻断槽内。
可选地，所述阻断槽由形成所述虚设开口的部分侧壁朝向远离所述虚设开口的方向凹陷形成。
可选地，所述阻断槽形成为沿所述虚设开口的周向延伸的环形槽。
可选地，所述虚设开口沿上下方向贯穿所述保护层，所述阻断槽形成在所述虚设开口的下端且延伸至所述保护层的下表面。
根据本申请的一些实施例，所述虚设开口贯穿所述保护层，且所述虚设开口的上表面具有第一宽度，所述第一宽度小于所述虚设开口的最大宽度。
根据本申请的一些实施例，所述保护层还覆盖所述钝化层暴露的侧面以及部分覆盖所述导电焊盘。
根据本申请的一些实施例，所述半导体器件还包括：种子层，所述种子层通过溅射形成在所述虚设开口的底部，且位于所述虚设凸块和所述钝化层之间。
本申请还提出了一种半导体器件的制备方法，所述半导体制备方法可用于制备上述实施例的半导体器件。
根据本申请实施例的半导体器件的制备方法，包括以下步骤：提供半导体衬底，所述半导体衬底上表面形成有钝化层；在所述钝化层上形成保护层；对所述保护层进行曝光显影，去除部分所述保护层以形成虚设开口；在所述保护层上形成掩膜层，对所述掩膜与所述虚设开口对应的区域进行曝光显影，以形成与虚设开口连通的电镀开口；在所述电镀开口和虚设开口内形成虚设凸块，去除所述掩膜层以显露所述虚设凸块。
可选地，在去除部分所述保护层形成所述虚设开口后，在所述保护层形成所述掩膜层之前，执行以下步骤：在所述保护层的上表面和虚设开口的底部溅 射形成种子层，在去除所述掩膜层以显露所述虚设凸块后，执行以下步骤：去除所述保护层上表面形成的种子层。
可选地，所述对所述保护层进行曝光显影，去除部分所述保护层以形成虚设开口，包括：采用直射光曝光以形成虚设开口，采用增加侧光曝光以形成阻断槽，所述阻断槽与所述虚设开口相通。
可选地，所述对所述保护层进行曝光显影，去除部分所述保护层以形成虚设开口，包括：采用预设掩膜版对所述保护层进行曝光，所述预设掩膜版包括第一区域部和第二区域部，所述第二区域部的透光度大于所述第一区域部的透光度；去除所述第一区域部对应的保护层以形成虚设开口；去除所述第二区域部对应的所述保护层的底部以形成阻断槽，所述阻断槽与所述虚设开口相通。
进一步地，在所述电镀开口和虚设开口内形成虚设凸块，还包括：在所述阻断槽内形成所述虚设凸块的阻断部。
附图说明
图1是根据本申请一个实施例的半导体器件的结构示意图；
图2-图11是根据本申请实施例的半导体器件的制备方法的各步骤的局部剖视图，其中图3是根据本申请一个实施例的半导体器件的制备方法中对保护层进行曝光显影的部分结构的剖视图，图4是根据本申请另一个实施例的半导体器件的制备方法中对保护层进行曝光显影的部分结构的剖视图；
图12是根据发明另一个实施例的半导体器件的结构示意图；
图13是根据发明又一个实施例的半导体器件的结构示意图；
图14是根据本申请一个实施例的半导体器件的制备方法的流程图；
图15是根据本申请另一个实施例的半导体器件的制备方法的流程图。
附图标记：
100：半导体器件；
1：半导体衬底，11：钝化层，12：导电焊盘；
2：保护层，21：虚设开口，22：阻断槽；
3：虚设凸块，31：阻断部；
4：种子层；
5：掩膜版，51：第一区域部：52：第二区域部；
6：导电凸块；
7：掩膜层；71：电镀开口，72：铜柱，73：焊锡接头。
具体实施方式
以下结合附图和实施例对本申请提出的一种半导体器件作进一步详细说明。
如图1所示，根据本申请实施例的半导体器件100可以包括半导体衬底1、钝化层11、保护层2和虚设凸块3。
如图1所示，钝化层11设在半导体衬底1的上表面，具体地，如图1-图11所示，钝化层11形成在半导体衬底1的上方且覆盖半导体衬底1的上表面，保护层2设在钝化层11的上表面且覆盖钝化层11的上表面，保护层2形成有虚设开口21，其中虚设凸块3能够用于与其它部件连接支撑；虚设凸块3部分位于虚设开口21内且与保护层2紧密贴合，即虚设凸块3部分通过虚设开口21伸入保护层2内且虚设开口21的侧壁紧密连接。如图1以及图10-图13所示，虚设凸块3的下端位于虚设开口21内且与虚设开口21的侧壁相连。
由此相比现有技术中虚设凸块3仅设在保护层2的上表面，虚设凸块3与保护层2之间通过金属和高分子材料的结合力连接，本申请中通过将虚设凸块3至少部分位于虚设开口21内且虚设开口21的侧壁紧密连接，不仅可以增加虚设凸块3与保护层2的接触面积以提高结合力，而且通过虚设开口21也可固定虚设凸块3，增强虚设凸块3与保护层2之间固定连接强度，提高虚设凸块3与保护层2之间的结合强度，降低虚设凸块3脱落的风险。
可选地，如图1所示，半导体器件100还包括至少一个导电凸块6，具体地，半导体衬底1上可设有导电焊盘12，导电焊盘12形成在半导体衬底1的上方，其中，导电焊盘12为金属焊盘，例如可以为铝焊盘或者铝铜焊盘，也可以为其它金属材料。半导体衬底1可以是体硅衬底或者绝缘体上硅衬底，也可以使用其它半导体材料，例如，可以是玻璃衬底或者陶瓷衬底等，对此本申请不做特殊限定。
钝化层11部分覆盖导电焊盘12，具体地，如图1-图11所示，钝化层11形成有开口以暴露出导电焊盘12，钝化层11的一部分可以覆盖导电焊盘12的边缘部分。其中对于钝化层11的材料而言，钝化层11可采用氧化硅、氮化 硅中的一种或者多种制成，例如，钝化层11可以为单层的氧化硅层，或者钝化层11也可以采用氮化硅层和氮化硅层层叠设置形成。
保护层2上设有开口且暴露出导电焊盘12，其中保护层2可覆盖钝化层11暴露的侧面以及部分覆盖导电焊盘12，如图1所示，保护层2和钝化层11内形成有适于导电凸块6穿过且露出导电焊盘12的开口，保护层2形成开口的一部分覆盖导电焊盘12的边缘。或者，保护层2可覆盖钝化层11的上表面，且保护层2形成开口的边缘侧面与钝化层11形成开口的边缘侧面相平齐。
可选地，保护层2可以由光刻胶形成，例如保护层2可以采用负性光刻胶形成也可以采用正性光刻胶形成，进一步地，保护层2可以为由聚酰亚胺形成的PI层，还可以是聚苯并恶唑(polybenzoxazole，PBO)层、苯并环丁烯(benzocyclobutene，BCB)或由其它合适的聚合物形成。具体地，在钝化层11的上表面可涂布光刻胶以形成保护层2，并采用光刻法通过曝光显影刻蚀等工艺形成开口以露出导电焊盘12。
导电凸块6和虚设凸块3均可以为一个或者多个，优选地，导电凸块6和虚设凸块3分别可以为多个，其中导电凸块6可用于与其它部件电连接，多个导电凸块6间隔开设置，每个导电凸块6依次穿过保护层2的开口和钝化层11的开口与导电焊盘12连接。
多个虚设凸块3间隔开设置，虚设凸块3能够用于与其它部件连接支撑，不具有电连接至其它部件的作用，对于虚设凸块3的设置而言，虚设凸块3可以设在半导体器件100与其它部件连接时应力集中的部位，从而有利于半导体器件100与其它部件的连接结合以提高组合后元件的结构性能。
可选地，虚设凸块3电镀成型，换言之，虚设凸块3通过电镀工艺形成在虚设开口21内，从而使得虚设凸块3与保护层2连接更加紧密，能够进一步地增强虚设凸块3和保护层2连接的稳定性，也有利于虚设凸块3的形成。具体地，可通过光刻法在保护层2上曝光显影形成虚设开口21，并通过在保护层2的上方涂胶形成掩膜层7，然后通过再次曝光显影工艺在掩膜层7形成与虚设开口21对应连通的电镀开口71，通过在电镀开口71和虚设开口21内电镀材料以形成虚设凸块3，电镀工艺后进行去胶工艺露出虚设凸块3以形成半导体器件100。传统方式中导电凸块6和虚设凸块3通常是一步电镀同时形成的， 由于虚设凸块6形成的水平位置较高，造成导电凸块6和虚设凸块3两者的高度差较大，与其他部件连接的时候会不平衡，而通过形成阻断部31还能够降低导电凸块6和虚设凸块3的高度差。
可选地，结合图5-图13所示，保护层2内形成有与虚设开口21连通的阻断槽22，虚设凸块3设有阻断部31，阻断部31位于阻断槽22内，通过阻断槽22和阻断部31的配合可在上下方向上固定虚设凸块3，增强虚设凸块3与保护层2之间的上下方向的结合力，防止虚设凸块3从保护层2脱离。具体地，如图3和图4所示，在形成虚设开口21的光刻过程中，可调整光源的强度和方向以在保护层2内形成阻断槽22，在电镀成型虚设凸块3的过程中采用电镀工艺在阻断槽22内形成阻断部31。
在如图1以及图5-图13所示的示例中，阻断槽22可以由形成虚设开口21的部分侧壁朝向远离虚设开口21的方向凹陷形成，具体地，阻断槽22形成在虚设开口21的侧部且与虚设开口21的侧部相连通，虚设凸块3的侧部设有与阻断槽22对应的阻断部31，阻断部31通过电镀成型形成在阻断槽22内，通过阻断槽22和阻断部31的配合可在上下方向上固定虚设凸块3，防止虚设凸块3从保护层2脱离。
进一步地，阻断槽22可以为沿虚设开口21周向延伸的环形槽，阻断部31形成位于环形槽结构匹配的环形形状，如此通过环形的阻断槽22和阻断部31可进一步地提高保护层2和虚设凸块3的结合强度，以进一步地防止虚设凸块3脱落。
可选地，结合图5-图13所示，虚设开口21沿上下方向贯穿保护层2，由此，使得虚设凸块3能够露出保护层2与其它部件连接，也能够进一步地增强虚设凸块3形成在虚设开口21内也能够增强虚设凸块3固定强度。而且结合图3所示，可以在形成在虚设开口21的过程中，通过增加侧光形成阻断槽22，其中侧光接触保护层2底部的钝化层11时发生发射，导致保护层2对应形成阻断槽22的部位被光照射显影后去除，有利于控制光源在光刻过程中形成阻断槽22，形成阻断槽22的方式不限于此。阻断槽22形成在虚设开口21的下端且延伸至保护层2的下表面，即阻断槽22的下端延伸至钝化层11的上表面，这样，阻断部31形成在阻断槽22内，阻断部31位于保护层2的下方，通过 保护层2可防止虚设凸块3脱落。
在本申请的一些示例中，如图13所示，虚设开口21贯穿保护层2，且虚设开口21的上表面具有第一宽度，第一宽度小于虚设开口21的最大宽度，也就是说，虚设开口21沿上下方向的纵截面的宽度不同，虚设开口21的上表面在纵截面上的宽度为第一宽度，其中虚设开口21具有最大宽度的位置低于虚设开口21的上表面，由此虚设开口21可形成上窄下宽的结构，从而可防止虚设凸块3从虚设开口21脱落。例如，虚设开口21可形成为圆台状，虚设开口21沿上下方向的纵截面形成为梯形，虚设开口21的宽度在从上至下的方向上逐渐增大。
在本申请的一些示例中，保护层2还覆盖钝化层11暴露的侧面以及部分覆盖导电焊盘12，在本申请的另一些示例中，保护层2可覆盖钝化层11的上表面且与钝化层11暴露出导电焊盘12的侧面相平齐。
可选地，半导体器件100还可以包括种子层4，如图6所示，种子层4通过溅射形成在虚设开口21的底部，且如图11所示最终形成的半导体器件100中种子层4位于虚设凸块3和钝化层11之间，由此，虚设凸块3的底部至少部分可通过种子层4与钝化层11连接，通过种子层4从而可进一步地增强虚设凸块3底部与钝化层11的结合强度，降低脱落风险。
本申请还提出了一种半导体器件100的制备方法，根据本申请实施例的半导体的制备方法可用于制备上述实施例的半导体器件100。
如图2-图15所示，根据本申请实施例的半导体器件100的制备方法，可以包括以下步骤：
S1：提供半导体衬底1，半导体衬底1上表面形成有钝化层11，其中半导体衬底1的上表面还设有导电焊盘12，钝化层11设在导电焊盘12的上方且钝化层11的一部分覆盖导电焊盘12的边缘，钝化层11上形成有开口以露出导电焊盘12，导电凸块6穿过钝化层11与导电焊盘12连接。
S2：如图2所示，在钝化层11上形成保护层2，具体地可在钝化层11的上表面涂布光刻胶以形成保护层2，例如可以采用光刻胶旋涂机在钝化层11上涂布光刻胶。其中对于光刻胶而言，光刻胶可以为正性光刻胶，例如可以为聚酰亚胺光刻胶，聚酰亚胺光刻胶具有突出的耐热性、良好的力学性能、绝缘 性和抗蚀性，在钝化层11的上方涂布聚酰亚胺光刻胶，可以起到绝缘、抗蚀、缓冲应力及平坦化的作用，同时PI(聚酰亚胺)层本身具有的防护功能和应力缓冲功能很大程度的提高了产品的结构可靠性，也能够保护芯片表面不受应力破坏，并使芯片表面更加平坦，有利于提高后续电镀工艺的均匀性和结合力。保护层2也可以采用负性光刻胶，根据不同的光刻胶可采用不同的掩膜版5进行图形化工艺。
S3：对保护层2进行曝光显影，去除部分保护层2以形成虚设开口21，具体地，可对保护层2进行曝光显影，去除保护层2对应形成所述虚设开口21的区域的部分以形成虚设开口21。如图3-图5所示，可以在保护层2的上方设置掩膜版5，通过掩膜版5对保护层2进行曝光，并通过显影液对光刻胶进行溶解，以去除保护层2形成虚设开口21部位的部分，从而可在保护层2内形成虚设开口21。
如图5所示，虚设开口21可沿上下方向延伸且贯穿保护层2，如图3所示，在进行曝光过程中，光源对准照射掩膜版5，其中光源发出的光可以包括直射光，即光沿上下方向垂直照射，通过显影后从而可在保护层2形成沿上下方向延伸的虚设开口21。在虚设开口21内可形成虚设凸块3，虚设凸块3通过虚设开口21部分位于保护层2内，从而通过保护层2可固定虚设凸块3，防止虚设凸块3脱落。
可选地，保护层2内还可以形成有阻断槽22，阻断槽22与虚设开口21连通，虚设凸块3形成在阻断槽22和虚设开口21内，虚设凸块3在阻断槽22内设有阻断部31。由此，通过阻断部31和阻断槽22的配合可在上下方向固定虚设凸块3，以进一步地防止虚设凸块3脱落。
对于阻断槽22的形成，可选地，在如图3所示的示例中，在执行对保护层2曝光显影，去除部分保护层2以形成虚设开口21中，可采用正性光刻法进行曝光显影，在曝光时，采用直射光曝光以形成虚设开口21，采用侧光曝光以形成阻断槽22，即在曝光过程中，可通过调整光源(例如UV灯)照射的方向以使得显影后形成虚设开口21和阻断槽22。具体地，如图3所示，照射光可以包括直射光(如图3所示的沿上下方向的光)和侧光，侧光照射在接触底部钝化层11时发生反射，由此使得保护层2的底部形成阻断槽22的部分被光 照射，这样在显影后，保护层2形成虚设开口21和阻断槽22的部分通过显影液去胶掏空，从而形成虚设开口21和阻断槽22。
在本申请的另一些示例中，如图4所示，在执行对保护层2曝光显影，去除部分保护层2以形成虚设开口21的步骤中，可采用负性光刻法，在负性光刻中使用的掩膜版5的透光度不同，掩膜版5的与形成虚设开口21位置对应的区域和掩膜版5的形成阻断槽22位置对应的区域的透光度不同，具体地，包括：采用预设掩膜版5对保护层2进行曝光，预设掩膜版5包括第一区域部51和第二区域部52，第二区域部52的透光度大于第二区域部52的透光度，去除第一区域部51对应的保护层2以形成虚设开口21，去除第二区域部52对应的保护层2的底部以形成阻断槽22，阻断槽22与虚设开口21相通。
如图4和图5所示，第一区域部51与形成虚设开口21的位置对应，第二区域部52与形成阻断槽22的位置对应，其中第二区域部52的透光度大于第一区域部51的透光度，这样，在曝光过程中，在到达形成虚设开口21位置和在形成阻断槽22位置的光的强度不同，光通过第二区域部52照射在保护层2上，这样光照在形成阻断槽22的保护层2的部分的强度，相对于掩膜版5未覆盖的保护层2的强度较弱，从而使得到达保护层2形成阻断槽22的部分的光不足以交联，由此在显影后，保护层2形成虚设开口21和阻断槽22位置处被掏空。进一步地在负性光刻法中采用的掩膜版5可使用mesh技术设计，比多将掩模版5的第二区域部52设置为网格状且可由至少两层材料构成。
S4：在所述保护层2上形成掩膜层7，对所述掩膜层7与所述虚设开口21对应的区域进行曝光显影，以形成与虚设开口21连通的电镀开口71；具体地如图7-图9所示，在保护层2内形成虚设开口21后，进行再次涂胶在保护层2的上表面形成掩膜层7，掩膜层7覆盖保护层2的上表面且覆盖虚设开口21，然后通过再次曝光显影在掩膜层7内形成电镀开口71，电镀开口71形成在虚设开口21的上方且与虚设开口21相对应，电镀开口71的横截面与虚设开口21上部的横截面相同，由此电镀开口71和虚设开口21在上下方向上对应连通。
S5：在所述电镀开口71和虚设开口21内形成虚设凸块3；如图9所示，具体地可通过在电镀开口71和虚设开口21内电镀材料以形成与电镀开口71和虚设开口21形状匹配的虚设凸块3。例如，可在电镀开口71和虚设开口21 内电镀铜材料以形成铜柱72，并可在铜柱72的上方电镀锡材料以形成焊锡接头73，铜柱72和焊锡接头73共同构成虚设凸块3。进一步地，曝光显影后在形成虚设开口21的侧部可形成阻断槽22，电镀后在阻断槽22内可形成阻断部31，阻断部31形成为虚设凸块3的一部分，通过虚设凸块3与保护层2的结合能够进一步地提高结合强度，防止脱落。
S6：去除掩膜层7以显露所述虚设凸块3；具体地，电镀完成后，采用去交工艺通过去胶液去除保护层2上方用来限定电镀位置的掩膜层7，使得虚设凸块3部分露出，方便与其它部件连接。进一步地，在进行去胶工艺后还可以对虚设凸块3的焊锡接头73进行回流，使得虚设凸块3结构更加稳定，也可以先对虚设凸块3的焊锡接头73进行回流之后再进行去胶工艺。
在本申请的一些具体实施例中，在去除部分保护层2以形成虚设开口21后，在所述保护层2上形成掩膜层7之前，执行以下步骤：S31：在保护层2的上表面和虚设开口21的底部溅射形成种子层4，如图10-图11所示，在去除所述掩膜层以显露所述虚设凸块后，执行以下步骤：S7：去除保护层2上表面形成的种子层4。如图6所示，虚设开口21的底部形成种子层4，种子层4位于虚设凸块3和钝化层11之间，通过形成种子层4从而可加强虚设凸块3和钝化层11的连接强度。其中在去除保护层2上表面形成的种子层4时可采用刻蚀法刻蚀去除种子层4，例如可以采用干法刻蚀也可以采用湿法刻蚀。
以上所述仅是本申请的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本申请原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本申请的保护范围。

Claims (15)

  1. 一种半导体器件，其中，包括：
    半导体衬底；
    钝化层，所述钝化层设在所述半导体衬底的上表面；
    保护层，所述保护层设在所述钝化层的上表面，所述保护层设有虚设开口；
    虚设凸块，所述虚设凸块部分位于所述虚设开口内且与所述保护层紧密贴合。
  2. 根据权利要求1所述的半导体器件，其中，还包括：至少一个导电凸块，所述半导体衬底上设有导电焊盘，所述钝化层部分覆盖所述导电焊盘，所述导电凸块穿过所述保护层和所述钝化层与所述导电焊盘连接。
  3. 根据权利要求1所述的半导体器件，其中，所述虚设凸块电镀成型。
  4. 根据权利要求1所述的半导体器件，其中，所述保护层内形成有与所述虚设开口相通的阻断槽，所述虚设凸块设有阻断部，所述阻断部位于所述阻断槽内。
  5. 根据权利要求4所述的半导体器件，其中，所述阻断槽由形成所述虚设开口的部分侧壁朝向远离所述虚设开口的方向凹陷形成。
  6. 根据权利要求4所述的半导体器件，其中，所述阻断槽形成为沿所述虚设开口的周向延伸的环形槽。
  7. 根据权利要求4所述的半导体器件，其中，所述虚设开口沿上下方向贯穿所述保护层，所述阻断槽形成在所述虚设开口的下端且延伸至所述保护层的下表面。
  8. 根据权利要求1所述的半导体器件，其中，所述虚设开口贯穿所述保护层，且所述虚设开口的上表面具有第一宽度，所述第一宽度小于所述虚设开口的最大宽度。
  9. 根据权利要求2所述的半导体器件，其中，所述保护层还覆盖所述钝化层暴露的侧面以及部分覆盖所述导电焊盘。
  10. 根据权利要求1所述的半导体器件，其中，还包括：种子层，所述种子层溅射形成在所述虚设开口的底部，且位于所述虚设凸块和所述钝化层之间。
  11. 一种半导体器件的制备方法，其中，包括：
    提供半导体衬底，所述半导体衬底上表面形成有钝化层；
    在所述钝化层上形成保护层；
    对所述保护层进行曝光显影，去除部分所述保护层以形成虚设开口；
    在所述保护层上形成掩膜层，对所述掩膜层与所述虚设开口对应的区域进行曝光显影，以形成与虚设开口连通的电镀开口；
    在所述电镀开口和虚设开口内形成虚设凸块；
    去除所述掩膜层以显露所述虚设凸块。
  12. 根据权利要求11所述的半导体器件的制备方法，其中，在去除部分所述保护层以形成所述虚设开口后，在所述保护层上形成所述掩膜层之前，执行以下步骤：在所述保护层的上表面和所述虚设开口的底部溅射形成种子层；
    在去除所述掩膜层以显露所述虚设凸块之后，执行以下步骤：
    去除所述保护层上表面形成的种子层。
  13. 根据权利要求11所述的半导体器件的制备方法，其中，所述对所述保护层进行曝光显影，去除部分所述保护层以形成虚设开口，包括：
    采用直射光曝光以形成虚设开口，采用增加侧光曝光以形成阻断槽，所述阻断槽与所述虚设开口相通。
  14. 根据权利要求11所述的半导体器件的制备方法，其中，所述对所述保护层进行曝光显影，去除部分所述保护层以形成虚设开口，包括：
    采用预设掩膜版对所述保护层进行曝光，所述预设掩膜版包括第一区域部和第二区域部，所述第二区域部的透光度大于所述第一区域部的透光度；
    去除所述第一区域部对应的保护层以形成虚设开口；
    去除所述第二区域部对应的所述保护层的底部以形成阻断槽，所述阻断槽与所述虚设开口相通。
  15. 根据权利要求13所述的半导体器件的制备方法，其中，在所述电镀开口和虚设开口内形成虚设凸块，还包括：
    在所述阻断槽内形成所述虚设凸块的阻断部。
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