WO2021196986A1 - 一种存储卡、识别方法和电子设备 - Google Patents

一种存储卡、识别方法和电子设备 Download PDF

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Publication number
WO2021196986A1
WO2021196986A1 PCT/CN2021/079575 CN2021079575W WO2021196986A1 WO 2021196986 A1 WO2021196986 A1 WO 2021196986A1 CN 2021079575 W CN2021079575 W CN 2021079575W WO 2021196986 A1 WO2021196986 A1 WO 2021196986A1
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WO
WIPO (PCT)
Prior art keywords
card
terminal
differential data
memory card
electrical connection
Prior art date
Application number
PCT/CN2021/079575
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English (en)
French (fr)
Inventor
王先进
许仲杰
Original Assignee
荣耀终端有限公司
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Publication date
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Publication of WO2021196986A1 publication Critical patent/WO2021196986A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/0772—Physical layout of the record carrier
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K7/00—Methods or arrangements for sensing record carriers, e.g. for reading patterns
    • G06K7/0013—Methods or arrangements for sensing record carriers, e.g. for reading patterns by galvanic contacts, e.g. card connectors for ISO-7816 compliant smart cards or memory cards, e.g. SD card readers
    • G06K7/0052—Methods or arrangements for sensing record carriers, e.g. for reading patterns by galvanic contacts, e.g. card connectors for ISO-7816 compliant smart cards or memory cards, e.g. SD card readers connectors capable of contacting cards of different formats, e.g. memory stick and SD card readers sharing at least one connector contact and the associated signal line, e.g. both using the same signal line for input or output of data

Definitions

  • This application relates to the technical field of electronic devices, and in particular to a memory card, an identification method, and an electronic device.
  • a memory card is a device that can be used to expand the storage space of an electronic device.
  • the memory card includes a memory card body and a memory card interface arranged on the memory card body.
  • the memory card body includes a packaging material and a control unit and a storage unit arranged in the packaging material.
  • the memory card interface includes a plurality of terminals (such as data The transmission terminal, the ground terminal, the power terminal and the clock terminal), the control unit and the storage unit are electrically connected, and the control unit and the memory card interface are also electrically connected.
  • the multiple terminals of the memory card interface are in contact with the multiple card socket terminals of the card socket to electrically connect the memory card body and the electronic device host.
  • the device host can perform read and write operations on the storage unit in the storage card body.
  • the read and write speed and board area of the memory card are two important indicators of the memory card.
  • UFS universal flash storage
  • the UFS card 01 supports the UFS protocol, and the UFS card 01 includes a card body 011 and an interface 012.
  • the card body 011 includes a packaging material and a storage unit and a control unit arranged in the packaging material, and the storage unit is electrically connected to the control unit.
  • the interface 012 is set on the card body 011.
  • the interface 012 includes 12 terminals, which are C/D 0121, VCCQ2 0122, REF_CLK 0123, VSS 0124, DOUT_T 0125, DOUT_C 0126, VCC 0127, VSS 0128, VSS 0129 , DIN_T 0130, DIN_C 0131 and VSS 0132.
  • the labels, names and definitions of the 12 terminals are shown in Table 1 below.
  • the UFS card uses a pair of differential data output terminals (that is, DOUT_T 0125 and DOUT_C 0126) and a pair of differential data input terminals (that is, DIN_T 0130 and DIN_C 0131) to perform differential serial data transmission with the electronic device host.
  • the transmission speed of the line data transmission method is faster, and the read and write speed of the memory card is faster.
  • the UFS card interface includes more terminals, up to 12, the UFS card's footprint (11mm ⁇ 15mm) and large volume (11mm ⁇ 15mm ⁇ 1mm) cannot be compared with the micro memory (nano memory). , NM) the card sockets of the card match.
  • the embodiments of the present application provide a memory card, an identification method, and an electronic device, which can reduce the area and volume of the memory card while ensuring the read and write speed of the memory card, so that the memory card can be compatible with the card socket of the NM card. match.
  • some embodiments of the present application provide a memory card, which includes a memory card body and a memory card interface; the shape and size of the memory card body and the NM card body are the same; the memory card interface is set in the storage On the card body, and the memory card interface includes a pair of differential data input terminals, a pair of differential data output terminals, a power supply terminal, a ground terminal, and a clock terminal.
  • a pair of differential data input terminals includes a first differential data input terminal and a second differential data input terminal. Differential data input terminals.
  • the pair of differential data input terminals are used to transmit the differential data input to the memory card body.
  • the pair of differential data output terminals includes a first differential data output terminal and a second differential data output terminal.
  • the data output terminal is used to transmit the differential data output by the memory card body, the power terminal is used for power supply, the ground terminal is used for grounding, and the clock terminal is used for transmitting clock signals; the first differential data input terminal, the second differential data input
  • the setting positions of the terminal, the first differential data output terminal, the second differential data output terminal, the power terminal, the ground terminal and the clock terminal on the memory card body are respectively the same as DAT1, COM, GND, DAT3, DAT2, VCC, DAT0 and CLK. Seven of them correspond to the setting positions on the card body of the NM card.
  • the memory card interface of the memory card includes a pair of differential data input terminals and a pair of differential data output terminals, and the pair of differential data input terminals are used for transmission to the memory card body.
  • Input differential data the pair of differential data output terminals is used to transmit the differential data output by the card body of the memory card, so after the memory card is inserted into the card socket of the electronic device host, the memory card can use the pair of differential data input terminals and The pair of differential data output terminals perform differential serial data transmission with the electronic device host.
  • the differential serial data transmission method has high accuracy and high transmission speed, and can ensure the read and write speed of the memory card.
  • the length of the NM card is 8.8mm
  • the width is 12.3mm
  • the thickness is 0.84mm.
  • the board area of the NM card is 8.8mm ⁇ 12.3mm.
  • the volume of the NM card is 8.8mm ⁇ 12.3mm ⁇ 0.84mm, which is smaller than the UFS card in the prior art. It also has a pair of differential data input terminals, a pair of differential data output terminals, power terminals, ground terminals, and The size of the clock terminal is small and basically negligible.
  • the memory card provided by the embodiment of the present application has a smaller footprint and a smaller footprint than a UFS card in the prior art, which can reduce the size of the memory card in the electronic device. Occupied space and board area in the host.
  • the location of a pair of differential data input terminals, a pair of differential data output terminals, power terminals, ground terminals and clock terminals on the memory card body Corresponding to the setting positions of seven of DAT1, COM, GND, DAT3, DAT2, VCC, DAT0 and CLK on the card body of the NM card, so the memory card can match the card socket of the NM card.
  • the memory card body includes a packaging structure and a control unit and a storage unit arranged in the packaging structure.
  • the power supply voltage supplied by the power supply terminal is equal to the working voltage of the storage unit, and the power supply voltage supplied by the power supply terminal is equal to the working voltage of the storage unit.
  • the working voltage of the control unit is not equal, the power terminal is directly electrically connected to the storage unit, and the electrical connection line between the power terminal and the control unit is connected in series with a voltage regulating device.
  • the voltage regulating device is used to regulate the power supply voltage supplied by the power terminal To be equal to the operating voltage of the control unit.
  • the operating voltage of the control unit is 1.8V.
  • the operating voltage of the storage unit is 3.0V.
  • the voltage regulating device is a low-dropout linear regulator.
  • This structure is simple and easy to implement.
  • the first differential data input terminal is arranged adjacent to the second differential data input terminal; the first differential data output terminal is arranged adjacent to the second differential data output terminal.
  • the environment of the first differential data input terminal and the second differential data input terminal is approximately the same, and the environment of the first differential data output terminal and the second differential data output terminal are approximately the same, and the external interference received is approximately equal. Cancel each other to ensure the accuracy of the input signal and output signal transmission.
  • the setting position of the first differential data input terminal on the card body of the memory card corresponds to the setting position of one of DAT1 and COM on the card body of the NM card
  • the second differential data input terminal is on the card body of the memory card.
  • the setting position on DAT1 and COM corresponds to the setting position of the other of DAT1 and COM on the card body of the NM card.
  • the setting position of the first differential data input terminal on the memory card body corresponds to the setting position of one of DAT0 and CLK on the NM card body
  • the second differential data input terminal is on the memory card body.
  • the setting position corresponds to the setting position of the other of DAT0 and CLK on the card body of the NM card.
  • the setting position of the first differential data output terminal on the card body of the memory card corresponds to the setting position of one of DAT0 and CLK on the card body of the NM card
  • the second differential data output terminal is on the card body of the memory card.
  • the setting position on DAT0 and CLK corresponds to the setting position of the other of DAT0 and CLK on the card body of the NM card.
  • the setting position of the first differential data output terminal on the memory card body corresponds to the setting position of one of DAT1 and COM on the NM card body
  • the second differential data output terminal is on the memory card body.
  • the setting position corresponds to the setting position of the other of DAT1 and COM on the card body of the NM card.
  • the distance between DAT1 and COM and the distance between DAT0 and CLK are relatively short. Therefore, the distance between the first differential data output terminal and the second differential data output terminal is relatively short.
  • the environment of the data output terminals is approximately the same, and the external interference received is approximately equal, which can cancel each other to further ensure the accuracy of the output signal transmission.
  • the memory card body includes a packaging structure, a control unit and a reference ground arranged in the packaging structure.
  • the encapsulation structure includes a first encapsulation layer and a second encapsulation layer that are stacked, the memory card interface is arranged on the first encapsulation layer, and the control unit and the reference ground are arranged on the second encapsulation layer.
  • the control unit has a pair of differential data input pins and a pair of differential data output pins. A pair of differential data input pins are electrically connected to a pair of differential data input terminals of the memory card interface, and the electrical connection line between a pair of differential data input pins and a pair of differential data input terminals of the memory card interface is the first electrical connection line.
  • a pair of differential data output pins are electrically connected to a pair of differential data output terminals of the memory card interface, and the electrical connection line between a pair of differential data output pins and a pair of differential data output terminals of the memory card interface is a second electrical connection.
  • the reference ground is electrically connected to the ground terminal of the memory card interface, and the electrical connection line between the reference ground and the ground terminal is the third electrical connection line.
  • the connection lines are the first group of third electrical connection lines, the second group of third electrical connection lines, and the third group of third electrical connection lines.
  • the first set of third electrical connection lines pass between the first electrical connection line and the second electrical connection line, and pass between a pair of differential data input terminals and a pair of differential data output terminals.
  • the second group of third electrical connection lines pass through the first electrical connection line away from the side of the second electrical connection line, and pass through the pair of differential data input terminals away from the side of the pair of differential data output terminals.
  • the third group of third electrical connection lines pass through the second electrical connection line away from the side of the first electrical connection line, and pass through the pair of differential data output terminals away from the side of the pair of differential data input terminals.
  • the isolation between a pair of differential data input terminals and a pair of differential data output terminals and between the first electrical connection line and the second electrical connection line can be achieved through the first set of third electrical connection lines, avoiding this one.
  • Mutual interference occurs between the pair of differential data input terminals and the pair of differential data output terminals, and between the first electrical connection line and the second electrical connection line.
  • a pair of differential data input terminals, a pair of differential data output terminals, a first electrical connection line, and a second electrical connection line and the memory card are realized through the second group of third electrical connection lines and the third group of third electrical connection lines.
  • the isolation between the external environment reduces the interference of the external environment noise on the pair of differential data input terminals, the pair of differential data output terminals, the first electrical connection line and the second electrical connection line.
  • control unit also has a ground pin.
  • the number of the ground pins is multiple, and the multiple ground pins include a first ground pin, a second ground pin, and a third ground pin.
  • the first ground pin, the second ground pin, and the third ground pin The pins are electrically connected to the reference ground.
  • the first ground pin is arranged between a pair of differential data input pins and a pair of differential data output pins, and the electrical connection line between the first ground pin and the reference ground is located between the first electrical connection line and the second electrical connection Between the lines.
  • the second ground pin is arranged on the side of the pair of differential data input pins away from the pair of differential data output pins, and the electrical connection line between the second ground pin and the reference ground is located at the first electrical connection line away from the second electrical connection line.
  • the third ground pin is arranged on the side of the pair of differential data output pins away from the pair of differential data input pins, and the electrical connection line between the third ground pin and the reference ground is located at the second electrical connection line away from the first One side of the electrical connection line.
  • the first electrical connection line between a pair of differential data input pins and a pair of differential data output pins and the first electrical connection line between a pair of differential data input pins and a pair of differential data output pins can be realized through the first ground pin and the electrical connection line between the first ground pin and the reference ground.
  • the isolation from the second electrical connection line prevents mutual interference between the pair of differential data input pins and the pair of differential data output pins and between the first electrical connection line and the second electrical connection line.
  • a pair of differential data input pins, a pair of differential data output pins, a first electrical connection line, a second electrical connection line, and the external environment of the memory card are realized through the second ground pin and the third ground pin.
  • the isolation of the external environment reduces the interference of the pair of differential data input pins, the pair of differential data output pins, the first electrical connection line and the second electrical connection line.
  • the location of the ground terminal on the card body of the memory card corresponds to the location of the GND on the card body of the NM card. Since the GND of the NM card is set on the NM card body at a position corresponding to the GND of the Nano SIM card on the card body of the Nano SIM card, the ground terminal, the GND of the NM card and the GND of the Nano SIM card correspond to the GND of the Nano SIM card. They are all used for grounding.
  • the card socket terminal used to contact the GND of the Nano SIM card, the ground terminal of the memory card or the GND of the NM card does not need to be connected to the Nano SIM card controller,
  • the memory card controller or the NM card controller is connected, in this way, the circuit complexity of the circuit board can be reduced, and the cost can be saved.
  • the position of the power terminal on the card body of the memory card corresponds to the position of the VCC on the card body of the NM card. Since the setting position of the VCC of the NM card on the body of the NM card corresponds to the setting position of the VCC of the Nano SIM card on the body of the Nano SIM card, and the power terminal, the VCC of the NM card and the VCC of the Nano SIM card are all It is used for power supply. Therefore, in the card socket interface of the electronic device, the card socket terminal used to contact the VCC of the Nano SIM card, the power terminal of the memory card or the VCC of the NM card does not need to be connected to the Nano SIM card controller and storage through a switch. The card controller or the NM card controller is connected, in this way, the circuit complexity of the circuit board can be reduced, and the cost can be saved.
  • the first differential data input terminal, the second differential data input terminal, the first differential data output terminal, the second differential data output terminal, the power supply terminal, the ground terminal, and the clock terminal are arranged at positions on the memory card body respectively Correspond to the setting positions of DAT1, COM, GND, DAT2, VCC, DAT0, and CLK on the card body of the NM card.
  • the correspondence here is not a one-to-one correspondence, but an arbitrary correspondence.
  • the detection terminal is an independent terminal, that is, there is no power between the detection terminal and the internal circuit of the memory card. Connected and not electrically connected to other terminals of the memory card.
  • the setting position of the DAT3 of the NM card on the body of the NM card corresponds to the setting position of the GND of the Nano SIM card on the body of the Nano SIM card
  • the Nano SIM card and the memory card provided in the embodiment of the application can both be It matches the card socket of the NM card. It is assumed that the card socket terminal on the NM card socket for contacting the DAT3 of the NM card is the first card socket terminal. Therefore, after inserting the card into the card socket, you can confirm with the The terminals contacted by the terminals of the first card socket are GND, DAT3, or there is no terminal contact, so as to achieve the purpose of identifying the Nano SIM card, the memory card provided in the embodiment of the present application, and the NM card.
  • an embodiment of the present application provides a method for identifying a Nano SIM card, an NM card, and the memory card described in the last technical solution in the first aspect through a card socket
  • the card socket includes a card socket body and a card socket interface
  • the main body of the card socket is surrounded by a card slot, which is used to accommodate the card body of the NM card.
  • the card socket interface is arranged on the inner wall of the card slot.
  • the DAT1, COM, GND, DAT3, DAT2, VCC, DAT0, and CLK of the NM card are in contact with each other, and the card holder terminal used to contact DAT3 among the eight card holder terminals is the first card holder terminal.
  • the method includes:
  • S200 Determine whether the terminal is a ground terminal or a signal terminal, or that no terminal is in contact with the first card socket terminal;
  • an embodiment of the present application provides an electronic device for performing the method of identifying a Nano SIM card, an NM card, and the memory card described in the last technical solution in the first aspect through a card holder described in the second aspect
  • the electronic device includes a card socket and a circuit board;
  • the card socket includes a card socket main body and a card socket interface, the card socket body encloses a card slot, the card socket interface is arranged on the inner wall of the card slot, the card socket interface has eight card sockets
  • the eight card socket terminals are used to contact DAT1, COM, GND, DAT3, DAT2, VCC, DAT0 and CLK of the NM card.
  • the card socket terminal used to contact DAT3 among the eight card socket terminals is the first card Socket terminal;
  • the circuit board includes a Nano SIM card controller, a memory card controller, an NM card controller, a switch, a detection circuit, and a control circuit.
  • the switch has a first end, a second end, a third end, and a fourth end. The second end is electrically connected to the Nano SIM card controller, the third end is electrically connected to the memory card controller, the fourth end is electrically connected to the NM card controller, and the detection circuit is used to detect The terminal contacted by the card socket terminal.
  • the control circuit is used to identify the card installed in the card slot as a Nano SIM card, memory card or NM card according to the detection result of the detection circuit, and control the first end of the switch to connect according to the identification result
  • the second end of the switch, or the first end of the control switch is connected to the third end of the switch, or the first end of the control switch is connected to the fourth end of the switch.
  • the control circuit in the electronic device provided by the embodiment of the present application can detect the terminal contacting the terminal of the first card holder through the detection circuit, and according to the detection result of the detection circuit, identify the card installed in the card slot as a Nano SIM card, Memory card or NM card, and according to the identification result, the first end of the control switch is connected to the second end of the switch, or the first end of the control switch is connected to the third end of the switch, or the first end of the control switch is connected to the fourth end of the switch Therefore, a Nano SIM card, a memory card, or an NM card can be installed in the card holder of the electronic device provided in the embodiments of the present application, and the corresponding process of the Nano SIM card, memory card, or NM card can be executed, so as to pass a card
  • the holder is compatible with Nano SIM cards, memory cards or NM cards.
  • Figure 1 (a) is a schematic diagram of the front structure of a UFS card provided in the prior art
  • Figure 1(b) is a schematic diagram of the back structure of the UFS card shown in Figure 1(a);
  • Figure 2 (a) is a schematic diagram of the front structure of the NM card
  • Figure 2 (b) is a schematic diagram of the back structure of the NM card
  • Figure 3(a) is a schematic diagram of the front structure of NanoSIM
  • Figure 3(b) is a schematic diagram of the back structure of NanoSIM
  • Figure 4 is a diagram of the correspondence between the setting positions of the terminals of the NM card and the setting positions of the terminals of the Nano SIM;
  • FIG. 5 is a schematic structural diagram of an electronic device provided by some embodiments of the application.
  • FIG. 6(a) is a schematic diagram of the front structure of a memory card provided by some embodiments of the application.
  • Figure 6(b) is a schematic diagram of the back structure of a memory card provided by some embodiments of the application.
  • FIG. 7 is a structural block diagram of a memory card provided by some embodiments of the application.
  • FIG. 8 is a schematic diagram of the internal structure of a memory card provided by some embodiments of the application.
  • FIG. 9 is a schematic structural diagram of an electronic device provided by some embodiments of the application.
  • FIG. 10 is a flowchart of a method for identifying a Nano SIM card, an NM card, and the memory card shown in FIG. 6(a) through a card holder provided by some embodiments of the application;
  • FIG. 11 is a schematic structural diagram of a detection circuit used in a method for identifying a Nano SIM card, an NM card, and a memory card shown in FIG. 6(a) through a card holder provided by some embodiments of the application.
  • 01-UFS card 011-card body; 012-interface; 0121-C/D; 0122-VCCQ2; 0123-REF_CLK; 0124-VSS; 0125-DOUT_T; 0126-DOUT_C; 0127-VCC; 0128-VSS; 0129- VSS; 0130-DIN_T; 0131-DIN_C; 0132-VSS; 02-NM card; 021- card body; 022-interface; 0221-DAT1; 0222-COM; 0223-GND; 0224-DAT3; 0225-DAT2; 0226 VCC; 0227-DAT0; 0228-CLK; 03-Nano SIM card; 031-card body; 032-interface; 0321-I/O; 0322-VPP; 0323-GND; 0324-VCC; 0325-RST; 0326-CLK ;1-electronic device host;11-circuit board;111-Nano SIM card controller;112-memory
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features.
  • the features defined with “first” and “second” may explicitly or implicitly include one or more of these features.
  • the embodiment of this application relates to a memory card and an electronic device.
  • the following introduces the memory card and subscriber identity module (SIM) card mentioned in the embodiment of this application:
  • the nano memory (NM) card is an ultra-micro memory card created by Huawei Technologies Co., Ltd. Refer to Figure 2(a) and Figure 2(b) for the structure of the NM card. As shown in Figure 2(a) and Figure 2(b), the length of the NM card 02 is 8.8mm, the width is 12.3mm, and the thickness is 0.84mm.
  • the NM card 02 includes a card body 021 and an interface 022.
  • the interface 022 is arranged on the card body 021.
  • the interface 022 includes 8 terminals, which are DAT1 0221, COM 0222, GND 0223, DAT3 0224, DAT2 0225, VCC 0226, DAT0 0227, and CLK 0228.
  • Figure 2(a) The labels, names and definitions of the 8 terminals are shown in Table 2 below, and the positions of the 8 terminals are shown in Figure 2(a). It should be noted that Figure 2(a) only shows the locations of the 8 terminals DAT1 0221, COM 0222, GND 0223, DAT3 0224, DAT2 0225, VCC 0226, DAT0 0227, and CLK 0228 on the card body 021. As an example, the positions of the 8 terminals on the card body 021 can also be other positions, and Figure 2(a) does not limit the application.
  • Terminal label Terminal name Terminal definition 0221 DAT1 Data terminal 1 0222 COM Command terminal 0223 GND Ground terminal 0224 DAT3 Data terminal 3 0225 DAT2 Data terminal 2 0226 VCC Power terminal 0227 DAT0 Data terminal 0 0228 CLK Clock terminal
  • the nano subscriber identity module (Nano SIM) card is a mobile phone micro-SIM card, which is smaller than the Micro-SIM card and has only 60% of the area of the first-generation SIM card.
  • the Nano SIM card 03 includes a card body 031 and an interface 032, and the interface 032 is provided on the card. On the body 031, the interface 032 includes 6 terminals. The 6 terminals are I/O 0321, VPP 0322, GND 0323, VCC 0324, RST 0325 and CLK 0326.
  • Table table 3 For the label, name and definition of the 6 terminals, see the following table table 3.
  • Terminal label Terminal name Terminal definition 0321 I/O Input and output terminals 0322 VPP Program voltage terminal 0323 GND Ground terminal 0324 VCC Supply voltage terminal 0325 RST Reset terminal 0326 CLK Clock terminal
  • the shape and size of the card body 021 of the aforementioned NM card and the card body 031 of the aforementioned Nano SIM card are the same.
  • the setting position of the DAT1 0221 of the NM card on the card body 021 of the NM card corresponds to the setting position of the I/O 0321 of the Nano SIM card on the card body 031 of the Nano SIM card.
  • the installation position of the COM 0222 of the NM card on the card body 021 of the NM card corresponds to the installation position of the VPP 0322 of the Nano SIM card on the card body 031 of the Nano SIM card.
  • the location of the GND 0223 of the NM card on the card body 021 of the NM card corresponds to the location of the GND 0323 of the Nano SIM card on the card body 031 of the Nano SIM card.
  • the setting position of the DAT3 0224 of the NM card on the card body 021 of the NM card corresponds to the setting position of the GND 0323 of the Nano SIM card on the card body 031 of the Nano SIM card.
  • the setting position of the DAT2 0225 of the NM card on the card body 021 of the NM card corresponds to the setting position of the VCC 0324 of the Nano SIM card on the card body 031 of the Nano SIM card.
  • the setting position of the VCC 0226 of the NM card on the card body 021 of the NM card corresponds to the setting position of the VCC 0324 of the Nano SIM card on the card body 031 of the Nano SIM card.
  • the setting position of the DAT0 0227 of the NM card on the card body 021 of the NM card corresponds to the setting position of the RST 0325 of the Nano SIM card on the card body 031 of the Nano SIM card.
  • the setting position of the CLK 0228 of the NM card on the card body 021 of the NM card corresponds to the setting position of the CLK 0326 of the Nano SIM card on the card body 031 of the Nano SIM card.
  • the corresponding relationship between the setting positions of the various terminals is referred to FIG. 4, and it can be seen from the corresponding relationship between the setting positions of these terminals that the Nano SIM card 03 can be matched with the card holder of the NM card 02.
  • the read and write speed of a memory card is an important indicator that affects the performance of the memory card.
  • electronic devices such as mobile phones and tablet computers tend to become thinner and have diversified functions
  • the space for installing memory cards in electronic devices is increasing.
  • the size and footprint of memory cards tend to be smaller and smaller.
  • the electronic device includes, but is not limited to, mobile phones, tablets, wearable devices, etc., including memory cards. device of.
  • FIG. 5 is a schematic structural diagram of an electronic device provided by some embodiments of the application.
  • the electronic device 1 includes a circuit board 11 and a card holder 12 provided on the circuit board 11.
  • the card socket 12 includes a card socket main body 121 and a card socket interface (not shown in the figure), and the card socket interface is electrically connected to the circuit board 11.
  • Some embodiments of the present application also provide a memory card 2, the memory card 2 supports the UFS card protocol, and the memory card 2 can be installed in the card socket 12 of the electronic device 1 for use, so as to expand the storage of the electronic device 1 space.
  • FIG. 6(a) and 6(b) are schematic diagrams of the structure of the memory card 2 provided by some embodiments of the application. As shown in FIG. 6(a) and FIG. 6(b), the memory card 2 includes a memory card body 21 and a memory card interface 22.
  • FIG. 6(a) shows eight terminals 221-228 corresponding to the eight terminal positions of the NM card 02.
  • the position of terminal 221 corresponds to terminal 0221
  • the position of terminal 222 corresponds to terminal 0222
  • the position of terminal 223 corresponds to terminal 0228
  • the position of terminal 224 corresponds to terminal 0227
  • the position of terminal 225 corresponds to terminal 0226
  • the position of terminal 226 corresponds to terminal 0223
  • terminal 227 The position of corresponds to terminal 0225
  • the position of terminal 228 corresponds to terminal 0224.
  • the memory card body 21 has the same shape and size as the card body 021 of the NM card 02 shown in FIGS. 2(a) and 2(b), and the memory card body 21 is the same as FIGS. 3(a) and 3(b)
  • the appearance and size of the card body 031 of the Nano SIM card shown are also the same.
  • the length of the NM card 02 is 8.8mm
  • the width is 12.3mm
  • the thickness is 0.84mm.
  • the board area of the NM card 02 is 8.8mm ⁇ 12.3mm
  • the volume of the NM card 02 is 8.8mm ⁇ 12.3mm ⁇ 0.84mm, which is smaller than the UFS card in the prior art and has a smaller footprint and volume
  • the size of the memory card interface 22 is small, which can be basically ignored.
  • the volume and board area of the memory card provided by the application embodiments are smaller than those of the UFS card in the prior art, which can reduce the memory card's occupied space and board area in the electronic device host.
  • FIG. 7 is a structural block diagram of a memory card 2 provided by some embodiments of the application.
  • the memory card body 21 includes a packaging structure 211 and a storage unit 212, a control unit 213, and a reference ground 215 arranged in the packaging structure 211.
  • the storage unit 212 is electrically connected to the control unit 213, and the storage unit 212 is connected to the storage unit 212.
  • the reference ground 215 is electrically connected, and the control unit 213 is electrically connected to the reference ground 215.
  • the packaging structure 211 is used to electrically connect the storage unit 212, the control unit 213, the reference ground 215, between the storage unit 212 and the control unit 213, between the storage unit 212 and the reference ground 215, and between the control unit 213 and the reference ground 215.
  • the circuit is encapsulated to protect the storage unit 212, the control unit 213, and the electrical connection circuit between the storage unit 212 and the control unit 213.
  • the material of the packaging structure 211 is a dielectric material, which includes but is not limited to ethylene-vinyl acetate (EVA), polyvinyl butyral (PVB), ionomers, and polyolefins. (polyolefins, PO), silicon, thermoplastic polyurethane and other materials.
  • the memory card interface 22 is provided on the memory card body 21, and the memory card interface 22 includes a pair of differential data input terminals and a pair of differential data output terminals.
  • the pair of differential data input terminals includes a first differential data input terminal and a second differential data input terminal, and the pair of differential data input terminals is used to transmit differential data input to the memory card body 21.
  • the pair of differential data output terminals includes a first differential data output terminal and a second differential data output terminal, and the pair of differential data output terminals is used to transmit the differential data output by the memory card body 21.
  • the first differential data input terminal, the second differential data input terminal, the first differential data output terminal, and the second differential data output terminal 224 are all electrically connected to the control unit 213 of the memory card body 21 (as shown in FIG. 7).
  • the first differential data input terminal, the second differential data input terminal, the first differential data output terminal, and the second differential data output terminal may be arranged on the memory card body 21 at different positions. There are many types. These 4 terminals can be any of the terminals 221-228.
  • Figure 6(a) only shows the memory card body 21.
  • the first differential data input terminal is the terminal 221 and the second differential data input
  • the terminal is an example of the terminal 222
  • the first differential data output terminal is the terminal 223
  • the second differential data output terminal is the terminal 224, which should not be considered as a limitation to the foregoing embodiment.
  • the pair of differential data input terminals is used to transmit the differential data input to the memory card body 21
  • the pair of differential data output terminals is used to transmit the differential data output by the memory card body 21, so after the memory card 2 is inserted into the card holder 12 of the electronic device 1, the memory card 2 can use the pair of differential data input terminals and
  • the pair of differential data output terminals performs differential serial data transmission with the electronic device 1.
  • the differential serial data transmission method has higher accuracy and faster transmission speed, which can ensure the reading and writing speed of the memory card 2.
  • the memory card interface 22 further includes a power terminal 225.
  • the power terminal 225 is electrically connected to the storage unit 212 and the control unit 213 (as shown in FIG. 7) of the memory card body 21, and the power terminal 225 is used to supply power to the storage unit 212 and the control unit 213.
  • the power supply terminal can have multiple positions on the memory card body 21, for example, it can be any one of the terminals 221-228.
  • Figure 6(a) only shows the power supply.
  • the location of the terminal on the memory card body 21 is an example of the terminal 225, and it should not be considered as a limitation to the foregoing embodiment.
  • the memory card interface 22 of the memory card 2 Compared with the two power terminals (VCCQ2 0122 and VCC 0127) used on the UFS card 01 for power supply (as shown in Figure 1(a)), the memory card interface 22 of the memory card 2 provided in the embodiment of the application uses one power supply
  • the terminal 225 provides power, and the number of power terminals is small, which can reduce the shape and size of the memory card body 21 to be the same as the shape and size of the card body 021 of the NM card 02.
  • the memory card interface 22 further includes a ground terminal 226.
  • the ground terminal 226 is electrically connected to the reference ground 215 (as shown in FIG. 7), and the ground terminal 226 is used for grounding.
  • the grounding terminal can be arranged in multiple positions on the memory card body 21, for example, it can be any one of the terminals 221-228.
  • Figure 6(a) only shows the grounding
  • the location of the terminal on the memory card body 21 is an example of the terminal 226, and it should not be considered as a limitation to the foregoing embodiment.
  • the storage of the memory card 2 provided in the embodiment of the application is The card interface 22 uses a ground terminal 226 for grounding, and the number of ground terminals is small, which can reduce the shape and size of the memory card body 21 to the same shape and size as the card body 021 of the NM card 02.
  • the memory card interface 22 further includes a clock terminal 227.
  • the clock terminal 227 is electrically connected to the control unit 213 (as shown in FIG. 7) of the memory card body 21, and the clock terminal 227 is used to transmit a clock signal.
  • the clock terminal can be arranged in multiple positions on the memory card body 21, for example, it can be any one of the terminals 221-228.
  • Figure 6(a) only shows the clock
  • the terminal is an example of the terminal 227 on the memory card body 21, which should not be considered as a limitation to the above-mentioned embodiment.
  • the first differential data input terminal, the second differential data input terminal, the first differential data output terminal, the second differential data output terminal, the power terminal, the ground terminal 226, and the clock terminal are arranged on the memory card body 21 at the same positions as DAT1. Seven of 0221, COM 0222, GND 0223, DAT3 0224, DAT2 0225, VCC 0226, DAT0 0227, CLK 0228 are set on the card body 021 of the NM card 02 (as shown in Figure 2(a)). One correspondence.
  • Figure 6(a) only shows that the first differential data input terminal, the second differential data input terminal, the first differential data output terminal, the second differential data output terminal, the power terminal, the ground terminal and the clock terminal are located in Figure 6 (
  • the terminals 221-227 of a) are an example, and should not be considered as a limitation to the above-mentioned embodiment.
  • the first differential data input terminal, the second differential data input terminal, the first differential data output terminal, the second differential data output terminal, the power terminal, the ground terminal, and the clock terminal are on the memory card body 21
  • the setting positions of DAT1 0221, COM 0222, GND 0223, DAT3 0224, DAT2 0225, VCC 0226, DAT0 0227, CLK 0228 are in the card body 021 of NM card 02 respectively (as shown in Figure 2(a))
  • the first differential data input terminal, the second differential data input terminal, the first differential data output terminal, the second differential data output terminal, the power terminal, the ground terminal and the clock terminal are in the memory card
  • the setting area on the body 21 is the same as the seven of DAT1 0221, COM 0222, GND 0223, DAT3 0224, DAT2 0225, VCC 0226, DAT0 0227, CLK 0228 in the card body 021 of the NM card 02 ( Figure 2(
  • the first differential data input terminal, the second differential data input terminal, the first differential data output terminal, the second differential data output terminal, the power supply terminal, the ground terminal and the clock terminal are arranged on the memory card body 21 in the same area as DAT1 0221. , COM 0222, GND 0223, DAT3 0224, DAT2 0225, VCC 0226, DAT0 0227, CLK 0228 between the setting areas on the card body 021 of the NM card 02 (as shown in Figure 2(a))
  • the shape, size, and center position of some regions are the same, and the shape, size, and center position of all regions may be the same, which is not specifically limited here. In some embodiments, as shown in FIG.
  • the setting area of the ground terminal 226 and the clock terminal 227 on the memory card body 21 are respectively connected with DAT1 0221, COM 0222, GND 0223, DAT2 0225, VCC 0226, DAT0 0227, CLK 0228 in the card body 021 of the NM card 02 (e.g. The shape, size, and center position of all areas between the setting areas shown in Fig. 2(a) are the same.
  • the pair of differential data input terminals, a pair of differential data output terminals, power terminals, ground terminals, and clock terminals of the memory card provided in the embodiments of the present application are arranged on the memory card body at the same positions as DAT1 0221, COM 0222, GND Seven of 0223, DAT3 0224, DAT2 0225, VCC 0226, DAT0 0227, CLK 0228 correspond to the setting positions on the card body 021 of the NM card 02 (as shown in Figure 2(a)). Therefore, the memory card can Match with the deck of the NM card.
  • the operating voltages of the storage unit 212 and the control unit 213 can be made equal. In this way, a power terminal can be used to directly supply power to the storage unit 212 and the control unit 213. In other embodiments, the operating voltage of the control unit 213 is not equal to the operating voltage of the storage unit 212. When the power supply voltage supplied by the power terminal is equal to the operating voltage of the storage unit 212, as shown in FIG.
  • the power terminal A first voltage regulating device 214 is connected in series to the electrical connection line with the control unit 213, and the first voltage regulating device 214 is used to regulate the power supply voltage supplied from the power terminal to be equal to the working voltage of the control unit 213.
  • a second voltage regulating device (not shown in the figure) is connected in series in the electrical connection line between the power supply terminal and the storage unit 212.
  • the voltage adjusting device is used to adjust the power supply voltage supplied from the power supply terminal to be equal to the operating voltage of the storage unit 212.
  • a third voltage regulating device (Not shown in the figure)
  • the electrical connection line between the power terminal and the storage unit 212 is connected in series with a fourth voltage regulating device (not shown in the figure), and the third voltage regulating device is used to supply the power supplied by the power terminal
  • the voltage is adjusted to be equal to the operating voltage of the control unit 213, and the fourth voltage adjusting device is used to adjust the power supply voltage supplied from the power terminal to be equal to the operating voltage of the storage unit 212.
  • FIG. 7 takes the position of the power terminal at the terminal 225 shown in FIG. 6(a) as an example for illustration.
  • the operating voltage of the control unit 213 may be 1.75V, 1.9V, or 1.8V, which is not specifically limited here. In some embodiments, the operating voltage of the control unit 213 is 1.8V.
  • the working voltage of the storage unit 212 can be 2.85V, 3.0V, 3.15V, which is not specifically limited here. In some embodiments, the operating voltage of the storage unit 212 is 3.0V.
  • the first voltage regulating device 214 may be a low dropout regulator (LDO). This structure is simple and easy to implement.
  • LDO low dropout regulator
  • the first differential data input terminal and the second differential data input terminal may be distributed or arranged adjacent to each other, which is not specifically limited here.
  • the first differential data input terminal 221 and the second differential data input terminal 222 are arranged adjacent to each other. In this way, the environment of the first differential data input terminal 221 and the second differential data input terminal 222 are approximately the same, the external interference received is approximately equal, and they can cancel each other to ensure the accuracy of input signal transmission.
  • the first differential data input terminal and the second differential data input terminal can be arranged on the memory card body 21 at various positions, as long as the first differential data input terminal and the second differential data input terminal meet the requirements of It is sufficient if the differential data input terminals are adjacent to each other.
  • Figure 6(a) only shows an example of the location of the first differential data input terminal 221 and the second differential data input terminal 222 on the memory card body 21, but not It is considered that the above-mentioned embodiment constitutes a limitation.
  • the first differential data input terminal and the second differential data input terminal can be divided into the positions of the terminals 226 and 228 in FIG. 6(a).
  • the setting position of the first differential data input terminal on the memory card body 21 is the same as one of DAT1 0221 and COM 0222 (as shown in Figure 2(a)) on the card body 021 of the NM card 02
  • the setting position of the second differential data input terminal on the memory card body 21 and the other of DAT1 0221 and COM 0222 (as shown in Figure 2(a)) in the card body 021 of the NM card 02 The setting positions on the corresponding position, that is, the first differential data input terminal and the second differential data input terminal are respectively located at the positions of the terminals 221 and 222 in FIG. 6(a), and the positions of the two can be interchanged.
  • the setting position of the first differential data input terminal on the memory card body 21 is the same as the setting position of one of DAT0 0227 and CLK 0228 (as shown in Figure 2(a)) on the card body 021 of the NM card 02.
  • the setting position of the second differential data input terminal on the memory card body 21 is the same as the setting position of the other of DAT0 0227 and CLK 0228 (as shown in Figure 2(a)) on the card body 021 of the NM card 02
  • the first differential data input terminal and the second differential data input terminal are respectively located at the positions of the terminals 223 and 224 in FIG. 6(a), and the positions of the two can be interchanged.
  • first differential data output terminal and the second differential data output terminal may be arranged dispersedly or adjacently, which is not specifically limited here.
  • first differential data output terminal 223 and the second differential data output terminal 224 are arranged adjacent to each other. In this way, the environment of the first differential data output terminal 223 and the second differential data output terminal 224 is approximately the same, the external interference received is approximately equal, and they can cancel each other to ensure the accuracy of output signal transmission.
  • the first differential data output terminal and the second differential data output terminal can be arranged in various positions on the memory card body 21, as long as they meet the requirements of the first differential data output terminal and the second differential data output terminal. It is sufficient if the differential data output terminals are adjacent.
  • FIG. 6(a) only shows an example of the location of the first differential data output terminal 223 and the second differential data output terminal 224 on the memory card body 21, but not It is considered that the above-mentioned embodiment constitutes a limitation.
  • the setting position of the first differential data output terminal on the memory card body 21 is the same as one of DAT0 0227 and CLK 0228 (as shown in Figure 2(a)) on the card body 021 of the NM card 02
  • the setting position of the second differential data output terminal on the memory card body 21 and the other of DAT0 0227 and CLK 0228 is in the card body 021 of the NM card 02
  • the setting position on the corresponding position, that is, the first differential data output terminal and the second differential data output terminal are located at the positions of the terminals 223 and 224 in Fig. 6(a), and the positions of the two can be interchanged.
  • the setting position of the first differential data output terminal on the memory card body 21 is the same as the setting position of one of DAT1 0221 and COM 0222 (as shown in Figure 2(a)) on the card body 021 of the NM card 02.
  • the setting position of the second differential data output terminal on the memory card body 21 is the same as the setting position of the other of DAT1 0221 and COM 0222 (as shown in Figure 2(a)) on the card body 021 of the NM card 02
  • the first differential data output terminal and the second differential data output terminal are located at the positions of the terminals 221 and 222 in FIG. 6(a), and the positions of the two can be interchanged.
  • the distance between DAT1 0221 and COM 0222 and the distance between DAT0 0227 and CLK 0228 are relatively short, so the distance between the first differential data output terminal and the second differential data output terminal is relatively short, and the first differential data output terminal
  • the environment where the second differential data output terminal is located is approximately the same, and the external interference received is approximately the same, which can cancel each other to further ensure the accuracy of output signal transmission.
  • Figure 6(a) shows that the memory card can have 8 terminals 221-228 corresponding to the terminal layout of the NM card 02, that is, the terminals 221-228 of the memory card, and its layout on the memory card It corresponds to the layout of terminals 0221, 0222, 0228, 0227, 0226, 0223, 0225, 0224 on the NM card 02.
  • the first differential data input terminal, the second differential data input terminal, the first differential data output terminal, the second differential data output terminal, the power terminal, the ground terminal and the clock terminal of the memory card can be located in 7 of the 221-228 terminals, respectively In terms of the position of the terminal, it is understandable that an extra terminal on the memory card may not be connected to the internal circuit of the memory card, or this terminal may be removed.
  • the memory card can have 7 terminals corresponding to the 7 terminal positions in the terminal 0221-0228 in the terminal layout of the NM card 02.
  • the memory card can only have 7 terminals, and its layout on the memory card is the same as the terminals on the NM card 02
  • the layout of 0221-0227 corresponds to the layout of terminals 0222-0228 on the NM card 02.
  • the first differential data input terminal, the second differential data input terminal, the first differential data output terminal, the second differential data output terminal, the power terminal, the ground terminal, and the clock terminal of the memory card are located in Figure 6 (a ) In the positions of terminals 221-227. In the following embodiments, this layout is taken as an example for description.
  • the memory card body 21 includes a packaging structure 211 and a control unit 213 and a reference ground 215 arranged in the packaging structure 211.
  • the encapsulation structure 211 includes a first encapsulation layer 2111 and a second encapsulation layer 2112 that are stacked.
  • the memory card interface 22 is disposed on the first encapsulation layer 2111 and exposed from the encapsulation structure.
  • the control unit 213 and the reference ground 215 are disposed in the second package.
  • the layer 2112 is on and enclosed in the packaging structure.
  • the control unit 213 has a pair of differential data input pins and a pair of differential data output pins.
  • a pair of differential data input pins are electrically connected to a pair of differential data input terminals (including a first differential data input terminal 221 and a second differential data input terminal 222) of the memory card interface 22, and a pair of differential data input pins are connected to the memory card
  • the electrical connection line between the pair of differential data input terminals of the interface 22 is the first electrical connection line c.
  • a pair of differential data output pins are electrically connected to a pair of differential data output terminals (including a first differential data output terminal 223 and a second differential data output terminal 224) of the memory card interface 22, and a pair of differential data output pins are connected to the storage
  • the electrical connection line between the pair of differential data output terminals of the card interface 22 is the second electrical connection line d.
  • the reference ground 215 is electrically connected to the ground terminal 226 of the memory card interface 22, and the electrical connection line between the reference ground 215 and the ground terminal 226 is the third electrical connection line b.
  • each group of third electrical connection lines includes at least one third electrical connection line, and the three groups of third electrical connection lines
  • the three electrical connection lines are the first group of third electrical connection lines b 1 , the second group of third electrical connection lines b 2, and the third group of third electrical connection lines b 3 .
  • a first set of third electrical connecting line between the connecting line between b 1 c is electrically connected to the second electrical line d passing through the first, and after a pair of differential data input terminal coupled to an output terminal of the differential data.
  • a second group of third electrical connecting line b 2 c via a first electrical connecting line is electrically connected to a second side away from the d line, and after a pair of differential data input terminal side away from the pair of differential data output terminals.
  • a third set of third electrical connecting line b 3 via a second electrical connecting line is electrically connected to a first side remote from the d line c, and after a pair of differential data output terminals away from a pair of differential data input terminal side.
  • a third group may be electrically connected by a first line b 1 achieve isolation between the differential data between a pair of differential input terminals and an output terminal, and a first data line electrically connected to the second electrical connecting line c d , Avoiding mutual interference between the pair of differential data input terminals and the pair of differential data output terminals and between the first electrical connection line c and the second electrical connection line d.
  • the isolation between the line d and the external environment of the memory card 2 reduces the interference of external environment noise on the pair of differential data input terminals, the pair of differential data output terminals, the first electrical connection line c, and the second electrical connection line d .
  • the control unit 213 also has a ground pin 2131.
  • the number of the grounding pins 2131 is multiple.
  • the multiple grounding pins 2131 include a first grounding pin 21311, a second grounding pin 21312, and a third grounding pin 21313.
  • the first grounding pin 21311, the second grounding pin 2131 Both the pin 21312 and the third ground pin 21313 are electrically connected to the reference ground 215.
  • the first ground pin 21311 is arranged between a pair of differential data input pins and a pair of differential data output pins.
  • the electrical connection line between the first ground pin 21311 and the reference ground 215 is located between the first electrical connection line c and The second electrical connection line d.
  • the second ground pin 21312 is arranged on the side of the pair of differential data input pins away from the pair of differential data output pins, and the electrical connection line between the second ground pin 21312 and the reference ground 215 is located on the first electrical connection line c is away from the side of the second electrical connection line d.
  • the third ground pin 21313 is arranged on the side of the pair of differential data output pins away from the pair of differential data input pins, and the electrical connection line between the third ground pin 21313 and the reference ground 215 is located on the second electrical connection line d is away from the side of the first electrical connection line c.
  • the first ground pin 21311 and the electrical connection line between the first ground pin 21311 and the reference ground 215 can realize a pair of differential data input pins and a pair of differential data output pins and a first
  • the isolation between the electrical connection line c and the second electrical connection line d avoids the difference between the pair of differential data input pins and the pair of differential data output pins and between the first electrical connection line c and the second electrical connection line d Mutual interference occurs between them.
  • a pair of differential data input pins, a pair of differential data output pins, a first electrical connection line c, a second electrical connection line d, and a memory card 2 are realized through the second ground pin 21312 and the third ground pin 21313.
  • the isolation between the external environment of the external environment reduces the interference of the external environment noise on the pair of differential data input pins, the pair of differential data output pins, the first electrical connection line c, and the second electrical connection line d.
  • the Nano SIM card 03 can be matched with the card holder of the NM card 02, and the memory card 2 provided in the embodiment of this application can also be matched with the card holder of the NM card 02. Therefore, the Nano SIM card 03 can be implemented in accordance with this application.
  • the memory card 2 provided in the example can share the same card socket.
  • the card socket 12 of the electronic device 1 can be an NM card socket matching the Nano SIM card 03, the memory card 2 provided in the embodiment of the present application, and the NM card 02.
  • FIG. 5 in order to enable the electronic device 1 to recognize and operate the Nano SIM card 03, the memory card 2 and the NM card 02 provided in the embodiments of the present application, FIG.
  • the electronic device 1 includes a circuit board 11 and a card holder 12.
  • the card holder 12 includes a card holder main body 121 and a card holder interface.
  • the card socket interface is arranged on the inner wall of the card slot.
  • the circuit board 11 includes a Nano SIM card controller 111, a memory card controller 112, an NM card controller 113, a switch 114, a detection circuit 115, and a control circuit 116.
  • the Nano SIM card controller 111 is used to control the operation of the Nano SIM card 03.
  • the memory card controller 112 is used to control the operation of the memory card 2 provided in the embodiment of the present application.
  • the NM card controller 113 is used to control the operation of the NM card 02.
  • the card socket interface of the card socket 12 is connected to the Nano SIM card controller 111, the memory card controller 112, or the NM card controller 113 through the switch 114.
  • One end of the card socket interface of the card socket 12 connected to the switch 114 is the first end k 1
  • one end of the Nano SIM card controller 111 connected to the switch 114 is the second end k 2
  • one end of the memory card controller 112 connected to the switch 114 is the third end.
  • the terminal k 3 , the terminal of the NM card controller 113 connected to the switch 114 is the fourth terminal k 4 .
  • the detection circuit 115 is used to detect the card installed in the card slot through the card socket interface, and the control circuit 116 is used to identify the card installed in the card slot as the Nano SIM card 03, memory card 2 or NM according to the detection result of the detection circuit 115 Card 02, and according to the identification result, the first terminal k 1 of the control switch 114 is connected to the second terminal k 2 of the switch 114, or the first terminal k 1 of the control switch 114 is connected to the third terminal k 3 of the switch 114, or the control switch The first terminal k 1 of 114 is connected to the fourth terminal k 4 of the switch 114.
  • first end k 1 , the second end k 2 , the third end k 3 and the fourth end k 4 all include multiple (for example, 6 or 8) connection terminals, and
  • the first end k 1 , the second end k 2 , the third end k 3 and the fourth end k 4 include the same number of connection terminals.
  • the second end k 2 includes a plurality of connection terminals respectively connected to the plurality of terminals of the Nano SIM card controller 111 in a one-to-one correspondence.
  • the third end k 3 includes a plurality of connection terminals respectively connected to the plurality of terminals of the memory card controller 112 in a one-to-one correspondence.
  • the fourth terminal k 4 includes a plurality of connection terminals respectively connected to a plurality of terminals of the NM card controller 113 in a one-to-one correspondence.
  • k 1 comprises a first end connected to a plurality of terminals and the third end comprises a plurality of connecting terminals k 3 is correspondingly connected.
  • first terminal and the fourth terminal k 1 k 4 is connected to a first terminal k 1 comprises a plurality of connection terminals connected to a fourth terminal of the plurality of terminals k 4 comprises a correspondingly connected.
  • the terminals of the k1-k4 terminals are connected to the power terminal and the ground terminal.
  • the detection circuit 115 detects that the card installed in the card holder 12 is a Nano SIM card 03
  • the first end k 1 of the switch 114 can be controlled by the control circuit 116 to connect to the second end k 2 of the switch 114 to
  • the Nano SIM card 03 is connected to the Nano SIM card controller 111 through the card socket interface of the card socket 12.
  • the control circuit 116 can control the first end k 1 of the switch 114 to connect to the third end k 3 of the switch 114, so that the memory card 2 can pass
  • the card socket interface of the card socket 12 is connected to the memory card controller 112.
  • the control circuit 116 can control the first end k 1 of the switch 114 to connect to the fourth end k 4 of the switch 114, so that the NM card 02 can pass
  • the card socket interface of the card socket 12 is connected to the NM card controller 113.
  • the electronic device 1 can recognize and operate the Nano SIM card 03, the memory card 2 and the NM card 02 provided in the embodiment of the present application. This structure is simple and easy to implement.
  • the card socket interface of the card socket 12 includes a plurality of card socket terminals, and the plurality of card socket terminals can all be connected to the Nano SIM card controller 111, the memory card controller 112 or the NM card controller 113 through the switch 114.
  • the connection can also be partially connected to the Nano SIM card controller 111, memory card controller 112, or NM card controller 113 through the switch 114.
  • the key to determining this result is: Nano SIM card 03, memory card 2 Whether there are terminals with the same function as the NM card 02 and corresponding to the setting positions on the card body.
  • the terminal does not need to be connected to the Nano SIM card controller 111, the memory card controller 112, or the NM card controller 113 through the switch 114. In this case, the complexity of the circuit can be reduced and the cost can be saved. If there is no such terminal, all the card socket terminals included in the card socket interface of the card socket 12 need to be connected to the Nano SIM card controller 111, the memory card controller 112 or the NM card controller 113 through the switch 114.
  • the arrangement position of the ground terminal 226 on the memory card body 21 and GND 0223 are on the card body 021 of the NM card 02 (as shown in FIG. 2(a)).
  • the GND 0223 of the NM card 02 is set on the card body 021 of the NM card 02
  • the GND 0323 of the Nano SIM card 03 is set on the part of the card body 031 of the Nano SIM card (as shown in Figure 3(a))
  • the ground terminals 226, GND 0223, and GND 0323 are all used for grounding. Therefore, the card socket interface of the card socket 12 in the electronic device 1 shown in FIG.
  • the ground terminal 226 of the NM card 02 or the GND 0223 of the NM card 02 does not need to be connected to the Nano SIM card controller 111, the memory card controller 112 or the NM card controller 113 through the switch 114. In this way, the circuit board 11 can be reduced. The complexity of the circuit saves costs.
  • the position of the power terminal 225 on the memory card body 21 is the same as the VCC 0226 on the card body 021 of the NM card 02 (as shown in FIG. 2(a)) Corresponding to the setting position. Since the setting position of the VCC 0226 of the NM card 02 on the card body 021 of the NM card 02 corresponds to the setting position of the VCC 0324 of the Nano SIM card on the card body 031 of the Nano SIM card (as shown in Figure 3(a)) , And the power terminals 225, VCC 0226, and VCC 0324 are all used for power supply. Therefore, the card socket interface of the card socket 12 in the electronic device 1 shown in FIG.
  • the terminal 225 or the card socket terminal contacted by the VCC 0226 of the NM card 02 does not need to be connected to the Nano SIM card controller 111, the memory card controller 112, or the NM card controller 113 through the switch 114. In this way, the circuit board 11 can be reduced. The complexity and cost savings.
  • the first differential data input terminal, the second differential data input terminal 222, the first differential data output terminal, and the second The setting positions of the two differential data output terminals, power terminals, ground terminals, and clock terminals on the memory card body 21 are the same as DAT1 0221, COM 0222, GND 0223, DAT2 0225, VCC 0226, DAT0 0227, CLK 0228 on the NM card 02
  • the setting position on the card body 021 (as shown in Figure 2(a)) corresponds to the setting position.
  • the correspondence does not mean one-to-one correspondence.
  • the position of the first differential data input terminal can correspond to DAT1 0221, COM 0222, GND 0223, The position of any one of DAT2 0225, VCC 0226, DAT0 0227, CLK 0228.
  • the detection terminal 228 and The memory card body 21 is not electrically connected and is an independent terminal, that is, the detection terminal is not electrically connected to the internal circuit of the memory card and is not electrically connected to other terminals of the memory card.
  • the setting position of the DAT3 0224 of the NM card on the card body 021 of the NM card corresponds to the setting position of the GND 0323 of the Nano SIM card on the card body 031 of the Nano SIM card
  • the Nano SIM card 03 is provided in the embodiment of this application.
  • the memory card 2 of the NM card can be matched with the card socket of NM card 02.
  • the socket terminal on the NM card socket used to contact DAT3 0224 of the NM card is the first socket terminal, so insert the card in Figure 9
  • the detection circuit 115 can detect the terminal contacting the first card socket terminal, and the control circuit 116 can determine the terminal contacted by the first card socket terminal according to the detection result of the detection circuit 115. It is GND 0323, DAT3 0224, or there is no terminal contact, to achieve the purpose of identifying the Nano SIM card 03, the memory card 2 and the NM card 02 provided in this embodiment of the application.
  • the card socket includes a card socket body and a card socket interface.
  • the card socket body encloses a card slot.
  • the card slot is used to accommodate the card body of the NM card 02.
  • the card socket interface is arranged on the inner wall of the card slot.
  • the card socket interface has eight There are two card socket terminals.
  • the eight card socket terminals are used to contact DAT1, COM, GND, DAT3, DAT2, VCC, DAT0 and CLK of the NM card.
  • the terminal is the first card socket terminal.
  • the method for identifying the Nano SIM card, the memory card and the NM card described in the foregoing embodiment includes:
  • S200 Determine whether the terminal is a ground terminal or a signal terminal, or no terminal is in contact with the first card socket terminal;
  • the card inserted in the card socket is identified as the memory card 2 described in the foregoing embodiment. Understandably, the detection terminal is an independent terminal, and it can be regarded that no terminal is in contact with the first card socket terminal.
  • Nano SIM card 03 the memory card 2 and the NM card 02 described in the above embodiment can be identified through the card holder.
  • step S300 the processes of the Nano SIM card 03, such as the initialization process and the subsequent use process, are executed.
  • step S400 the process of the NM card 02 is executed, such as the initialization process and the subsequent use process.
  • step S500 the procedures of the memory card 2, such as the initialization procedure and the subsequent use procedure, are executed.
  • the detection circuit 115 shown in FIG. 11 can be used to detect that the terminal contacting the first card socket terminal is a ground terminal or a signal terminal, or that no terminal is in contact with the first card socket terminal.
  • the detection circuit 115 is a circuit formed by connecting two buffers 1151 and a resistor 1152 (resistance value of 1M ⁇ ), and the detection circuit 115 has an A terminal, a B terminal and a C terminal, and the B terminal and the first A card socket terminal is connected, and voltages of different voltage values are successively supplied to the detection circuit 115 from the A terminal, for example, 1.8V and 0V are successively supplied.
  • the first card socket terminal is in contact with the ground terminal. If it is detected that the voltage value of the C terminal changes with the voltage value supplied by the A terminal and is equal to the current voltage supplied by the A terminal, it is determined that no terminal is in contact with the first card socket terminal. If it is detected that the voltage value of the C terminal is less than the current voltage supplied by the A terminal by more than a preset value, it is determined that the first card socket terminal is in contact with the signal terminal.
  • the preset value is greater than 0, and the specific preset value may be 0.2V, 0.3V, 0.5V, etc., which is not specifically limited here.
  • Nano SIM card 03, the memory card 2 and the NM card 02 provided in the embodiment of the present application are inserted into the card holder 12 can be detected by setting a mechanical spring device in the card holder 12.
  • the above detection circuit and detection method can only be used to detect the Nano SIM card 03, the memory card 2 and the NM card 02 provided in this embodiment of the application, that is, there are only the Nano SIM card controller 111 and the memory card controller in the electronic device. 112.
  • the detection circuit and the detection method can be adapted to distinguish two card scenarios.
  • the Nano SIM card controller 111 and the memory card controller 112 the above method flow only needs to distinguish whether the terminal in contact with the first card socket terminal is a ground terminal or if no terminal is in contact with the first card socket terminal.

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Abstract

本申请实施例提供一种存储卡、识别方法和电子设备，涉及电子设备技术领域，能够在保证存储卡的读写速度的同时，使存储卡能够与NM卡的卡座相匹配。该存储卡包括存储卡卡体和存储卡接口；存储卡卡体与NM卡的卡体的外形和尺寸相同；存储卡接口设置于存储卡卡体上，且该存储卡接口包括一对差分数据输入端子、一对差分数据输出端子、电源端子、接地端子和时钟端子，一对差分数据输入端子包括第一差分数据输入端子和第二差分数据输入端子，一对差分数据输出端子包括第一差分数据输出端子和第二差分数据输出端子。本申请实施例提供的存储卡用于扩充电子设备的存储空间。

Description

一种存储卡、识别方法和电子设备
本申请要求于2020年03月31日提交国家知识产权局、申请号为202010249573.3、发明名称为“一种存储卡、识别方法和电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及电子设备技术领域，尤其涉及一种存储卡、识别方法和电子设备。
背景技术
存储卡是一种可用于扩充电子设备存储空间的设备。存储卡包括存储卡卡体和设置在存储卡卡体上的存储卡接口，存储卡卡体包括封装材料以及设置在封装材料内的控制单元和存储单元，存储卡接口包括多个端子(比如数据传输端子、接地端子、电源端子和时钟端子)，控制单元与存储单元电连接，控制单元与存储卡接口也电连接。当存储卡插入电子设备主机的卡座内时，存储卡接口的多个端子与卡座的多个卡座端子相接触，以将存储卡卡体与电子设备主机电连接在一起，这样，电子设备主机可以对存储卡卡体内的存储单元进行读写操作。
存储卡的读写速度和占板面积是存储卡的两项重要指标。目前市场上存在一种通用闪存(universal flash storage，UFS)卡，该UFS卡的结构参照图1(a)和图1(b)。如图1(a)和图1(b)所示，UFS卡01支持UFS协议，UFS卡01包括卡体011和接口012。卡体011包括封装材料和设置于封装材料中的存储单元和控制单元，存储单元与控制单元电连接。接口012设置于卡体011上，接口012包括12个端子，该12个端子分别为C/D 0121、VCCQ2 0122、REF_CLK 0123、VSS 0124、DOUT_T 0125、DOUT_C 0126、VCC 0127、VSS 0128、VSS 0129、DIN_T 0130、DIN_C 0131和VSS 0132。该12个端子的标号、名称及定义参见下表表1。
表1
Figure PCTCN2021079575-appb-000001
Figure PCTCN2021079575-appb-000002
该UFS卡通过一对差分数据输出端子(也即是DOUT_T 0125和DOUT_C 0126)和一对差分数据输入端子(也即是DIN_T 0130和DIN_C 0131)与电子设备主机进行差分串行数据传输，差分串行数据传输方式的传输速度较快，存储卡的读写速度较快。但是，由于UFS卡的接口包括的端子较多，多达12个，UFS卡的占板面积(为11mm×15mm)和体积较大(为11mm×15mm×1mm)，不能与微型存储(nano memory，NM)卡的卡座相匹配。
发明内容
本申请的实施例提供一种存储卡、识别方法和电子设备，能够在保证存储卡的读写速度的同时，缩小存储卡的占板面积和体积，使存储卡能够与NM卡的卡座相匹配。
为达到上述目的，本申请的实施例采用如下技术方案：
第一方面，本申请一些实施例提供一种存储卡，该存储卡包括存储卡卡体和存储卡接口；存储卡卡体与NM卡的卡体的外形和尺寸相同；存储卡接口设置于存储卡卡体上，且该存储卡接口包括一对差分数据输入端子、一对差分数据输出端子、电源端子、接地端子和时钟端子，一对差分数据输入端子包括第一差分数据输入端子和第二差分数据输入端子，该一对差分数据输入端子用于传输向存储卡卡体输入的差分数据，一对差分数据输出端子包括第一差分数据输出端子和第二差分数据输出端子，该一对差分数据输出端子用于传输存储卡卡体输出的差分数据，该电源端子用于供电，该接地端子用于接地，该时钟端子用于传输时钟信号；第一差分数据输入端子、第二差分数据输入端子、第一差分数据输出端子、第二差分数据输出端子、电源端子、接地端子和时钟端子在存储卡卡体上的设置位置分别与DAT1、COM、GND、DAT3、DAT2、VCC、DAT0和CLK中的七个在NM卡的卡体上的设置位置相对应。
与现有技术相比，由于本申请实施例提供的存储卡的存储卡接口包括一对差分数据输入端子和一对差分数据输出端子，该一对差分数据输入端子用于传输向存储卡卡体输入的差分数据，该一对差分数据输出端子用于传输存储卡卡体输出的差分数据，因此在存储卡插入电子设备主机的卡座内之后，存储卡可以采用该一对差分数据输入端子以及该一对差分数据输出端子与电子设备主机进行差分串行数据传输，差分串行数据传输方式的准确性较高，传输速度较快，能够保证存储卡的读写速度。而且，由于存储卡卡体与NM卡的卡体的外形和尺寸相同，NM卡的长度为8.8mm，宽度为12.3mm，厚度为0.84mm，NM卡的占板面积为8.8mm×12.3mm，NM卡的体积为8.8mm×12.3mm×0.84mm，比现有技术的UFS卡的占板面积和体积小，且一对差分数据输入端子、一对差分数据输出端子、电源端子、接地端子和时钟端子的尺寸较小，基本可以忽略不计，因此本申请实施例提供的存储卡的体积和占板面积比现有技术的UFS卡的占板面积和体积小，可以减小存储卡在电子设备主机内的占用空间和占板面积。同时，由于存储卡卡体与NM卡的卡体的外形和尺寸相同，一对差分数据输入端子、一对差分数据输出端子、电源端子、接地端子和时钟端子在存储卡卡体上的设置位置分别与DAT1、COM、GND、DAT3、DAT2、VCC、DAT0和CLK中的七个在NM卡的卡体上的设置位置相对应，因此，存储卡能够与NM卡的卡座相匹配。
可选地，存储卡卡体包括封装结构和设置于该封装结构内的控制单元和存储单元，由电源端子供入的电源电压与存储单元的工作电压相等，由电源端子供入的电源电压与控制单元的工作电压不相等，电源端子与存储单元直接电连接，电源端子与控制单元之间的电连接线路中串接有电压调节装置，电压调节装置用于将由电源端子供入的电源电压调节至与控制单元的工作电压相等。这样一来，在控制单元的工作电压与存储单元的工作电压不相等的情况下，仍可以采用一个电源端子同时向存储单元和控制单元供电，无需在存储卡卡体上设置两个电源端子来分别向存储单元和控制单元供电，因此，能够减少存储卡的端子的数量，有利于减小存储卡的体积和占板面积。
可选地，控制单元的工作电压为1.8V。
可选地，存储单元的工作电压为3.0V。
可选地，电压调节装置为低压差线性稳压器。此结构简单，容易实现。
可选地，第一差分数据输入端子与第二差分数据输入端子相邻设置；第一差分数据输出端子与第二差分数据输出端子相邻设置。这样一来，第一差分数据输入端子和第二差分数据输入端子所处环境近似相同，第一差分数据输出端子和第二差分数据输出端子所处环境近似相同，受到的外界干扰近似相等，能够相互抵消以保证输入信号和输出信号传输的准确性。
可选地，第一差分数据输入端子在存储卡卡体上的设置位置与DAT1和COM中的一个在NM卡的卡体上的设置位置相对应，第二差分数据输入端子在存储卡卡体上的设置位置与DAT1和COM中的另一个在NM卡的卡体上的设置位置相对应。或者，第一差分数据输入端子在存储卡卡体上的设置位置与DAT0和CLK中的一个在NM卡的卡体上的设置位置相对应，第二差分数据输入端子在存储卡卡体上的设置位置与DAT0和CLK中的另一个在NM卡的卡体上的设置位置相对应。由于DAT1与COM之间的距离以及DAT0与CLK之间的距离均较近，因此第一差分数据输入端子和第二差分数据输入端子所处环境近似相同，受到的外界干扰近似相等，能够相互抵消以进一步保证输入信号传输的准确性。
可选地，第一差分数据输出端子在存储卡卡体上的设置位置与DAT0和CLK中的一个在NM卡的卡体上的设置位置相对应，第二差分数据输出端子在存储卡卡体上的设置位置与DAT0和CLK中的另一个在NM卡的卡体上的设置位置相对应。或者，第一差分数据输出端子在存储卡卡体上的设置位置与DAT1和COM中的一个在NM卡的卡体上的设置位置相对应，第二差分数据输出端子在存储卡卡体上的设置位置与DAT1和COM中的另一个在NM卡的卡体上的设置位置相对应。DAT1与COM之间的距离以及DAT0与CLK之间的距离均较近，因此第一差分数据输出端子与第二差分数据输出端子之间的距离较近，第一差分数据输出端子和第二差分数据输出端子所处环境近似相同，受到的外界干扰近似相等，能够相互抵消以进一步保证输出信号传输的准确性。
可选地，存储卡卡体包括封装结构以及设置于该封装结构内的控制单元和参考地。封装结构包括层叠设置的第一封装层和第二封装层，存储卡接口设置于第一封装层上，控制单元和参考地设置于第二封装层上。控制单元具有一对差分数据输入引脚和一对差分数据输出引脚。一对差分数据输入引脚与存储卡接口的一对差分数据输入端子电 连接，一对差分数据输入引脚与存储卡接口的一对差分数据输入端子之间的电连接线路为第一电连接线路。一对差分数据输出引脚与存储卡接口的一对差分数据输出端子电连接，且一对差分数据输出引脚与存储卡接口的一对差分数据输出端子之间的电连接线路为第二电连接线路。参考地与存储卡接口的接地端子电连接，参考地与接地端子之间的电连接线路为第三电连接线路。第三电连接线路为多条，多条第三电连接线路组成三组第三电连接线路，每组第三电连接线路均包括至少一条第三电连接线路，且所述三组第三电连接线路分别为第一组第三电连接线路、第二组第三电连接线路和第三组第三电连接线路。第一组第三电连接线路经过第一电连接线路与第二电连接线路之间，并经过一对差分数据输入端子与一对差分数据输出端子之间。第二组第三电连接线路经过第一电连接线路远离第二电连接线路的一侧，并经过一对差分数据输入端子远离一对差分数据输出端子的一侧。第三组第三电连接线路经过第二电连接线路远离第一电连接线路的一侧，并经过一对差分数据输出端子远离一对差分数据输入端子的一侧。这样一来，可以通过第一组第三电连接线路实现一对差分数据输入端子与一对差分数据输出端子之间以及第一电连接线路与第二电连接线路之间的隔离，避免该一对差分数据输入端子与该一对差分数据输出端子之间以及第一电连接线路与第二电连接线路之间产生相互干扰。同时通过第二组第三电连接线路和第三组第三电连接线路实现了一对差分数据输入端子、一对差分数据输出端子、第一电连接线路以及第二电连接线路与存储卡的外界环境之间的隔离，减少外界环境噪声对该一对差分数据输入端子、该一对差分数据输出端子、第一电连接线路以及第二电连接线路产生干扰。
可选地，控制单元还具有接地引脚。该接地引脚的数量为多个，多个接地引脚包括第一接地引脚、第二接地引脚和第三接地引脚，第一接地引脚、第二接地引脚和第三接地引脚均与参考地电连接。第一接地引脚设置于一对差分数据输入引脚与一对差分数据输出引脚之间，第一接地引脚与参考地之间的电连接线路位于第一电连接线路与第二电连接线路之间。第二接地引脚设置于一对差分数据输入引脚远离一对差分数据输出引脚的一侧，且第二接地引脚与参考地之间的电连接线路位于第一电连接线路远离第二电连接线路的一侧。第三接地引脚设置于一对差分数据输出引脚远离一对差分数据输入引脚的一侧，且第三接地引脚与参考地之间的电连接线路位于第二电连接线路远离第一电连接线路的一侧。这样一来，可以通过第一接地引脚以及第一接地引脚与参考地之间的电连接线路实现一对差分数据输入引脚与一对差分数据输出引脚之间以及第一电连接线路与第二电连接线路之间的隔离，避免该一对差分数据输入引脚与一对差分数据输出引脚之间以及第一电连接线路与第二电连接线路之间产生相互干扰。同时通过第二接地引脚和第三接地引脚实现了一对差分数据输入引脚、一对差分数据输出引脚、第一电连接线路以及第二电连接线路与存储卡的外界环境之间的隔离，减少外界环境噪声对该一对差分数据输入引脚、一对差分数据输出引脚、第一电连接线路以及第二电连接线路产生干扰。
可选地，接地端子在存储卡卡体上的设置位置与GND在NM卡的卡体上的设置位置相对应。由于NM卡的GND在NM卡的卡体上的设置位置与Nano SIM卡的GND在Nano SIM卡的卡体上的部分设置位置相对应，且接地端子、NM卡的GND和Nano SIM卡的GND均用于接地，因此电子设备内卡座的卡座接口中用于与Nano SIM卡的 GND、存储卡的接地端子或NM卡的GND接触的卡座端子无需通过开关与Nano SIM卡控制器、存储卡控制器或者NM卡控制器连接，这样一来，可以降低电路板的电路的复杂度，节省成本。
可选地，电源端子在存储卡卡体上的设置位置与VCC在NM卡的卡体上的设置位置相对应。由于NM卡的VCC在NM卡的卡体上的设置位置与Nano SIM卡的VCC在Nano SIM卡的卡体上的设置位置相对应，且电源端子、NM卡的VCC和Nano SIM卡的VCC均用于供电，因此电子设备内卡座的卡座接口中用于与Nano SIM卡的VCC、存储卡的电源端子或NM卡的VCC接触的卡座端子无需通过开关与Nano SIM卡控制器、存储卡控制器或者NM卡控制器连接，这样一来，可以降低电路板的电路的复杂度，节省成本。
可选地，第一差分数据输入端子、第二差分数据输入端子、第一差分数据输出端子、第二差分数据输出端子、电源端子、接地端子和时钟端子在存储卡卡体上的设置位置分别与DAT1、COM、GND、DAT2、VCC、DAT0、CLK在NM卡的卡体上的设置位置相对应，此处对应不是一一对应，而是任意对应。存储卡卡体上与DAT3在NM卡的卡体上的设置位置相对应的位置未设置端子或者设有检测端子，该检测端子为独立端子，即该检测端子与存储卡内部电路之间未电连接且与存储卡的其他端子无电连接。由于NM卡的DAT3在NM卡的卡体上的设置位置与Nano SIM卡的GND在Nano SIM卡的卡体上的设置位置相对应，且Nano SIM卡和本申请实施例提供的存储卡均可以与NM卡的卡座相匹配，假设NM卡的卡座上用于与NM卡的DAT3接触的卡座端子为第一卡座端子，因此在将卡插入卡座内之后，可以通过确定与该第一卡座端子接触的端子为GND、DAT3，或者没有端子接触，来达到识别Nano SIM卡、本申请实施例提供的存储卡和NM卡的目的。
第二方面，本申请实施例提供一种通过卡座识别Nano SIM卡、NM卡和如上第一方面中最后一个技术方案所述的存储卡的方法，卡座包括卡座主体和卡座接口，卡座主体围成卡槽，卡槽用于容纳NM卡的卡体，卡座接口设置于卡槽的内壁上，卡座接口具有八个卡座端子，该八个卡座端子分别用于与NM卡的DAT1、COM、GND、DAT3、DAT2、VCC、DAT0和CLK接触，该八个卡座端子中用于与DAT3接触的卡座端子为第一卡座端子，该方法包括：
S100：检测与第一卡座端子接触的端子；
S200：判断所述端子是接地端子或者信号端子，或者没有端子与所述第一卡座端子接触；
S300：当与所述第一卡座端子接触的端子为接地端子时，则识别所述卡座内插入的卡为Nano SIM卡；
S400：当与所述第一卡座端子接触的端子为信号端子时，则识别所述卡座内插入的卡为NM卡；
S500：当没有端子与所述第一卡座端子接触时，则识别所述卡座内插入的卡为权利要求8所述的存储卡。这样一来，可以实现Nano SIM卡、NM卡和如上第一方面中最后一个技术方案所述的存储卡的识别。
第三方面，本申请实施例提供一种电子设备，用于执行第二方面所述的通过卡座 识别Nano SIM卡、NM卡和如上第一方面中最后一个技术方案所述的存储卡的方法，该电子设备包括卡座和电路板；卡座包括卡座主体和卡座接口，卡座主体围成卡槽，卡座接口设置于该卡槽的内壁上，卡座接口具有八个卡座端子，八个卡座端子分别用于与NM卡的DAT1、COM、GND、DAT3、DAT2、VCC、DAT0和CLK接触，八个卡座端子中用于与DAT3接触的卡座端子为第一卡座端子；电路板包括Nano SIM卡控制器、存储卡控制器、NM卡控制器、开关、检测电路和控制电路，开关具有第一端、第二端、第三端和第四端，第一端与卡座接口电连接，第二端与Nano SIM卡控制器电连接，第三端与存储卡控制器电连接，第四端与NM卡控制器电连接，检测电路用于检测与第一卡座端子接触的端子，控制电路用于根据该检测电路的检测结果，识别安装于卡槽内的卡为Nano SIM卡、存储卡或者NM卡，并根据识别结果，控制开关的第一端连接开关的第二端，或者控制开关的第一端连接开关的第三端，或者控制开关的第一端连接开关的第四端。
由于本申请实施例提供的电子设备中的控制电路可以通过检测电路检测与第一卡座端子接触的端子，并根据该检测电路的检测结果，识别安装于卡槽内的卡为Nano SIM卡、存储卡或者NM卡，并根据识别结果，控制开关的第一端连接开关的第二端，或者控制开关的第一端连接开关的第三端，或者控制开关的第一端连接开关的第四端，因此，本申请实施例提供的电子设备的卡座内可以安装Nano SIM卡、存储卡或者NM卡，并能够执行Nano SIM卡、存储卡或者NM卡的对应的流程，以能够通过一个卡座兼容Nano SIM卡、存储卡或者NM卡。
附图说明
图1(a)为现有技术提供的一种UFS卡的正面结构示意图；
图1(b)为图1(a)所示UFS卡的背面结构示意图；
图2(a)为NM卡的正面结构示意图；
图2(b)为NM卡的背面结构示意图；
图3(a)为Nano SIM的正面结构示意图；
图3(b)为Nano SIM的背面结构示意图；
图4为NM卡的端子的设置位置与Nano SIM的端子的设置位置之间的对应关系图；
图5为本申请一些实施例提供的电子设备的结构示意图；
图6(a)为本申请一些实施例提供的存储卡的正面结构示意图；
图6(b)为本申请一些实施例提供的存储卡的背面结构示意图；
图7为本申请一些实施例提供的存储卡的结构框图；
图8为本申请一些实施例提供的存储卡的内部结构示意图；
图9为本申请一些实施例提供的电子设备的结构示意图；
图10为本申请一些实施例提供的通过卡座识别Nano SIM卡、NM卡和图6(a)所示的存储卡的方法的流程图；
图11为本申请一些实施例提供的通过卡座识别Nano SIM卡、NM卡和图6(a)所示的存储卡的方法中使用的检测电路的结构示意图。
附图标记：
01-UFS卡；011-卡体；012-接口；0121-C/D；0122-VCCQ2；0123-REF_CLK；0124-VSS；0125-DOUT_T；0126-DOUT_C；0127-VCC；0128-VSS；0129-VSS；0130-DIN_T；0131-DIN_C；0132-VSS；02-NM卡；021-卡体；022-接口；0221-DAT1；0222-COM；0223-GND；0224-DAT3；0225-DAT2；0226-VCC；0227-DAT0；0228-CLK；03-Nano SIM卡；031-卡体；032-接口；0321-I/O；0322-VPP；0323-GND；0324-VCC；0325-RST；0326-CLK；1-电子设备主机；11-电路板；111-Nano SIM卡控制器；112-存储卡控制器；113-NM卡控制器；114-开关；115-检测电路；1151-缓冲器；1152-电阻；116-控制电路；12-卡座；121-卡座主体；2-存储卡；21-存储卡卡体；211-封装结构；212-存储单元；213-控制单元；2131-接地引脚；21311-第一接地引脚；21312-第二接地引脚；21313-第三接地引脚；214-第一电压调节装置；215-参考地；22-存储卡接口；221-228-存储卡的端子。
具体实施方式
在本申请实施例中，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。
本申请实施例涉及一种存储卡和电子设备，以下对本申请实施例所提到的存储卡和用户身份识别(subscriber identity module，SIM)卡进行介绍：
微型存储(nano memory，NM)卡，是华为技术有限公司自创的一种超微型存储卡。NM卡的结构参照图2(a)和图2(b)。如图2(a)和图2(b)所示，NM卡02的长度为8.8mm，宽度为12.3mm，厚度为0.84mm。NM卡02包括卡体021和接口022。接口022设置于卡体021上。接口022包括8个端子，该8个端子分别为DAT1 0221、COM 0222、GND 0223、DAT3 0224、DAT2 0225、VCC 0226、DAT0 0227和CLK 0228。该8个端子的标号、名称及定义参见下表表2，8个端子的位置参考图2(a)。需要说明的是，图2(a)仅示出了DAT1 0221、COM 0222、GND 0223、DAT3 0224、DAT2 0225、VCC 0226、DAT0 0227和CLK 0228这8个端子在卡体021上的设置位置的一种示例，这8个端子在卡体021上的设置位置也可以为其他位置，图2(a)并不对本申请构成限定。
表2
端子标号 端子名称 端子定义
0221 DAT1 数据端子1
0222 COM 命令端子
0223 GND 接地端子
0224 DAT3 数据端子3
0225 DAT2 数据端子2
0226 VCC 电源端子
0227 DAT0 数据端子0
0228 CLK 时钟端子
超微型用户身份识别(nano subscriber identity module，Nano SIM)卡，是一种手机微型SIM卡，比Micro-SIM卡更小，只有第一代SIM卡60％的面积。Nano SIM卡 的结构参照图3(a)和图3(b)，如图3(a)和图3(b)所示，Nano SIM卡03包括卡体031和接口032，接口032设置于卡体031上，接口032包括6个端子，该6个端子分别为I/O 0321、VPP 0322、GND 0323、VCC 0324、RST 0325和CLK 0326，该6个端子的标号、名称及定义参见下表表3。
表3
端子标号 端子名称 端子定义
0321 I/O 输入输出端子
0322 VPP 程序电压端子
0323 GND 接地端子
0324 VCC 供电电压端子
0325 RST 重置端子
0326 CLK 时钟端子
需要说明的是，上述NM卡的卡体021与上述Nano SIM卡的卡体031的外形和尺寸相同。上述NM卡的DAT1 0221在NM卡的卡体021上的设置位置与上述Nano SIM卡的I/O 0321在Nano SIM卡的卡体031上的设置位置相对应。上述NM卡的COM 0222在NM卡的卡体021上的设置位置与上述Nano SIM卡的VPP 0322在Nano SIM卡的卡体031上的设置位置相对应。上述NM卡的GND 0223在NM卡的卡体021上的设置位置与上述Nano SIM卡的GND 0323在Nano SIM卡的卡体031上的部分设置位置相对应。上述NM卡的DAT3 0224在NM卡的卡体021上的设置位置与上述Nano SIM卡的GND 0323在Nano SIM卡的卡体031上的设置位置相对应。上述NM卡的DAT2 0225在NM卡的卡体021上的设置位置与上述Nano SIM卡的VCC 0324在Nano SIM卡的卡体031上的设置位置相对应。上述NM卡的VCC 0226在NM卡的卡体021上的设置位置与上述Nano SIM卡的VCC 0324在Nano SIM卡的卡体031上的设置位置相对应。上述NM卡的DAT0 0227在NM卡的卡体021上的设置位置与上述Nano SIM卡的RST 0325在Nano SIM卡的卡体031上的设置位置相对应。上述NM卡的CLK 0228在NM卡的卡体021上的设置位置与上述Nano SIM卡的CLK 0326在Nano SIM卡的卡体031上的设置位置相对应。具体的，该各个端子的设置位置之间的对应关系参照图4，由这些端子的设置位置之间的对应关系可知：Nano SIM卡03可以与NM卡02的卡座相匹配。
存储卡的读写速度是影响存储卡的性能的一项重要指标，同时，随着手机、平板电脑等电子设备趋向于薄型化和功能多样化发展，电子设备内用于安装存储卡的空间越来越小，存储卡的体积和占板面积也趋向于小型化发展。
为了同时达到提高存储卡的读写速度和减小存储卡的体积的目的，本申请一些实施例提供了一种电子设备，该电子设备包括但不限于手机、平板、可穿戴设备等包括存储卡的设备。
图5为本申请一些实施例提供的电子设备的结构示意图，如图5所示，该电子设备1包括电路板11和设置于该电路板11上的卡座12。该卡座12包括卡座主体121和卡座接口(图中未示出)，卡座接口与电路板11电连接。
本申请一些实施例还提供了一种存储卡2，该存储卡2支持UFS卡的协议，且该 存储卡2能够安装于电子设备1的卡座12内进行使用，以扩充电子设备1的存储空间。
图6(a)和图6(b)为本申请一些实施例提供的存储卡2的结构示意图。如图6(a)和图6(b)所示，该存储卡2包括存储卡卡体21和存储卡接口22。
需要说明的是，在上述实施例中，存储卡接口22的结构形式有多种，图6(b)仅给出了存储卡接口22的一种结构形式，并不能认为对上述实施例构成限定。
图6(a)中示出了与NM卡02的8个端子位置相对应的8个端子221-228。端子221的位置对应端子0221，端子222的位置对应端子0222，端子223的位置对应端子0228，端子224的位置对应端子0227，端子225的位置对应端子0226，端子226的位置对应端子0223，端子227的位置对应端子0225，端子228的位置对应端子0224。
存储卡卡体21与图2(a)和图2(b)所示的NM卡02的卡体021的外形和尺寸相同，存储卡卡体21与图3(a)和图3(b)所示的Nano SIM卡的卡体031的外形和尺寸也相同。
由于存储卡卡体21与NM卡02的卡体021的外形和尺寸相同，NM卡02的长度为8.8mm，宽度为12.3mm，厚度为0.84mm，NM卡02的占板面积为8.8mm×12.3mm，NM卡02的体积为8.8mm×12.3mm×0.84mm，比现有技术的UFS卡的占板面积和体积小，且存储卡接口22的尺寸较小，基本可以忽略不计，因此本申请实施例提供的存储卡的体积和占板面积比现有技术的UFS卡的占板面积和体积小，可以减小存储卡在电子设备主机内的占用空间和占板面积。
图7为本申请一些实施例提供的存储卡2的结构框图。如图7所示，存储卡卡体21包括封装结构211和设置于该封装结构211内的存储单元212、控制单元213和参考地215，存储单元212与控制单元213电连接，存储单元212与参考地215电连接，控制单元213与参考地215电连接。封装结构211用于对存储单元212、控制单元213、参考地215、存储单元212与控制单元213之间、存储单元212与参考地215之间以及控制单元213与参考地215之间的电连接线路进行封装，以保护存储单元212、控制单元213以及存储单元212与控制单元213之间的电连接线路。封装结构211的材料为介电材料，该介电材料包括但不限于乙烯醋酸乙烯酯(ethylene-vinyl acetate，EVA)、聚乙烯醇缩丁醛(polyvinyl butyral，PVB)，离聚物、聚烯烃(polyolefins，PO)，硅、热塑性聚氨酯等材料。
如图6(a)所示，存储卡接口22设置于存储卡卡体21上，且该存储卡接口22包括一对差分数据输入端子和一对差分数据输出端子。一对差分数据输入端子包括第一差分数据输入端子和第二差分数据输入端子，该一对差分数据输入端子用于传输向存储卡卡体21输入的差分数据。一对差分数据输出端子包括第一差分数据输出端子和第二差分数据输出端子，该一对差分数据输出端子用于传输存储卡卡体21输出的差分数据。第一差分数据输入端子、第二差分数据输入端子、第一差分数据输出端子和第二差分数据输出端子224均与存储卡卡体21的控制单元213(如图7所示)电连接。
需要说明的是，在上述实施例中，第一差分数据输入端子、第二差分数据输入端子、第一差分数据输出端子和第二差分数据输出端子在存储卡卡体21上的设置位置可以有多种，这4个端子可以是端子221-228中的任意一个，图6(a)仅给出了在存储卡卡体21上，第一差分数据输入端子是端子221、第二差分数据输入端子是端子222、 第一差分数据输出端子是端子223和第二差分数据输出端子是端子224的一种示例，并不能认为对上述实施例构成的限定。
由于本申请实施例提供的存储卡2的存储卡接口22包括一对差分数据输入端子和一对差分数据输出端子，该一对差分数据输入端子用于传输向存储卡卡体21输入的差分数据，该一对差分数据输出端子用于传输存储卡卡体21输出的差分数据，因此在存储卡2插入电子设备1的卡座12内之后，存储卡2可以采用该一对差分数据输入端子以及该一对差分数据输出端子与电子设备1进行差分串行数据传输，差分串行数据传输方式的准确性较高，传输速度较快，能够保证存储卡2的读写速度。
如图6(a)所示，存储卡接口22还包括电源端子225。电源端子225与存储卡卡体21的存储单元212和控制单元213(如图7所示)均电连接，电源端子225用于向存储单元212和控制单元213供电。
需要说明的是，在上述实施例中，电源端子在存储卡卡体21上的设置位置可以有多种，例如可以是端子221-228中的任意一个，图6(a)仅给出了电源端子在存储卡卡体21上的设置位置是端子225一种示例，并不能认为对上述实施例构成的限定。
相比于UFS卡01上采用两个电源端子(分别为VCCQ2 0122和VCC 0127)供电(如图1(a)所示)，本申请实施例提供的存储卡2的存储卡接口22采用一个电源端子225供电，电源端子的数量较少，能够将存储卡卡体21的外形和尺寸缩小至与NM卡02的卡体021的外形和尺寸相同。
如图6(a)所示，存储卡接口22还包括接地端子226。接地端子226与参考地215电连接(如图7所示)，接地端子226用于接地。
需要说明的是，在上述实施例中，接地端子在存储卡卡体21上的设置位置可以有多种，例如可以是端子221-228中的任意一个，图6(a)仅给出了接地端子在存储卡卡体21上的设置位置是端子226的一种示例，并不能认为对上述实施例构成的限定。
相比于UFS卡01上采用四个接地端子(分别为VSS 0124、VSS 0128、VSS 0129和VSS 0132)接地(如图1(a)所示)，本申请实施例提供的存储卡2的存储卡接口22采用一个接地端子226接地，接地端子的数量较少，能够将存储卡卡体21的外形和尺寸缩小至与NM卡02的卡体021的外形和尺寸相同。
如图6(a)所示，存储卡接口22还包括时钟端子227。时钟端子227与存储卡卡体21的控制单元213(如图7所示)电连接，时钟端子227用于传输时钟信号。
需要说明的是，在上述实施例中，时钟端子在存储卡卡体21上的设置位置可以有多种，例如可以是端子221-228中的任意一个，图6(a)仅给出了时钟端子在存储卡卡体21上端子227的一种示例，并不能认为对上述实施例构成的限定。
第一差分数据输入端子、第二差分数据输入端子、第一差分数据输出端子、第二差分数据输出端子、电源端子、接地端子226和时钟端子在存储卡卡体21上的设置位置分别与DAT1 0221、COM 0222、GND 0223、DAT3 0224、DAT2 0225、VCC 0226、DAT0 0227、CLK 0228中的七个在NM卡02的卡体021(如图2(a)所示)上的设置位置分别一一对应。
图6(a)仅给出了第一差分数据输入端子、第二差分数据输入端子、第一差分数据输出端子、第二差分数据输出端子、电源端子、接地端子和时钟端子分别位于图6 (a)的端子221-227一种示例，并不能认为对上述实施例构成的限定。
另外，需要说明的是，第一差分数据输入端子、第二差分数据输入端子、第一差分数据输出端子、第二差分数据输出端子、电源端子、接地端子和时钟端子在存储卡卡体21上的设置位置分别与DAT1 0221、COM 0222、GND 0223、DAT3 0224、DAT2 0225、VCC 0226、DAT0 0227、CLK 0228中的七个在NM卡02的卡体021(如图2(a)所示)上的设置位置相对应，是指：第一差分数据输入端子、第二差分数据输入端子、第一差分数据输出端子、第二差分数据输出端子、电源端子、接地端子和时钟端子在存储卡卡体21上的设置区域分别与DAT1 0221、COM 0222、GND 0223、DAT3 0224、DAT2 0225、VCC 0226、DAT0 0227、CLK 0228中的七个在NM卡02的卡体021(如图2(a)所示)上的设置区域之间至少部分区域的形状、大小和中心位置相同，且当本申请实施例提供的存储卡2插入NM卡02的卡座时，NM卡02的卡座的卡座接口内用于与DAT1 0221、COM 0222、GND 0223、DAT3 0224、DAT2 0225、VCC 0226、DAT0 0227、CLK 0228中的七个接触的卡座端子能够与第一差分数据输入端子、第二差分数据输入端子、第一差分数据输出端子、第二差分数据输出端子、电源端子、接地端子和时钟端子分别接触。第一差分数据输入端子、第二差分数据输入端子、第一差分数据输出端子、第二差分数据输出端子、电源端子、接地端子和时钟端子在存储卡卡体21上的设置区域分别与DAT1 0221、COM 0222、GND 0223、DAT3 0224、DAT2 0225、VCC 0226、DAT0 0227、CLK 0228中的七个在NM卡02的卡体021(如图2(a)所示)上的设置区域之间可以部分区域的形状、大小和中心位置相同，也可以全部区域的形状、大小和中心位置相同，在此不做具体限定。在一些实施例中，如图6(a)所示，第一差分数据输入端子221、第二差分数据输入端子222、第一差分数据输出端子223、第二差分数据输出端子224、电源端子225、接地端子226和时钟端子227在存储卡卡体21上的设置区域分别与DAT1 0221、COM 0222、GND 0223、DAT2 0225、VCC 0226、DAT0 0227、CLK 0228在NM卡02的卡体021(如图2(a)所示)上的设置区域之间全部区域的形状、大小和中心位置相同。
由于本申请实施例提供的存储卡的一对差分数据输入端子、一对差分数据输出端子、电源端子、接地端子和时钟端子在存储卡卡体上的设置位置分别与DAT1 0221、COM 0222、GND 0223、DAT3 0224、DAT2 0225、VCC 0226、DAT0 0227、CLK 0228中的七个在NM卡02的卡体021(如图2(a)所示)上的设置位置相对应，因此，存储卡能够与NM卡的卡座相匹配。
为了使电源端子能够同时向存储卡卡体21的存储单元212和控制单元213供电，在一些实施例中，可以使存储单元212和控制单元213的工作电压相等。这样一来，就可以采用一个电源端子直接向存储单元212和控制单元213供电。在另一些实施例中，控制单元213的工作电压与存储单元212的工作电压不相等，当由电源端子供入的电源电压与存储单元212的工作电压相等时，如图7所示，电源端子与控制单元213之间的电连接线路中串接有第一电压调节装置214，该第一电压调节装置214用于将由电源端子供入的电源电压调节至与控制单元213的工作电压相等。当由电源端子供入的电源电压与控制单元213的工作电压相等时，电源端子与存储单元212之间的电连接线路中串接有第二电压调节装置(图中未示出)，第二电压调节装置用于将由电 源端子供入的电源电压调节至与存储单元212的工作电压相等。当由电源端子供入的电源电压与存储单元212的工作电压和控制单元213的工作电压均不等时，电源端子与控制单元213之间的电连接线路中串接有第三电压调节装置(图中未示出)，电源端子与存储单元212之间的电连接线路中串接有第四电压调节装置(图中未示出)，第三电压调节装置用于将由电源端子供入的电源电压调节至与控制单元213的工作电压相等，第四电压调节装置用于将由电源端子供入的电源电压调节至与存储单元212的工作电压相等。这样一来，在控制单元213的工作电压与存储单元212的工作电压不相等的情况下，仍可以采用一个电源端子同时向存储单元212和控制单元213供电，无需在存储卡卡体21上设置两个电源端子来分别向存储单元212和控制单元213供电，因此，能够减少存储卡的端子的数量，有利于减小存储卡的体积和占板面积。图7中以电源端子位于图6(a)所示的端子225的位置为例进行示意。
在上述实施例中，控制单元213的工作电压可以为1.75V、1.9V、1.8V，在此不做具体限定。在一些实施例中，控制单元213的工作电压为1.8V。存储单元212的工作电压可以为2.85V、3.0V、3.15V，在此不做具体限定。在一些实施例中，存储单元212的工作电压为3.0V。
在一些实施例中，第一电压调节装置214可以为低压差线性稳压器(low dropout regulator，LDO)。此结构简单，容易实现。
第一差分数据输入端子与第二差分数据输入端子可以分散设置，也可以相邻设置，在此不做具体限定。在一些实施例中，如图6(a)所示，第一差分数据输入端子221与第二差分数据输入端子222相邻设置。这样一来，第一差分数据输入端子221和第二差分数据输入端子222所处环境近似相同，受到的外界干扰近似相等，能够相互抵消以保证输入信号传输的准确性。
需要说明的是，在上述实施例中，第一差分数据输入端子和第二差分数据输入端子在存储卡卡体21上的设置位置可以有多种，只要满足第一差分数据输入端子与第二差分数据输入端子相邻即可，图6(a)仅给出了第一差分数据输入端子221和第二差分数据输入端子222在存储卡卡体21上的设置位置的一种示例，并不能认为对上述实施例构成的限定。例如第一差分数据输入端子与第二差分数据输入端子可以分为位于图6(a)中端子226和228的位置。
在一些实施例中，第一差分数据输入端子在存储卡卡体21上的设置位置与DAT1 0221和COM 0222(如图2(a)所示)中的一个在NM卡02的卡体021上的设置位置相对应，第二差分数据输入端子在存储卡卡体21上的设置位置与DAT1 0221和COM 0222(如图2(a)所示)中的另一个在NM卡02的卡体021上的设置位置相对应，即第一差分数据输入端子和第二差分数据输入端子分别位于图6(a)中端子221和222的位置，两者位置可以互换。或者，第一差分数据输入端子在存储卡卡体21上的设置位置与DAT0 0227和CLK 0228(如图2(a)所示)中的一个在NM卡02的卡体021上的设置位置相对应，第二差分数据输入端子在存储卡卡体21上的设置位置与DAT0 0227和CLK 0228(如图2(a)所示)中的另一个在NM卡02的卡体021上的设置位置相对应，即第一差分数据输入端子和第二差分数据输入端子分别位于图6(a)中端子223和224的位置，两者位置可以互换。由于DAT1 0221与COM 0222 之间的距离以及DAT0 0227与CLK 0228之间的距离均较近，因此第一差分数据输入端子和第二差分数据输入端子所处环境近似相同，受到的外界干扰近似相等，能够相互抵消以进一步保证输入信号传输的准确性。
同理地，第一差分数据输出端子与第二差分数据输出端子可以分散布置，也可以相邻布置，在此不做具体限定。在一些实施例中，如图6(a)所示，第一差分数据输出端子223与第二差分数据输出端子224相邻设置。这样一来，第一差分数据输出端子223和第二差分数据输出端子224所处环境近似相同，受到的外界干扰近似相等，能够相互抵消以保证输出信号传输的准确性。
需要说明的是，在上述实施例中，第一差分数据输出端子和第二差分数据输出端子在存储卡卡体21上的设置位置可以有多种，只要满足第一差分数据输出端子和第二差分数据输出端子相邻即可，图6(a)仅给出了第一差分数据输出端子223和第二差分数据输出端子224在存储卡卡体21上的设置位置的一种示例，并不能认为对上述实施例构成的限定。
在一些实施例中，第一差分数据输出端子在存储卡卡体21上的设置位置与DAT0 0227和CLK 0228(如图2(a)所示)中的一个在NM卡02的卡体021上的设置位置相对应，第二差分数据输出端子在存储卡卡体21上的设置位置与DAT0 0227和CLK 0228(如图2(a)所示)中的另一个在NM卡02的卡体021上的设置位置相对应，即第一差分数据输出端子和第二差分数据输出端子位于图6(a)中端子223和224的位置，两者位置可以互换。或者，第一差分数据输出端子在存储卡卡体21上的设置位置与DAT1 0221和COM 0222(如图2(a)所示)中的一个在NM卡02的卡体021上的设置位置相对应，第二差分数据输出端子在存储卡卡体21上的设置位置与DAT1 0221和COM 0222(如图2(a)所示)中的另一个在NM卡02的卡体021上的设置位置相对应，即第一差分数据输出端子和第二差分数据输出端子位于图6(a)中端子221和222的位置，两者位置可以互换。DAT1 0221与COM 0222之间的距离以及DAT0 0227与CLK 0228之间的距离均较近，因此第一差分数据输出端子与第二差分数据输出端子之间的距离较近，第一差分数据输出端子和第二差分数据输出端子所处环境近似相同，受到的外界干扰近似相等，能够相互抵消以进一步保证输出信号传输的准确性。
需要说明的是，图6(a)示出了存储卡可以具有与NM卡02的端子布局相对应的8个端子221-228，即存储卡的端子221-228，其在存储卡上的布局与NM卡02上端子0221，0222,0228,0227,0226,0223,0225,0224的布局相对应。存储卡的第一差分数据输入端子、第二差分数据输入端子、第一差分数据输出端子、第二差分数据输出端子、电源端子、接地端子和时钟端子可以分别位于221-228个端子中7个端子的位置上，可以理解的，存储卡上多出的一个端子可以不与存储卡的内部电路相连接，或者去掉这个端子。存储卡可以具有NM卡02的端子布局中端子0221-0228中7个端子位置相对应的7个端子，比如存储卡可以只具有7个端子，其在存储卡上的布局与NM卡02上端子0221-0227的布局相对应，或者与NM卡02上端子0222-0228的布局相对应。
作为一种示例，存储卡的第一差分数据输入端子、第二差分数据输入端子、第一 差分数据输出端子、第二差分数据输出端子、电源端子、接地端子和时钟端子分位于图6(a)中的端子221-227的位置。以下实施例中，以此布局为例进行说明。
为了防止一对差分数据输入端子与一对差分数据输出端子之间产生相互干扰，同时为了减少外界环境噪声对该一对差分数据输入端子和该一对差分数据输出端子产生干扰，在一些实施例中，图8为本申请一些实施例提供的存储卡的内部结构示意图。如图8所示，存储卡卡体21包括封装结构211以及设置于该封装结构211内的控制单元213和参考地215。封装结构211包括层叠设置的第一封装层2111和第二封装层2112，存储卡接口22设置于第一封装层2111上且从封装结构中露出，控制单元213和参考地215设置于第二封装层2112上且封闭在封装结构中。控制单元213具有一对差分数据输入引脚和一对差分数据输出引脚。一对差分数据输入引脚与存储卡接口22的一对差分数据输入端子(包括第一差分数据输入端子221和第二差分数据输入端子222)电连接，一对差分数据输入引脚与存储卡接口22的一对差分数据输入端子之间的电连接线路为第一电连接线路c。一对差分数据输出引脚与存储卡接口22的一对差分数据输出端子(包括第一差分数据输出端子223和第二差分数据输出端子224)电连接，且一对差分数据输出引脚与存储卡接口22的一对差分数据输出端子之间的电连接线路为第二电连接线路d。参考地215与存储卡接口22的接地端子226电连接，参考地215与接地端子226之间的电连接线路为第三电连接线路b。第三电连接线路b为多条，多条第三电连接线路b组成三组第三电连接线路，每组第三电连接线路均包括至少一条第三电连接线路，且所述三组第三电连接线路分别为第一组第三电连接线路b 1、第二组第三电连接线路b 2和第三组第三电连接线路b 3。第一组第三电连接线路b 1经过第一电连接线路c与第二电连接线路d之间，并经过一对差分数据输入端子与一对差分数据输出端子之间。第二组第三电连接线路b 2经过第一电连接线路c远离第二电连接线路d的一侧，并经过一对差分数据输入端子远离一对差分数据输出端子的一侧。第三组第三电连接线路b 3经过第二电连接线路d远离第一电连接线路c的一侧，并经过一对差分数据输出端子远离一对差分数据输入端子的一侧。
这样一来，可以通过第一组第三电连接线路b 1实现一对差分数据输入端子与一对差分数据输出端子之间以及第一电连接线路c与第二电连接线路d之间的隔离，避免该一对差分数据输入端子与该一对差分数据输出端子之间以及第一电连接线路c与第二电连接线路d之间产生相互干扰。同时通过第二组第三电连接线路b 2和第三组第三电连接线路b 3实现了一对差分数据输入端子、一对差分数据输出端子、第一电连接线路c以及第二电连接线路d与存储卡2的外界环境之间的隔离，减少外界环境噪声对该一对差分数据输入端子、该一对差分数据输出端子、第一电连接线路c以及第二电连接线路d产生干扰。
为了防止第一电连接线路c与第二电连接线路d之间，以及第一电连接线路c和第二电连接线路d与存储卡2的外界环境之间产生干扰，在一些实施例中，如图8所示，控制单元213还具有接地引脚2131。该接地引脚2131的数量为多个，多个接地引脚2131包括第一接地引脚21311、第二接地引脚21312和第三接地引脚21313，第一接地引脚21311、第二接地引脚21312和第三接地引脚21313均与参考地215电连接。第一接地引脚21311设置于一对差分数据输入引脚与一对差分数据输出引脚之间， 第一接地引脚21311与参考地215之间的电连接线路位于第一电连接线路c与第二电连接线路d之间。第二接地引脚21312设置于一对差分数据输入引脚远离一对差分数据输出引脚的一侧，且第二接地引脚21312与参考地215之间的电连接线路位于第一电连接线路c远离第二电连接线路d的一侧。第三接地引脚21313设置于一对差分数据输出引脚远离一对差分数据输入引脚的一侧，且第三接地引脚21313与参考地215之间的电连接线路位于第二电连接线路d远离第一电连接线路c的一侧。
这样一来，可以通过第一接地引脚21311以及第一接地引脚21311与参考地215之间的电连接线路实现一对差分数据输入引脚与一对差分数据输出引脚之间以及第一电连接线路c与第二电连接线路d之间的隔离，避免该一对差分数据输入引脚与一对差分数据输出引脚之间以及第一电连接线路c与第二电连接线路d之间产生相互干扰。同时通过第二接地引脚21312和第三接地引脚21313实现了一对差分数据输入引脚、一对差分数据输出引脚、第一电连接线路c以及第二电连接线路d与存储卡2的外界环境之间的隔离，减少外界环境噪声对该一对差分数据输入引脚、一对差分数据输出引脚、第一电连接线路c以及第二电连接线路d产生干扰。
如前文描述可知，Nano SIM卡03可以与NM卡02的卡座相匹配，本申请实施例提供的存储卡2也可以与NM卡02的卡座相匹配，因此Nano SIM卡03与本申请实施例提供的存储卡2可以共用同一卡座。这样一来，如图5所示，电子设备1的卡座12可以为匹配Nano SIM卡03、本申请实施例提供的存储卡2以及NM卡02的NM卡卡座。在此基础上，为了使电子设备1能够识别并运行Nano SIM卡03、本申请实施例提供的存储卡2和NM卡02，图9为本申请一些实施例提供的电子设备的结构示意图。如图9所示，电子设备1包括电路板11和卡座12，卡座12包括卡座主体121和卡座接口，卡座主体121围成卡槽，卡槽用于容纳NM卡02的卡体，卡座接口设置于该卡槽的内壁上。电路板11包括Nano SIM卡控制器111、存储卡控制器112、NM卡控制器113、开关114、检测电路115和控制电路116。Nano SIM卡控制器111用于控制Nano SIM卡03运行。存储卡控制器112用于控制本申请实施例提供的存储卡2运行。NM卡控制器113用于控制NM卡02运行。卡座12的卡座接口通过开关114与Nano SIM卡控制器111、存储卡控制器112或者NM卡控制器113连接。卡座12的卡座接口连接开关114的一端为第一端k 1，Nano SIM卡控制器111连接开关114的一端为第二端k 2，存储卡控制器112连接开关114的一端为第三端k 3，NM卡控制器113连接开关114的一端为第四端k 4。检测电路115用于通过卡座接口检测安装于卡槽内的卡，控制电路116用于根据检测电路115的检测结果，识别安装于卡槽内的卡为Nano SIM卡03、存储卡2或者NM卡02，并根据识别结果，控制开关114的第一端k 1连接开关114的第二端k 2，或者控制开关114的第一端k 1连接开关114的第三端k 3，或者控制开关114的第一端k 1连接开关114的第四端k 4。
在上述实施例中，需要说明的是，第一端k 1、第二端k 2、第三端k 3和第四端k 4均包括多个(比如6个或者8个)连接端子，且第一端k 1、第二端k 2、第三端k 3和第四端k 4包括的连接端子的数量相等。第一端k 1的多个连接端子分别与卡座接口内的多个卡座端子一一对应连接。第二端k 2包括多个连接端子分别与Nano SIM卡控制器111的多个端子一一对应连接。第三端k 3包括多个连接端子分别与存储卡控制器112的多 个端子一一对应连接。第四端k 4包括多个连接端子分别与NM卡控制器113的多个端子一一对应连接。当第一端k 1与第二端k 2连接时，第一端k 1包括的多个连接端子与第二端k 2包括的多个连接端子一一对应连接。当第一端k 1与第三端k 3连接时，第一端k 1包括的多个连接端子与第三端k 3包括的多个连接端子一一对应连接。当第一端k 1与第四端k 4连接时，第一端k 1包括的多个连接端子与第四端k 4包括的多个连接端子一一对应连接。可以理解地，k1-k4端子中与电源端子和地端子相连的端子。
这样一来，若检测电路115检测出安装于卡座12内的卡为Nano SIM卡03，则可以通过控制电路116控制开关114的第一端k 1连接开关114的第二端k 2，以使Nano SIM卡03通过卡座12的卡座接口与Nano SIM卡控制器111连接。若检测电路115检测出安装于卡座12内的卡为存储卡2，则可以通过控制电路116控制开关114的第一端k 1连接开关114的第三端k 3，以使存储卡2通过卡座12的卡座接口与存储卡控制器112连接。若检测电路115检测出安装于卡座12内的卡为NM卡02，则可以通过控制电路116控制开关114的第一端k 1连接开关114的第四端k 4，以使NM卡02通过卡座12的卡座接口与NM卡控制器113连接。由此使电子设备1能够识别并运行Nano SIM卡03、本申请实施例提供的存储卡2和NM卡02。此结构简单，容易实现。
在上述实施例中，卡座12的卡座接口包括多个卡座端子，该多个卡座端子可以全部通过开关114与Nano SIM卡控制器111、存储卡控制器112或者NM卡控制器113连接，也可以部分通过开关114与Nano SIM卡控制器111、存储卡控制器112或者NM卡控制器113连接，在此不做具体限定，决定此结果的关键为：Nano SIM卡03、存储卡2和NM卡02上是否存在具有作用相同且在卡体上的设置位置相对应的端子。若存在这样的端子，则该端子无需通过开关114与Nano SIM卡控制器111、存储卡控制器112或者NM卡控制器113连接，此时可以降低电路的复杂度，节省成本。若不存在这样的端子，则卡座12的卡座接口包括的全部卡座端子均需通过开关114与Nano SIM卡控制器111、存储卡控制器112或者NM卡控制器113连接。
在一些实施例中，如图6(a)所示，接地端子226在存储卡卡体21上的设置位置与GND 0223在NM卡02的卡体021(如图2(a)所示)上的设置位置相对应。由于NM卡02的GND 0223在NM卡02的卡体021上的设置位置与Nano SIM卡03的GND 0323在Nano SIM卡的卡体031(如图3(a)所示)上的部分设置位置相对应，且接地端子226、GND 0223和GND 0323均用于接地，因此图9所示的电子设备1内卡座12的卡座接口中用于与Nano SIM卡03的GND 0323、存储卡2的接地端子226或NM卡02的GND 0223接触的卡座端子无需通过开关114与Nano SIM卡控制器111、存储卡控制器112或者NM卡控制器113连接，这样一来，可以降低电路板11的电路的复杂度，节省成本。
在一些实施例中，如图6(a)所示，电源端子225在存储卡卡体21上的设置位置与VCC 0226在NM卡02的卡体021(如图2(a)所示)上的设置位置相对应。由于NM卡02的VCC 0226在NM卡02的卡体021上的设置位置与Nano SIM卡的VCC 0324在Nano SIM卡的卡体031(如图3(a)所示)上的设置位置相对应，且电源端子225、VCC 0226和VCC 0324均用于供电，因此图9所示的电子设备1内卡座12的卡座接口中用于与Nano SIM卡03的VCC 0324、存储卡2的电源端子225或NM 卡02的VCC 0226接触的卡座端子无需通过开关114与Nano SIM卡控制器111、存储卡控制器112或者NM卡控制器113连接，这样一来，可以降低电路板11的电路的复杂度，节省成本。
为了识别Nano SIM卡03、本申请实施例提供的存储卡2和NM卡02，在一些实施例中，第一差分数据输入端子、第二差分数据输入端子222、第一差分数据输出端子、第二差分数据输出端子、电源端子、接地端子和时钟端子在存储卡卡体21上的设置位置分别与DAT1 0221、COM 0222、GND 0223、DAT2 0225、VCC 0226、DAT0 0227、CLK 0228在NM卡02的卡体021(如图2(a)所示)上的设置位置相对应，此处对应不是指一一对应，例如第一差分数据输入端子的位置可以对应DAT1 0221、COM 0222、GND 0223、DAT2 0225、VCC 0226、DAT0 0227、CLK 0228中的任意一个端子的位置。存储卡卡体21上与DAT3 0224在NM卡02的卡体021(如图2(a)所示)上的设置位置相对应的位置未设置端子或者设有检测端子228，该检测端子228与存储卡卡体21之间未电连接，为独立端子，即该检测端子与存储卡内部电路之间未电连接且与存储卡的其他端子无电连接。由于NM卡的DAT3 0224在NM卡的卡体021上的设置位置与Nano SIM卡的GND 0323在Nano SIM卡的卡体031上的设置位置相对应，且Nano SIM卡03和本申请实施例提供的存储卡2均可以与NM卡02的卡座相匹配，假设NM卡的卡座上用于与NM卡的DAT3 0224接触的卡座端子为第一卡座端子，因此在将卡插入图9所示电子设备的卡座内之后，可以通过检测电路115检测与该第一卡座端子接触的端子，并通过控制电路116根据检测电路115的检测结果，判断该第一卡座端子接触的端子为GND 0323、DAT3 0224，或者没有端子接触，来达到识别Nano SIM卡03、本申请实施例提供的存储卡2和NM卡02的目的。
本申请一些实施例还提供了一种通过卡座识别Nano SIM卡、上述实施例所述的存储卡和NM卡的方法。其中，卡座包括卡座主体和卡座接口，卡座主体围成卡槽，卡槽用于容纳NM卡02的卡体，卡座接口设置于该卡槽的内壁上，卡座接口具有八个卡座端子，该八个卡座端子分别用于与NM卡的DAT1、COM、GND、DAT3、DAT2、VCC、DAT0和CLK接触，该八个卡座端子中用于与DAT3接触的卡座端子为第一卡座端子，如图10所示，识别Nano SIM卡、上述实施例所述的存储卡和NM卡的方法包括：
S100：检测与第一卡座端子接触的端子；
S200：判断该端子是接地端子或者信号端子，或者没有端子与所述第一卡座端子接触；
S300：当与第一卡座端子接触的端子为接地端子时，则识别卡座内插入的卡为Nano SIM卡03，与第一卡座端子接触的端子为GND 0323；
S400：当与第一卡座端子接触的端子为信号端子时，则识别卡座内插入的卡为NM卡02，与第一卡座端子接触的端子为DAT3 0224；
S500：当没有端子与第一卡座端子接触时，则识别卡座内插入的卡为上述实施例所述的存储卡2。可以理解地，检测端子为独立端子，可以视为没有端子与第一卡座端子接触。
这样一来，就可以通过卡座识别Nano SIM卡03、上述实施例所述的存储卡2和 NM卡02。
在步骤S300之后，执行Nano SIM卡03的流程，如初始化流程，以及后续使用流程。
在步骤S400之后，执行NM卡02的流程，如初始化流程，以及后续使用流程。
在步骤S500之后，执行存储卡2的流程，如初始化流程，以及后续使用流程。
具体地，可以采用图11所示的检测电路115来检测与第一卡座端子接触的端子为接地端子或者信号端子，或者没有端子与第一卡座端子接触。如图11所示，检测电路115为由两个缓冲器1151和一个电阻1152(阻值为1MΩ)连接形成的一个电路，且检测电路115具有A端、B端和C端，B端与第一卡座端子连接，由A端向检测电路115先后供入不同电压值的电压，比如先后供入1.8V和0V的电压。若检测到C端的电压值恒为0，则判断第一卡座端子接触的是接地端子。若检测到C端的电压值随A端供入的电压值变化而变化，且等于当前A端供入的电压值，则判断无端子与第一卡座端子接触。若检测到C端的电压值比当前A端供入的电压值小预设值以上，则判断第一卡座端子接触的是信号端子。
在上述实施例中，预设值大于0，具体的预设值可以为0.2V、0.3V或者0.5V等等，在此不做具体限定。
需要说明的是，Nano SIM卡03、本申请实施例提供的存储卡2和NM卡02是否插入卡座12内可以通过在卡座12内设置机械弹簧装置检测到。
可以理解地，上述检测电路和检测方法可以只用于检测Nano SIM卡03、本申请实施例提供的存储卡2和NM卡02，即电子设备中只有Nano SIM卡控制器111、存储卡控制器112、NM卡控制器113中的2个时，检测电路和检测方法可以适配为区分两种卡的场景。例如Nano SIM卡控制器111，存储卡控制器112，那么上述方法流程只需要区分与第一卡座端子接触的端子是接地端子还是没有端子与第一卡座端子接触。
在本说明书的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
最后应说明的是：以上实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的精神和范围。

Claims (11)

  1. 一种存储卡，其特征在于，包括：
    存储卡卡体，与NM卡的卡体的外形和尺寸相同；
    存储卡接口，设置于所述存储卡卡体上，且所述存储卡接口包括一对差分数据输入端子和一对差分数据输出端子、电源端子、接地端子和时钟端子，所述一对差分数据输入端子包括第一差分数据输入端子和第二差分数据输入端子，所述一对差分数据输入端子用于传输向所述存储卡卡体输入的差分数据，所述一对差分数据输出端子包括第一差分数据输出端子和第二差分数据输出端子，所述一对差分数据输出端子用于传输所述存储卡卡体输出的差分数据，所述电源端子用于供电，所述接地端子用于接地，所述时钟端子用于传输时钟信号；
    所述第一差分数据输入端子、所述第二差分数据输入端子、所述第一差分数据输出端子、所述第二差分数据输出端子、所述电源端子、所述接地端子和所述时钟端子在所述存储卡卡体上的设置位置分别与DAT1、COM、GND、DAT3、DAT2、VCC、DAT0和CLK中的七个在所述NM卡的卡体上的设置位置相对应。
  2. 根据权利要求1所述的存储卡，其特征在于，所述存储卡卡体包括封装结构和设置于所述封装结构内的控制单元和存储单元，由所述电源端子供入的电源电压与所述存储单元的工作电压相等，由所述电源端子供入的电源电压与所述控制单元的工作电压不相等，所述电源端子与所述存储单元直接电连接，所述电源端子与所述控制单元之间的电连接线路中串接有电压调节装置，所述电压调节装置用于将由所述电源端子供入的电源电压调节至与所述控制单元的工作电压相等。
  3. 根据权利要求1或2所述的存储卡，其特征在于，所述第一差分数据输入端子与所述第二差分数据输入端子相邻设置；
    所述第一差分数据输出端子与所述第二差分数据输出端子相邻设置。
  4. 根据权利要求3所述的存储卡，其特征在于，所述第一差分数据输入端子在所述存储卡卡体上的设置位置与DAT1和COM中的一个在所述NM卡的卡体上的设置位置相对应，所述第二差分数据输入端子在所述存储卡卡体上的设置位置与DAT1和COM中的另一个在所述NM卡的卡体上的设置位置相对应，所述第一差分数据输出端子在所述存储卡卡体上的设置位置与DAT0和CLK中的一个在所述NM卡的卡体上的设置位置相对应，所述第二差分数据输出端子在所述存储卡卡体上的设置位置与DAT0和CLK中的另一个在所述NM卡的卡体上的设置位置相对应；
    或者，所述第一差分数据输入端子在所述存储卡卡体上的设置位置与DAT0和CLK中的一个在所述NM卡的卡体上的设置位置相对应，所述第二差分数据输入端子在所述存储卡卡体上的设置位置与DAT0和CLK中的另一个在所述NM卡的卡体上的设置位置相对应，所述第一差分数据输出端子在所述存储卡卡体上的设置位置与DAT1和COM中的一个在所述NM卡的卡体上的设置位置相对应，所述第二差分数据输出端子在所述存储卡卡体上的设置位置与DAT1和COM中的另一个在所述NM卡的卡体上的设置位置相对应。
  5. 根据权利要求3或4所述的存储卡，其特征在于，所述存储卡卡体包括封装结构以及设置于所述封装结构内的控制单元和参考地，所述封装结构包括层叠设置的第 一封装层和第二封装层，所述存储卡接口设置于所述第一封装层上，所述控制单元和所述参考地设置于所述第二封装层上；
    所述控制单元具有一对差分数据输入引脚和一对差分数据输出引脚；
    所述一对差分数据输入引脚与所述存储卡接口的一对差分数据输入端子电连接，且所述一对差分数据输入引脚与所述存储卡接口的一对差分数据输入端子之间的电连接线路为第一电连接线路；
    所述一对差分数据输出引脚与所述存储卡接口的一对差分数据输出端子电连接，且所述一对差分数据输出引脚与所述存储卡接口的一对差分数据输出端子之间的电连接线路为第二电连接线路；
    所述参考地与所述存储卡接口的接地端子电连接，所述参考地与所述存储卡接口的接地端子之间的电连接线路为第三电连接线路，所述第三电连接线路为多条，多条所述第三电连接线路组成三组第三电连接线路，每组第三电连接线路均包括至少一条第三电连接线路，且所述三组第三电连接线路分别为第一组第三电连接线路、第二组第三电连接线路和第三组第三电连接线路；
    所述第一组第三电连接线路经过所述第一电连接线路与所述第二电连接线路之间，并经过所述一对差分数据输入端子与所述一对差分数据输出端子之间；
    所述第二组第三电连接线路经过所述第一电连接线路远离所述第二电连接线路的一侧，并经过所述一对差分数据输入端子远离所述一对差分数据输出端子的一侧；
    所述第三组第三电连接线路经过所述第二电连接线路远离所述第一电连接线路的一侧，并经过所述一对差分数据输出端子远离所述一对差分数据输入端子的一侧。
  6. 根据权利要求5所述的存储卡，其特征在于，所述控制单元还具有接地引脚，所述接地引脚的数量为多个，多个所述接地引脚包括第一接地引脚、第二接地引脚和第三接地引脚，所述第一接地引脚、所述第二接地引脚和所述第三接地引脚均与所述参考地电连接；
    所述第一接地引脚设置于所述一对差分数据输入引脚与所述一对差分数据输出引脚之间，所述第一接地引脚与所述参考地之间的电连接线路位于所述第一电连接线路与所述第二电连接线路之间；
    所述第二接地引脚设置于所述一对差分数据输入引脚远离所述一对差分数据输出引脚的一侧，所述第二接地引脚与所述参考地之间的电连接线路位于所述第一电连接线路远离所述第二电连接线路的一侧；
    所述第三接地引脚设置于所述一对差分数据输出引脚远离所述一对差分数据输入引脚的一侧，所述第三接地引脚与所述参考地之间的电连接线路位于所述第二电连接线路远离所述第一电连接线路的一侧。
  7. 根据权利要求1～6中任一项所述的存储卡，其特征在于，所述接地端子在所述存储卡卡体上的设置位置与GND在所述NM卡的卡体上的设置位置相对应。
  8. 根据权利要求1～7中任一项所述的存储卡，其特征在于，所述电源端子在所述存储卡卡体上的设置位置与VCC在所述NM卡的卡体上的设置位置相对应。
  9. 根据权利要求1～7中任一项所述的存储卡，其特征在于，所述第一差分数据输入端子、所述第二差分数据输入端子、所述第一差分数据输出端子、所述第二差分数 据输出端子、所述电源端子、所述接地端子和所述时钟端子在所述存储卡卡体上的设置位置分别与DAT1、COM、GND、DAT2、VCC、DAT0、CLK在所述NM卡的卡体上的设置位置相对应；所述存储卡卡体上与DAT3在所述NM卡的卡体上的设置位置相对应的位置未设置端子或者设有检测端子，所述检测端子与所述存储卡卡体之间未电连接。
  10. 一种通过卡座识别Nano SIM卡、NM卡和权利要求9所述的存储卡的方法，所述卡座包括卡座主体和卡座接口，所述卡座主体围成卡槽，所述卡槽用于容纳NM卡的卡体，所述卡座接口设置于所述卡槽的内壁上，所述卡座接口具有八个卡座端子，所述八个卡座端子分别用于与NM卡的DAT1、COM、GND、DAT3、DAT2、VCC、DAT0和CLK接触，所述八个卡座端子中用于与所述DAT3接触的卡座端子为第一卡座端子，其特征在于，所述方法包括：
    检测与所述第一卡座端子接触的端子；
    判断所述端子是接地端子或者信号端子，或者没有端子与所述第一卡座端子接触；
    当与所述第一卡座端子接触的端子为接地端子时，则识别所述卡座内插入的卡为Nano SIM卡；
    当与所述第一卡座端子接触的端子为信号端子时，则识别所述卡座内插入的卡为NM卡；
    当没有端子与所述第一卡座端子接触时，则识别所述卡座内插入的卡为所述的存储卡。
  11. 一种电子设备，用于执行权利要求10所述方法，其特征在于，包括：
    卡座，包括卡座主体和卡座接口，所述卡座主体围成卡槽，所述卡座接口设置于所述卡槽的内壁上，所述卡座接口具有八个卡座端子，所述八个卡座端子分别用于与NM卡的DAT1、COM、GND、DAT3、DAT2、VCC、DAT0和CLK接触，所述八个卡座端子中用于与所述DAT3接触的卡座端子为第一卡座端子；
    电路板，包括Nano SIM卡控制器、存储卡控制器、NM卡控制器、开关、检测电路和控制电路，所述开关具有第一端、第二端、第三端和第四端，所述第一端与所述卡座接口电连接，所述第二端与所述Nano SIM卡控制器电连接，所述第三端与所述存储卡控制器电连接，所述第四端与所述NM卡控制器电连接，所述检测电路用于检测与所述第一卡座端子接触的端子，所述控制电路用于根据所述检测电路的检测结果，识别安装于所述卡槽内的卡为Nano SIM卡、存储卡或者NM卡，并根据识别结果，控制所述开关的第一端连接所述开关的第二端，或者控制所述开关的第一端连接所述开关的第三端，或者控制所述开关的第一端连接所述开关的第四端。
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