WO2021190287A1 - 静电保护电路及全芯片静电保护电路 - Google Patents

静电保护电路及全芯片静电保护电路 Download PDF

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WO2021190287A1
WO2021190287A1 PCT/CN2021/079552 CN2021079552W WO2021190287A1 WO 2021190287 A1 WO2021190287 A1 WO 2021190287A1 CN 2021079552 W CN2021079552 W CN 2021079552W WO 2021190287 A1 WO2021190287 A1 WO 2021190287A1
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Prior art keywords
terminal
inverter
voltage
electrostatic protection
protection circuit
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PCT/CN2021/079552
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English (en)
French (fr)
Inventor
许杞安
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长鑫存储技术有限公司
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Priority to EP21773278.3A priority Critical patent/EP3934042B1/en
Priority to US17/431,123 priority patent/US20220285928A1/en
Publication of WO2021190287A1 publication Critical patent/WO2021190287A1/zh

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
    • H02H9/045—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere
    • H02H9/046—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere responsive to excess voltage appearing at terminals of integrated circuits
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H1/00—Details of emergency protective circuit arrangements
    • H02H1/0007—Details of emergency protective circuit arrangements concerning the detecting means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H01L27/0285—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements bias arrangements for gate electrode of field effect transistors, e.g. RC networks, voltage partitioning circuits
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
    • H02H3/20—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to excess voltage
    • H02H3/22—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to excess voltage of short duration, e.g. lightning
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/02—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess current
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/02—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess current
    • H02H9/025—Current limitation using field effect transistors

Definitions

  • This application relates to the field of integrated circuit technology, in particular to an electrostatic protection circuit and a full-chip electrostatic protection circuit.
  • Electrostatic protection has become more and more important. According to statistics, more than 30% of the failures of semiconductor products are caused by electrostatic damage. In order to better protect the integrated circuit from electrostatic damage, it is necessary to set up an electrostatic protection circuit to protect the integrated circuit.
  • the RC time constant of the existing electrostatic protection circuit is usually 0.1 ⁇ s to 1 ⁇ s.
  • the existing electrostatic protection circuit requires a larger RC time constant in order to achieve a better electrostatic protection effect, so that the area of the electrostatic protection circuit is larger. , It will occupy a larger design space.
  • an electrostatic protection circuit including:
  • a detection module the first terminal of the detection module is connected to a first voltage, and the second terminal of the detection module is connected to a second voltage; the detection module is used to detect the type of the first voltage and pass the detection result through all The third terminal output of the detection module;
  • a bleeder module a first end of the bleeder module is connected to the first voltage, and a second end of the bleeder module is connected to the second voltage;
  • a control module a first terminal of the control module is connected to the first voltage, a second terminal of the control module is connected to the second voltage, a third terminal of the control module and a third terminal of the detection module
  • the fourth end of the control module is connected to the third end of the discharge module; the control module is used to control the discharge module to be turned on or off based on the detection result of the detection module.
  • the above-mentioned electrostatic protection circuit has a small RC time constant under the premise of achieving the required electrostatic protection effect, and the area of the electrostatic protection circuit is small and does not occupy much design space.
  • a full-chip electrostatic protection circuit including:
  • a core circuit a first terminal of the core circuit is connected to the first voltage, and a second terminal of the core circuit is connected to the second voltage;
  • a first diode, the anode of the first diode is connected to the signal input terminal of the core circuit, and the cathode of the first diode is connected to the first voltage;
  • a second diode the anode of the second diode is connected to the second voltage, and the cathode of the second diode is connected to the signal input terminal of the core circuit;
  • a third diode, the anode of the third diode is connected to the signal output terminal of the core circuit, and the cathode of the third diode is connected to the first voltage;
  • a fourth diode, an anode of the fourth diode is connected to the second voltage, and a cathode of the fourth diode is connected to the signal output terminal of the core circuit.
  • the above-mentioned full-chip electrostatic protection circuit can realize the electrostatic protection of four pressure modes by combining the diode and the electrostatic protection circuit, which effectively improves the electrostatic protection capability of the product; it better ensures that the electrostatic protection device does not work during the startup and normal operation of the power supply. Conduction; without affecting the normal function of the existing core circuit, the normal operation of the circuit is ensured.
  • FIG. 1 is a circuit diagram of an electrostatic protection circuit provided in an embodiment
  • Figure 2a is a circuit diagram of an electrostatic protection circuit provided in another embodiment
  • 2b is a circuit diagram of an electrostatic protection circuit provided in another embodiment
  • FIG. 3 is a circuit diagram of a full-chip electrostatic protection circuit provided in an embodiment
  • FIG. 4 is a circuit diagram of a full-chip electrostatic protection circuit provided in another embodiment.
  • an electrostatic protection circuit of the present application includes: a detection module 10, a first end of the detection module 10 is connected to a first voltage VDD, and a second end of the detection module 10 is connected to a second voltage VSS; the detection module 10 is used to detect the type of the first voltage VDD, and the detection result is output through the third terminal of the detection module 10 (ie, terminal A in FIG.
  • the discharge module 11, the first terminal of the discharge module 11 Connect the first voltage VDD, the second terminal of the bleeder module 11 is connected to the second voltage VSS; the control module 12, the first terminal of the control module 12 is connected to the first voltage VDD, and the second terminal of the control module 12 is connected to the second voltage VSS,
  • the third end of the control module 12 is connected to the third end of the detection module 10; the fourth end of the control module 12 (that is, the C end in FIG. 1) is connected to the third end of the bleeder module 11; the control module 12 is used for Based on the detection result of the detection module 10, the discharge module 11 is controlled to be turned on or off.
  • the above-mentioned electrostatic protection circuit has a small RC time constant under the premise of achieving the required electrostatic protection effect, and the area of the electrostatic protection circuit is small and does not occupy much design space.
  • the detection module 10 includes: a capacitor C1, the first terminal of the capacitor C1 is used as the first terminal of the detection module 10 to be connected to the first voltage VDD, and the second terminal of the capacitor C1 is used as the third terminal of the detection module 10; R1, the first end of the resistor R1 is connected to the second end of the capacitor C1, and the second end of the resistor R1 is used as the second end of the detection module 10.
  • the capacitor C1 may include but is not limited to a metal-dielectric layer-metal capacitor or a MOS capacitor;
  • the resistor R1 may include but is not limited to a polysilicon resistor or a doped region resistor.
  • the bleeder module 11 may include a bleeder transistor MESD, and the bleeder transistor MESD may be an NMOS tube.
  • the drain of the bleeder transistor MESD serves as the first terminal of the bleeder module 11 to connect to the first voltage VDD
  • the source of the bleeder transistor MESD serves as the second terminal of the bleeder module 11 to connect to the second voltage VSS
  • the gate of the bleeder transistor MESD The pole serves as the third end of the bleeder module 11 and is connected to the fourth end of the control module 12.
  • control module 12 includes a positive feedback loop, and the positive feedback loop includes an inverter and a PMOS transistor.
  • the control module 12 includes: a first inverter 121, the first terminal of the first inverter 121 serves as the third terminal of the control module 12, and the first terminal of the first inverter 121 is connected to the detection module 10
  • the second terminal of the first inverter 121 is connected to the second voltage VSS; the second inverter 122, the first terminal of the second inverter 122 is connected to the fourth terminal of the first inverter 121
  • the second terminal of the second inverter 122 is connected to the second voltage VSS, the third terminal of the second inverter 122 is connected to the first voltage VDD;
  • the source of the first PMOS transistor MP1 is connected to the first voltage VDD; the drain of the first PMOS transistor MP1 is connected to the third terminal of the first inverter 121;
  • the first PMOS transistor MP1 and the second inverter 122 form a positive feedback
  • the first inverter 121 includes a second PMOS tube MP2 and a second NMOS tube MN2; the gate of the second PMOS tube MP2 and the gate of the second NMOS tube MN2 are connected together to serve as the first control module 12
  • the source of the second PMOS tube MP2 is connected to the drain of the first PMOS tube MP1
  • the drain of the second PMOS tube MP2 is connected with the drain of the second NMOS tube MN2 to jointly serve as the first inverter 121
  • the source of the second NMOS transistor MN2 serves as the second end of the first inverter 121.
  • the second inverter 122 includes a third PMOS tube MP3 and a third NMOS tube MN3; the gate of the third PMOS tube MP3 and the gate of the third NMOS tube MN3 are connected together to form a second inverter. 122, the source of the third PMOS tube MP3 serves as the third terminal of the second inverter 122, and the source of the third PMOS tube MP3 and the source of the first PMOS tube MP1 together serve as the first terminal of the control module 12.
  • One end is connected to the first voltage VDD, the drain of the third PMOS transistor MP3 and the drain of the third NMOS transistor MN3 are connected together as the fourth end of the second inverter 122, and the source of the third NMOS transistor MN3 is used as the first The second terminal of the two inverters 122.
  • the electrostatic protection circuit further includes a pull-down resistor R2, the first end of the pull-down resistor R2 is connected to the fourth end of the second inverter 122 as the fourth end of the control module 12, and the second end of the pull-down resistor R2 is connected
  • the second voltage VSS, the second end of the pull-down resistor R2, the second end of the first inverter 121 and the second end of the second inverter 122 together constitute the second end of the control module 12.
  • the resistance R2 may include, but is not limited to, a polysilicon resistance or a doped region resistance.
  • the working principle of the electrostatic protection circuit shown in FIG. 1 is: when static electricity occurs, the third end of the detection module 10 (that is, end A in FIG. 1) is coupled to a high level through a capacitor C1, and the second NMOS transistor MN2 conducts After passing through the second NMOS transistor MN2, the fourth terminal of the first inverter 121 (ie, terminal B in FIG. 1) is low, the third PMOS transistor MP3 is turned on, and the fourth terminal ( That is, the voltage at terminal C in FIG. 1 rises, and the bleeder transistor MESD starts to conduct and bleed the electrostatic current; the rise of the voltage at the fourth terminal of the control module 12 will cause the conduction of the first PMOS tube to become weaker, which in turn makes the first PMOS transistor weaker.
  • the voltage at the fourth terminal of the inverter 121 further reduces and further increases the gate voltage of the discharge transistor MESD.
  • Such a positive feedback method can accelerate the speed of electrostatic discharge.
  • the feedback through the first PMOS tube MP1 and the third NMOS tube MN3 can ensure that the fourth terminal of the first inverter 121 is still low Level, so as to ensure that the fourth terminal of the control module 12 remains at a high level, so that the electrostatic discharge time becomes longer, so as to ensure the conduction speed and electrostatic discharge capacity of the discharge transistor MESD, thereby making the RC of the electrostatic protection circuit
  • the time constant can be reduced, and the reduction of the RC time constant can make the size of the electrostatic protection circuit smaller, so that the design space occupied by the electrostatic protection circuit becomes smaller.
  • the positive feedback loop includes an inverter, a PMOS transistor, and an NMOS transistor.
  • the electrostatic protection circuit in this example further includes a first NMOS tube MN1 on the basis of the electrostatic protection circuit of FIG. The gate is connected to the fourth terminal of the second inverter 122.
  • the gate of the first NMOS transistor MN1 is connected to the drain of the third PMOS transistor MP3 and the drain of the third NMOS transistor MN3,
  • the drain of the first NMOS transistor MN1 is connected to the fourth terminal of the first inverter 121
  • the source of the first NMOS transistor MN1 is connected to the second voltage VSS
  • the source of the first NMOS transistor MN1 is connected to the second NMOS transistor MN2.
  • the source of MN3 and the source of the third NMOS transistor MN3 jointly serve as the second end of the control module 12.
  • the first PMOS transistor MP1, the first NMOS transistor MN1 and the second inverter 122 form a positive feedback loop.
  • the working principle of the electrostatic protection circuit shown in FIG. 2a is: when static electricity occurs, the third terminal of the detection module 10 (that is, the terminal A in FIG. 2a) is coupled to a high level through the capacitor C1, and the second NMOS tube MN2 Turned on, after passing through the second NMOS transistor MN2, the fourth terminal of the first inverter 121 (ie, terminal B in FIG.
  • the third PMOS transistor MP3 is turned on, and the fourth terminal of the control module 12 (I.e., terminal C in Figure 2a) is at a high level, the bleeder transistor MESD conducts and discharges the electrostatic current; the increase in the voltage at the fourth terminal of the control module 12 will cause the conduction of the first PMOS tube to become weaker, and at the same time make the first PMOS transistor weaker.
  • An NMOS transistor MN1 is turned on, which can further accelerate the pull-down of the potential of the fourth terminal of the first inverter 121, so that the voltage of the fourth terminal of the first inverter 121 decreases more quickly and further improves the bleeder transistor MESD.
  • Grid voltage such a positive feedback method can accelerate the speed of electrostatic discharge.
  • the second NMOS tube MN2 is turned off and the second PMOS tube MP2 is turned on, but because the fourth terminal of the control module 12 is still high Level, the first PMOS tube MP1 is turned off, the first NMOS tube MN1 is turned on, and the first NMOS tube MN1 is turned on to pull the level of the fourth terminal of the first inverter 121 low, so that the first inverter 121 The level of the fourth terminal of the first inverter 121 is further reduced.
  • the feedback through the first PMOS tube MP1, the third NMOS tube MN3, and the first NMOS tube MN1 can ensure that the fourth terminal of the first inverter 121 is still at a low level, thereby It is ensured that the fourth terminal of the control module 12 is maintained at a high level, so that the electrostatic discharge time becomes longer than that of the electrostatic protection circuit shown in FIG. 1. Further, by setting an appropriate size for MN3, for example, increasing the channel width of the first NMOS transistor MN1, the fourth terminal of the first inverter 121 can always maintain a low level during the electrostatic discharge process until the electrostatic charge is discharged.
  • the conduction speed and electrostatic discharge capacity of the discharge transistor MESD are ensured, so that the RC time constant of the electrostatic protection circuit can be reduced, and the reduction of the RC time constant can make the size of the electrostatic protection circuit smaller, thereby making The design space occupied by the electrostatic protection circuit becomes smaller.
  • the positive feedback loop includes an inverter and an NMOS tube; specifically, as shown in Figure 2b, the electrostatic protection circuit in this example can also be compared to Figure 2a by removing the first PMOS tube.
  • MP1 other circuit structures in this example are the same as the corresponding structures in FIG. 2a, and will not be repeated here.
  • the first NMOS transistor MN1 and the second inverter 122 form a positive feedback loop.
  • the working principle of the electrostatic protection circuit shown in FIG. 2b is: when static electricity occurs, the third end of the detection module 10 (that is, end A in FIG. 2b) is coupled to a high level through the capacitor C1, and the second NMOS transistor MN2 Turned on, after passing through the second NMOS transistor MN2, the fourth terminal of the first inverter 121 (ie, terminal B in FIG.
  • the third PMOS transistor MP3 is turned on, and the fourth terminal of the control module 12 (I.e., the C terminal in Figure 2b) is high, the bleeder transistor MESD is turned on to discharge the electrostatic current; the increase in the voltage at the fourth terminal of the control module 12 will turn on the first NMOS transistor MN1, which can speed up the
  • the pull-down of the potential of the fourth terminal of an inverter 121 causes the voltage of the fourth terminal of the first inverter 121 to decrease more quickly and further increases the gate voltage of the discharge transistor MESD.
  • Such a positive feedback method can accelerate the electrostatic discharge. Speed.
  • the second NMOS tube MN2 is turned off and the second PMOS tube MP2 is turned on, but because the fourth terminal of the control module 12 is still high Level, the first NMOS transistor MN1 is turned on, and the first NMOS transistor MN1 is turned on to pull down the level of the fourth terminal of the first inverter 121, so that the level of the fourth terminal of the first inverter 121 is further reduced.
  • the feedback through the third NMOS tube MN3 and the first NMOS tube MN1 can ensure that the fourth terminal of the first inverter 121 is still at a low level, thereby ensuring that the fourth terminal of the control module 12 remains at a high level.
  • this application also provides a full-chip electrostatic protection circuit, including: the electrostatic protection circuit shown in FIG. 1; the core circuit 13, the first end of the core circuit 13 is connected to the first voltage VDD, the core circuit The second terminal is connected to the second voltage VSS; the core circuit 13 can be any existing circuit that needs electrostatic protection, and its specific structure will not be described again this time; the first diode Dp1, the first diode Dp1 The anode is connected to the signal input terminal of the core circuit 13 (ie, the Input terminal in FIG.
  • the cathode of the first diode Dp1 is connected to the first voltage VDD; the second diode DN1, the anode of the second diode DN1 Connected to the second voltage VSS, the cathode of the second diode DN1 is connected to the signal input end of the core circuit 13; the third diode Dp2, the anode of the third diode Dp2 and the signal output end of the core circuit 13 ( That is, the Output terminal in Figure 3) is connected, the cathode of the third diode Dp2 is connected to the first voltage VDD; the fourth diode DN2, the anode of the fourth diode DN2 is connected to the second voltage VSS, the fourth diode The negative pole of the tube DN2 is connected to the signal output terminal of the core circuit 13.
  • this application also provides a full-chip electrostatic protection circuit, including: the electrostatic protection circuit shown in FIG. 2a; the core circuit 13, the first end of the core circuit 13 is connected to the first voltage VDD, the core circuit 13 The second terminal is connected to the second voltage VSS; the core circuit 13 can be any existing circuit that needs electrostatic protection, and its specific structure will not be described again this time; the first diode Dp1, the first diode Dp1 The anode is connected to the signal input terminal of the core circuit 13 (ie, the Input terminal in FIG.
  • the cathode of the first diode Dp1 is connected to the first voltage VDD; the second diode DN1, the anode of the second diode DN1 Connected to the second voltage VSS, the cathode of the second diode DN1 is connected to the signal input end of the core circuit 13; the third diode Dp2, the anode of the third diode Dp2 and the signal output end of the core circuit 13 ( That is, the Output terminal in Figure 3) is connected, the cathode of the third diode Dp2 is connected to the first voltage VDD; the fourth diode DN2, the anode of the fourth diode DN2 is connected to the second voltage VSS, the fourth diode The negative pole of the tube DN2 is connected to the signal output terminal of the core circuit 13.
  • this application also provides a full-chip electrostatic protection circuit.
  • the full-chip electrostatic protection circuit described in this embodiment is substantially the same as the full-chip electrostatic protection circuit shown in FIG. 4, and the difference between the two The only point is that the electrostatic protection circuit in the full-chip electrostatic protection circuit shown in FIG. 4 is the electrostatic protection circuit shown in FIG. 2a, and the electrostatic protection circuit in the full-chip protection circuit in this embodiment is shown in FIG. 2b. ESD protection circuit shown.
  • the full-chip electrostatic protection circuit shown in Figure 3 and Figure 4 has four pressure modes of electrostatic protection, the four pressure modes are PD mode (PD-mode), ND mode (ND-mode), NS mode (NS- mode) and PS mode (PS-mode); among them, in the PD mode, the full-chip electrostatic protection circuit discharges the electrostatic current through the first diode Dp1 or the third diode Dp2; in the ND mode, the full-chip electrostatic protection circuit passes through The second diode DN1, the fourth diode DN2 and the discharge transistor MESD discharge electrostatic current; in the NS mode, the full-chip electrostatic protection circuit discharges the electrostatic current through the second diode DN1 and the fourth diode DN2; In the PS mode, the full-chip electrostatic protection circuit discharges the electrostatic current through the first diode Dp1 or the third diode Dp2 and the discharge transistor MESD.
  • PD mode PD mode
  • ND-mode ND mode
  • NS- mode NS

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Abstract

本申请涉及一种静电保护电路及全芯片静电保护电路，其中静电保护电路包括检测模块、泄放模块和控制模块。检测模块用于检测第一电压的类型，并输出检测结果，控制模块用于基于检测模块的检测结果控制泄放模块导通或关闭。

Description

静电保护电路及全芯片静电保护电路
相关申请的交叉引用
本申请要求于2020年3月26日提交中国专利局、申请号为202010224007.7、发明名称为“静电保护电路及全芯片静电保护电路”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及集成电路技术领域，特别是涉及一种静电保护电路及全芯片静电保护电路。
背景技术
现在半导体的制程越来越先进，半导体器件越来越小，结深(junction depth)越来越浅，氧化层越来越薄，半导体集成电路的可靠性面临的挑战越来越大，尤其是静电保护变得愈发重要。据统计，大约超过30％的半导体产品的失效是有静电损伤引起的。为了更好的保护集成电路不受静电损伤，需要设置静电保护电路对集成电路进行保护。
现有的静电保护电路的RC时间常数通常为0.1μs～1μs，然而，现有的静电保护电路为了达到较好的静电保护效果需要较大的RC时间常数，从而使得静电保护电路的面积较大，会占用较大的设计空间。
发明内容
在本申请的第一方面，提供了一种静电保护电路，包括：
检测模块，所述检测模块的第一端连接第一电压，所述检测模块的第二端连接第二电压；所述检测模块用于检测所述第一电压的类型，并将检测结果经由所述检测模块第三端输出；
泄放模块，所述泄放模块的第一端连接所述第一电压，所述泄放模块的第二端连接所述第二电压；
控制模块，所述控制模块的第一端连接所述第一电压，所述控制模块的第二端连接所述第二电压，所述控制模块的第三端与所述检测模块的第三端相连接；所述控制模块的第四端与所述泄放模块的第三端相连接；所述控制模块用于基于所述检测模块的检测结果控制所述泄放模块导通或关闭。
上述静电保护电路在达到所需的静电保护效果的前提下具有较小的RC时间常数，静电保护电路的面积较小，不会占用较多的设计空间。
在本申请的第二方面，还提供了一种全芯片静电保护电路，包括：
根据本申请的第一方面的静电保护电路；
核心电路，所述核心电路的第一端连接所述第一电压，所述核心电路的第二端连接所述第二电压；
第一二极管，所述第一二极管的正极与所述核心电路的信号输入端相连接，所述第一二极管的负极连接所述第一电压；
第二二极管，所述第二二极管的正极连接所述第二电压，所述第二二极管的负极与所述核心电路的信号输入端相连接；
第三二极管，所述第三二极管的正极与所述核心电路的信号输出端相连接，所述第三二极管的负极连接所述第一电压；
第四二极管，所述第四二极管的正极连接所述第二电压，所述第四二极管的负极与所述核心电路的信号输出端相连接。
上述全芯片静电保护电路通过将二极管与静电保护电路结合起来可以实现四种压力模式的静电保护，有效地提高了产品的静电保护能力；更好的保证了电源启动和正常工作时静电保护器件不导通；在不影响现有核心电路的正常功能，保证了电路的正常工作。
附图说明
为了更好地描述和说明本申请的实施例，可参考一幅或多幅附图，但用于描述附图的附加细节或示例不应当被认为是对本申请的发明创造、目前所描述的实施例或优选方式中任何一者的范围的限制。
图1为一实施例中提供的静电保护电路的电路图；
图2a为另一实施例中提供的静电保护电路的电路图；
图2b为另一实施例中提供的静电保护电路的电路图；
图3为一实施例中提供的全芯片静电保护电路的电路图；
图4为另一实施例中提供的全芯片静电保护电路的电路图。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的首选实施例。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本申请的公开内容更加透彻全面。
需要说明的是，当一个元件被认为是“连接”另一个元件，它可以是直接连接到另一个元件并与之结合为一体，或者可能同时存在居中元件。本文所使用的术语“安装”、“一端”、“另一端”以及类似的表述只是为了说明的目的。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
在一个实施例中，如图1所示，本申请一种静电保护电路，包括：检测模块10，检测模块10的第一端连接第一电压VDD，检测模块10的第二端连接第二电压VSS；检测模块10用于检测第一电压VDD的类型，并将检测结果经由检测模块10第三端(即图1中的A端)输出；泄放模块11，泄放模块11的第一端连接第一电压VDD，泄放模块11的第二端连接第二电压VSS；控制模块12，控制模块12的第一端连接第一电压VDD，控制模块12的第二端连接第二电压VSS，控制模块12的第三端与检测模块10的第三端相连接；控制模块12的第四端(即图1中的C端)与泄放模块11的第三端相连接；控制模块12用于基于检测模块10的检测结果控制泄放模块11导通或关闭。
上述静电保护电路在达到所需的静电保护效果的前提下具有较小的RC时 间常数，静电保护电路的面积较小，不会占用较多的设计空间。
在一个示例中，所检测模块10包括：电容C1，电容C1的第一端作为检测模块10的第一端连接第一电压VDD，电容C1的第二端作为检测模块10的第三端；电阻R1，电阻R1的第一端连接电容C1的第二端，电阻R1的第二端作为检测模块10的第二端。
具体的，电容C1可以包括但不仅限于金属-介电层-金属电容或MOS电容；电阻R1可以包括但不仅限于多晶硅电阻或掺杂区电阻。
在一个示例中，泄放模块11可以包括泄放晶体管MESD，泄放晶体管MESD可以为NMOS管。泄放晶体管MESD的漏极作为泄放模块11的第一端连接第一电压VDD，泄放晶体管MESD的源极作为泄放模块11的第二端连接第二电压VSS，泄放晶体管MESD的栅极作为泄放模块11的第三端与控制模块12的第四端相连接。
在一个示例中，控制模块12包括正反馈回路，正反馈回路包括一个反相器及一个PMOS管。
在一个示例中，控制模块12包括：第一反相器121，第一反相器121的第一端作为控制模块12的第三端，第一反相器121的第一端与检测模块10的第三端相连接，第一反相器121的第二端连接第二电压VSS；第二反相器122，第二反相器122的第一端与第一反相器121的第四端相连接，第二反相器122的第二端连接第二电压VSS，第二反相器122的第三端连接第一电压VDD；第一PMOS管MP1，第一PMOS管MP1的栅极与第二反相器122的第四端相连接；第一PMOS管MP1的源极连接第一电压VDD；第一PMOS管MP1的漏极与第一反相器121的第三端相连接；其中，第一PMOS管MP1与第二反相器122构成正反馈回路。
在一个示例中，第一反相器121包括第二PMOS管MP2及第二NMOS管MN2；第二PMOS管MP2的栅极与第二NMOS管MN2的栅极相连接共同作为控制模块12的第三端，第二PMOS管MP2的源极与第一PMOS管MP1的漏极相连接，第二PMOS管MP2的漏极与第二NMOS管MN2的漏极相连接共同作为第一反相器121的第四端(即图1中的B端)；第二NMOS管MN2的源极作为第一反相器121的第二端。
在一个示例中，第二反相器122包括第三PMOS管MP3及第三NMOS管MN3；第三PMOS管MP3的栅极与第三NMOS管MN3的栅极相连接共同作第二反相器122的第一端，第三PMOS管MP3的源极作为第二反相器122的第三端，第三PMOS管MP3的源极与第一PMOS管MP1的源极共同作为控制模块12的第一端连接第一电压VDD，第三PMOS管MP3的漏极与第三NMOS管MN3的漏极相连接共同作为第二反相器122的第四端，第三NMOS管MN3的源极作为第二反相器122的第二端。
在一个示例中，静电保护电路还包括下拉电阻R2，下拉电阻R2的第一端与第二反相器122的第四端相连作为控制模块12的第四端，下拉电阻R2的第二端连接第二电压VSS，下拉电阻R2的第二端与第一反相器121的第二端及第二反相器122的第二端共同构成控制模块12的第二端。
具体的，电阻R2可以包括但不仅限于多晶硅电阻或掺杂区电阻。
图1所示的静电保护电路的工作原理为：在静电发生时，检测模块10的第三端(即图1中的A端)通过电容C1被耦合为高电平，第二NMOS管MN2导通，经过第二NMOS管MN2之后，第一反相器121的第四端(即图1中的B端)为低电平，第三PMOS管MP3导通，控制模块12的第四端(即图1中的C端)电压升高，泄放晶体管MESD开始导通泄放静电电流；控制模块12第四端电压的升高会导致第一PMOS管的导通变弱，进而使得第一反相器121的第四端电压进一步降低并进一步提高泄放晶体管MESD的栅极电压，这样的正反馈方式可以加速静电泄放的速度。经过一定时间后，当检测模块10的第三端被电阻R1放电电压变低时，第二NMOS管MN2关掉，第二PMOS管MP2导通，但由于控制模块12的第四端仍为高电平，第一PMOS管MP1关掉，第三NMOS管MN3导通，因此，经过第一PMOS管MP1及第三NMOS管MN3的反馈能够保证第一反相器121的第四端仍为低电平，从而确保控制模块12的第四端保持为高电平，使得静电泄放的时间变长，从而保证泄放晶体管MESD的导通速度及静电泄放能力，从而使得静电保护电路的RC时间常数可以变小，而RC时间常数变小又可以使得静电保护电路的尺寸变小，从而使得静电保护电路占用的设计空间变小。
在另一个示例中，正反馈回路包括一个反相器、一个PMOS管及一个NMOS管。具体的，如图2a所示，相较于图1的静电保护电路，本示例中的静电保护 电路在图1的静电保护电路的基础上还包括第一NMOS管MN1，第一NMOS管MN1的栅极与第二反相器122的第四端相连接，具体的，第一NMOS管MN1的栅极与第三PMOS管MP3的漏极以及所述第三NMOS管MN3的漏极相连接，第一NMOS管MN1的漏极与第一反相器121的第四端相连接，第一NMOS管MN1的源极连接第二电压VSS，第一NMOS管MN1的源极与第二NMOS管MN2的源极及第三NMOS管MN3的源极共同作为控制模块12的第二端。其中，第一PMOS管MP1、第一NMOS管MN1与第二反相器122构成正反馈回路。
图2a中所示的静电保护电路的工作原理为：在静电发生时，检测模块10的第三端(即图2a中的A端)通过电容C1被耦合为高电平，第二NMOS管MN2导通，经过第二NMOS管MN2之后，第一反相器121的第四端(即图2a中的B端)为低电平，第三PMOS管MP3导通，控制模块12的第四端(即图2a中的C端)为高电平，泄放晶体管MESD导通泄放静电电流；控制模块12第四端电压的升高会导致第一PMOS管的导通变弱，同时使得第一NMOS管MN1导通，这样可以进一步加快对第一反相器121的第四端电位的下拉，使得第一反相器121的第四端电压更快地降低并进一步提高泄放晶体管MESD的栅极电压，这样的正反馈方式可以加速静电泄放的速度。经过一定时间后，当检测模块10的第三端被电阻R1放电电压变低时，第二NMOS管MN2关掉，第二PMOS管MP2导通，但由于控制模块12的第四端仍为高电平，第一PMOS管MP1关掉，第一NMOS管MN1导通，第一NMOS管MN1导通可以将第一反相器121的第四端的电平拉低，使得第一反相器121的第四端的电平进一步降低，因此，经过第一PMOS管MP1、第三NMOS管MN3及第一NMOS管MN1的反馈能够保证第一反相器121的第四端仍为低电平，从而确保控制模块12的第四端保持为高电平，使得静电泄放的时间相对于图1所示静电保护电路变长。进一步，通过对MN3设置合适的尺寸，例如增加第一NMOS管MN1的沟道宽度，可以使得第一反向器121的第四端在静电泄放过程中始终维持低电平，直到静电荷泄放完毕，从而保证泄放晶体管MESD的导通速度及静电泄放能力，使得静电保护电路的RC时间常数可以变小，而RC时间常数变小又可以使得静电保护电路的尺寸变小，从而使得静电保护电路占用的设计空间变小。
当然，在其他示例中，正反馈回路包括一个反相器及一个NMOS管；具体的，如图2b所示，本示例中的静电保护电路也可以相较于图2a为去除了第一PMOS管MP1，该示例中的其他电路结构均与图2a中对应的结构相同，此处不 再累述。该示例中，第一NMOS管MN1与第二反相器122构成正反馈回路。
图2b中所示的静电保护电路的工作原理为：在静电发生时，检测模块10的第三端(即图2b中的A端)通过电容C1被耦合为高电平，第二NMOS管MN2导通，经过第二NMOS管MN2之后，第一反相器121的第四端(即图2b中的B端)为低电平，第三PMOS管MP3导通，控制模块12的第四端(即图2b中的C端)为高电平，泄放晶体管MESD导通泄放静电电流；控制模块12第四端电压的升高会使得第一NMOS管MN1导通，这样可以加快对第一反相器121的第四端电位的下拉，使得第一反相器121的第四端电压更快地降低并进一步提高泄放晶体管MESD的栅极电压，这样的正反馈方式可以加速静电泄放的速度。经过一定时间后，当检测模块10的第三端被电阻R1放电电压变低时，第二NMOS管MN2关掉，第二PMOS管MP2导通，但由于控制模块12的第四端仍为高电平，第一NMOS管MN1导通，第一NMOS管MN1导通可以将第一反相器121的第四端的电平拉低，使得第一反相器121的第四端的电平进一步降低，因此，经过第三NMOS管MN3及第一NMOS管MN1的反馈能够保证第一反相器121的第四端仍为低电平，从而确保控制模块12的第四端保持为高电平，从而保证泄放晶体管MESD的导通速度及静电泄放能力，从而使得静电保护电路的RC时间常数可以变小，而RC时间常数变小又可以使得静电保护电路的尺寸变小，从而使得静电保护电路占用的设计空间变小。
请参阅图3，本申请还提供一种全芯片静电保护电路，包括：如图1所示的静电保护电路；核心电路13，核心电路13的第一端连接第一电压VDD，核心电路13的第二端连接第二电压VSS；核心电路13可以为现有任意一种需要进行静电保护的电路，其具体结构此次不再累述；第一二极管Dp1，第一二极管Dp1的正极与核心电路13的信号输入端(即图3中的Input端)相连接，第一二极管Dp1的负极连接第一电压VDD；第二二极管DN1，第二二极管DN1的正极连接述第二电压VSS，第二二极管DN1的负极与核心电路13的信号输入端相连接；第三二极管Dp2，第三二极管Dp2的正极与核心电路13的信号输出端(即图3中的Output端)相连接，第三二极管Dp2的负极连接第一电压VDD；第四二极管DN2，第四二极管DN2的正极连接第二电压VSS，第四二极管DN2的负极与核心电路13的信号输出端相连接。
请参阅图4，本申请还提供一种全芯片静电保护电路，包括：如图2a所示 的静电保护电路；核心电路13，核心电路13的第一端连接第一电压VDD，核心电路13的第二端连接第二电压VSS；核心电路13可以为现有任意一种需要进行静电保护的电路，其具体结构此次不再累述；第一二极管Dp1，第一二极管Dp1的正极与核心电路13的信号输入端(即图3中的Input端)相连接，第一二极管Dp1的负极连接第一电压VDD；第二二极管DN1，第二二极管DN1的正极连接述第二电压VSS，第二二极管DN1的负极与核心电路13的信号输入端相连接；第三二极管Dp2，第三二极管Dp2的正极与核心电路13的信号输出端(即图3中的Output端)相连接，第三二极管Dp2的负极连接第一电压VDD；第四二极管DN2，第四二极管DN2的正极连接第二电压VSS，第四二极管DN2的负极与核心电路13的信号输出端相连接。
当然，在其他实施例中，本申请还提供一种全芯片静电保护电路，本实施中所述的全芯片静电保护电路与图4中所示的全芯片静电保护电路大致相同，二者的区别仅在于：图4中所示的全芯片静电保护电路中的静电保护电路为图2a中所示的静电保护电路，而本实施例中的全芯片保护电路中的静电保护电路为图2b中所示的静电保护电路。
如图3及图4所示的全芯片静电保护电路具有四种压力模式的静电保护，四种压力模式分别为PD模式(PD-mode)、ND模式(ND-mode)、NS模式(NS-mode)及PS模式(PS-mode)；其中，在PD模式下全芯片静电保护电路经由第一二极管Dp1或第三二极管Dp2泄放静电电流；ND模式下全芯片静电保护电路经由第二二极管DN1、第四二极管DN2及泄放晶体管MESD泄放静电电流；NS模式下全芯片静电保护电路经由第二二极管DN1及第四二极管DN2泄放静电电流；PS模式下全芯片静电保护电路经由第一二极管Dp1或第三二极管Dp2及泄放晶体管MESD泄放静电电流。
上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权 利要求为准。

Claims (12)

  1. 一种静电保护电路，包括：
    检测模块，所述检测模块的第一端连接第一电压，所述检测模块的第二端连接第二电压；所述检测模块用于检测所述第一电压的类型，并将检测结果经由所述检测模块第三端输出；
    泄放模块，所述泄放模块的第一端连接所述第一电压，所述泄放模块的第二端连接所述第二电压；
    控制模块，所述控制模块的第一端连接所述第一电压，所述控制模块的第二端连接所述第二电压，所述控制模块的第三端与所述检测模块的第三端相连接；所述控制模块的第四端与所述泄放模块的第三端相连接；所述控制模块用于基于所述检测模块的检测结果控制所述泄放模块导通或关闭。
  2. 根据权利要求1所述的静电保护电路，其中，所述检测模块包括：
    电容，所述电容的第一端作为所述检测模块的第一端，所述电容的第二端作为所述检测模块的第三端；
    电阻，所述电阻的第一端连接所述电容的第二端，所述电阻的第二端作为所述检测模块的第二端。
  3. 根据权利要求1所述的静电保护电路，其中，所述电容包括金属-介电层-金属电容或MOS电容，所述电阻包括多晶硅电阻或掺杂区电阻。
  4. 根据权利要求1所述的静电保护电路，其中，所述泄放模块包括泄放晶体管。
  5. 根据权利要求4所述的静电保护电路，其中，所述泄放晶体管包括NMOS管，所述泄放晶体管的漏极作为所述泄放模块的第一端，所述泄放晶体管的源极作为所述泄放模块的第二端，所述泄放晶体管的栅极作为所述泄放模块的第三端。
  6. 根据权利要求1所述的静电保护电路，其中，所述控制模块包括正反馈回路，所述正反馈回路包括一个反相器及一个NMOS管，或所述正反馈回路包括一个反相器及一个PMOS管，或所述正反馈回路包括一个反相器、一个PMOS管及一个NMOS管。
  7. 根据权利要求6所述的静电保护电路，其中，所述控制模块包括：
    第一反相器，所述第一反相器的第一端作为所述控制模块的第三端，所述第一反相器的第二端连接所述第二电压；
    第二反相器，所述第二反相器的第一端与所述第一反相器的第四端相连接，所述第二反相器的第二端连接所述第二电压，所述第二反相器的第三端连接所述第一电压；
    第一PMOS管，所述第一PMOS管的栅极与所述第二反相器的第四端相连接；所述第一PMOS管的源极连接第一电压，所述第一PMOS管的源极与所述第二反相器的第三端共同作为所述控制模块的第一端；所述第一PMOS管漏极与所述第一反相器的第三端相连接；其中，
    所述第一PMOS管与所述第二反相器构成所述正反馈回路。
  8. 根据权利要求6所述的静电保护电路，其中，所述控制模块包括：
    第一反相器，所述第一反相器的第一端作为所述控制模块的第三端，所述第一反相器的第二端连接所述第二电压；
    第二反相器，所述第二反相器的第一端与所述第一反相器的第四端相连接，所述第二反相器的第二端连接所述第二电压，所述第二反相器的第三端连接所述第一电压；
    所述第一NMOS管的栅极与所述第二反相器的第四端相连接，所述第一NMOS管的漏极与所述第一反相器的第四端相连接，所述第一NMOS管的源极连接所述第二电压；其中，
    所述第一NMOS管与所述第二反相器构成所述正反馈回路。
  9. 根据权利要求6所述的静电保护电路，其中，所述控制模块包括：
    第一反相器，所述第一反相器的第一端作为所述控制模块的第三端，所述第一反相器的第二端连接所述第二电压；
    第二反相器，所述第二反相器的第一端与所述第一反相器的第四端相连接，所述第二反相器的第二端连接所述第二电压，所述第二反相器的第三端连接所述第一电压；
    第一PMOS管，所述第一PMOS管的栅极与所述第二反相器的第四端相连接；所述第一PMOS管的源极连接第一电压，所述第一PMOS管的源极与所述 第二反相器的第三端共同作为所述控制模块的第一端；所述第一PMOS管漏极与所述第一反相器的第三端相连接；
    所述第一NMOS管的栅极与所述第二反相器的第四端相连接，所述第一NMOS管的漏极与所述第一反相器的第四端相连接，所述第一NMOS管的源极连接所述第二电压；其中，
    所述第一PMOS管、所述第一NMOS管与所述第二反相器构成所述正反馈回路。
  10. 根据权利要求7至9中任一项所述的静电保护电路，其中，
    所述第一反相器包括第二PMOS管及第二NMOS管；所述第二PMOS管的栅极与所述第二NMOS管的栅极相连接共同作为所述控制模块的第三端，所述第二PMOS管的源极与所述第一PMOS管的漏极相连接，所述第二PMOS管的漏极与所述第二NMOS管的漏极相连接共同作为所述第一反相器的第四端；所述第二NMOS管的源极作为所述第一反相器的第二端；
    所述第二反相器包括第三PMOS管及第三NMOS管；所述第三PMOS管的栅极与所述第三NMOS管的栅极相连接共同作为所述第二反相器的第一端，所述第三PMOS管的源极作为所述第二反相器的第三端，所述第三PMOS管的源极与所述第一PMOS管的源极共同作为所述控制模块的第一端，所述第三PMOS管的漏极与所述第三NMOS管的漏极相连接共同作为所述第二反相器的第四端，所述第三NMOS管的源极作为所述第二反相器的第二端。
  11. 根据权利要求10所述的静电保护电路，其中，所述静电保护电路还包括下拉电阻，所述下拉电阻的第一端与所述第二反相器的第四端作为所述控制模块的第四端，所述下拉电阻的第二端连接第二电压，所述下拉电阻的第二端与所述第一反相器的第二端及所述第二反相器的第二端共同构成所述控制模块的第二端。
  12. 一种全芯片静电保护电路，包括：
    如权利要求1至11中任一项所述的静电保护电路；
    核心电路，所述核心电路的第一端连接所述第一电压，所述核心电路的第二端连接所述第二电压；
    第一二极管，所述第一二极管的正极与所述核心电路的信号输入端相连接， 所述第一二极管的负极连接所述第一电压；
    第二二极管，所述第二二极管的正极连接所述第二电压，所述第二二极管的负极与所述核心电路的信号输入端相连接；
    第三二极管，所述第三二极管的正极与所述核心电路的信号输出端相连接，所述第三二极管的负极连接所述第一电压；
    第四二极管，所述第四二极管的正极连接所述第二电压，所述第四二极管的负极与所述核心电路的信号输出端相连接。
PCT/CN2021/079552 2020-03-26 2021-03-08 静电保护电路及全芯片静电保护电路 WO2021190287A1 (zh)

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CN113452004B (zh) 2022-09-27
EP3934042B1 (en) 2023-05-24

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