WO2021189776A1 - 一种掩模板、显示面板以及电子设备 - Google Patents

一种掩模板、显示面板以及电子设备 Download PDF

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Publication number
WO2021189776A1
WO2021189776A1 PCT/CN2020/113573 CN2020113573W WO2021189776A1 WO 2021189776 A1 WO2021189776 A1 WO 2021189776A1 CN 2020113573 W CN2020113573 W CN 2020113573W WO 2021189776 A1 WO2021189776 A1 WO 2021189776A1
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WIPO (PCT)
Prior art keywords
pull
transistor
module
node
area
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2020/113573
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English (en)
French (fr)
Inventor
唐延宗
肖军城
赵斌
张鑫
赵军
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Application filed by Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority to US16/972,595 priority Critical patent/US11709424B2/en
Publication of WO2021189776A1 publication Critical patent/WO2021189776A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509—Filters, e.g. light shielding masks
    • G02F1/133514—Colour filters
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/0005—Production of optical devices or components in so far as characterised by the lithographic processes or materials used therefor
    • G03F7/0007—Filters, e.g. additive colour filters; Components for display devices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/1303—Apparatus specially adapted to the manufacture of LCDs
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509—Filters, e.g. light shielding masks
    • G02F1/133512—Light shielding layers, e.g. black matrix
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509—Filters, e.g. light shielding masks
    • G02F1/133514—Colour filters
    • G02F1/133516—Methods for their manufacture, e.g. printing, electro-deposition or photolithography
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/26—Phase shift masks [PSM]; PSM blanks; Preparation thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes

Definitions

  • This application relates to the field of display technology, and in particular to a mask, a display panel and an electronic device.
  • the resolution of electronic devices such as display screens, TVs, and mobile phones is getting higher and higher.
  • the increase in the resolution corresponds to the increase in the number of pixels.
  • the increase in the number of pixels will bring about various problems that need to be overcome. technical challenge.
  • the area of a single sub-pixel of an electronic device with 8K resolution is one-fourth of the area of a single sub-pixel of an electronic device with 4K resolution, which is accompanied by the difficulty in preparing the corresponding mask and the increase in cost.
  • the prior art is preparing 65-inch 8K resolution display panels and 85 When a display panel with a resolution of 8K is required, different sizes of masks are required, and the development cost is high.
  • the size of the mask refers to the size of the light-shielding area on the mask.
  • the existing 8K electronic equipment has at least the technical problem of preparing masks of different sizes for display panels of different sizes, and needs to be improved.
  • the present application provides a mask, a display panel, and an electronic device to solve the technical problem that at least the existing 8K electronic device needs to prepare masks of different sizes for display panels of different sizes.
  • the present application provides a mask for preparing a color filter substrate, which includes:
  • An opening pattern pattern is formed on the mask substrate
  • the mask includes a plurality of repeating areas, the repeating area includes a first area corresponding to the opening pattern and a second area surrounding the first area; the second area includes a row-direction arrangement and The first side area and the second side area are parallel, and the third side area and the fourth side area are arranged and parallel in the column direction; the first side area is far from the side of the opening pattern to The first distance of the opening pattern pattern is smaller than the second distance from the side of the second side area away from the opening pattern pattern to the opening pattern pattern.
  • the third distance from the side of the third side area away from the opening pattern to the opening pattern pattern is equal to the distance of the fourth side area away from the opening pattern pattern.
  • the value of the first distance is less than 12 microns, and the value of the second distance is greater than 32 microns.
  • the value of the first distance is less than 10 micrometers, and the value of the second distance is greater than 34 micrometers.
  • the width value of the opening pattern pattern is 28 micrometers.
  • the sum of the first distance and the second distance is 44 microns.
  • the present application also provides a display panel, which includes a color filter substrate and an array substrate that are arranged oppositely, and the color filter substrate includes:
  • the color filter substrate includes a plurality of pixel regions arranged in an array and corresponding to sub-pixels, and the pixel region includes a first region corresponding to the opening and a second region surrounding the first region, so The second region is formed with the black matrix; the second region includes a first side region and a second side region arranged in a row direction and parallel, and a third side region and a fourth side region arranged in a column direction and parallel Side area; the fifth distance from the side of the first side area away from the opening to the opening, which is smaller than the sixth distance from the side of the second side area away from the opening to the opening .
  • the value of the fifth distance is less than 18 micrometers, and the value of the sixth distance is greater than 18 micrometers.
  • the width value of the opening is 16 micrometers, and the sum of the fifth distance and the sixth distance is 56 micrometers.
  • the present application also provides an electronic device, including the display panel described in any one of the above.
  • the contact area between the drain of the clock input transistor of the pull-up module in the m1th GOA unit and the active layer is smaller than the clock input of the pull-up module in the m2th GOA unit The contact area between the drain of the transistor and the active layer.
  • the present application also provides an electronic device, including a display panel, the display panel including a color filter substrate and an array substrate that are arranged oppositely, and the color filter substrate includes:
  • the color filter substrate includes a plurality of pixel regions arranged in an array and corresponding to sub-pixels, and the pixel region includes a first region corresponding to the opening and a second region surrounding the first region, so The second region is formed with the black matrix; the second region includes a first side region and a second side region arranged in a row direction and parallel, and a third side region and a fourth side region arranged in a column direction and parallel Side area; the fifth distance from the side of the first side area away from the opening to the opening, which is smaller than the sixth distance from the side of the second side area away from the opening to the opening .
  • the display panel includes:
  • the GOA unit includes a pull-up module, and the pull-up module includes a clock input transistor connected to a clock signal;
  • N clock signal lines extending in the column direction and arranged in parallel;
  • clock signal connecting lines extending in the row direction and arranged in parallel, the clock signal connecting lines correspond to the GOA unit one-to-one, and are used to connect the clock input transistor of the pull-up module in the GOA unit to the corresponding clock signal String;
  • the n clock signal lines include an n1-th clock signal line and an n2-th clock signal line
  • the n2-th clock signal line is formed on the side of the n1-th clock signal line away from the GOA unit ,
  • the voltage drop value of the clock input transistor of the pull-up module in the m1th GOA unit connected to the n1th clock signal line is greater than the voltage drop of the pull-up module in the m2th GOA unit connected to the n2th clock signal line
  • the voltage drop value of the clock input transistor is greater than the voltage drop value of the clock input transistor.
  • the size of the clock input transistor of the pull-up module in the m1th GOA unit is larger than the size of the clock input transistor of the pull-up module in the m2th GOA unit.
  • the clock input transistor includes a plurality of sub-transistors connected in an array, and the number of sub-transistors of the clock input transistor of the pull-up module in the m1th GOA unit is greater than that of the m2th GOA unit The number of sub-transistors within the clock input transistor of the pull-up module.
  • the source area of the clock input transistor of the pull-up module in the m1th GOA unit is larger than the source area of the clock input transistor of the pull-up module in the m2th GOA unit; And/or, the drain area of the clock input transistor of the pull-up module in the m1th GOA unit is larger than the drain area of the clock input transistor of the pull-up module in the m2th GOA unit.
  • the contact area between the source of the clock input transistor of the pull-up module in the m1th GOA unit and the active layer is smaller than the clock input of the pull-up module in the m2th GOA unit The contact area between the source of the transistor and the active layer.
  • the n-th level GOA unit includes:
  • a pull-up control module connected to the first node, and used to pull up the potential of the first node during the display time period;
  • the logical addressing module includes a second node, the logical addressing module is connected to the first node, and is configured to raise the potential of the second node twice during the display time period, and in the blank time period , Pulling up the potential of the first node through the second node;
  • a pull-up module connected to the first node, for pulling up the potentials of the n-th stage transmission signal, the first output signal, and the second output signal;
  • a first pull-down module connected to the first node, and used to pull down the potential of the first node during the blank time period
  • the second pull-down module is connected to the first node and the third node, and is used to pull down the potentials of the first node and the third node respectively during the display time period;
  • a third pull-down module connected to the third node and the second pull-down module, and is used to pull down the potential of the third node during a blank time period;
  • a first pull-down maintenance module including the third node, the first pull-down maintenance module is connected to the first node and the first pull-down module, and is configured to maintain a low potential of the first node;
  • the second pull-down maintaining module is connected to the third node and the pull-up module, and is used to maintain the low level of the n-th stage transmission signal, the first output signal, and the second output signal.
  • the pull-up control module includes a first transistor and a second transistor, and the gate and the first electrode of the first transistor and the gate of the second transistor are both connected to the n-th transistor. Two-level signal transmission, the second electrode of the first transistor is connected to the first electrode and the fourth node of the second transistor, and the second electrode of the second transistor is connected to the first node.
  • the source and drain layer material resistivity of the clock input transistor of the pull-up module in the m1th GOA unit is greater than the source of the clock input transistor of the pull-up module in the m2th GOA unit Material resistivity of drain layer.
  • the source and drain layer thickness of the clock input transistor of the pull-up module in the m1th GOA unit is smaller than the source and drain of the clock input transistor of the pull-up module in the m2th GOA unit Polar layer thickness.
  • the contact area between the drain of the clock input transistor of the pull-up module in the m1th GOA unit and the active layer is smaller than the clock input of the pull-up module in the m2th GOA unit The contact area between the drain of the transistor and the active layer.
  • the present application provides a mask, a display panel, and an electronic device.
  • the mask includes a mask substrate and an opening pattern pattern formed on the mask substrate; wherein the mask includes a plurality of repeating regions, and the repeat
  • the area includes a first area corresponding to the opening pattern and a second area surrounding the first area; the second area includes a first side area and a second side area that are arranged in a row direction and are parallel, and The third side area and the fourth side area are arranged in a column direction and are parallel; the first side area is far from the side of the opening pattern pattern to the first distance from the opening pattern pattern, which is smaller than the second The side area is away from the side of the opening pattern pattern to a second distance from the opening pattern pattern.
  • the mask abandons the existing mask opening pattern, such as the design of the shading area in the center of the repeated area (used to form the pixel area), and moves it to the side, so that the black matrix opening of the target size can be obtained based on the diffraction effect Or color film layer without changing the size of the opening pattern.
  • display panels with the same resolution and different sizes can use the same size mask.
  • the difference between these masks is only the distance between the opening pattern and the edge of the repeated area. Different, it solves the technical problem that at least the existing 8K electronic equipment needs to prepare different size mask plates for different size display panels, and reduces the production cost of the product.
  • FIG. 1 is a schematic diagram of the effect of the mask in the prior art.
  • Fig. 2a is a top view of a repeated area of a mask provided by an embodiment of the application.
  • Fig. 2b is a cross-sectional view of a repeated area of a mask provided by an embodiment of the application.
  • FIG. 3a is a schematic structural diagram of a display panel provided by an embodiment of the application.
  • FIG. 3b is a top view of a pixel area of a color filter substrate provided by an embodiment of the application.
  • 3c is a cross-sectional view of a pixel area of a color filter substrate provided by an embodiment of the application.
  • 4a to 4o are schematic diagrams of preparing the display panel provided by the embodiment of the application.
  • FIG. 5 is a schematic diagram of another structure of a display panel provided by an embodiment of the application.
  • FIG. 6 is a schematic circuit diagram of a display panel provided by an embodiment of the application.
  • FIG. 7 is a schematic circuit diagram of a GOA circuit provided by an embodiment of the application.
  • FIGS 8a to 8c are sequence diagrams of embodiments of the application.
  • FIG. 9 is a schematic diagram of the design of the target pattern provided by the embodiment of the application.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with “first” and “second” may explicitly or implicitly include one or more of the features. In the description of the present application, “multiple” means two or more than two, unless otherwise specifically defined.
  • connection should be understood in a broad sense, unless otherwise clearly specified and limited.
  • it can be a fixed connection or a detachable connection.
  • Connected or integrally connected it can be mechanically connected, or electrically connected or can communicate with each other; it can be directly connected or indirectly connected through an intermediate medium, it can be the internal communication of two components or the interaction of two components relation.
  • an intermediate medium it can be the internal communication of two components or the interaction of two components relation.
  • the "above” or “below” of the first feature of the second feature may include direct contact between the first and second features, or may include the first and second features Not in direct contact but through other features between them.
  • the "above”, “above” and “above” of the first feature on the second feature include the first feature directly above and obliquely above the second feature, or it simply means that the first feature is higher in level than the second feature.
  • the “below”, “below” and “below” of the second feature of the first feature include the first feature directly below and obliquely below the second feature, or it simply means that the level of the first feature is smaller than the second feature.
  • the sub-pixels of each pixel of the liquid crystal display panel are arranged in rows.
  • the arrangement direction of the sub-pixels is the row direction, and the way perpendicular to the row direction is the column direction.
  • the row width value refers to a certain area in the row direction. The size of the width value.
  • the repetitive area refers to an area on the mask.
  • the mask is composed of repetitive areas that are arranged and distributed.
  • the pixel area refers to the area corresponding to a smallest light-emitting unit (ie, sub-pixel) in the display panel.
  • the pixel area Including the light-emitting area and the light-shielding area surrounding the light-emitting area; in the process of preparing the display panel, the alignment of the mask and the substrate is to align the repeated area of the mask with the pixel area of the substrate.
  • Figure 1 is a schematic diagram of the effect of the existing mask.
  • the light-shielding area of the mask is set in the middle of the pixel area.
  • the row width of a single sub-pixel in a 65-inch 8K resolution display panel is 52 microns.
  • the row width value of the pixel area of the mask 1 corresponding to the 65-inch 8K resolution display panel is also 52 microns, and the row width value of a single sub-pixel in the 85-inch 8K resolution display panel is 72 microns, and the 85-inch 8K resolution
  • the row width value of the pixel area of the mask plate 2 corresponding to the display panel is also 72 microns.
  • the single light-transmitting area of the mask plate 1 is 12 microns, and the line width value of the single light-transmitting area of the mask 2 is 22 microns.
  • the light-transmitting area forms a slit, and light is diffracted through the slit. According to the principle of light diffraction, The smaller the slit, the larger the diffraction range of light.
  • the black matrix is a negative photoresist, and the area not irradiated with light is etched to form an opening.
  • the line width of the actual effective shielding area of the mask 1 is 16 microns (that is, the diffraction range of a single slit is 6 microns), and the resulting 65-inch 8K resolution display panel has a single sub-pixel
  • the line width of the light exit area is 16 microns
  • the actual effective shielding area of the mask 2 has a line width of 18 microns (that is, the diffraction range of a single slit is 5 microns), forming a single sub-pixel of an 85-inch 8K resolution display panel
  • the line width of the light-emitting area is 18 microns, which is also in line with the principle of light diffraction.
  • the existing 8K electronic equipment has at least the technical problem of preparing masks of different sizes for display panels of different sizes, and needs to be improved. Then, the present application provides a mask, a display panel, and an electronic device, which can solve the technical problem that at least the existing 8K electronic device needs to prepare masks of different sizes for display panels of different sizes.
  • the mask provided by this application includes:
  • the opening pattern 12 is formed on the mask substrate 11 and is used to form a black matrix or a color filter layer of the color filter substrate, and the black matrix includes an opening for filling the color filter layer;
  • the mask includes a plurality of repeating areas Z, and the repeating area Z includes a first area Z1 corresponding to the opening pattern 12 and a second area Z2 surrounding the first area Z1;
  • the zone Z2 includes a first side region C1 and a second side region C2 arranged in a row direction and parallel, and a third side region C3 and a fourth side region C4 arranged and parallel in a column direction;
  • the first distance h1 from the side of the area C1 away from the opening pattern 12 to the opening pattern 12 is smaller than the second side area C2 from the side away from the opening pattern 12 to the opening pattern pattern pattern
  • the second distance of 12 is h2.
  • This embodiment provides a mask, which includes a mask substrate, an opening pattern pattern, formed on the mask substrate, and used to form a black matrix or a color film layer of the color filter substrate, and the black matrix It includes an opening for filling the color filter layer; wherein the mask includes a plurality of repeating areas, and the repeating area includes a first area corresponding to the opening pattern and a second area surrounding the first area; The second region includes a first side region and a second side region that are arranged in a row direction and are parallel, and a third side region and a fourth side region that are arranged and parallel in a column direction; the first side region The first distance from the side of the opening pattern to the opening pattern is smaller than the second distance from the side of the second side area away from the opening pattern to the opening pattern.
  • the mask abandons the existing mask opening pattern, such as the design of the shading area in the center of the repeated area, and moves it to the side, so that the black matrix opening or color film layer of the target size can be obtained based on the diffraction effect, and it is not It is necessary to change the size of the opening pattern.
  • display panels with the same resolution and different sizes can use the same size mask. The difference between these masks is that the distance between the opening pattern and the Z edge of the repeated area is different, which solves the existing problem.
  • the 8K electronic device has at least the technical problem of preparing masks of different sizes for display panels of different sizes, which reduces the cost of product manufacturing.
  • the third distance h3 from the side of the third side area C3 away from the side of the opening pattern 12 to the opening pattern 12 is equal to that the fourth side area C4 is far away from the The fourth distance h4 from the side of the opening pattern 12 to the opening pattern 12.
  • the value of the first distance h1 is less than 12 microns, and the value of the second distance h2 is greater than 32. Micrometers.
  • the value of the first distance h1 is less than 10 microns, and the value of the second distance h2 is greater than 34. Micrometers.
  • the width of the opening pattern 12 is 28 microns.
  • the sum of the first distance h1 and the second distance h2 is 44 microns.
  • the opening pattern 12 is formed by patterning a material with a light transmittance of 0, and the material includes metallic chromium and the like.
  • a straight line with a light transmittance of 0 is formed between adjacent repeating regions Z to ensure the slit effect.
  • the width of the straight line is less than 1 micron, which will not affect the pattern of the black matrix below the region. .
  • the display panel provided by the embodiment of the present application includes: an array substrate 21 and a color filter substrate 22 arranged oppositely, and the color filter substrate 22 includes:
  • the color filter substrate 22 includes a plurality of pixel regions W arranged in an array and corresponding to sub-pixels, and the pixel regions W include first regions W1 and corresponding to the openings. And a second area W2 surrounding the first area W1, the second area W2 is formed with the black matrix 222; the second area W2 includes a first side area D1 and a second side area D1 that are arranged in a row direction and are parallel.
  • the color filter substrate of the display panel includes a base substrate, and a black matrix is formed on the base substrate.
  • the black matrix includes an opening for filling the color film layer and is formed in all The color filter layer in the opening; wherein the color filter substrate includes a plurality of pixel regions arranged in an array and corresponding to sub-pixels, and the pixel region includes a first region corresponding to the opening and surrounding the first region A second area of an area, the second area is formed with the black matrix; the second area includes a first side area and a second side area arranged in a row direction and parallel, and a column direction arranged and parallel The third side area and the fourth side area; the fifth distance from the side of the first side area away from the opening to the opening is smaller than the side of the second side area away from the opening The sixth distance to the opening.
  • display panels of the same resolution and different sizes can use the same size mask.
  • the difference between these masks is only the distance between the opening pattern and the edge of the pixel area, which solves the problem of the existing 8K electronic equipment.
  • the technical problem of preparing mask plates of different sizes for display panels of different sizes reduces the production cost of products.
  • the value of the fifth distance L1 is less than 18 microns, and the value of the sixth distance L2 is greater than 18 microns.
  • the width of the opening is 16 microns, and the sum of the fifth distance L1 and the sixth distance L2 is 56 microns.
  • Step 1 Provide a base substrate.
  • a transparent glass substrate or the like is provided as the base substrate 41.
  • Step 2 A black matrix material layer is formed on the base substrate.
  • a black matrix material layer 42 is formed on a base substrate 41 such as a transparent glass substrate.
  • the material of the black matrix material layer is a negative photoresist, and the area shielded by the mask is removed.
  • Step 3 Align the first mask plate and the base substrate.
  • a first mask Y1 is used, and each repeated area Z corresponding to the pixel area W of the first mask Y1 adopts the design of the embodiment shown in Figs. 2a and 2b. Align the first mask Y1 with the base substrate obtained in step 2.
  • Step 4 The black matrix material is patterned to form a black matrix.
  • photolithography processing is performed on the black matrix material layer 42 to obtain the black matrix 43.
  • Step 5 Coating the red color resist material layer.
  • a red photoresist layer 44 is coated on the entire surface.
  • the material of the red photoresist layer is a positive photoresist, and the area shielded by the mask is reserved.
  • Step 6 Align the second mask plate and the base substrate.
  • a second mask Y2 is used, and the second mask Y2 only adopts the design of the embodiment shown in FIGS. 2a and 2b in the repetitive area Z corresponding to the pixel area W corresponding to the red sub-pixel.
  • the second mask Y2 is aligned with the base substrate obtained in step 5.
  • Step 7 The red photoresist layer is patterned.
  • Step 8 Coating a layer of green color resist material.
  • a green photoresist layer 46 is coated on the entire surface.
  • the material of the green photoresist layer is a positive photoresist, and the area shielded by the mask is reserved.
  • Step 9 Align the third mask plate and the base substrate.
  • a third mask plate Y3 is used, and the third mask plate Y3 only adopts the design of the embodiment shown in FIGS. 2a and 2b in the repeated area Z corresponding to the pixel area W corresponding to the green sub-pixel. Align the third mask Y3 with the base substrate obtained in step 8.
  • Step 10 The green photoresist layer is patterned.
  • Step 11 Coating a layer of blue color resist material.
  • a blue photoresist layer 48 is coated on the entire surface.
  • the material of the blue photoresist layer is a positive photoresist, and the area shielded by the mask is reserved.
  • Step 12 align the fourth mask plate and the base substrate.
  • a fourth mask Y4 is used, and the fourth mask Y4 only uses the design of the embodiment shown in FIG. 2a and FIG. 2b in the repeating area Z corresponding to the pixel area W corresponding to the blue sub-pixel.
  • the fourth mask plate Y4 is aligned with the base substrate obtained in step 11.
  • Step 13 The blue photoresist layer is patterned.
  • the blue photoresist layer 48 is subjected to photolithography processing based on the fourth mask using equipment such as an exposure machine to obtain the blue filter layer 49.
  • Step 14 Prepare the support column.
  • a support column 410 is prepared on the black matrix of the base substrate obtained in step 13.
  • Step 15 Prepare a planarization layer and a common electrode layer.
  • step 14 macromolecular organic particles are successively used to prepare a planarization layer 411, and a transparent conductive material such as TIO is used to prepare a common electrode layer 412 on the planarization layer 411.
  • the area of a single sub-pixel of an 8K resolution electronic device is one-fourth of the area of a single sub-pixel of a 4K resolution electronic device. This is accompanied by a reduction in the contact area between the support pillars (ps) in the panel and the bottom layer.
  • the contact area between the support column and the bottom layer is 20 micrometers * 20 micrometers or less. Such a small contact area will cause the support column to easily peel off from the bottom layer, and the peeling of the support column will cause the liquid crystal to appear blank. , The whole face pressure is abnormal and other problems;
  • the loading (voltage drop) of 8K ultra-high-resolution electronic equipment is heavier and the charging time is shorter. It uses GOA (Gate on Array, gate drive circuit integrated on the array substrate) drive and thick copper design, resulting in ultra-high-resolution electronics.
  • the device is extremely sensitive to the impedance difference between the CK (clock) signals in the GOA.
  • the resolution of 8K electronic equipment is 7680*4320, and there are 4320 rows of GOA units in total.
  • the GOA drive architecture of 12CK signal lines that is, 12 clock signal lines
  • the impedance difference of CK signal lines can reach the kiloohm level. As a result, there is a difference between the CK graphics and the scan line waveform output by the corresponding GOA unit, which in turn leads to problems such as water balance lines in the panel display.
  • the display panel provided by the embodiment of the present application includes:
  • the array substrate 51 is formed with a driving circuit layer, pixel electrodes, etc.;
  • the color filter substrate 52 is arranged opposite to the array substrate 51;
  • the plastic frame 53 is used to encapsulate the array substrate 51 and the color filter substrate 52, and form a sealed space therewith, and the sealed space is filled with liquid crystal;
  • the supporting column 54 is formed on the array substrate 51 or the color filter substrate, and is used to support the array substrate 51 and the color filter substrate 52.
  • the color filter substrate 52 adopts the structure provided by any of the above-mentioned embodiments, or is prepared by the mask provided by any of the embodiments.
  • the display panel in view of the technical problem of CK impedance difference, as shown in FIG. 6, in the non-display area where the plastic frame 53 is located, the display panel is formed with:
  • the GOA unit 601 includes a pull-up module, and the pull-up module includes a clock input transistor connected to a clock signal;
  • N clock signal lines 602 extending in the column direction and arranged in parallel;
  • clock signal connection lines 603 extending in the row direction and arranged in parallel, the clock signal connection lines 603 correspond to the GOA unit 601 one-to-one, and are used to connect the clock input transistors of the pull-up modules in the GOA unit 601 to Corresponding clock signal line 602;
  • the n clock signal lines include an n1-th clock signal line and an n2-th clock signal line
  • the n2-th clock signal line is formed on the side of the n1-th clock signal line away from the GOA unit
  • the voltage drop value of the clock input transistor of the pull-up module in the m1th GOA unit connected to the n1th clock signal line is greater than the voltage drop of the pull-up module in the m2th GOA unit connected to the n2th clock signal line
  • the voltage drop value of the clock input transistor is different from n1 and n2 and belongs to 1 to n
  • m1 is different from m2 and belongs to 1 to m.
  • the display panel includes 4320 GOA units 601, 12 clock signal lines 602 (CK1 to CK12 in Figure 6), and each clock signal line 602 is connected to 360 GOA units 601 . Then it can be foreseen that in the column direction and the row direction, the difference in voltage drop between the GOA unit 601 connected to CK12 and the GOA unit 601 connected to CK1 is the product of the sum of the resistance R1 and the resistance R2 and the current I, the difference between the resistance R1 and the resistance R2 And can reach the kiloohm level. Based on this current situation, this application abandons the voltage drop improvement of the clock signal line, and originally proposes to adjust the parameters of the clock input transistor (that is, the thin film transistor connected to the external clock signal) in the GOA unit to change its corresponding voltage. Down value.
  • the clock input transistor that is, the thin film transistor connected to the external clock signal
  • This embodiment provides a display panel that includes m GOA units arranged in a column direction, the GOA unit includes a pull-up module, the pull-up module includes a clock input transistor connected to a clock signal, and the column direction extends and N clock signal lines arranged in parallel, m clock signal connecting lines extending in the row direction and arranged in parallel, the clock signal connecting lines correspond to the GOA unit one-to-one, and are used to pull up the module in the GOA unit
  • the clock input transistor is connected to the corresponding clock signal line; wherein, the clock signal line includes an n1-th clock signal line and an n2-th clock signal line, and the n2-th clock signal line is formed on the n1-th clock signal Line away from the GOA unit, the voltage drop value of the clock input transistor of the pull-up module in the m1th GOA unit connected to the n1th clock signal line is greater than the voltage drop value of the clock input transistor connected to the n2th clock signal line The voltage drop value of the clock input transistor of the
  • the voltage drop value of the clock input transistors in different GOA units by adjusting the voltage drop value of the clock input transistors in different GOA units, the voltage drop value caused by the different lengths of the clock signal line and the clock signal connection line can be compensated, so that each GOA unit and the clock drive chip can be compensated.
  • the voltage drop between them is approximately the same, which alleviates the CK impedance difference of the 8K ultra-high resolution electronic equipment, and improves the technical problem of the 8K ultra-high resolution electronic equipment that causes the difference in the output signal of the GOA unit.
  • the display panel includes an active layer, a first metal layer, and a second metal layer.
  • the active layer is patterned to form the channel region of the transistor, and the first metal layer is patterned to form the gate and the gate.
  • Scan lines and clock signal lines, the second metal layer is patterned to form clock signal connection lines, the source and drain of the transistor, etc.
  • the CK signal is connected to the source of the clock input transistor in the GOA unit, and the CK signal passes through the clock signal.
  • the line (first metal layer) input is transmitted through the via hole to the clock signal connection line (the second metal layer) and hung to the source stage of the clock input transistor.
  • the parameters of the clock input transistor include multiple dimensions such as the size of the transistor, the resistivity of the film material, and the thickness of the film. For clock input transistors connected to different clock signal lines, only one parameter can be adjusted. It is also possible to adjust multiple parameters at the same time, so that the voltage drop between the GOA unit connected to all the clock signal lines and the clock driving chip is approximately the same.
  • the voltage drop values of clock input transistors belonging to different GOA units connected to the same clock signal line are the same.
  • the size parameters of the clock input transistors connected to different clock signal lines are different, that is, the size of the sub-transistor of the clock input transistor of the pull-up module in the m1th GOA unit is larger than that in the m2th GOA unit The size of the sub-transistor of the clock input transistor of the pull-up module.
  • the clock input transistor includes a plurality of sub-transistors connected in an array, and the number of sub-transistors of the clock input transistor of the pull-up module in the m1th GOA unit is greater than that of the first The number of sub-transistors of the clock input transistor of the pull-up module in m2 GOA units.
  • each transistor is realized by using the sub-transistors of the array in series. The more the number of sub-transistors in series, the greater the resistance value of the transistor.
  • This embodiment adjusts the sub-transistor data of the transistor based on this. During the preparation, it is only necessary to change the number of light-shielding regions of the mask plate corresponding to the clock input transistor sub-transistors in different GOA units to obtain this embodiment.
  • the source area of the clock input transistor of the pull-up module in the m1th GOA unit is larger than the source area of the clock input transistor of the pull-up module in the m2th GOA unit.
  • the active layer parameters, gate parameters, drain parameters (including material resistivity, area, thickness), and source parameters (including material resistivity, thickness) are the same, the larger the source area, the greater the resistance of the transistor The larger the value is, the voltage drop value of the transistor is adjusted based on this in this embodiment.
  • the preparation only the area of the light-shielding area of the mask corresponding to the source of the clock input transistor in different GOA units needs to be changed to obtain this embodiment.
  • the contact area between the source of the clock input transistor of the pull-up module in the m1th GOA unit and the active layer is smaller than that of the clock input transistor of the pull-up module in the m2th GOA unit The contact area between the source electrode and the active layer.
  • the active layer parameters, gate parameters, drain parameters (including material resistivity, area, thickness), and source parameters are the same, the contact between the source and the active layer The smaller the area, the larger the resistance value of the transistor.
  • This embodiment adjusts the voltage drop value of the transistor based on this. During the preparation, only the mask plate corresponding to the source connection via hole of the clock input transistor in the different GOA units needs to be changed. The area of the region can be obtained in this embodiment.
  • the drain area of the clock input transistor of the pull-up module in the m1th GOA unit is larger than the drain area of the clock input transistor of the pull-up module in the m2th GOA unit.
  • the active layer parameters, gate parameters, source parameters (including material resistivity, area, thickness), and drain parameters (including material resistivity, thickness) are the same, the larger the drain area, the resistance of the transistor The larger the value is, this embodiment adjusts the voltage drop value of the transistor based on this.
  • the preparation only the area of the light-shielding area of the mask plate corresponding to the drain of the clock input transistor in different GOA units needs to be changed to obtain this embodiment.
  • the contact area between the drain of the clock input transistor of the pull-up module in the m1th GOA unit and the active layer is smaller than that of the clock input transistor of the pull-up module in the m2th GOA unit The contact area between the drain and the active layer.
  • the active layer parameters, gate parameters, drain parameters (including material resistivity, area, thickness), and source parameters (including material resistivity, area, thickness) are the same, the contact between the drain and the active layer The smaller the area, the greater the resistance value of the transistor.
  • This embodiment adjusts the voltage drop value of the transistor based on this. During the preparation, only the mask plate corresponding to the drain connection via hole of the clock input transistor in the different GOA units needs to be changed. The area of the region can be obtained in this embodiment.
  • the source and drain layer material resistivity of the clock input transistor of the pull-up module in the m1th GOA unit is greater than the source and drain of the clock input transistor of the pull-up module in the m2th GOA unit Resistivity of the pole layer material.
  • the active layer parameters, gate parameters, drain parameters (including area and thickness), and source parameters (including area and thickness) are the same, the greater the resistivity of the source and drain layer materials, the greater the resistance of the transistor The larger the value is, this embodiment adjusts the voltage drop value of the transistor based on this.
  • the source and drain material provided in the present application includes a 4-layer structure, from bottom to top, they are metal titanium Ti, metal aluminum Al, metal copper Cu, and metal titanium Ti.
  • they are metal titanium Ti, metal aluminum Al, metal copper Cu, and metal titanium Ti.
  • changing the thickness of metallic aluminum Al and metallic copper Cu can change the resistivity of the source and drain layer materials. Since the resistivity of copper is less than that of aluminum, the metal layer is deposited When the source and drain layer of the clock input transistor of the pull-up module in the m1th GOA unit is deposited thicker aluminum layer, and the source and drain layer of the clock input transistor of the pull-up module in the m2th GOA unit is deposited thinner The aluminum layer can realize this embodiment.
  • the source and drain layer thickness of the clock input transistor of the pull-up module in the m1th GOA unit is smaller than the source and drain layer of the clock input transistor of the pull-up module in the m2th GOA unit thickness.
  • the active layer parameters, gate parameters, drain parameters (including material resistivity and area), and source parameters (including material resistivity and area) are the same, the smaller the thickness of the source and drain layer material, the transistor The greater the resistance value of, the voltage drop value of the transistor is adjusted in this embodiment based on this.
  • only source and drain materials of different thicknesses need to be deposited in different regions to obtain this embodiment.
  • the embodiment of the present application also provides a GOA circuit, and the GOA circuit provided in the embodiment of the present application includes m The cascaded GOA unit, as shown in FIG. 7, where the GOA unit includes a pull-up control module 701, a logical addressing module 702, a pull-up module 703, a first pull-down module 704, a second pull-down module 705, and a third pull-down module 706, a first pull-down maintenance module 707 and a second pull-down maintenance module 708.
  • the pull-up control module 701 is connected to the first node Q, and is used to pull up the potential of the first node Q during the display period.
  • the logical addressing module 702 includes a second node M.
  • the logical addressing module is connected to the first node and is used to raise the potential of the second node twice during the display time period. The potential of a node is pulled high.
  • the pull-up module 703 is connected to the first node Q, and is used to pull up the potentials of the n-th stage transmission signal Cout(n), the first output signal WR(n), and the second output signal RD(n).
  • the first pull-down module 704 is connected to the first node Q, and is used to pull down the potential of the first node Q during the blank period.
  • the second pull-down module 705 is connected to the first node Q and the third node QB, and is used to pull down the potentials of the first node Q and the third node QB respectively during the display time period.
  • the third pull-down module 706 is connected to the third node QB and the second pull-down module 705, and is used to pull down the potential of the third node QB during the blank period.
  • the first pull-down maintenance module 707 includes a third node QB, and the first pull-down maintenance module 707 is connected to the first node Q and the first pull-down module 704 for maintaining the low potential of the first node Q.
  • the second pull-down maintaining module 708 is connected to the third node QB and the pull-up module 703, and is used to maintain the n-th stage transmission signal Cout(n), the first output signal WR(n), and the second output signal RD(n). Low potential.
  • the display panel needs to pass through the display time period Promgraming and the blank time period Blank when displaying the picture.
  • the display time period is the actual display time period of each frame
  • the blank time period is the time period between the actual display times of adjacent frames.
  • the tenth transistor T23, the eleventh transistor T22, and the twelfth transistor T21 in the pull-up module 703 are all the above clock input transistors.
  • the clock driving chip needs to input 3 clock signals CKa, CKb and CKc for the same GOA unit.
  • each clock signal line is divided into 3 sub-clock signal lines, which are used to transmit CKa, CKb and CKc respectively.
  • Each clock signal connection line is further divided into three sub-clock signal connection lines, which respectively connect the clock signals CKa, CKb, and CKc to the corresponding clock input transistors.
  • the charging rate of the first node Q is guaranteed during the blank time period, thereby increasing the threshold voltage margin allowed by the GOA circuit and improving The stability of the GOA circuit is improved, and the development difficulty of the transistor manufacturing process is reduced.
  • the pull-up control module 701 includes a first transistor T11 and a second transistor T12.
  • the gate and the first electrode of the first transistor T11 and the gate of the second transistor T12 are both connected to the n-2th stage.
  • the second electrode of the first transistor T11 is connected to the first electrode of the second transistor T12, and the second electrode of the second transistor T12 is connected to the first node Q.
  • the logical addressing module 702 includes a third transistor T91, a fourth transistor T92, a fifth transistor T71, a sixth transistor T72, a seventh transistor T73, an eighth transistor T81, a ninth transistor T91, a first storage capacitor Cbt3, and a third transistor
  • the gate of T91 is connected to the n-2th level transmission signal Cout(n-2)
  • the first electrode of the third transistor T91 is connected to the first low-potential signal VGL1
  • the second electrode of the third transistor T91 is connected to the fourth transistor T92.
  • the first electrode, the gate and the second electrode of the fourth transistor T92 are all connected to the high potential signal VGH, the gate of the fifth transistor T71 is connected to the first input signal LSP, and the first electrode of the fifth transistor T71 is connected to the n-2th stage
  • the second electrode of the fifth transistor T71 is connected to the first electrode of the sixth transistor T72 and the first electrode of the seventh transistor T73, and the gate of the sixth transistor T72 is connected to the first input signal.
  • the second electrode of the sixth transistor T72 and the gate of the seventh transistor T73 are both connected to the second node M, the second electrode of the seventh transistor T73 is connected to the high potential signal VGH, and the gate of the eighth transistor T81 is connected to the second node M,
  • the first electrode of the eighth transistor T81 is connected to the high potential signal VGH, the second electrode of the eighth transistor T81 is connected to the first electrode of the ninth transistor T91, the gate of the ninth transistor T91 is connected to the reset signal Total-Reset, and the ninth transistor T91
  • the second electrode of Cbt3 is connected to the first node Q, the first plate of the first storage capacitor Cbt3 is connected to the second electrode of the third transistor T91, and the second plate is connected to the second node M.
  • the pull-up module 703 includes a tenth transistor T23, an eleventh transistor T22, a twelfth transistor T21, a thirteenth transistor T6, a second storage capacitor Cbt1, and a third storage capacitor Cbt2.
  • the gate of a transistor T22 and the gate of the twelfth transistor T21 are both connected to the first node Q, the first electrode of the tenth transistor T23 is connected to the first clock signal CKa, and the second electrode of the tenth transistor T23 is connected to the nth stage.
  • the first electrode of the eleventh transistor T22 is connected to the second clock signal CKb, the second electrode of the eleventh transistor T22 is connected to the first output signal WR(n), and the first electrode of the twelfth transistor T21 is connected to the first output signal WR(n).
  • the electrode is connected to the third clock signal CKc, the second electrode of the twelfth transistor T21 is connected to the second output signal RD(n), the gate of the thirteenth transistor T6 is connected to the first node Q, and the first electrode of the thirteenth transistor T6 Connected to the fourth node N, the second electrode of the thirteenth transistor T6 is connected to the first output signal WR(n), the first plate of the second storage capacitor Cbt1 is connected to the first node Q, and the second plate is connected to the first output signal WR(n), the first plate of the third storage capacitor Cbt2 is connected to the first node Q, and the second plate is connected to the second output signal RD(n).
  • the first pull-down module 704 includes a fourteenth transistor T33 and a fifteenth transistor T34.
  • the gate of the fourteenth transistor T33 and the gate of the fifteenth transistor T34 are both connected to the second input signal VST.
  • the first electrode is connected to the first node Q
  • the second electrode of the fourteenth transistor T33 is connected to the first electrode of the fifteenth transistor T34 and the fourth node N
  • the second electrode of the fifteenth transistor T34 is connected to the first low potential signal VGL1 .
  • the second pull-down module 705 includes a sixteenth transistor T31, a seventeenth transistor T32, and an eighteenth transistor T55.
  • the gate of the sixteenth transistor T31 and the gate of the seventeenth transistor T32 are connected to the n+2 stage signal Cout(n+2), the first electrode of the sixteenth transistor T31 is connected to the first node Q, the second electrode of the sixteenth transistor T31 is connected to the first electrode of the seventeenth transistor T32 and the fourth node N, the seventeenth
  • the second electrode of the transistor T32 is connected to the first low-potential signal VGL1, the gate of the eighteenth transistor T55 is connected to the n-2th level transmission signal Cout(n-2), and the first electrode of the eighteenth transistor T55 is connected to the first With two low-level signals VGL2, the first electrode of the eighteenth transistor T55 is connected to the third node QB.
  • the third pull-down module 706 includes a nineteenth transistor T102 and a twentieth transistor T101.
  • the gate of the nineteenth transistor T102 is connected to the second node, and the first electrode of the nineteenth transistor T102 is connected to the second low potential signal VGL2,
  • the second electrode of the nineteenth transistor T102 is connected to the first electrode of the twentieth transistor T101, the gate of the twentieth transistor T101 is connected to the reset signal Total-Reset, and the second electrode of the twentieth transistor T101 is connected to the third node QB.
  • the first pull-down sustaining module 707 includes a twenty-first transistor T44, a twenty-second transistor T45, a twenty-third transistor T51, a twenty-fourth transistor T52, a twenty-fifth transistor T53, and a twenty-sixth transistor T54,
  • the gate of the twenty-first transistor T44 and the gate of the twenty-second transistor T45 are connected to the third node QB, the first electrode of the twenty-first transistor T44 is connected to the first node Q, and the second electrode of the twenty-first transistor T44 is connected to the first node Q.
  • the electrode is connected to the first electrode of the twenty-second transistor T45 and the fourth node N
  • the second electrode of the twenty-second transistor T45 is connected to the first low-potential signal VGL1
  • the gate of the twenty-third transistor T51 is connected to the first electrode
  • the high potential signal VGH the second electrode of the twenty-third transistor T51 is connected to the first electrode of the twenty-fourth transistor T52
  • the gate of the twenty-fourth transistor T52 is connected to the first node Q
  • the second electrode of the twenty-fourth transistor T52 is connected to the first node Q.
  • the two electrodes are connected to the second low-potential signal VGL2, the gate of the twenty-fifth transistor T53 is connected to the second electrode of the twenty-third transistor T51, the first electrode of the twenty-fifth transistor T53 is connected to the high-potential signal VGH, and the twenty-fifth transistor T53 is connected to the high-potential signal VGH.
  • the second electrode of the five transistor T53 is connected to the first electrode of the twenty-sixth transistor T54 and the third node QB, the gate of the twenty-sixth transistor T54 is connected to the first node Q, and the second electrode of the twenty-sixth transistor T54 is connected The second low level signal VGL2.
  • the second pull-down sustain module 708 includes a twenty-seventh transistor T43, a twenty-eighth transistor T42, and a twenty-ninth transistor T41, the gate of the twenty-seventh transistor T43, the gate of the twenty-eighth transistor T42, and the second The gates of the nineteenth transistor T41 are all connected to the third node QB, the first electrode of the twenty-seventh transistor T43 is connected to the first low-potential signal VGL1, and the second electrode of the twenty-seventh transistor T43 is connected to the n-th stage transmission signal Cout.
  • the first electrode of the twenty-eighth transistor T42 is connected to the third low potential signal VGL3, the second electrode of the twenty-eighth transistor T42 is connected to the first output signal WR(n), and the second electrode of the twenty-ninth transistor T41 is connected to the first output signal WR(n).
  • One electrode is connected to the third low potential signal VGL3, and the second electrode of the twenty-ninth transistor T41 is connected to the second output signal RD(n).
  • the GOA circuit of the present application includes m cascaded GOA units, wherein the stage transmission signal output by the nth stage GOA unit is the nth stage transmission signal Cout(n), 2 ⁇ n ⁇ m, and n is an integer .
  • the n-2th level transmission signal Cout(n-2) is the level transmission signal before and one level apart from the nth level transmission signal Cout(n), and the n+2 level transmission signal Cout(n+2) It is the level transmission signal before and one level apart from the nth level transmission signal Cout(n).
  • the first input signal LSP, the second input signal VST, and the reset signal Total-Reset are all provided by an external timing device.
  • the GOA circuit provided in this embodiment is a real-time compensation circuit, which requires GOA to output a normal drive timing display screen in the display time period corresponding to each frame, and output a wide pulse timing in the blank time period between each frame for threshold voltage Vth For detection.
  • Fig. 8a shows the timing of each signal in the display period Promgraming and blank period Blank of the GOA circuit of the embodiment of the present application.
  • the display time period includes a first display stage S1, a second display stage S2, a third display stage S3, a fourth display stage S4, and a fifth display stage S5.
  • the n-2th level transmission signal Cout(n-2) rises to a high potential
  • the first transistor T11 and the second transistor T12 are turned on
  • the first node Q is pulled to a high potential
  • the second The fourteenth transistor T52, the twenty-sixth transistor T54, the tenth transistor T23, the eleventh transistor T22, and the twelfth transistor T21 are turned on. Since the first node Q and the third node QB are connected to form an inverter structure, The potentials between them are opposite. Therefore, the third node QB is at a low potential.
  • the twenty-seventh transistor T43, the twenty-eighth transistor T42, the twenty-ninth transistor T41, the twenty-first transistor T44, and the twenty-second transistor T45 are all turned off, at the same time, the n+2 level pass signal Cout(n+2) is at a low level, the sixteenth transistor T31 and the seventeenth transistor T32 are turned off, the second input signal VST is at a low level, and the fourteenth transistor T33 and the fifteenth transistor T34 are turned off.
  • the first timing signal CKa, the second timing signal CKb, and the third timing signal CKc are at a low level, and the n-th stage transmission signal Cout(n), the first output signal WR(n), and the second output signal RD(n) The output is low. Since the n-2th stage transmission signal Cout(n-2) is at a high level, the third transistor T91 is turned on, and the point P connected to the first plate of the first storage capacitor Cbt3 is reset to a low level, and the second plate is connected At the same time, the second node M is low.
  • the first input signal LSP rises to a high potential.
  • the n-2th stage transmission signal Cout(n-2) maintains a high potential
  • the second node M is raised to a high potential
  • the fourth transistor T92 When it is turned on, point P maintains a low level. Since signals such as the reset signal Totaol-Rest and the second input signal VST are at a low level, the first node Q maintains a high level, and the third node QB maintains a low level.
  • the first input signal LSP drops from a high level to a low level
  • the fifth transistor T71 and the sixth transistor T72 are turned off
  • the n-2th stage transfer signal Cout(n-2) changes from a high level to a low level.
  • Low potential so the third transistor T91 is turned off, and the potential at point P is switched from a low potential to a high potential.
  • the second node M is coupled to a higher potential.
  • the first timing signal Cka, the second timing signal CKb, and the third timing signal CKc change from a low level to a high level, so the n-th stage transmission signal Cout(n), the first output signal WR(n), and the second output signal
  • the potential of RD(n) is also raised to a high potential, and at the same time, due to the existence of the second storage capacitor Cbt1 and the third storage capacitor Cbt2, the first node Q is coupled to a higher potential.
  • the first timing signal Cka, the second timing signal CKb, and the third timing signal CKc are switched from a high level to a low level, and the n-th stage transmission signal Cout(n), the first output signal WR(n ) And the potential of the second output signal RD(n) is pulled to a low potential, and the signal coupling of the first node Q is reduced, which is consistent with the potential in the second display stage S2.
  • the n+2 level transmission signal Cout(n+2) rises from a low level to a high level
  • the sixteenth transistor T31 and the seventeenth transistor T32 are turned on, and the potential of the first node Q is pulled down
  • the twenty-fourth transistor T52, the twenty-sixth transistor T54, the tenth transistor T23, the eleventh transistor T22, and the twelfth transistor T21 are turned off, and the potential of the third node QB is raised to a high potential.
  • the seven transistors T43, the twenty-eighth transistor T42, the twenty-ninth transistor T41, the twenty-first transistor T44, and the twenty-second transistor T45 are all turned on, the first node Q, the n-th stage transmission signal Cout(n), The first output signal WR(n) and the second output signal RD(n) maintain a low level.
  • the blank period includes a first blank period B1, a second blank period B2, a third blank period B3, and a fourth blank period B4.
  • the reset signal Total reset rises to a high potential
  • the ninth transistor T82 is turned on, and the potential of the first node Q is pulled to a high potential.
  • the twenty-fourth transistor T52, the twenty-sixth transistor T54, and the tenth transistor T23, the eleventh transistor T22 and the twelfth transistor T21 are turned on. Since the first node Q and the third node QB are connected to form an inverter structure, the potential between them is opposite, so the third node QB is at a low level.
  • the twenty-seventh transistor T43, the twenty-eighth transistor T42, the twenty-ninth transistor T41, the twenty-first transistor T44, and the twenty-second transistor T45 are all turned off, and at the same time, the n+2 stage transmits the signal Cout (n+2) is at a low potential, the sixteenth transistor T31 and the seventeenth transistor T32 are turned off, the second input signal VST is at a low potential, and the fourteenth transistor T33 and the fifteenth transistor T34 are turned off.
  • the first timing signal CKa, the second timing signal CKb, and the third timing signal CKc are at a low level, and the n-th stage transmission signal Cout(n), the first output signal WR(n), and the second output signal RD(n) The output is low.
  • the reset signal Toatal reset drops to a low level
  • the ninth transistor T82 is turned off
  • the first timing signal Cka maintains a low level
  • the second timing signal CKb and the third timing signal CKc rise to a high level
  • the nth stage The level transmission signal Cout(n) maintains a low level
  • the first output signal WR(n) and the second output signal RD(n) output a high level.
  • the first node Q is coupled to a higher potential.
  • the second input signal VST rises from a low potential to a high potential
  • the fourteenth transistor T33 and the fifteenth transistor T34 are turned on, the potential of the first node Q is pulled down to a low potential
  • the twenty-fourth The transistor T52, the twenty-sixth transistor T54, the tenth transistor T23, the eleventh transistor T22, and the twelfth transistor T21 are turned off, and the potential of the third node QB is raised to a high potential.
  • the twenty-seventh transistor T43, the twenty-eighth transistor The transistor T42, the twenty-ninth transistor T41, the twenty-first transistor T44 and the twenty-second transistor T45 are all turned on, and the first node Q, the first output signal WR(n) and the second output signal RD(n) are pulled down To a low level, the n-th stage transmission signal Cout(n) maintains a low level.
  • the first input signal LSP rises to a high level
  • the fifth transistor T71 and the sixth transistor T72 are turned on, and because the n-2th stage transmission signal Cout(n-2) is at a low level, the second node M is reset to a low level, and the eighth transistor T81 is turned off.
  • the first node Q, the n-th stage transmission signal Cout(n), the first output signal WR(n), and the second output signal RD(n) maintain a low level.
  • the GOA circuit provided by the embodiment of the present application is a real-time compensation GOA circuit, and through the above process, a driving signal is provided for the scan line, so that the display panel can display a picture.
  • the third transistor T91 and the fourth transistor T92 are both turned on, so that P The potential of point and the second node M are low.
  • the third transistor T91 and the fourth transistor T92 are both turned on, the potential of point P remains low, and the potential of the second node M is pulled up for the first time.
  • the third transistor T91 is turned off, and the fourth transistor T92 is turned on, which pulls the potential of point P high. Due to the coupling effect, the potential of the second node M is pulled high for the second time.
  • the potential of the first node Q is pulled higher compared to the prior art, and the charging rate is ensured, thereby increasing the allowable threshold voltage margin of the GOA circuit and improving the stability of the GOA circuit , which reduces the difficulty of the development of the transistor manufacturing process.
  • a display panel with a POA (PS on Array, PS on the array substrate) structure is taken as an example.
  • the contact film layer 511 of the array substrate 51 in contact with the support pillar 54 (that is, the bottom layer above) is formed with a convex-concave pattern 55, and the convex-concave pattern 55 is used to increase the contact film layer 511 and the contact film 511.
  • the contact area of the support column 54 is taken as an example.
  • the convex-concave pattern includes a target pattern formed by the contact film layer by at least one of protrusions, recesses, or protrusions and recesses.
  • the contact film layer is formed by recesses.
  • the contact film layer may form the target pattern only by at least one of a convex manner or a convex-concave fitting manner.
  • the other part of the target pattern is formed by recessing.
  • the display panel provided by this embodiment increases the contact area between the support column and the bottom layer, and does not need to change the size of a single sub-pixel, which alleviates the technical problem that the support column is easily peeled off in the existing 8K ultra-high resolution electronic device.
  • the convex-concave pattern 55 provided in the embodiment of the present application has a grid-like shape corresponding to the target pattern.
  • the grid size is 1 to 6 microns
  • the interval is 1 to 6 microns
  • the depth is less than 0.5 microns.
  • the contact film layer (generally an organic material layer) can be lithographically implemented through a mask.
  • the contact film layer can be lithographically implemented through a mask. For example, for the setting area of the convex and concave pattern, by changing the grid design of the RGB/PFA mask here, using a mask with a transmittance of 80% to 90%, the transmittance is reduced, and part of the photoresist is removed by the developer. , The film thickness is reduced by 0.5 microns to form convex and concave patterns.
  • the driving circuit is formed in the third side region D3, and the convex-concave pattern is formed in the third side region D3.
  • the convex-concave pattern is formed in the third side region D3.
  • a light-shielding pattern pattern corresponding to the target pattern of the convex-concave pattern is formed, and the light transmittance of the light-shielding pattern pattern is 80% to 90%, thereby realizing the correspondence in the black matrix
  • the target pattern in which depressions are formed in the area is used as the convex-concave pattern.
  • the support pillars are formed on the color filter substrate.
  • the color filter substrate includes a base substrate and a black matrix formed on the base substrate.
  • the black matrix is arranged in the array and corresponds to the opening of the sub-pixel light-emitting area; the supporting column is formed on the black matrix, That is, the black matrix is the above-mentioned contact film layer, and the black matrix is formed with a convex-concave pattern in the contact area with the supporting column.
  • the support pillars are formed on the color filter substrate ,
  • the color filter substrate includes a base substrate, a black matrix formed on the base substrate, and a color filter layer, the black matrix is arranged around the array and the color filter layer corresponding to the light emitting area of the sub-pixel; the support column is formed On the black matrix, that is, the black matrix is the above-mentioned contact film layer, and the black matrix is formed with a convex-concave pattern in the contact area with the supporting column.
  • the support pillars are formed on the color filter substrate ,
  • the color filter substrate includes a base substrate, a black matrix formed on the base substrate, and a color filter layer formed on the black matrix;
  • the support column is formed on the color filter layer and is located on the In the area where the color film layer overlaps the black matrix, that is, the color film is the contact film layer mentioned above, and the color film layer is formed with a convex-concave pattern in the contact area with the support column.
  • the support pillars are formed on the color filter substrate ,
  • the color filter substrate includes a base substrate, a black matrix formed on the base substrate, and a color filter layer formed on the black matrix;
  • the support column is formed on the color filter layer and is located on the In the area where the color filter layer and the black matrix overlap, that is, the color filter layer is the above contact film layer, the color filter layer is formed with a convex-concave pattern in the contact area with the support column, and the black matrix A convex-concave pattern is also formed in the contact area between the color filter layer and the supporting column.
  • the support pillars are formed on the array substrate.
  • the substrate includes a base substrate, a drive circuit layer formed on the base substrate, and a planarization layer formed on the drive circuit layer; the support column is formed on the planarization layer, that is, the planarization layer
  • the planarization layer is formed with a convex-concave pattern in the contact area with the support column.
  • the support pillars are formed on the array substrate, and the array substrate It includes a base substrate, a drive circuit layer formed on the base substrate, a color resist layer formed on the drive circuit layer, and a planarization layer formed on the color resist layer; the support pillar is formed On the planarization layer, that is, the planarization layer is the above-mentioned contact film layer, and the planarization layer is formed with a convex-concave pattern in the contact area with the support column.
  • COA Color Filter on Array, RGB on the array substrate
  • POA PS on Array, PS on the array substrate
  • the support pillars are formed on the array substrate, and the array substrate It includes a base substrate, a drive circuit layer formed on the base substrate, a color resist layer formed on the drive circuit layer, and a planarization layer formed on the color resist layer (RGB layer);
  • the support column is formed on the planarization layer, that is, the planarization layer is the contact film layer described above, the planarization layer is formed with a convex-concave pattern in the contact area with the support column, and the color resist layer is A convex-concave pattern is also formed in the contact area between the planarization layer and the supporting column.
  • the material of the planarization layer is PFA (macromolecular organic transparent material)
  • the thickness of the planarization layer is about 1.5 micrometers
  • the thickness of the black matrix, color film layer and color resist layer is 2 to 3 micrometers
  • the support column includes a main support column (Main ps) and a secondary support column (Sub ps), and the contact film layer can form parameters (including size, shape, and Depth, etc.) the same convex-concave pattern can also form convex-concave patterns with different parameters (including size, shape, depth, etc.).
  • the depth of the convex-concave pattern 15 formed at the contact film layer contacting the main support pillar is greater than that of the contact auxiliary support The depth of the convex-concave pattern formed at the pillar.
  • the present application also provides an electronic device, including the display panel provided in any of the foregoing embodiments.
  • the electronic device includes a display panel, the display panel includes a color filter substrate and an array substrate that are arranged oppositely, and the color filter substrate includes:
  • the color filter substrate includes a plurality of pixel regions arranged in an array and corresponding to sub-pixels, and the pixel region includes a first region corresponding to the opening and a second region surrounding the first region, so The second region is formed with the black matrix; the second region includes a first side region and a second side region arranged in a row direction and parallel, and a third side region and a fourth side region arranged in a column direction and parallel Side area; the fifth distance from the side of the first side area away from the opening to the opening, which is smaller than the sixth distance from the side of the second side area away from the opening to the opening .
  • the electronic device includes a display panel
  • the display panel includes:
  • the GOA unit includes a pull-up module, and the pull-up module includes a clock input transistor connected to a clock signal;
  • N clock signal lines extending in the column direction and arranged in parallel;
  • clock signal connecting lines extending in the row direction and arranged in parallel, the clock signal connecting lines correspond to the GOA unit one-to-one, and are used to connect the clock input transistor of the pull-up module in the GOA unit to the corresponding clock signal String;
  • the n clock signal lines include an n1-th clock signal line and an n2-th clock signal line
  • the n2-th clock signal line is formed on the side of the n1-th clock signal line away from the GOA unit ,
  • the voltage drop value of the clock input transistor of the pull-up module in the m1th GOA unit connected to the n1th clock signal line is greater than the voltage drop of the pull-up module in the m2th GOA unit connected to the n2th clock signal line
  • the voltage drop value of the clock input transistor is greater than the voltage drop value of the clock input transistor.
  • the size of the clock input transistor of the pull-up module in the m1th GOA unit is larger than the clock input of the pull-up module in the m2th GOA unit The size of the transistor.
  • the clock input transistor includes a plurality of sub-transistors connected in an array, and the number of sub-transistors of the clock input transistor of the pull-up module in the m1th GOA unit is greater than The number of sub-transistors of the clock input transistor of the pull-up module in the m2th GOA unit.
  • the source area of the clock input transistor of the pull-up module in the m1th GOA unit is larger than the clock of the pull-up module in the m2th GOA unit
  • the source area of the input transistor; and/or, the drain area of the clock input transistor of the pull-up module in the m1th GOA unit is larger than the drain area of the clock input transistor of the pull-up module in the m2th GOA unit area.
  • the contact area between the source and the active layer of the clock input transistor of the pull-up module in the m1th GOA unit is smaller than that in the m2th GOA unit The contact area between the source of the clock input transistor of the pull-up module and the active layer.
  • the nth level GOA unit includes:
  • a pull-up control module connected to the first node, and used to pull up the potential of the first node during the display time period;
  • the logical addressing module includes a second node, the logical addressing module is connected to the first node, and is configured to raise the potential of the second node twice during the display time period, and in the blank time period , Pulling up the potential of the first node through the second node;
  • a pull-up module connected to the first node, for pulling up the potentials of the n-th stage transmission signal, the first output signal, and the second output signal;
  • a first pull-down module connected to the first node, and used to pull down the potential of the first node during the blank time period
  • the second pull-down module is connected to the first node and the third node, and is used to pull down the potentials of the first node and the third node respectively during the display time period;
  • a third pull-down module connected to the third node and the second pull-down module, and is used to pull down the potential of the third node during a blank time period;
  • a first pull-down maintenance module including the third node, the first pull-down maintenance module is connected to the first node and the first pull-down module, and is configured to maintain a low potential of the first node;
  • the second pull-down maintaining module is connected to the third node and the pull-up module, and is used to maintain the low level of the n-th stage transmission signal, the first output signal, and the second output signal.
  • the pull-up control module includes a first transistor and a second transistor, the gate and the first electrode of the first transistor, and the second transistor The gates are all connected to the n-2th stage signal transmission, the second electrode of the first transistor is connected to the first electrode and the fourth node of the second transistor, and the second electrode of the second transistor is connected to the first One node.
  • the source and drain layer material resistivity of the clock input transistor of the pull-up module in the m1th GOA unit is greater than that of the m2th GOA unit.
  • the material resistivity of the source and drain layer of the clock input transistor of the module is greater than that of the m2th GOA unit.
  • the source and drain layer thickness of the clock input transistor of the pull-up module in the m1th GOA unit is smaller than that of the pull-up module in the m2th GOA unit The source and drain layer thickness of the clock input transistor.
  • the contact area between the drain of the clock input transistor of the pull-up module in the m1th GOA unit and the active layer is smaller than that in the m2th GOA unit The contact area between the drain of the clock input transistor of the pull-up module and the active layer.
  • the present application provides a mask, a display panel, and an electronic device.
  • the mask includes a mask substrate, an opening pattern pattern, formed on the mask substrate, and used to form a black matrix or a color film layer of the color film substrate ,
  • the black matrix includes openings for filling the color filter layer; wherein, the mask includes a plurality of repeating regions, the repeating regions include a first region corresponding to the opening pattern pattern, and surrounding the first region The second region;
  • the second region includes a first side region and a second side region arranged in a row direction and parallel, and a third side region and a fourth side region arranged in a column direction and parallel; the The first distance from the side of the first side area away from the side of the opening pattern to the opening pattern is smaller than the side of the second side area away from the side of the opening pattern to the first distance from the side of the opening pattern.
  • the mask abandons the existing mask opening pattern, such as the design of the shading area in the center of the repeated area, and moves it to the side, so that the black matrix opening or color film layer of the target size can be obtained based on the diffraction effect, and it is not It is necessary to change the size of the opening pattern.
  • display panels with the same resolution and different sizes can use the same size mask.
  • the difference between these masks is that the distance between the opening pattern and the edge of the repeated area is different, which solves the existing 8K
  • the electronic device at least has the technical problem of preparing masks of different sizes for display panels of different sizes, which reduces the production cost of products.

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Abstract

本申请提供一种掩模板、显示面板以及电子设备，该掩模板将开口图形图案向重复区域的侧边移动，基于该结构相同分辨率不同尺寸的显示面板可以使用相同尺寸的掩模板，这些掩模板的区别仅仅是开口图形图案与重复区域边缘的距离不同，解决了现有8K电子设备至少存在需要针对不同尺寸显示面板制备不同尺寸掩模板的技术问题。

Description

一种掩模板、显示面板以及电子设备 技术领域
本申请涉及显示技术领域，尤其涉及一种掩模板、显示面板以及电子设备。
背景技术
随着显示技术的发展，显示屏、电视、手机等电子设备的分辨率越来越高，与分辨率提高对应的是像素数量的增多，像素数量的增多会带来各种各样需要攻克的技术难题。
例如，8K分辨率电子设备的单个子像素的面积，是4K分辨率电子设备的单个子像素的面积的四分之一，伴随的是对应掩模板的制备难度以及成本增加。在实际产品制备过程中，针对相同分辨率不同尺寸的显示面板，由于单个子像素的面积不同，需要开发制备不同尺寸的掩模板，例如现有技术在制备65寸8K分辨率的显示面板和85寸8K分辨率的显示面板时，就需要使用不同尺寸的掩模板，开发成本高，此时掩模板的尺寸是指掩模板上遮光区的尺寸。
因此，现有8K电子设备至少存在需要针对不同尺寸显示面板制备不同尺寸掩模板的技术问题，需要改进。
技术问题
本申请提供一种掩模板、显示面板以及电子设备，以解决现有8K电子设备至少存在需要针对不同尺寸显示面板制备不同尺寸掩模板的技术问题。
技术解决方案
为解决上述问题，本申请提供的技术方案如下：
本申请提供一种掩模板，用于制备彩膜基板，其包括：
掩模板基板；
开口图形图案，形成于所述掩模板基板上；
其中，所述掩模板包括多个重复区域，所述重复区域包括所述开口图形图案对应的第一区域、以及围绕所述第一区域的第二区域；所述第二区域包括行方向排列且平行的第一侧边区域和第二侧边区域、以及列方向排列且平行的第 三侧边区域和第四侧边区域；所述第一侧边区域远离所述开口图形图案的侧边到所述开口图形图案的第一距离，小于所述第二侧边区域远离所述开口图形图案的侧边到所述开口图形图案的第二距离。
在本申请的掩模板中，所述第三侧边区域远离所述开口图形图案的侧边到所述开口图形图案的第三距离，等于所述第四侧边区域远离所述开口图形图案的侧边到所述开口图形图案的第四距离。
在本申请的掩模板中，所述第一距离的值小于12微米，所述第二距离的值大于32微米。
在本申请的掩模板中，所述第一距离的值小于10微米，所述第二距离的值大于34微米。
在本申请的掩模板中，在所述行方向上，所述开口图形图案的宽度值为28微米。
在本申请的掩模板中，所述第一距离与所述第二距离的和为44微米。
本申请还提供一种显示面板，其包括相对设置的彩膜基板和阵列基板，所述彩膜基板包括：
衬底基板；
形成在所述衬底基板上的黑色矩阵，所述黑色矩阵包括用于填充彩膜层的开口；
形成在所述开口内的彩膜层；
其中，所述彩膜基板包括多个阵列排布、且与子像素对应的像素区域，所述像素区域包括所述开口对应的第一区域、以及围绕所述第一区域的第二区域，所述第二区域形成有所述黑色矩阵；所述第二区域包括行方向排列且平行的第一侧边区域和第二侧边区域、以及列方向排列且平行的第三侧边区域和第四侧边区域；所述第一侧边区域远离所述开口的侧边到所述开口的第五距离，小于所述第二侧边区域远离所述开口的侧边到所述开口的第六距离。
在本申请的显示面板中，在所述行方向上，所述第五距离的值小于18微米，所述第六距离的值大于18微米。
在本申请的显示面板中，在所述行方向上，所述开口的宽度值为16微米，所述第五距离与所述第六距离的和为56微米。
本申请还提供一种电子设备，包括上述任一项所述的显示面板。
在本申请的显示面板中，所述第m1个GOA单元内的上拉模块的时钟输入晶体管的漏极与有源层的接触面积小于所述第m2个GOA单元内的上拉模块的时钟输入晶体管的漏极与有源层的接触面积。
本申请还提供一种电子设备，包括显示面板，所述显示面板包括相对设置的彩膜基板和阵列基板，所述彩膜基板包括：
衬底基板；
形成在所述衬底基板上的黑色矩阵，所述黑色矩阵包括用于填充彩膜层的开口；
形成在所述开口内的彩膜层；
其中，所述彩膜基板包括多个阵列排布、且与子像素对应的像素区域，所述像素区域包括所述开口对应的第一区域、以及围绕所述第一区域的第二区域，所述第二区域形成有所述黑色矩阵；所述第二区域包括行方向排列且平行的第一侧边区域和第二侧边区域、以及列方向排列且平行的第三侧边区域和第四侧边区域；所述第一侧边区域远离所述开口的侧边到所述开口的第五距离，小于所述第二侧边区域远离所述开口的侧边到所述开口的第六距离。
在本申请的电子设备中，显示面板包括：
列方向排布的m个GOA单元，所述GOA单元包括上拉模块，所述上拉模块包括连接时钟信号的时钟输入晶体管；
列方向延伸且平行设置的n个时钟信号线；
行方向延伸且平行设置的m个时钟信号连接线，所述时钟信号连接线与所述GOA单元一一对应，用于将所述GOA单元内上拉模块的时钟输入晶体管连接至对应的时钟信号线；
其中，n个所述时钟信号线包括第n1个时钟信号线和第n2个时钟信号线，所述第n2个时钟信号线形成在所述第n1个时钟信号线远离所述GOA单元的一侧，连接所述第n1个时钟信号线的第m1个GOA单元内上拉模块的时钟输入晶体管的压降值，大于连接所述第n2个时钟信号线的第m2个GOA单元内上拉模块的时钟输入晶体管的压降值。
在本申请的电子设备中，所述第m1个GOA单元内的上拉模块的时钟输 入晶体管的尺寸，大于所述第m2个GOA单元内的上拉模块的时钟输入晶体管的尺寸。
在本申请的电子设备中，所述时钟输入晶体管包括阵列连接的多个子晶体管，所述第m1个GOA单元内的上拉模块的时钟输入晶体管的子晶体管的数量大于所述第m2个GOA单元内的上拉模块的时钟输入晶体管的子晶体管的数量。
在本申请的电子设备中，所述第m1个GOA单元内的上拉模块的时钟输入晶体管的源极面积大于所述第m2个GOA单元内的上拉模块的时钟输入晶体管的源极面积；和/或，所述第m1个GOA单元内的上拉模块的时钟输入晶体管的漏极面积大于所述第m2个GOA单元内上拉模块的时钟输入晶体管的漏极面积。
在本申请的电子设备中，所述第m1个GOA单元内的上拉模块的时钟输入晶体管的源极与有源层的接触面积小于所述第m2个GOA单元内的上拉模块的时钟输入晶体管的源极与有源层的接触面积。
在本申请的电子设备中，第n级GOA单元包括：
上拉控制模块，与第一节点连接，用于在显示时间段将所述第一节点的电位拉高；
逻辑寻址模块，包括第二节点，所述逻辑寻址模块与所述第一节点连接，用于在所述显示时间段，对所述第二节点电位进行两次拉高，在空白时间段，通过所述第二节点将所述第一节点的电位拉高；
上拉模块，与所述第一节点连接，用于将第n级级传信号、第一输出信号和第二输出信号的电位拉高；
第一下拉模块，与所述第一节点连接，用于在空白时间段将所述第一节点的电位拉低；
第二下拉模块，与所述第一节点和第三节点连接，用于在显示时间段分别将所述第一节点和所述第三节点的电位拉低；
第三下拉模块，与所述第三节点和所述第二下拉模块连接，用于在空白时间段将所述第三节点的电位拉低；
第一下拉维持模块，包括所述第三节点，所述第一下拉维持模块与所述第 一节点和所述第一下拉模块连接，用于维持所述第一节点的低电位；
第二下拉维持模块，与所述第三节点和所述上拉模块连接，用于维持所述第n级级传信号、所述第一输出信号和所述第二输出信号的低电位。
在本申请的电子设备中，所述上拉控制模块包括第一晶体管和第二晶体管，所述第一晶体管的栅极和第一电极、以及所述第二晶体管的栅极均连接第n-2级级传信号，所述第一晶体管的第二电极连接所述第二晶体管的第一电极和第四节点，所述第二晶体管的第二电极连接所述第一节点。
在本申请的电子设备中，所述第m1个GOA单元内的上拉模块的时钟输入晶体管的源漏极层材料电阻率大于所述第m2个GOA单元内上拉模块的时钟输入晶体管的源漏极层材料电阻率。
在本申请的电子设备中，所述第m1个GOA单元内的上拉模块的时钟输入晶体管的源漏极层厚度小于所述第m2个GOA单元内的上拉模块的时钟输入晶体管的源漏极层厚度。
在本申请的电子设备中，所述第m1个GOA单元内的上拉模块的时钟输入晶体管的漏极与有源层的接触面积小于所述第m2个GOA单元内的上拉模块的时钟输入晶体管的漏极与有源层的接触面积。
有益效果
本申请提供一种掩模板、显示面板以及电子设备，该掩模板包括掩模板基板，开口图形图案，形成于所述掩模板基板上；其中，所述掩模板包括多个重复区域，所述重复区域包括所述开口图形图案对应的第一区域、以及围绕所述第一区域的第二区域；所述第二区域包括行方向排列且平行的第一侧边区域和第二侧边区域、以及列方向排列且平行的第三侧边区域和第四侧边区域；所述第一侧边区域远离所述开口图形图案的侧边到所述开口图形图案的第一距离，小于所述第二侧边区域远离所述开口图形图案的侧边到所述开口图形图案的第二距离。该掩模板放弃现有掩模板开口图形图案，如遮光区等位于重复区域(用于形成像素区域)中心的设计，将其向侧边移动，这样就可以基于衍射效应得到目标尺寸的黑色矩阵开口或者彩膜层，同时不需要改变开口图形图案的尺寸，基于该结构相同分辨率不同尺寸的显示面板可以使用相同尺寸的掩模板，这些掩模板的区别仅仅是开口图形图案与重复区域边缘的距离不同，解决 了现有8K电子设备至少存在需要针对不同尺寸显示面板制备不同尺寸掩模板的技术问题，降低了产品制备成本。
附图说明
图1为现有技术中的掩模板的效果示意图。
图2a为本申请实施例提供的掩模板重复区域的俯视图。
图2b为本申请实施例提供的掩模板重复区域的剖视图。
图3a为本申请实施例提供的显示面板的结构示意图。
图3b为本申请实施例提供的彩膜基板像素区域的俯视图。
图3c为本申请实施例提供的彩膜基板像素区域的剖视图。
图4a至图4o为本申请实施例提供的显示面板的制备示意图。
图5为本申请实施例提供的显示面板的另一种结构示意图。
图6为本申请实施例提供的显示面板的电路示意图。
图7为本申请实施例提供的GOA电路的电路示意图。
图8a至图8c为本申请实施例的时序图。
图9为本申请实施例提供的目标图案的设计示意图。
本发明的实施方式
为使本申请的目的、技术方案及效果更加清楚、明确，以下参照附图并举实施例对本申请进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。在图中，结构相近的单元是用以相同标号表示。
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”、“顺时针”、“逆时针”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接或可以相互通讯；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本申请中的具体含义。
在本申请中，除非另有明确的规定和限定，第一特征在第二特征之“上”或之“下”可以包括第一和第二特征直接接触，也可以包括第一和第二特征不是直接接触而是通过它们之间的另外的特征接触。而且，第一特征在第二特征“之上”、“上方”和“上面”包括第一特征在第二特征正上方和斜上方，或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”包括第一特征在第二特征正下方和斜下方，或仅仅表示第一特征水平高度小于第二特征。
下文的公开提供了许多不同的实施方式或例子用来实现本申请的不同结构。为了简化本申请的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本申请。此外，本申请可以在不同例子中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。此外，本申请提供了的各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的 应用和/或其他材料的使用。
液晶显示面板各像素的子像素是设置按行设置的，在本申请中，子像素的排列方向就是行方向，与行方向垂直的方式就是列方向，行宽度值是指某个区域在行方向上的宽度值大小。
在本申请中，重复区域是指掩模板上的一个区域，掩模板是由陈列分布的重复区域组成的，像素区域是指显示面板中一个最小发光单元(即子像素)对应的区域，像素区域包括出光区以及围绕出光区的遮光区；在制备显示面板的过程中，对位掩模板与基板就是将掩模板的重复区域与基板的像素区域进行对位。
图1为现有掩模板的效果示意图，掩模板的遮光区设置在像素区域的正中间，如图1所示，在65寸8K分辨率的显示面板中单个子像素的行宽度值为52微米，65寸8K分辨率的显示面板对应的掩模板1的像素区域行宽度值也是52微米，在85寸8K分辨率的显示面板中单个子像素的行宽度值为72微米，85寸8K分辨率的显示面板对应的掩模板2的像素区域行宽度值也是72微米，若采用相同尺寸的掩模板，即遮光区的行宽度值为28微米时，在行方向上，掩模板1的单个透光区的行宽度值为12微米，掩模板2的单个透光区的行宽度值为22微米，在光刻时，透光区形成狭缝，光线透过狭缝产生衍射，根据光的衍射原理，狭缝越小，光的衍射范围越大。
黑色矩阵是负性光阻，没有照射到光线的区域被蚀刻到形成开口。那么，如图1所示，掩模板1遮光区的实际有效遮挡范围的行宽度值为16微米(即单个缝隙的衍射范围为6微米)，形成的65寸8K分辨率显示面板单个子像素的出光区的行宽度为16微米，掩模板2遮光区的实际有效遮挡范围的行宽度值为18微米(即单个缝隙的衍射范围为5微米)，形成的85寸8K分辨率显示面板单个子像素的出光区的行宽度为18微米，这也是符合光的衍射原理的。但是这会导致65寸8K分辨率显示面板单个子像素的出光区行宽度与85寸8K分辨率显示面板单个子像素的出光区行宽度不同，后续在形成RGB彩膜层时，需要使用不同尺寸的掩模板。
因此，现有8K电子设备至少存在需要针对不同尺寸显示面板制备不同尺寸掩模板的技术问题，需要改进。那么，本申请提供一种掩模板、显示面板以 及电子设备，可以解决现有8K电子设备至少存在需要针对不同尺寸显示面板制备不同尺寸掩模板的技术问题。
如图2a以及图2b所示，本申请提供的掩模板包括：
掩模板基板11；
开口图形图案12，形成于所述掩模板基板11上，用于形成所述彩膜基板的黑色矩阵或者彩膜层，所述黑色矩阵包括用于填充彩膜层的开口；
其中，所述掩模板包括多个重复区域Z，所述重复区域Z包括所述开口图形图案12对应的第一区域Z1、以及围绕所述第一区域Z1的第二区域Z2；所述第二区域Z2包括行方向排列且平行的第一侧边区域C1和第二侧边区域C2、以及列方向排列且平行的第三侧边区域C3和第四侧边区域C4；所述第一侧边区域C1远离所述开口图形图案12的侧边到所述开口图形图案12的第一距离h1，小于所述第二侧边区域C2远离所述开口图形图案12的侧边到所述开口图形图案12的第二距离h2。
本实施例提供一种掩模板，该掩模板包括掩模板基板，开口图形图案，形成于所述掩模板基板上，用于形成所述彩膜基板的黑色矩阵或者彩膜层，所述黑色矩阵包括用于填充彩膜层的开口；其中，所述掩模板包括多个重复区域，所述重复区域包括所述开口图形图案对应的第一区域、以及围绕所述第一区域的第二区域；所述第二区域包括行方向排列且平行的第一侧边区域和第二侧边区域、以及列方向排列且平行的第三侧边区域和第四侧边区域；所述第一侧边区域远离所述开口图形图案的侧边到所述开口图形图案的第一距离，小于所述第二侧边区域远离所述开口图形图案的侧边到所述开口图形图案的第二距离。该掩模板放弃现有掩模板开口图形图案，如遮光区等位于重复区域中心的设计，将其向侧边移动，这样就可以基于衍射效应得到目标尺寸的黑色矩阵开口或者彩膜层，同时不需要改变开口图形图案的尺寸，基于该结构相同分辨率不同尺寸的显示面板可以使用相同尺寸的掩模板，这些掩模板的区别仅仅是开口图形图案与重复区域Z边缘的距离不同，解决了现有8K电子设备至少存在需要针对不同尺寸显示面板制备不同尺寸掩模板的技术问题，降低了产品制备成本。
在一种实施例中，所述第三侧边区域C3远离所述开口图形图案12的侧边 到所述开口图形图案12的第三距离h3，等于所述第四侧边区域C4远离所述开口图形图案12的侧边到所述开口图形图案12的第四距离h4。
在一种实施例中，挡掩模板用于制备85寸以及85寸以上尺寸8K分辨率的显示面板时，所述第一距离h1的值小于12微米，所述第二距离h2的值大于32微米。
在一种实施例中，挡掩模板用于制备85寸以及85寸以上尺寸8K分辨率的显示面板时，所述第一距离h1的值小于10微米，所述第二距离h2的值大于34微米。
在一种实施例中，挡掩模板用于制备65寸以及65寸以上尺寸8K分辨率的显示面板时，在所述行方向上，所述开口图形图案12的宽度值为28微米。
在一种实施例中，挡掩模板用于制备85寸8K分辨率的显示面板时，在本申请的掩模板中，所述第一距离h1与所述第二距离h2的和为44微米。
在一种实施例中，开口图形图案12为光透光率为0的材料图案化形成，该材料包括金属铬等。
在一种实施例中，相邻重复区域Z之间形成有一条光透光率为0的直线，以保证狭缝效应，该直线的宽度小于1微米，不会影响该区域下方黑色矩阵的图案。
如图3a、3b以及图3c所示，本申请实施例提供的显示面板包括：相对设置的阵列基板21和彩膜基板22，所述彩膜基板22包括：
衬底基板221；
形成在所述衬底基板上的黑色矩阵222，所述黑色矩阵包括用于填充彩膜层223的开口；
形成在所述开口内的彩膜层223；
其中，如图3b以及图3c所示，所述彩膜基板22包括多个阵列排布、且与子像素对应的像素区域W，所述像素区域W包括所述开口对应的第一区域W1、以及围绕所述第一区域W1的第二区域W2，所述第二区域W2形成有所述黑色矩阵222；所述第二区域W2包括行方向排列且平行的第一侧边区域D1和第二侧边区域D2、以及列方向排列且平行的第三侧边区域D3和第四侧边区域D4； 所述第一侧边区域D1远离所述开口的侧边到所述开口的第五距离L1，小于所述第二侧边区域远离所述开口的侧边到所述开口的第六距离L2。
本实施例提供一种显示面板，该显示面板的彩膜基板包括衬底基板，形成在所述衬底基板上的黑色矩阵，所述黑色矩阵包括用于填充彩膜层的开口，形成在所述开口内的彩膜层；其中，所述彩膜基板包括多个阵列排布、且与子像素对应的像素区域，所述像素区域包括所述开口对应的第一区域、以及围绕所述第一区域的第二区域，所述第二区域形成有所述黑色矩阵；所述第二区域包括行方向排列且平行的第一侧边区域和第二侧边区域、以及列方向排列且平行的第三侧边区域和第四侧边区域；所述第一侧边区域远离所述开口的侧边到所述开口的第五距离，小于所述第二侧边区域远离所述开口的侧边到所述开口的第六距离。基于该结构，相同分辨率不同尺寸的显示面板可以使用相同尺寸的掩模板，这些掩模板的区别仅仅是开口图形图案与像素区域边缘的距离不同，解决了现有8K电子设备至少存在需要针对不同尺寸显示面板制备不同尺寸掩模板的技术问题，降低了产品制备成本。
在一种实施例中，在85寸以及85寸以上尺寸8K分辨率的显示面板中，在所述行方向上，所述第五距离L1的值小于18微米，所述第六距离L2的值大于18微米。
在一种实施例中，在85寸8K分辨率的显示面板中，在所述行方向上，所述开口的宽度值为16微米，所述第五距离L1与所述第六距离L2的和为56微米。
在一种实施例中，为了得到图3a所示实施例中的彩膜基板，如图4a至图4o所示，本申请实施例还提供了以下彩膜基板制备方法，该方法包括：
步骤1、提供衬底基板。
如图4a所示，提供透明玻璃基板等作为衬底基板41。
步骤2、在衬底基板上形成黑色矩阵材料层。
如图4b所示，在透明玻璃基板等衬底基板41上，形成黑色矩阵材料层42。其中，黑色矩阵材料层的材料为负性光阻，被掩模板遮光的区域被去除。
步骤3、对位第一掩模板和所述衬底基板。
如图4c所示，取用第一掩模板Y1，该第一掩模板Y1的每个与像素区域 W对应的重复区域Z均采用图2a及图2b所示实施例的设计。将第一掩模板Y1与步骤2得到的衬底基板进行对位。
步骤4、图案化处理黑色矩阵材料形成黑色矩阵。
如图4d所示，使用曝光机等设备基于第一掩模板，对黑色矩阵材料层42进行光刻处理，得到黑色矩阵43。
步骤5、涂布红色色阻材料层。
如图4e所示，在步骤4得到的衬底基板上，整面涂布红色光阻层44。其中，红色光阻层的材料为正性光阻，被掩模板遮光的区域保留。
步骤6、对位第二掩模板和所述衬底基板。
如图4f所示，取用第二掩模板Y2，该第二掩模板Y2仅在红色子像素对应的像素区域W对应的重复区域Z采用图2a及图2b所示实施例的设计。将第二掩模板Y2与步骤5得到的衬底基板进行对位。
步骤7、图案化处理红色光阻层。
如图4g所示，使用曝光机等设备基于第二掩模板，对红色光阻层44进行光刻处理，得到红色滤光层45。
步骤8、涂布绿色色阻材料层。
如图4h所示，在步骤7得到的衬底基板上，整面涂布绿色光阻层46。其中，绿色光阻层的材料为正性光阻，被掩模板遮光的区域保留。
步骤9、对位第三掩模板和所述衬底基板。
如图4i所示，取用第三掩模板Y3，该第三掩模板Y3仅在绿色子像素对应的像素区域W对应的重复区域Z采用图2a及图2b所示实施例的设计。将第三掩模板Y3与步骤8得到的衬底基板进行对位。
步骤10、图案化处理绿色光阻层。
如图4j所示，使用曝光机等设备基于第三掩模板，对绿色光阻层46进行光刻处理，得到绿色滤光层47。
步骤11、涂布蓝色色阻材料层。
如图4k所示，在步骤10得到的衬底基板上，整面涂布蓝色光阻层48。其中，蓝色光阻层的材料为正性光阻，被掩模板遮光的区域保留。
步骤12、对位第四掩模板和所述衬底基板。
如图4l所示，取用第四掩模板Y4，该第四掩模板Y4仅在蓝色子像素对应的像素区域W对应的重复区域Z采用图2a及图2b所示实施例的设计。将第四掩模板Y4与步骤11得到的衬底基板进行对位。
步骤13、图案化处理蓝色光阻层。
如图4m所示，使用曝光机等设备基于第四掩模板，对蓝色光阻层48进行光刻处理，得到蓝色滤光层49。
步骤14、制备支撑柱。
如图4n所示，在步骤13得到的衬底基板的黑色矩阵上制备支撑柱410。
步骤15、制备平坦化层以及公共电极层。
如图4o所示，在步骤14得到的衬底基板上，依次使用大分子有机颗粒制备平坦化层411，使用TIO等透明导电材料在平坦化层411制备公共电极层412。
针对8K超高分辨率显示面板，除去上述8K电子设备存在的需要针对不同尺寸显示面板制备不同尺寸掩模板的技术问题，至少还存在以下技术问题：
8K分辨率电子设备的单个子像素的面积，是4K分辨率电子设备的单个子像素的面积的四分之一，伴随的是面板内支撑柱(ps)与底层接触面积的减少，在8K分辨率电子设备中，支撑柱与底层的接触面积为20微米*20微米甚至更小，这么小的接触面积将导致支撑柱容易从底层上剥落(peeling)，而支撑柱剥落会导致液晶出现空白边、整面压力异常等问题；
8K超高分辨率电子设备的loading(压降)较重，充电时间较短，采用GOA(Gate on Array，栅极驱动电路集成在阵列基板上)驱动以及厚铜设计，导致超高分辨率电子设备对GOA中各CK(时钟)信号之间的阻抗差异极为敏感。8K电子设备的分辨率为7680*4320，总共有4320行GOA单元，采用12CK信号线(即12个时钟信号线)的GOA驱动架构，CK信号线的阻抗差异可达到千欧姆级别，阻抗差异会导致CK图形和相应GOA单元输出的扫描线波形存在差异，进而导致面板显示出现水平衡线等问题。
为了解决这些技术问题，在一种实施例中，如图5所示，本申请实施例提供的显示面板包括：
阵列基板51，形成有驱动电路层以及像素电极等；
彩膜基板52，与阵列基板51相对设置；
胶框53，用于封装阵列基板51及彩膜基板52，并与之形成密封空间，密封空间内填充有液晶；
支撑柱54，形成在阵列基板51或者彩膜基板上，用于支撑阵列基板51及彩膜基板52。
在一种实施例中，如图5所示，在每一个像素区W内，彩膜基板52采用上述任一实施例提供的结构，或者通过任一实施例提供的掩模板制备得到。
在一种实施例中，针对CK阻抗差异技术问题，如图6所示，在胶框53所在的非显示区内，显示面板形成有：
列方向排布的m个GOA单元601，所述GOA单元601包括上拉模块，所述上拉模块包括连接时钟信号的时钟输入晶体管；
列方向延伸且平行设置的n个时钟信号线602；
行方向延伸且平行设置的m个时钟信号连接线603，所述时钟信号连接线603与所述GOA单元601一一对应，用于将所述GOA单元601内上拉模块的时钟输入晶体管连接至对应的时钟信号线602；
其中，n个所述时钟信号线包括第n1个时钟信号线和第n2个时钟信号线，所述第n2个时钟信号线形成在所述第n1个时钟信号线远离所述GOA单元的一侧，连接所述第n1个时钟信号线的第m1个GOA单元内上拉模块的时钟输入晶体管的压降值，大于连接所述第n2个时钟信号线的第m2个GOA单元内上拉模块的时钟输入晶体管的压降值，n1与n2不同，且属于1至n，m1与m2不同，且属于1至m。
以显示面板的分辨率是7680*4320为例，显示面板包括4320个GOA单元601、12个时钟信号线602(图6中的CK1至CK12)，每个时钟信号线602连接360个GOA单元601，那么可以预见在列方向上和行方向上，连接CK12的GOA单元601与连接CK1的GOA单元601的压降值差异为电阻R1和电阻R2之和与电流I的乘积，电阻R1和电阻R2之和可达到千欧姆级别。基于该现状，本申请放弃对时钟信号线进行压降改进，而独创性的提出对GOA单元内的时钟输入晶体管(即连接外界时钟信号的薄膜晶体管)的参数进行调整， 以改变其对应的压降值。
本实施例提供一种显示面板，该显示面板包括列方向排布的m个GOA单元，所述GOA单元包括上拉模块，所述上拉模块包括连接时钟信号的时钟输入晶体管，列方向延伸且平行设置的n个时钟信号线，行方向延伸且平行设置的m个时钟信号连接线，所述时钟信号连接线与所述GOA单元一一对应，用于将所述GOA单元内上拉模块的时钟输入晶体管连接至对应的时钟信号线；其中，所述时钟信号线包括第n1个时钟信号线和第n2个时钟信号线，所述第n2个时钟信号线形成在所述第n1个时钟信号线远离所述GOA单元的一侧，连接所述第n1个时钟信号线的第m1个GOA单元内上拉模块的时钟输入晶体管的压降值，大于连接所述第n2个时钟信号线的第m2个GOA单元内上拉模块的时钟输入晶体管的压降值。基于该电路结构，通过调整不同GOA单元内时钟输入晶体管的压降值，使得对由于时钟信号线和时钟信号连接线长度不同导致的压降值可以得到补偿，进而使得各GOA单元与时钟驱动芯片之间的压降值近似相同，缓解了8K超高分辨率电子设备存在的CK阻抗差异，改善了8K超高分辨率电子设备存在的导致GOA单元输出信号差异的技术问题。
在一种实施例中，显示面板包括有源层、第一金属层、第二金属层，所述有源层图案化形成晶体管的沟道区，第一金属层图案化形成栅极、栅极扫描线以及时钟信号线，第二金属层图案化形成时钟信号连接线、晶体管的源极、漏极等，此时，CK信号与GOA单元中时钟输入晶体管的源级相连，CK信号通过时钟信号线(第一金属层)输入，经过转接孔传输到时钟信号连接线(第二金属层)挂到时钟输入晶体管的源级。
在一种实施例中，时钟输入晶体管的参数包括晶体管的尺寸、膜层材料的电阻率、膜层厚度等多个维度，针对连接不同时钟信号线的时钟输入晶体管，可以仅调整一种参数，也可以同时调整多种参数，以使得连接所有时钟信号线的GOA单元到时钟驱动芯片之间的压降近似相同。
在一种实施例中，连接同一时钟信号线的、属于不同GOA单元的时钟输入晶体管的压降值相同。
在一种实施例中，连接不同时钟信号线的时钟输入晶体管的尺寸参数不同，即第m1个GOA单元内上拉模块的时钟输入晶体管的子晶体管的尺寸， 大于所述第m2个GOA单元内上拉模块的时钟输入晶体管的子晶体管的尺寸。
在一种实施例中，如图6所示，时钟输入晶体管包括阵列连接的多个子晶体管形成，所述第m1个GOA单元内上拉模块的时钟输入晶体管的子晶体管的数量，大于所述第m2个GOA单元内上拉模块的时钟输入晶体管的子晶体管的数量。在实际制备过程中，每个晶体管都是采用阵列的子晶体管串联方式实现的，串联的子晶体管的数量越多，晶体管的电阻值越大，本实施例基于此对晶体管的子晶体管数据进行调整，在制备时，仅需改变不同GOA单元中时钟输入晶体管子晶体管对应的掩模板遮光区域的数量即可得到本实施例。
在一种实施例中，所述第m1个GOA单元内上拉模块的时钟输入晶体管的源极面积，大于所述第m2个GOA单元内上拉模块的时钟输入晶体管的源极面积。针对有源层参数、栅极参数、漏极参数(包括材料电阻率、面积、厚度)、源极部分参数(包括材料电阻率、厚度)相同的情况下，源极面积越大，晶体管的电阻值越大，本实施例基于此对晶体管的压降值进行调整，在制备时，仅需改变不同GOA单元中时钟输入晶体管源极对应的掩模板遮光区域的面积即可得到本实施例。
在一种实施例中，所述第m1个GOA单元内上拉模块的时钟输入晶体管的源极与有源层的接触面积，小于所述第m2个GOA单元内上拉模块的时钟输入晶体管的源极与有源层的接触面积。针对有源层参数、栅极参数、漏极参数(包括材料电阻率、面积、厚度)、源极参数(包括材料电阻率、面积、厚度)相同的情况下，源极与有源层的接触面积越小，晶体管的电阻值越大，本实施例基于此对晶体管的压降值进行调整，在制备时，仅需改变不同GOA单元中时钟输入晶体管源极连接过孔对应的掩模板透光区域的面积即可得到本实施例。
在一种实施例中，所述第m1个GOA单元内上拉模块的时钟输入晶体管的漏极面积，大于所述第m2个GOA单元内上拉模块的时钟输入晶体管的漏极面积。针对有源层参数、栅极参数、源极参数(包括材料电阻率、面积、厚度)、漏极部分参数(包括材料电阻率、厚度)相同的情况下，漏极面积越大，晶体管的电阻值越大，本实施例基于此对晶体管的压降值进行调整，在制备时，仅需改变不同GOA单元中时钟输入晶体管漏极对应的掩模板遮光区域的面积 即可得到本实施例。
在一种实施例中，所述第m1个GOA单元内上拉模块的时钟输入晶体管的漏极与有源层的接触面积，小于所述第m2个GOA单元内上拉模块的时钟输入晶体管的漏极与有源层的接触面积。针对有源层参数、栅极参数、漏极参数(包括材料电阻率、面积、厚度)、源极参数(包括材料电阻率、面积、厚度)相同的情况下，漏极与有源层的接触面积越小，晶体管的电阻值越大，本实施例基于此对晶体管的压降值进行调整，在制备时，仅需改变不同GOA单元中时钟输入晶体管漏极连接过孔对应的掩模板透光区域的面积即可得到本实施例。
在一种实施例中，所述第m1个GOA单元内上拉模块的时钟输入晶体管的源漏极层材料电阻率，大于所述第m2个GOA单元内上拉模块的时钟输入晶体管的源漏极层材料电阻率。针对有源层参数、栅极参数、漏极部分参数(包括面积、厚度)、源极部分参数(包括面积、厚度)相同的情况下，源漏极层材料电阻率越大，晶体管的电阻值越大，本实施例基于此对晶体管的压降值进行调整，在制备时，仅需使用不同电阻率的材料，或者改变不同电阻率材料的材料配比即可得到本实施例。在一种实施例中，本申请提供的源漏极材料包括4层结构，自下至上依次为金属钛Ti、金属铝Al、金属铜Cu、金属钛Ti，在保证所有晶体管的金属铝Al和金属铜Cu总膜层厚度一定的基础上，改变金属铝Al和金属铜Cu的厚度，可以实现源漏极层材料电阻率的改变，由于铜的电阻率小于铝的电阻率，在沉积金属层时，针对第m1个GOA单元内上拉模块的时钟输入晶体管的源漏极层沉积较厚的铝层，针对第m2个GOA单元内上拉模块的时钟输入晶体管的源漏极层沉积较薄的铝层，即可实现本实施例。
在一种实施例中，所述第m1个GOA单元内上拉模块的时钟输入晶体管的源漏极层厚度，小于所述第m2个GOA单元内上拉模块的时钟输入晶体管的源漏极层厚度。针对有源层参数、栅极参数、漏极部分参数(包括材料电阻率、面积)、源极部分参数(包括材料电阻率、面积)相同的情况下，源漏极层材料厚度越小，晶体管的电阻值越大，本实施例基于此对晶体管的压降值进行调整，在制备时，仅需在不同区域沉积不同厚度的源漏极材料即可得到本实 施例。
同时，随着显示面板分辨率的增大，需要实时的对GOA单元输出的信号进行补偿，基于此，本申请实施例还提供了一种GOA电路，本申请实施例提供的GOA电路包括m个级联的GOA单元，如图7所示，其中GOA单元包括上拉控制模块701、逻辑寻址模块702、上拉模块703、第一下拉模块704、第二下拉模块705、第三下拉模块706、第一下拉维持模块707和第二下拉维持模块708。
上拉控制模块701与第一节点Q连接，用于在显示时间段将第一节点Q的电位拉高。
逻辑寻址模块702包括第二节点M，逻辑寻址模块与第一节点连接，用于在显示时间段，对第二节点电位进行两次拉高，在空白时间段，通过第二节点将第一节点的电位拉高。
上拉模块703与第一节点Q连接，用于将第n级级传信号Cout(n)、第一输出信号WR(n)和第二输出信号RD(n)的电位拉高。
第一下拉模块704与第一节点Q连接，用于在空白时间段将第一节点Q的电位拉低。
第二下拉模块705与第一节点Q和第三节点QB连接，用于在显示时间段分别将第一节点Q和第三节点QB的电位拉低。
第三下拉模块706与第三节点QB和第二下拉模块705连接，用于在空白时间段将第三节点QB的电位拉低。
第一下拉维持模块707包括第三节点QB，第一下拉维持模块707与第一节点Q和第一下拉模块704连接，用于维持第一节点Q的低电位。
第二下拉维持模块708与第三节点QB和上拉模块703连接，用于维持第n级级传信号Cout(n)、第一输出信号WR(n)和第二输出信号RD(n)的低电位。
显示面板在显示画面时需要经过显示时间段Promgraming和空白时间段Blank，其中显示时间段为每帧画面的实际显示时间段，空白时间段为相邻帧画面的实际显示时间之间的时间段。
在图7所示的实施例中，上拉模块703中的第十晶体管T23、第十一晶体管T22以及第十二晶体管T21均为上文中的时钟输入晶体管，在图7所示的 实施例中，时钟驱动芯片需要为同一个GOA单元输入3个时钟信号CKa、CKb以及CKc，那么此时，每一个时钟信号线又被分为3个子时钟信号线，分别用于传输CKa、CKb以及CKc，每个时钟信号连接线又被分为3个子时钟信号连接线，分别将时钟信号CKa、CKb以及CKc连接至对应的时钟输入晶体管。
本实施例通过在显示时间段对第二节点M的电位进行两次拉高，使得在空白时间段，第一节点Q的充电率得到保证，进而使得GOA电路允许的阈值电压余量提升，提高了GOA电路的稳定性，降低了晶体管制程的开发难度。
如图7所示，上拉控制模块701包括第一晶体管T11和第二晶体管T12，第一晶体管T11的栅极和第一电极、以及第二晶体管T12的栅极均连接第n-2级级传信号Cout(n-2)，第一晶体管T11的第二电极连接第二晶体管T12的第一电极，第二晶体管T12的第二电极连接第一节点Q。
逻辑寻址模块702包括第三晶体管T91、第四晶体管T92、第五晶体管T71、第六晶体管T72、第七晶体管T73、第八晶体管T81、第九晶体管T91和第一存储电容Cbt3，第三晶体管T91的栅极连接第n-2级级传信号Cout(n-2)，第三晶体管T91的第一电极连接第一低电位信号VGL1，第三晶体管T91的第二电极连接第四晶体管T92的第一电极，第四晶体管T92的栅极和第二电极均连接高电位信号VGH，第五晶体管T71的栅极连接第一输入信号LSP，第五晶体管T71的第一电极连接第n-2级级传信号Cout(n-2)，第五晶体管T71的第二电极连接第六晶体管T72的第一电极和第七晶体管T73的第一电极，第六晶体管T72的栅极连接第一输入信号，第六晶体管T72的第二电极和第七晶体管T73的栅极均连接第二节点M，第七晶体管T73的第二电极连接高电位信号VGH，第八晶体管T81的栅极连接第二节点M，第八晶体管T81的第一电极连接高电位信号VGH，第八晶体管T81的第二电极连接第九晶体管T91的第一电极，第九晶体管T91的栅极连接复位信号Total-Reset，第九晶体管T91的第二电极连接第一节点Q，第一存储电容Cbt3的第一极板连接第三晶体管T91的第二电极，第二极板连接第二节点M。
上拉模块703包括第十晶体管T23、第十一晶体管T22、第十二晶体管T21、第十三晶体管T6、第二存储电容Cbt1和第三存储电容Cbt2，第十晶体管T23的栅极、第十一晶体管T22的栅极以及第十二晶体管T21的栅极均连接第一 节点Q，第十晶体管T23的第一电极连接第一时钟信号CKa，第十晶体管T23的第二电极连接第n级级传信号Cout(n)，第十一晶体管T22的第一电极连接第二时钟信号CKb，第十一晶体管T22的第二电极连接第一输出信号WR(n)，第十二晶体管T21的第一电极连接第三时钟信号CKc，第十二晶体管T21的第二电极连接第二输出信号RD(n)，第十三晶体管T6的栅极连接第一节点Q，第十三晶体管T6的第一电极连接第四节点N，第十三晶体管T6的第二电极连接第一输出信号WR(n)，第二存储电容Cbt1的第一极板连接第一节点Q，第二极板连接第一输出信号WR(n)，第三存储电容Cbt2的第一极板连接第一节点Q，第二极板连接第二输出信号RD(n)。
第一下拉模块704包括第十四晶体管T33和第十五晶体管T34，第十四晶体管T33的栅极和第十五晶体管T34的栅极均连接第二输入信号VST，第十四晶体管T33的第一电极连接第一节点Q，第十四晶体管T33的第二电极连接第十五晶体管T34的第一电极和第四节点N，第十五晶体管T34的第二电极连接第一低电位信号VGL1。
第二下拉模块705包括第十六晶体管T31、第十七晶体管T32和第十八晶体管T55，第十六晶体管T31的栅极和第十七晶体管T32的栅极连接第n+2级级传信号Cout(n+2)，第十六晶体管T31的第一电极连接第一节点Q，第十六晶体管T31的第二电极连接第十七晶体管T32的第一电极和第四节点N，第十七晶体T32管的第二电极连接第一低电位信号VGL1，第十八晶体管T55的栅极连接第n-2级级传信号Cout(n-2)，第十八晶体管T55的第一电极连接第二低电位信号VGL2，第十八晶体管T55的第一电极连接第三节点QB。
第三下拉模块706包括第十九晶体管T102和第二十晶体管T101，第十九晶体管T102的栅极连接所述第二节点，第十九晶体管T102的第一电极连接第二低电位信号VGL2，第十九晶体管T102的第二电极连接第二十晶体管T101的第一电极，第二十晶体管T101的栅极连接复位信号Total-Reset，第二十晶体管T101的第二电极连接第三节点QB。
第一下拉维持模块707包括第二十一晶体管T44、第二十二晶体管T45、第二十三晶体管T51、第二十四晶体管T52、第二十五晶体管T53和第二十六晶体管T54，第二十一晶体管T44的栅极和第二十二晶体管T45的栅极连接第 三节点QB，第二十一晶体管T44的第一电极连接第一节点Q，第二十一晶体管T44的第二电极连接第二十二晶体管T45的第一电极和第四节点N，第二十二晶体管T45的第二电极连接第一低电位信号VGL1，第二十三晶体管T51的栅极和第一电极连接高电位信号VGH，第二十三晶体管T51的第二电极连接第二十四晶体管T52的第一电极，第二十四晶体管T52的栅极连接第一节点Q，第二十四晶体管T52的第二电极连接第二低电位信号VGL2，第二十五晶体管T53的栅极连接第二十三晶体管T51的第二电极，第二十五晶体管T53的第一电极连接高电位信号VGH，第二十五晶体管T53的第二电极连接第二十六晶体管T54的第一电极和第三节点QB，第二十六晶体管T54的栅极连接第一节点Q，第二十六晶体管T54的第二电极连接第二低电位信号VGL2。
第二下拉维持模块708包括第二十七晶体管T43、第二十八晶体管T42和第二十九晶体管T41，第二十七晶体管T43的栅极、第二十八晶体管T42的栅极以及第二十九晶体管T41的栅极均连接第三节点QB，第二十七晶体管T43的第一电极连接第一低电位信号VGL1，第二十七晶体管T43的第二电极连接第n级级传信号Cout(n)，第二十八晶体管T42的第一电极连接第三低电位信号VGL3，第二十八晶体管T42的第二电极连接第一输出信号WR(n)，第二十九晶体管T41的第一电极连接第三低电位信号VGL3，第二十九晶体管T41的第二电极连接第二输出信号RD(n)。
在本申请的GOA电路中，包括m个级联的GOA单元，其中第n级GOA单元输出的级传信号为第n级级传信号Cout(n)，2≤n≤m，且n为整数。第n-2级级传信号Cout(n-2)为第n级级传信号Cout(n)之前且与其相隔一级的级传信号，第n+2级级传信号Cout(n+2)为第n级级传信号Cout(n)之前且与其相隔一级的级传信号。
在本申请的GOA电路中，第一输入信号LSP、第二输入信号VST、复位信号Total-Reset均由外部时序器提供。
本实施例提供的GOA电路为实时补偿电路，要求GOA在每一帧对应的显示时间段输出正常的驱动时序显示画面，而在每一帧之间的空白时间段输出宽脉冲时序进行阈值电压Vth探测用。图8a示出了本申请实施例的GOA电路在显示时间段Promgraming和空白时间段Blank内各信号的时序，其中各信号 在高电位和低电位时的电压设置数值如表1中所示。
Figure PCTCN2020113573-appb-000001
表1
下面结合图8b和图8c对显示时间段和空白时间段内GOA电路的工作进行具体说明。
如图8b所示，显示时间段包括第一显示阶段S1、第二显示阶段S2、第三显示阶段S3、第四显示阶段S4和第五显示阶段S5。
在第一显示阶段S1，第n-2级级传信号Cout(n-2)升为高电位，第一晶体管T11与第二晶体管T12打开，第一节点Q被拉升为高电位，第二十四晶体管T52、第二十六晶体管T54、第十晶体管T23、第十一晶体管T22与第十二晶体管T21打开，由于第一节点Q与第三节点QB之间连接构成了反相器结构，它们之间的电位相反，因此，第三节点QB处于低电位，第二十七晶体管T43、第二十八晶体管T42、第二十九晶体管T41、第二十一晶体管T44与第二十二晶体管T45均关闭，同时，第n+2级级传信号Cout(n+2)处于低电位，第十六晶体管T31和第十七晶体管T32关闭，第二输入信号VST为低电位， 第十四晶体管T33与第十五晶体管T34关闭。第一时序信号CKa、第二时序信号CKb和第三时序信号CKc处于低电位，第n级级传信号信号Cout(n)、第一输出信号WR(n)和第二输出信号RD(n)输出低电位。由于第n-2级级传信号Cout(n-2)为高电位，第三晶体管T91打开，第一存储电容Cbt3的第一极板连接的P点被复位成低电位，第二极板连接的第二节点M同时为低电位。
在第二显示阶段S2，第一输入信号LSP升为高电位，此时第n-2级级传信号Cout(n-2)维持高电位，第二节点M被抬升至高电位，第四晶体管T92打开，P点维持低电位，由于复位信号Totaol-Rest和第二输入信号VST等信号为低电位，第一节点Q维持高电位，第三节点QB维持低电位。
在第三显示阶段S3，第一输入信号LSP由高电位降为低电位，第五晶体管T71及第六晶体管T72关闭，第n-2级级传信号Cout(n-2)由高电位变为低电位，因此第三晶体管T91关闭，P点电位由低电位切换为高电位，由于第一存储电容Cbt3的存在，第二节点M受到耦合作用，被抬升至更高电位。第一时序信号Cka、第二时序信号CKb和第三时序信号CKc由低电位变为高电位，因此第n级级传信号Cout(n)、第一输出信号WR(n)以及第二输出信号RD(n)的电位也被抬升至高电位，同时由于第二存储电容Cbt1及第三存储电容Cbt2的存在，第一节点Q被耦合至更高电位。
在第四显示阶段S4，第一时序信号Cka、第二时序信号CKb和第三时序信号CKc由高电位切换为低电位，第n级级传信号Cout(n)、第一输出信号WR(n)以及第二输出信号RD(n)的电位被拉至低电位，第一节点Q的信号耦合降低，与第二显示阶段S2时的电位一致。
在第五显示阶段S5，第n+2级级传信号Cout(n+2)由低电位升至高电位，第十六晶体管T31及第十七晶体管T32打开，第一节点Q的电位被拉低至低电位，第二十四晶体管T52、第二十六晶体管T54、第十晶体管T23、第十一晶体管T22与第十二晶体管T21关闭，第三节点QB的电位被抬升至高电位，第二十七晶体管T43、第二十八晶体管T42、第二十九晶体管T41、第二十一晶体管T44与第二十二晶体管T45均打开，第一节点Q、第n级级传信号Cout(n)、第一输出信号WR(n)以及第二输出信号RD(n)维持低电位。
如图8c所示，空白时间段包括第一空白阶段B1、第二空白阶段B2、第 三空白阶段B3和第四空白阶段B4。
在第一空白阶段B1，复位信号Total reset升为高电位，第九晶体管T82打开，第一节点Q的电位被拉至高电位，第二十四晶体管T52、第二十六晶体管T54、第十晶体管T23、第十一晶体管T22与第十二晶体管T21打开，由于第一节点Q与第三节点QB之间连接构成了反相器结构，它们之间的电位相反，因此，第三节点QB处于低电位，第二十七晶体管T43、第二十八晶体管T42、第二十九晶体管T41、第二十一晶体管T44与第二十二晶体管T45均关闭，同时，第n+2级级传信号Cout(n+2)处于低电位，第十六晶体管T31和第十七晶体管T32关闭，第二输入信号VST为低电位，第十四晶体管T33与第十五晶体管T34关闭。第一时序信号CKa、第二时序信号CKb和第三时序信号CKc处于低电位，第n级级传信号信号Cout(n)、第一输出信号WR(n)和第二输出信号RD(n)输出低电位。
在第二空白阶段B2，复位信号Toatal reset降为低电位，第九晶体管T82关闭，第一时序信号Cka维持低电位，第二时序信号CKb及第三时序信号CKc升为高电位，第n级级传信号信号Cout(n)维持低电位，第一输出信号WR(n)和第二输出信号RD(n)输出高电位。第一节点Q被耦合至更高电位。
在第三空白阶段B3，第二输入信号VST由低电位升为高电位，第十四晶体管T33与第十五晶体管T34打开，第一节点Q的电位被拉低至低电位，第二十四晶体管T52、第二十六晶体管T54、第十晶体管T23、第十一晶体管T22与第十二晶体管T21关闭，第三节点QB的电位被抬升至高电位，第二十七晶体管T43、第二十八晶体管T42、第二十九晶体管T41、第二十一晶体管T44与第二十二晶体管T45均打开，第一节点Q、第一输出信号WR(n)和第二输出信RD(n)拉低至低电位，第n级级传信号Cout(n)维持低电位。
在第四空白阶段B4，第一输入信号LSP升为高电位，第五晶体管T71及第六晶体管T72打开，由于第n-2级级传信号Cout(n-2)为低电位，第二节点M被复位为低电位，第八晶体管T81关闭。第一节点Q、第n级级传信号Cout(n)、第一输出信号WR(n)和第二输出信RD(n)维持低电位。
本申请实施例提供的GOA电路为实时补偿型GOA电路，通过上述过程，为扫描线提供驱动信号，以使显示面板显示画面。
在上述过程中，通过在第一存储电容Cbt3的第一极板侧设置第三晶体管T91和第四晶体管T92，在第一显示阶段S1，第三晶体管T91和第四晶体管T92均打开，使得P点和第二节点M电位为低电位，在第二显示阶段S2，第三晶体管T91和第四晶体管T92均打开，P点的电位维持低电位，第二节点M电位进行第一次拉高，在第三显示阶段S3，第三晶体管T91关闭，第四晶体管T92打开，将P点电位拉高，由于耦合作用，第二节点M的电位进行了第二次拉高。因此，在第一空白阶段B1，第一节点Q的电位相对于现有技术被拉至更高，充电率得到保证，进而使得GOA电路允许的阈值电压余量提升，提高了GOA电路的稳定性，降低了晶体管制程的开发难度。
在一种实施例中，针对支撑柱容易剥落技术问题，以POA(PS on Array，PS在阵列基板上)结构的显示面板为例，如图5所示，在与所述支撑柱54的接触区域内，所述阵列基板51的与所述支撑柱54接触的接触膜层511(即上文中的底层)形成有凸凹图案55，所述凸凹图案55用于增大所述接触膜层511与所述支撑柱54的接触面积。
在一种实施例中，凸凹图案包括所述接触膜层通过凸起、凹陷、或者凸起凹陷配合中的至少一个方式所形成的目标图案，例如下文实施例中接触膜层通过凹陷这一方式所形成的目标图案，在其他实施例中，所述接触膜层可以仅通过凸起方式或者凸起凹陷配合方式中的至少一个方式形成目标图案，凸起凹陷配合方式是指接触膜层通过凸起形成目标图案的一部分，通过凹陷形成目标图案的其他部分。
本实施例提供的显示面板增大了支撑柱与底层的接触面积，并且不需要改变单个子像素的尺寸，缓解了现有8K超高分辨率电子设备存在的支撑柱容易剥落的技术问题。
在一种实施例中，如图9所示，本申请实施例提供的凸凹图案55对应目标图案的形状为网格状。在一些实施例中，网格大小为1至6微米，间隔为1至6微米，深度小于0.5微米即可，通过掩模板对接触膜层(一般为有机材料层)进行光刻即可实现本实施例，如针对凸凹图案的设置区域，通过改变此处RGB/PFA掩模板的网格设计，使用透过率80％～90％的掩模板，降低透过率，部分光阻被显影液去除，达到膜厚降低0.5微米形成凸凹图案的需求。
在一种实施例中，驱动电路形成在第三侧边区域D3的范围内，凸凹图案形成在第三侧边区域D3的范围内，例如，凸凹图案形成在第三侧边区域D3内。对应的，掩模板在第三侧边区域C3内，形成有与凸凹图案的目标图案对应的遮光图形图案，遮光图形图案的光透过率为80％至90％，进而实现在黑色矩阵的对应区域内形成凹陷的目标图案作为凸凹图案。
在一种实施例中，显示面板为COA(Color Filter on Array，RGB在阵列基板上)结构以及非POA(PS on Array，PS在阵列基板上)结构时，支撑柱形成在彩膜基板上，彩膜基板包括衬底基板以及形成在所述衬底基板上的黑色矩阵，所述黑色矩阵围绕阵列排布且与子像素出光区对应的开口；所述支撑柱形成在所述黑色矩阵上，即黑色矩阵为上文中的接触膜层，所述黑色矩阵在与所述支撑柱的接触区域内形成有凸凹图案。
在一种实施例中，显示面板为非COA(Color Filter on Array，RGB在阵列基板上)结构以及非POA(PS on Array，PS在阵列基板上)结构时，支撑柱形成在彩膜基板上，彩膜基板包括衬底基板、形成在所述衬底基板上的黑色矩阵以及彩膜层，所述黑色矩阵围绕阵列排布且与子像素出光区对应的彩膜层；所述支撑柱形成在所述黑色矩阵上，即黑色矩阵为上文中的接触膜层，所述黑色矩阵在与所述支撑柱的接触区域内形成有凸凹图案。
在一种实施例中，显示面板为非COA(Color Filter on Array，RGB在阵列基板上)结构以及非POA(PS on Array，PS在阵列基板上)结构时，支撑柱形成在彩膜基板上，彩膜基板包括衬底基板、形成在所述衬底基板上的黑色矩阵、以及形成在所述黑色矩阵上的彩膜层；所述支撑柱形成在所述彩膜层上，且位于所述彩膜层与所述黑色矩阵重叠的区域内，即彩膜为上文中的接触膜层，所述彩膜层在与所述支撑柱的接触区域内形成有凸凹图案。
在一种实施例中，显示面板为非COA(Color Filter on Array，RGB在阵列基板上)结构以及非POA(PS on Array，PS在阵列基板上)结构时，支撑柱形成在彩膜基板上，彩膜基板包括衬底基板、形成在所述衬底基板上的黑色矩阵、以及形成在所述黑色矩阵上的彩膜层；所述支撑柱形成在所述彩膜层上，且位于所述彩膜层与所述黑色矩阵重叠的区域内，即彩膜层为上文中的接触膜层，所述彩膜层在与所述支撑柱的接触区域内形成有凸凹图案，所述黑 色矩阵在所述彩膜层与所述支撑柱的接触区域内，也形成有凸凹图案。
在一种实施例中，显示面板为非COA(Color Filter on Array，RGB在阵列基板上)结构以及POA(PS on Array，PS在阵列基板上)结构时，支撑柱形成在阵列基板上，阵列基板包括衬底基板、形成在所述衬底基板上的驱动电路层、以及形成在所述驱动电路层上的平坦化层；所述支撑柱形成在所述平坦化层上，即平坦化层为上文中的接触膜层，所述平坦化层在与所述支撑柱的接触区域内形成有凸凹图案。
在一种实施例中，显示面板为COA(Color Filter on Array，RGB在阵列基板上)结构以及POA(PS on Array，PS在阵列基板上)结构时，支撑柱形成在阵列基板上，阵列基板包括衬底基板、形成在所述衬底基板上的驱动电路层、形成在所述驱动电路层上的色阻层、以及形成在所述色阻层上的平坦化层；所述支撑柱形成在所述平坦化层上，即平坦化层为上文中的接触膜层，所述平坦化层在与所述支撑柱的接触区域内形成有凸凹图案。
在一种实施例中，显示面板为COA(Color Filter on Array，RGB在阵列基板上)结构以及POA(PS on Array，PS在阵列基板上)结构时，支撑柱形成在阵列基板上，阵列基板包括衬底基板、形成在所述衬底基板上的驱动电路层、形成在所述驱动电路层上的色阻层、以及形成在所述色阻层(RGB层)上的平坦化层；所述支撑柱形成在所述平坦化层上，即平坦化层为上文中的接触膜层，所述平坦化层在与所述支撑柱的接触区域内形成有凸凹图案，所述色阻层在所述平坦化层与所述支撑柱的接触区域内，也形成有凸凹图案。
在一种实施例中，平坦化层的材料为PFA(大分子有机透明材料)，平坦化层的厚度为1.5微米左右，黑色矩阵、彩膜层以及色阻层的厚度为2至3微米，那么基于该厚度值，形成凸凹图案之后，并不会影响膜层的原有功能。
在一种实施例中，支撑柱包括主支撑柱(Main ps)和辅支撑柱(Sub ps)，接触膜层在接触主支撑柱和辅支撑柱的区域，可以形成参数(包括大小、形状以及深度等)相同的凸凹图案，也可以形成参数(包括大小、形状以及深度等)不相同的凸凹图案，例如接触膜层在接触主支撑柱处形成的凸凹图案15的深度，大于在接触辅支撑柱处形成的凸凹图案的深度。
本申请还提供一种电子设备，包括上述任一实施例提供的显示面板。
在一种实施例中，所述电子设备包括显示面板，所述显示面板包括相对设置的彩膜基板和阵列基板，所述彩膜基板包括：
衬底基板；
形成在所述衬底基板上的黑色矩阵，所述黑色矩阵包括用于填充彩膜层的开口；
形成在所述开口内的彩膜层；
其中，所述彩膜基板包括多个阵列排布、且与子像素对应的像素区域，所述像素区域包括所述开口对应的第一区域、以及围绕所述第一区域的第二区域，所述第二区域形成有所述黑色矩阵；所述第二区域包括行方向排列且平行的第一侧边区域和第二侧边区域、以及列方向排列且平行的第三侧边区域和第四侧边区域；所述第一侧边区域远离所述开口的侧边到所述开口的第五距离，小于所述第二侧边区域远离所述开口的侧边到所述开口的第六距离。
在一种实施例中，所述电子设备包括显示面板，所述显示面板包括：
列方向排布的m个GOA单元，所述GOA单元包括上拉模块，所述上拉模块包括连接时钟信号的时钟输入晶体管；
列方向延伸且平行设置的n个时钟信号线；
行方向延伸且平行设置的m个时钟信号连接线，所述时钟信号连接线与所述GOA单元一一对应，用于将所述GOA单元内上拉模块的时钟输入晶体管连接至对应的时钟信号线；
其中，n个所述时钟信号线包括第n1个时钟信号线和第n2个时钟信号线，所述第n2个时钟信号线形成在所述第n1个时钟信号线远离所述GOA单元的一侧，连接所述第n1个时钟信号线的第m1个GOA单元内上拉模块的时钟输入晶体管的压降值，大于连接所述第n2个时钟信号线的第m2个GOA单元内上拉模块的时钟输入晶体管的压降值。
在一种实施例中，在本申请的电子设备中，所述第m1个GOA单元内的上拉模块的时钟输入晶体管的尺寸，大于所述第m2个GOA单元内的上拉模块的时钟输入晶体管的尺寸。
在一种实施例中，在本申请的电子设备中，所述时钟输入晶体管包括阵列连接的多个子晶体管，所述第m1个GOA单元内的上拉模块的时钟输入晶体管 的子晶体管的数量大于所述第m2个GOA单元内的上拉模块的时钟输入晶体管的子晶体管的数量。
在一种实施例中，在本申请的电子设备中，所述第m1个GOA单元内的上拉模块的时钟输入晶体管的源极面积大于所述第m2个GOA单元内的上拉模块的时钟输入晶体管的源极面积；和/或，所述第m1个GOA单元内的上拉模块的时钟输入晶体管的漏极面积大于所述第m2个GOA单元内上拉模块的时钟输入晶体管的漏极面积。
在一种实施例中，在本申请的电子设备中，所述第m1个GOA单元内的上拉模块的时钟输入晶体管的源极与有源层的接触面积小于所述第m2个GOA单元内的上拉模块的时钟输入晶体管的源极与有源层的接触面积。
在一种实施例中，在本申请的电子设备中，第n级GOA单元包括：
上拉控制模块，与第一节点连接，用于在显示时间段将所述第一节点的电位拉高；
逻辑寻址模块，包括第二节点，所述逻辑寻址模块与所述第一节点连接，用于在所述显示时间段，对所述第二节点电位进行两次拉高，在空白时间段，通过所述第二节点将所述第一节点的电位拉高；
上拉模块，与所述第一节点连接，用于将第n级级传信号、第一输出信号和第二输出信号的电位拉高；
第一下拉模块，与所述第一节点连接，用于在空白时间段将所述第一节点的电位拉低；
第二下拉模块，与所述第一节点和第三节点连接，用于在显示时间段分别将所述第一节点和所述第三节点的电位拉低；
第三下拉模块，与所述第三节点和所述第二下拉模块连接，用于在空白时间段将所述第三节点的电位拉低；
第一下拉维持模块，包括所述第三节点，所述第一下拉维持模块与所述第一节点和所述第一下拉模块连接，用于维持所述第一节点的低电位；
第二下拉维持模块，与所述第三节点和所述上拉模块连接，用于维持所述第n级级传信号、所述第一输出信号和所述第二输出信号的低电位。
在一种实施例中，在本申请的电子设备中，所述上拉控制模块包括第一晶 体管和第二晶体管，所述第一晶体管的栅极和第一电极、以及所述第二晶体管的栅极均连接第n-2级级传信号，所述第一晶体管的第二电极连接所述第二晶体管的第一电极和第四节点，所述第二晶体管的第二电极连接所述第一节点。
在一种实施例中，在本申请的电子设备中，所述第m1个GOA单元内的上拉模块的时钟输入晶体管的源漏极层材料电阻率大于所述第m2个GOA单元内上拉模块的时钟输入晶体管的源漏极层材料电阻率。
在一种实施例中，在本申请的电子设备中，所述第m1个GOA单元内的上拉模块的时钟输入晶体管的源漏极层厚度小于所述第m2个GOA单元内的上拉模块的时钟输入晶体管的源漏极层厚度。
在一种实施例中，在本申请的电子设备中，所述第m1个GOA单元内的上拉模块的时钟输入晶体管的漏极与有源层的接触面积小于所述第m2个GOA单元内的上拉模块的时钟输入晶体管的漏极与有源层的接触面积。
根据上述实施例可知：
本申请提供一种掩模板、显示面板以及电子设备，该掩模板包括掩模板基板，开口图形图案，形成于所述掩模板基板上，用于形成所述彩膜基板的黑色矩阵或者彩膜层，所述黑色矩阵包括用于填充彩膜层的开口；其中，所述掩模板包括多个重复区域，所述重复区域包括所述开口图形图案对应的第一区域、以及围绕所述第一区域的第二区域；所述第二区域包括行方向排列且平行的第一侧边区域和第二侧边区域、以及列方向排列且平行的第三侧边区域和第四侧边区域；所述第一侧边区域远离所述开口图形图案的侧边到所述开口图形图案的第一距离，小于所述第二侧边区域远离所述开口图形图案的侧边到所述开口图形图案的第二距离。该掩模板放弃现有掩模板开口图形图案，如遮光区等位于重复区域中心的设计，将其向侧边移动，这样就可以基于衍射效应得到目标尺寸的黑色矩阵开口或者彩膜层，同时不需要改变开口图形图案的尺寸，基于该结构相同分辨率不同尺寸的显示面板可以使用相同尺寸的掩模板，这些掩模板的区别仅仅是开口图形图案与重复区域边缘的距离不同，解决了现有8K电子设备至少存在需要针对不同尺寸显示面板制备不同尺寸掩模板的技术问题，降低了产品制备成本。
以上对本申请实施例所提供的一种掩模板、显示面板以及电子设备进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (20)

  1. 一种掩模板，用于制备彩膜基板，其包括：
    掩模板基板；
    开口图形图案，形成于所述掩模板基板上；
    其中，所述掩模板包括多个重复区域，所述重复区域包括所述开口图形图案对应的第一区域、以及围绕所述第一区域的第二区域；所述第二区域包括行方向排列且平行的第一侧边区域和第二侧边区域、以及列方向排列且平行的第三侧边区域和第四侧边区域；所述第一侧边区域远离所述开口图形图案的侧边到所述开口图形图案的第一距离，小于所述第二侧边区域远离所述开口图形图案的侧边到所述开口图形图案的第二距离。
  2. 如权利要求1所述的掩模板，其中，所述第三侧边区域远离所述开口图形图案的侧边到所述开口图形图案的第三距离，等于所述第四侧边区域远离所述开口图形图案的侧边到所述开口图形图案的第四距离。
  3. 如权利要求1所述的掩模板，其中，所述第一距离的值小于12微米，所述第二距离的值大于32微米。
  4. 如权利要求1所述的掩模板，其中，所述第一距离的值小于10微米，所述第二距离的值大于34微米。
  5. 如权利要求1所述的掩模板，其中，在所述行方向上，所述开口图形图案的宽度值为28微米。
  6. 如权利要求5所述的掩模板，其中，所述第一距离与所述第二距离的和为44微米。
  7. 一种显示面板，其包括相对设置的彩膜基板和阵列基板，所述彩膜基板包括：
    衬底基板；
    形成在所述衬底基板上的黑色矩阵，所述黑色矩阵包括用于填充彩膜层的开口；
    形成在所述开口内的彩膜层；
    其中，所述彩膜基板包括多个阵列排布、且与子像素对应的像素区域，所述像素区域包括所述开口对应的第一区域、以及围绕所述第一区域的第二区 域，所述第二区域形成有所述黑色矩阵；所述第二区域包括行方向排列且平行的第一侧边区域和第二侧边区域、以及列方向排列且平行的第三侧边区域和第四侧边区域；所述第一侧边区域远离所述开口的侧边到所述开口的第五距离，小于所述第二侧边区域远离所述开口的侧边到所述开口的第六距离。
  8. 如权利要求7所述的显示面板，其中，在所述行方向上，所述第五距离的值小于18微米，所述第六距离的值大于18微米。
  9. 如权利要求7所述的显示面板，其中，在所述行方向上，所述开口的宽度值为16微米，所述第五距离与所述第六距离的和为56微米。
  10. 一种电子设备，其包括显示面板，所述显示面板包括相对设置的彩膜基板和阵列基板，所述彩膜基板包括：
    衬底基板；
    形成在所述衬底基板上的黑色矩阵，所述黑色矩阵包括用于填充彩膜层的开口；
    形成在所述开口内的彩膜层；
    其中，所述彩膜基板包括多个阵列排布、且与子像素对应的像素区域，所述像素区域包括所述开口对应的第一区域、以及围绕所述第一区域的第二区域，所述第二区域形成有所述黑色矩阵；所述第二区域包括行方向排列且平行的第一侧边区域和第二侧边区域、以及列方向排列且平行的第三侧边区域和第四侧边区域；所述第一侧边区域远离所述开口的侧边到所述开口的第五距离，小于所述第二侧边区域远离所述开口的侧边到所述开口的第六距离。
  11. 如权利要求10所述的电子设备，其中，所述显示面板包括：
    列方向排布的m个GOA单元，所述GOA单元包括上拉模块，所述上拉模块包括连接时钟信号的时钟输入晶体管；
    列方向延伸且平行设置的n个时钟信号线；
    行方向延伸且平行设置的m个时钟信号连接线，所述时钟信号连接线与所述GOA单元一一对应，用于将所述GOA单元内上拉模块的时钟输入晶体管连接至对应的时钟信号线；
    其中，n个所述时钟信号线包括第n1个时钟信号线和第n2个时钟信号线，所述第n2个时钟信号线形成在所述第n1个时钟信号线远离所述GOA单元的 一侧，连接所述第n1个时钟信号线的第m1个GOA单元内上拉模块的时钟输入晶体管的压降值，大于连接所述第n2个时钟信号线的第m2个GOA单元内上拉模块的时钟输入晶体管的压降值。
  12. 如权利要求11所述的电子设备，其中，所述第m1个GOA单元内的上拉模块的时钟输入晶体管的尺寸，大于所述第m2个GOA单元内的上拉模块的时钟输入晶体管的尺寸。
  13. 如权利要求12所述的电子设备，其中，所述时钟输入晶体管包括阵列连接的多个子晶体管，所述第m1个GOA单元内的上拉模块的时钟输入晶体管的子晶体管的数量大于所述第m2个GOA单元内的上拉模块的时钟输入晶体管的子晶体管的数量。
  14. 如权利要求12所述的电子设备，其中，所述第m1个GOA单元内的上拉模块的时钟输入晶体管的源极面积大于所述第m2个GOA单元内的上拉模块的时钟输入晶体管的源极面积；和/或，所述第m1个GOA单元内的上拉模块的时钟输入晶体管的漏极面积大于所述第m2个GOA单元内上拉模块的时钟输入晶体管的漏极面积。
  15. 如权利要求12所述的电子设备，其中，所述第m1个GOA单元内的上拉模块的时钟输入晶体管的源极与有源层的接触面积小于所述第m2个GOA单元内的上拉模块的时钟输入晶体管的源极与有源层的接触面积。
  16. 如权利要求11所述的电子设备，其中，第n级GOA单元包括：
    上拉控制模块，与第一节点连接，用于在显示时间段将所述第一节点的电位拉高；
    逻辑寻址模块，包括第二节点，所述逻辑寻址模块与所述第一节点连接，用于在所述显示时间段，对所述第二节点电位进行两次拉高，在空白时间段，通过所述第二节点将所述第一节点的电位拉高；
    上拉模块，与所述第一节点连接，用于将第n级级传信号、第一输出信号和第二输出信号的电位拉高；
    第一下拉模块，与所述第一节点连接，用于在空白时间段将所述第一节点的电位拉低；
    第二下拉模块，与所述第一节点和第三节点连接，用于在显示时间段分别 将所述第一节点和所述第三节点的电位拉低；
    第三下拉模块，与所述第三节点和所述第二下拉模块连接，用于在空白时间段将所述第三节点的电位拉低；
    第一下拉维持模块，包括所述第三节点，所述第一下拉维持模块与所述第一节点和所述第一下拉模块连接，用于维持所述第一节点的低电位；
    第二下拉维持模块，与所述第三节点和所述上拉模块连接，用于维持所述第n级级传信号、所述第一输出信号和所述第二输出信号的低电位。
  17. 如权利要求16所述的电子设备，其中，所述上拉控制模块包括第一晶体管和第二晶体管，所述第一晶体管的栅极和第一电极、以及所述第二晶体管的栅极均连接第n-2级级传信号，所述第一晶体管的第二电极连接所述第二晶体管的第一电极和第四节点，所述第二晶体管的第二电极连接所述第一节点。
  18. 如权利要求11所述的电子设备，其中，所述第m1个GOA单元内的上拉模块的时钟输入晶体管的源漏极层材料电阻率大于所述第m2个GOA单元内上拉模块的时钟输入晶体管的源漏极层材料电阻率。
  19. 如权利要求11所述的电子设备，其中，所述第m1个GOA单元内的上拉模块的时钟输入晶体管的源漏极层厚度小于所述第m2个GOA单元内的上拉模块的时钟输入晶体管的源漏极层厚度。
  20. 如权利要求12所述的电子设备，其中，所述第m1个GOA单元内的上拉模块的时钟输入晶体管的漏极与有源层的接触面积小于所述第m2个GOA单元内的上拉模块的时钟输入晶体管的漏极与有源层的接触面积。
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CN111091775A (zh) * 2020-03-22 2020-05-01 深圳市华星光电半导体显示技术有限公司 一种显示面板以及电子设备
CN111090195A (zh) * 2020-03-22 2020-05-01 深圳市华星光电半导体显示技术有限公司 一种显示面板以及电子设备
CN111090190A (zh) * 2020-03-22 2020-05-01 深圳市华星光电半导体显示技术有限公司 一种掩模板、显示面板以及电子设备

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