WO2021189300A1 - 存储芯片堆叠封装及电子设备 - Google Patents

存储芯片堆叠封装及电子设备 Download PDF

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Publication number
WO2021189300A1
WO2021189300A1 PCT/CN2020/081132 CN2020081132W WO2021189300A1 WO 2021189300 A1 WO2021189300 A1 WO 2021189300A1 CN 2020081132 W CN2020081132 W CN 2020081132W WO 2021189300 A1 WO2021189300 A1 WO 2021189300A1
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Prior art keywords
memory chip
substrate
memory
chip
stack package
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PCT/CN2020/081132
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English (en)
French (fr)
Inventor
焦慧芳
赫然
栗炜
刘静遐
李檀
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华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP20927593.2A priority Critical patent/EP4123695A4/en
Priority to PCT/CN2020/081132 priority patent/WO2021189300A1/zh
Priority to CN202080094663.8A priority patent/CN115004355A/zh
Publication of WO2021189300A1 publication Critical patent/WO2021189300A1/zh

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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Definitions

  • This application relates to the field of semiconductor technology, and in particular to a memory chip stack package and electronic equipment.
  • DRAM dynamic random access memory
  • I/O input/output
  • some DRAM chip stacking packages are stacked with large areas of DRAM chips, and the contacts of the chip are combined with through silicon vias through micro-bumps.
  • TSV is connected to the substrate; in some DRAM chip stack packages, additional redistribution layer (RDL) is added to rewire the contacts in the center of the chip to both ends; these settings will cause the cost of the chip stack package Increase.
  • RDL redistribution layer
  • the present application provides a memory chip stack package and an electronic device.
  • the memory chip stack package can avoid the use of micro-bumps combined with through silicon vias (TSV) or the use of increased weight on the basis that the area meets the requirements.
  • TSV through silicon vias
  • RDL wiring layer
  • the embodiment of the present application provides a memory chip stack package, which includes a substrate and a multilayer memory chip stacked on the substrate in turn;
  • the multilayer memory chip includes: a first memory chip and a first memory chip arranged in parallel on a first layer Two memory chips, the third memory chip and the fourth memory chip arranged side by side on the second layer, and the fifth memory chip on the third layer; the active surfaces of the first memory chip and the second memory chip Toward the upper surface of the substrate, the passive surfaces of the third memory chip and the fourth memory chip are attached to the passive surfaces of the first memory chip and the second memory chip, respectively; the first memory chip The contacts on the active surfaces of the chip and the second memory chip are connected to the substrate; the contacts on the active surfaces of the third memory chip and the fourth memory chip are connected to the leads of the substrate;
  • the passive surface of the fifth memory chip overlaps the active surfaces of the third memory chip and the fourth memory chip, and the contacts on the active surface of the fifth memory chip are connected to the lead wires of the substrate .
  • the memory chip stack package includes at least five memory chips stacked in multiple layers in sequence, wherein the two memory chips arranged on the first layer face down and are directly connected to the substrate (for example, through bumps and the substrate).
  • the upper surface of the substrate is connected, or connected to the lower surface of the substrate through a window on the substrate); the non-active surfaces of the two chips on the second layer are attached to the upper surfaces of the two memory chips on the first layer, respectively.
  • the surface is connected with the lead of the substrate (for example, it can be connected with the upper surface of the substrate); the non-active surface of a memory chip of the third layer is lapped on the two memory chips of the second layer, and the active surface is connected with the lead of the substrate.
  • the memory chip stack package of the present application on the basis of ensuring that the area of the package structure meets the requirements, the use of micro-bump combined with TSV or RDL connection technology is avoided, and the interconnection between the five memory chips and the substrate can be realized. , Thereby greatly reducing the manufacturing cost of the memory chip stack package.
  • the substrate is provided with a first window connecting the upper surface and the lower surface of the substrate at a position corresponding to the first memory chip, and the substrate is located at a position corresponding to the second memory chip.
  • the position is provided with a second window connecting the upper surface and the lower surface of the substrate; the contacts on the active surface of the first memory chip are connected to the lower surface of the first substrate through the first window, The contacts on the active surface of the second memory chip are connected with the lower surface of the first substrate through the second window to effectively reduce the manufacturing cost of the package structure.
  • the contacts on the active surfaces of the third memory chip and the fourth memory chip are connected to the upper surface of the substrate by leads; in order to effectively reduce the manufacturing cost of the package structure.
  • the active surface of the fifth memory chip faces the side away from the substrate, and the contacts on the active surface of the fifth memory chip are connected to the upper surface of the substrate by leads. . That is, the active surface of the memory chip arranged on the third layer faces upwards and is connected to the upper surface of the substrate by lead; the lead connection between all the memory chips in the package structure and the substrate is ensured, so as to reduce the manufacturing cost.
  • the active surface of the fifth storage chip faces the upper surface of the substrate; There are third windows on the upper and lower surfaces of the substrate; the orthographic projections of the third memory chip and the fourth memory chip on the substrate do not overlap with the third window; the fifth The contacts on the active surface of the memory chip are connected with the lower surface of the substrate through the third window. That is, the active surface of the memory chip arranged on the third layer is facing down, and it is connected to the bottom surface of the substrate through the window on the substrate; the lead connection between all the memory chips in the package structure and the substrate is ensured to reduce Production costs.
  • the multi-layer memory chip further includes a sixth memory chip located on the fourth layer; the active surface of the sixth memory chip faces a side away from the substrate, and the sixth memory chip
  • the contacts on the active surface of the memory chip are connected to the upper surface of the substrate by leads. That is, on the basis of the active surface of the memory chip arranged on the third layer facing down and the lead connection with the lower surface of the substrate through the window on the substrate, the sixth memory chip on the fourth layer is arranged and connected to the upper surface of the substrate.
  • Surface lead connection guarantees the lead connection between all memory chips and the substrate in the package structure to reduce manufacturing costs.
  • the orthographic projections of the third memory chip and the first memory chip on the substrate overlap, and the fourth memory chip and the second memory chip are on the substrate.
  • the orthographic projections coincide; to reduce the area of the package structure.
  • the orthographic projections of the sixth memory chip and the fifth memory chip on the substrate overlap, so as to avoid the subsequent lead connection of the sixth memory chip to other memory chips in the lower layer. Unnecessary occlusion.
  • all memory chips in the memory chip stack package have the same specifications, and the contact of each memory chip is located on the central axis of the active surface.
  • all memory chips in the memory chip stack package are DRAM chips.
  • the multi-layer memory chips sequentially stacked on the substrate form a memory module, and the first memory chip and the second memory chip in the memory module are arranged side by side along a first direction;
  • the chip stack package includes two memory modules arranged side by side along a second direction; the second direction is perpendicular to the first direction.
  • the entire packaging structure can be made close to a square shape, ensuring that the stress in the first direction and the second direction is relatively balanced when the packaging structure is installed, thus The risk of warpage of the package structure is reduced.
  • it is equivalent to packaging two RANKs in one packaging structure, thereby improving the integration of the packaging structure.
  • a groove structure is provided on the upper surface of the substrate, and all memory chips located in the first layer are arranged in the groove structure; in order to reduce the thickness of the entire package structure.
  • four of the first storage chip, the second storage chip, the third storage chip, the fourth storage chip, and the fifth storage chip are used to provide parallel Read and write access function, the remaining one is used to store ECC to realize error correction function.
  • An embodiment of the present application also provides an electronic device including a CPU and a memory chip stack package in any one of the foregoing possible implementation modes; the memory chip stack package is connected to the CPU.
  • the bit width of the CPU is 64 bits
  • the first storage chip, the second storage chip, the third storage chip, the fourth storage chip, and the fifth storage chip Four of the memory chips are used to provide 16-bit parallel read and write access functions, and the remaining one is used to save ECC for error correction; thus ensuring that even if there is a data error, the ECC will automatically correct it so that the electronic device can continue to be normal Work will not be interrupted by errors.
  • the sixth memory chip in the memory chip stack package is used to implement the chipkill function; thus, the memory chip can be used to replace the failed memory core to solve the error correction method that cannot be covered by the ECC.
  • FIG. 1 is a schematic structural diagram of a memory chip provided by an embodiment of the application.
  • FIG. 2 is a schematic diagram of a planar structure of a memory chip stack package provided by an embodiment of the application;
  • FIG. 3 is a schematic diagram of a side structure of a memory chip stack package provided by an embodiment of the application.
  • FIG. 4 is a schematic diagram of a side structure of a memory chip stack package provided by an embodiment of the application.
  • FIG. 5 is a schematic diagram of a side structure of a memory chip stack package provided by an embodiment of the application.
  • FIG. 6 is a schematic diagram of a side structure of a memory chip stack package provided by an embodiment of the application.
  • FIG. 7 is a schematic diagram of a planar structure of a memory chip stack package provided by an embodiment of the application.
  • FIG. 8 is a schematic diagram of a side structure of a memory chip stack package provided by an embodiment of the application.
  • FIG. 9 is a schematic diagram of a side structure of a memory chip stack package provided by an embodiment of the application.
  • An embodiment of the application provides an electronic device, which may be an electronic product such as a server, a computer, a portable android device (Pad), a notebook, and a vehicle-mounted computer.
  • the embodiment of the application does not impose special restrictions on the specific form of the electronic device.
  • the electronic device includes a printed circuit board (PCB), and a memory chip stack package and a CPU arranged on the PCB; the memory chip stack package and the CPU are electrically connected through the PCB to realize interconnection transmission.
  • the memory chip stack package can be soldered on a pad of the PCB through a connection structure (such as a solder ball) provided at the bottom.
  • the memory chip stack package provided by the embodiment of the application includes at least five memory chips, which can avoid the use of micro-bumps, TSVs, and TSVs on the basis of ensuring that the area of the package structure meets the requirements. Technologies such as redistribution layer (RDL) cause high cost problems.
  • RDL redistribution layer
  • all memory chips in the memory chip stack package are the same.
  • all memory chips may be DRAM chips.
  • the above-mentioned DRAM chip may adopt a DDR SDRAM (double data rate synchronous dynamic random access memory) chip, referred to as DDR; for example, DDR4, DDR5, and so on.
  • DDR double data rate synchronous dynamic random access memory
  • DDR4 double data rate synchronous dynamic random access memory
  • DDR5 double data rate synchronous dynamic random access memory
  • ECC Error Correction Code
  • the current common CPU bit width is 64 bits
  • 4 DDRs with a bit width of 16 bits are a RANK (also called a memory block; that is, a DRAM chipset that the CPU can access at the same time, or in other words, the CPU must follow this
  • the fifth DRAM chip is required to store ECC (error correction code) in order to realize the function of error checking and correction.
  • ECC error correction code
  • the memory chip stack package provided by the embodiment of the present application includes at least 5 memory chips, which can well meet the normal data transmission from the CPU to the DRAM chip, and while improving the performance of the storage system, it further realizes the miniaturization of the storage system. change.
  • the active surface of the memory chip can also be referred to as the front side, The non-active face can be called the back face.
  • the active surface of the chip is provided with contacts (that is, conductive terminals, pads), and the chip is electrically connected to the substrate through the pads.
  • contacts that is, conductive terminals, pads
  • a plurality of contacts p are provided at the central axis of the active surface.
  • an embodiment of the present application provides a memory chip stack package, which includes a substrate 1 and five memory chips stacked on the substrate 1 in sequence.
  • the five memory chips are the first memory chip 10, the second memory chip 20, the third memory chip 30, the fourth memory chip 40, and the fifth memory chip 50, and the five memory chips (10, 20, 30, 40, 50) Distributed in three layers, and five memory chips (10, 20, 30, 40, 50) are respectively provided with contacts on the active surface.
  • Figure 2 is just to illustrate the relative position of the multi-layer chips clearly, and the chips are schematically shown in a staggered manner. For the actual relative positional relationship of each layer of chips in the horizontal direction, please refer to Figure 3 and the text below. Description part.
  • the first memory chip 10 and the second memory chip 20 are arranged side by side on the upper surface of the substrate 1 along the first direction AA', that is, the first memory chip 10 and the second memory chip 20 are stacked in sequence.
  • the first layer in a multi-layer memory chip.
  • the first memory chip 10 and the second memory chip 20 may be directly attached to the upper surface of the substrate 1 through an attach film F.
  • the first direction AA' can be perpendicular to the central axis of the memory chip (refer to Figure 2).
  • the active surfaces of the first memory chip 10 and the second memory chip 20 face the side of the substrate 1; that is, the active surfaces of the first memory chip 10 and the second memory chip 20 face down, and the non-active Face up.
  • the contacts on the active surfaces of the first memory chip 10 and the second memory chip 20 are connected to the substrate 1.
  • first memory chip 10 and the second memory chip 20 are located on the upper surface of the substrate 1, and the active surfaces of the first memory chip 10 and the second memory chip 20 face the substrate 1, the first memory chip 10.
  • connection method between the second memory chip 20 and the substrate 1 there is no need to adopt TSV or RDL, etc., and it is sufficient to use a conventional ordinary connection method (such as lead connection, bump connection).
  • the substrate 1 is provided with a first window 11 connecting the upper surface and the lower surface of the substrate 1 at positions corresponding to the first memory chip 10 and the second memory chip 20, respectively.
  • the second window 12 that is, the substrate 1 is provided with hollow areas at positions corresponding to the first memory chip 10 and the second memory chip 20, respectively.
  • the contacts on the active surface of the first memory chip 10 are wire bonded to the lower surface of the substrate 1 through the first window 11, and the contacts on the active surface of the second memory chip 20 are connected to the bottom surface of the substrate 1 through the second window 12.
  • the bottom surface of the substrate 1 is connected by wires; that is, the first memory chip 10 and the second memory chip 20 located on the first layer are connected to the substrate 1 in a flip chip window wire bonding manner.
  • first window 11 should be located as far as possible directly under the contacts of the first memory chip 10 to ensure that the leads of the first memory chip 10 are connected to the substrate 1; the second window 12 should be as close as possible It is located directly below the contacts of the second storage chip 20 to ensure that the second storage chip 20 is connected to the lead of the substrate 1.
  • the contacts on the active surfaces of the first memory chip 10 and the second memory chip 20 are directly connected to the upper surface of the substrate 1 through bumps B (bump). connect.
  • the third memory chip 30 and the fourth memory chip 40 are located in the second layer of the stacked multi-layer memory chips, the third memory chip 30 is stacked and attached to the first memory chip 10, and the fourth memory chip is The chip 40 is stacked and attached to the second memory chip 20.
  • the third memory chip 30 and the fourth memory chip 40 are also arranged side by side in the first direction AA'.
  • the non-active surface of the third memory chip 30 can be attached to the upper surface of the first memory chip 10 through the adhesive layer F
  • the non-active surface of the fourth memory chip 40 can be pasted through the adhesive layer F.
  • the attachment layer F is attached to the upper surface of the second memory chip 20.
  • the active surfaces of the third storage chip 30 and the fourth storage chip 40 face the side away from the substrate 1; that is, the active surfaces of the third storage chip 30 and the fourth storage chip 40 face upwards, and the non-active surfaces face downwards.
  • the contacts on the active surfaces of the third memory chip 30 and the fourth memory chip 40 are connected to the substrate 1 by leads.
  • the contacts on the active surface of the third memory chip 30 are connected to the upper surface of the substrate 1 by leads, and the contacts on the active surface of the fourth memory chip 40 are connected to The upper surface of the substrate 1 is connected by wires.
  • the upper surface of the substrate 1 may be provided with pads on the edge regions located on both sides along the first direction, so as to ensure the third storage chip 30 and the fourth storage chip 40 The contacts are respectively connected to the pad leads on both sides.
  • interleaving arrangement of the leads of the third memory chip 30 and the fourth memory chip 40 in FIG. 3 and subsequent figures is only a schematic representation of the spatial interleaving of the leads, and the leads do not directly contact each other.
  • the contacts on the active surfaces of the third memory chip 30 and the fourth memory chip 40 may be connected to the lower surface of the substrate 1 by leads through windows located at the edges of both sides of the substrate 1.
  • the fifth memory chip 50 is located on the third layer among the stacked multi-layer chips, and the active surface of the fifth memory chip 50 faces the side away from the substrate 1; that is, the fifth memory chip 50 has The source side is facing up, and the non-active side is facing down.
  • the passive surface of the fifth memory chip 50 overlaps the active surfaces of the third memory chip 30 and the fourth memory chip 40, and the contacts of the active surface of the fifth memory chip 50 are connected to the upper surface of the substrate 1 by leads.
  • the fifth storage chip 50 should not cover the contacts on the active surfaces of the third storage chip 30 and the fourth storage chip 40;
  • the fifth storage chip 50 may be located in the area between the contacts on the active surfaces of the third storage chip 30 and the fourth storage chip 40, that is, the fifth storage chip 50 and the third storage chip 30 and the third storage chip 30 The areas between the contacts of the four memory chips 40 overlap.
  • the fifth storage chip 50 may be attached to the upper surface of the area between the contacts of the third storage chip 30 and the fourth storage chip 40 through the adhesive layer F.
  • the gap between the first memory chip 10 and the second memory chip 20 can be reduced as much as possible if the process conditions permit.
  • the edges of the third storage chip 30 may be flush with the edges of the first storage chip 10, and the edges of the fourth storage chip 40 are flush with the edges of the second storage chip 20; that is, The third memory chip 30 overlaps the orthographic projection of the first memory chip 10 on the substrate 1, and the fourth memory chip 40 overlaps the orthographic projection of the second memory chip 20 on the substrate 1.
  • the memory chip stack package provided by this embodiment stacks five memory chips in three layers, and the two memory chips in the first layer are arranged with their active faces facing down and are directly connected to the substrate (for example, through bumps).
  • the point is connected to the upper surface of the substrate, or connected to the lower surface of the substrate through a window on the substrate); the non-active surfaces of the two chips on the second layer are attached to the upper surfaces of the two memory chips on the first layer, respectively ,
  • the active surface is connected to the lead of the substrate (for example, it can be connected to the upper surface of the substrate); the non-active surface of a memory chip in the third layer is overlapped on the two memory chips in the second layer, and the active surface is connected to the substrate The upper surface of the lead connection.
  • the memory chip stack package of the present application on the basis of ensuring that the area of the package structure meets the requirements, the use of micro-bump combined with TSV or RDL and other connection technologies can be avoided, and one of the five memory chips and the substrate can be achieved.
  • the interconnection between the memory chips greatly reduces the manufacturing cost of the memory chip stack package.
  • the difference between the memory chip stack package provided in this embodiment and the memory chip stack package in the first embodiment is:
  • the substrate 1 is provided with a third window 13 connecting the upper surface and the lower surface of the substrate 1 in the area corresponding to the first storage chip 10 and the second storage chip 20, and at the same time, the third storage chip 30 and the fourth storage chip 40 should be ensured. It does not extend above the third window 13, that is, the orthographic projections of the third memory chip 30 and the fourth memory chip 40 on the substrate 1 and the third window 13 do not overlap.
  • the active surface of the fifth memory chip 50 located on the third layer faces the side of the substrate 1, that is, the active surface of the fifth memory chip 50 faces downward, and the non-active surface faces upward.
  • the contacts on the active surface of the fifth memory chip 50 are lead-connected to the lower surface of the substrate 1 through the third window 13. It is understandable that, in this case, it should be ensured as far as possible that the third window 13 is located directly below the contacts of the fifth storage chip 50 to ensure that the fifth storage chip 50 is connected to the lead of the substrate 1.
  • the memory chip stack package provided by this embodiment stacks five memory chips in three layers, and the two memory chips on the first layer are arranged with their active faces facing down and are directly connected to the substrate (for example, through bumps and the upper part of the substrate).
  • the substrate lead connection (for example, it can be connected to the upper surface of the substrate); the non-active surface of a memory chip of the third layer is arranged to overlap between the two memory chips of the second layer, and the active surface is located on the substrate
  • the window is connected to the bottom surface of the substrate.
  • the memory chip stack package of this embodiment on the basis of ensuring that the area of the package structure meets the requirements, the use of micro-bump combined with TSV or RDL and other connection technologies can be avoided, and five memory chips and substrates can be realized. Therefore, the manufacturing cost of the memory chip stack package is greatly reduced.
  • the gap between the first memory chip 10 and the second memory chip 20 must meet the requirements of the lead between the fifth memory chip 50 and the lower surface of the substrate 1. On the basis of the connection process, it should be reduced as much as possible.
  • a longer lead is required to connect to the pads on the edge regions on both sides of the upper surface of the substrate 1.
  • a shorter lead can be used to connect to the lower surface of the substrate 1 directly below through the third window 13, thereby effectively increasing the frequency of the transmission signal.
  • the settings of the first memory chip 10, the second memory chip 20, the third memory chip 30, and the fourth memory chip 40, etc. please refer to the first embodiment.
  • the difference between the memory chip stack package provided in this embodiment and the memory chip stack package in the second embodiment is:
  • the memory chip stack package further includes a sixth memory chip 60 on the fourth layer.
  • the active surface of the sixth memory chip 60 faces the side away from the substrate 1, that is, the active surface of the sixth memory chip 60 faces upward. The active side is facing down.
  • the contacts on the active surface of the sixth memory chip 60 are lead-connected to the upper surface of the substrate 1.
  • the sixth memory chip 60 may be adhered to the upper surface of the fifth memory chip 50 through the adhesive layer F.
  • the edge of the sixth memory chip 60 and the fifth memory chip 50 can be arranged.
  • the edges of is flush, that is, the orthographic projections of the sixth memory chip 60 and the fifth memory chip 50 on the substrate 1 coincide.
  • the memory chip stack package provided by this embodiment stacks six memory chips on four layers, and the two memory chips on the first layer are arranged with their active faces facing down and are directly connected to the substrate (for example, through bumps and the upper part of the substrate).
  • the substrate lead connection (for example, it can be connected to the upper surface of the substrate); the non-active surface of a memory chip on the third layer faces the area between the contacts of the two memory chips on the second layer, there is
  • the source surface is connected to the bottom surface of the substrate through a window located on the substrate; the non-active surface of the memory chip on the fourth layer is attached to the upper surface of the memory chip on the third layer, and the active surface is connected to the upper surface of the substrate Lead connection.
  • the memory chip stack package of this embodiment on the basis of ensuring that the area of the package structure meets the requirements, avoiding the use of micro-bump combined with TSV or RDL and other connection technologies, six memory chips and substrates can be realized. Therefore, the manufacturing cost of the memory chip stack package is greatly reduced.
  • the settings of the first memory chip 10, the second memory chip 20, the third memory chip 30, and the fourth memory chip 40 can be referred to in the first embodiment.
  • the related description of the fifth memory chip 50 and the substrate 1 please refer to the related description in the second embodiment above, which will not be repeated here.
  • the internal includes five memory chips, and the four memory chips form a RANK to provide parallel read and write access functions; the other memory chip can be used to store
  • the error correction code ie ECC
  • ECC error correction code
  • the memory chip is used as an ECC memory chip.
  • the package structure of the third embodiment it includes six memory chips inside, and the four memory chips form a RANK to provide parallel read and write access functions; one memory chip can be used to store error correction codes to achieve error correction functions ; Another memory chip can be used in place of a failed chip. When any other memory chip fails, it can be replaced to solve the error correction method that cannot be covered by ECC, that is, to realize the chipkill function.
  • the memory chip stack package includes five 16-bit memory chips (such as DDR chips), five memory chips can be used.
  • the two memory chips provide 16-bit parallel read and write access functions, and the other is used to save ECC for error correction.
  • the bit and the first memory chip 10 of the first layer are And the second memory chip 20 are arranged side by side in the first direction AA'.
  • the entire package structure is elongated (for example, the size of the package structure in some embodiments is about 17.2mm ⁇ 9.5mm), so that The packaging structure receives unbalanced stress in the first direction AA′ and the second direction perpendicular to the first direction during installation, which may easily cause the risk of warpage of the entire packaging structure.
  • the multi-layer memory chips sequentially stacked on the substrate 1 in the foregoing embodiment are defined as a memory module.
  • Two storage modules: the first storage module U1 and the second storage module U2 are arranged side by side in the second vertical direction AA′.
  • the entire packaging structure can be made close to a square (for example, the size of the packaging structure in some embodiments is about 20mm ⁇ 20mm), ensuring Therefore, the stresses in the first direction and the second direction of the package structure are relatively balanced during installation, thereby reducing the risk of warpage of the package structure.
  • the size of the packaging structure in some embodiments is about 20mm ⁇ 20mm
  • the settings of the storage chips in the first storage module U1 and the second storage module U2 may be completely the same.
  • the storage chips in the first storage module U1 and the second storage module U2 may adopt the arrangement of five storage chips in the first embodiment.
  • the settings of the storage chips in the first storage module U1 and the second storage module U2 may not be completely the same.
  • the first storage module U1 may adopt the configuration of five storage chips in the first embodiment
  • the second storage module U2 may adopt the configuration of six storage chips in the third embodiment.
  • a groove structure may be provided on the upper surface of the substrate 1 S, the memory chips (such as 10, 20) located in the first layer are arranged in the groove structure S; that is, the memory chips located in the first layer are embedded in the substrate 1.
  • the method of embedding the memory chip of the first layer in the substrate 1 can be selected according to the thickness of the memory chip of the first layer and the substrate 1.
  • the memory chips of the first layer may be partially embedded in the substrate 1, that is, the depth of the groove structure S on the substrate 1 is less than that of the first layer.
  • the thickness of the memory chip of one layer, and the part of the memory chip of the first layer is exposed in the groove structure S.
  • the memory chips (such as 10 and 20) of the first layer are all embedded in the substrate 1, and the upper surface of the memory chips of the first layer and the substrate 1 The upper surface of is substantially flush, that is, the depth of the groove structure S on the substrate 1 is substantially the same as the thickness of the memory chip of the first layer.
  • the memory chip of the first layer may be a DRAM chip of about 100 ⁇ m, and the memory chip of the first layer is completely embedded in the substrate 1.
  • its thickness is equivalent to reducing the thickness of a layer of memory chip.
  • the thickness is equivalent to the thickness of two layers of memory chips stacked on the substrate 1, and at the same time, the lead between the uppermost memory chip and the substrate can be reduced. length.

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Abstract

本申请提供一种存储芯片堆叠封装及电子设备，能够避免因采用micro-bump结合TSV或者采用RDL等技术造成制作成本高的问题。该存储芯片堆叠封装包括基板以及依次堆叠在基板上的多层存储芯片；多层存储芯片包括：位于第一层的第一、第二存储芯片，位于第二层的第三、第四存储芯片，以及位于第三层的第五存储芯片；基板在对应第一存储芯片和第二存储芯片的位置设置有第一、第二窗口；第一存储芯片和第二存储芯片与基板直接连接；第三存储芯片和第四存储芯片与基板的引线连接；第五存储芯片搭接在第三存储芯片和第四存储芯片上；第五存储芯片与基板引线连接。

Description

存储芯片堆叠封装及电子设备 技术领域
本申请涉及半导体技术领域，尤其涉及一种存储芯片堆叠封装及电子设备。
背景技术
随着高性能计算机和便携式电子装置的发展，需要在尽可能小的电路板面积内集成更多的芯片，芯片更紧凑的物理布置方法因此也得到了发展。多芯片堆叠封装的方法可以有效节省电路板面积，成为现在很多便携式装置中存储芯片封装的主流模式。例如在智能手机中，将多颗共用I/O(input/output，输入/输出)口的动态随机存储(dynamic random access memory，DRAM)芯片堆叠后封装在一起，再布置于印制电路板上，通过共用I/O口与手机中央处理器(central processing unit，CPU)互联，构成高速的微处理-存储系统。
在保证DRAM芯片堆叠封装面积满足需求的前提下，一些DRAM芯片堆叠封装中，通过设置DRAM芯片大面积重合堆叠，芯片的触点通过微凸点(micro-bump)结合硅通孔(through silicon via，TSV)连接到基板；一些DRAM芯片堆叠封装中，通过额外增加重布线层(redistribution layer，RDL)，将芯片中心的触点重新布线至两端；这些设置方式均会导致芯片堆叠封装的成本增加。
发明内容
本申请提供一种存储芯片堆叠封装及电子设备，该存储芯片堆叠封装在面积满足需求的基础上，能够避免因采用微凸点(micro-bump)结合硅通孔(TSV)、或者采用增加重布线层(RDL)等造成制作成本高的问题。
本申请实施例提供一种存储芯片堆叠封装，包括基板以及依次堆叠在所述基板上的多层存储芯片；所述多层存储芯片包括：位于第一层、并列设置的第一存储芯片和第二存储芯片，位于第二层、并列设置的第三存储芯片和第四存储芯片，以及位于第三层的第五存储芯片；所述第一存储芯片和所述第二存储芯片的有源面朝向所述基板的上表面，所述第三存储芯片和所述第四存储芯片的无源面分别贴在所述第一存储芯片和第二存储芯片的无源面上；所述第一存储芯片和所述第二存储芯片的有源面上的触点与所述基板连接；所述第三存储芯片和所述第四存储芯片的有源面上的触点与所述基板引线连接；所述第五存储芯片的无源面搭接在所述第三存储芯片和第四存储芯片的有源面上，所述第五存储芯片的有源面上的触点与所述基板引线连接。
该存储芯片堆叠封装中，包括依次堆叠在多层的至少五个存储芯片，其中，设置在第一层的两个存储芯片有源面朝下，与基板直接连接(例如，通过凸点与基板的上表面连接，或者通过基板上的窗口与基板的下表面连接)；设置第二层的两个芯片的非有源面分别贴附在第一层的两个存储芯片的上表面，有源面与基板引线连接(例如可以与基板的上表面引线连接)；设置第三层的一个存储芯片非有源面搭接在第二层的两个存储芯片上，有源面与基板引线连接。采用本申请的存储芯片堆叠封装，在保证封装结构的面积满足需求的基础上，避免了采用micro-bump结合TSV或者采用RDL等连接技术，即可实现五个存储芯片与基板之间的互连，从而大幅降低了存储芯片堆叠 封装的制作成本。
在一些可能实现的方式中，所述基板在对应所述第一存储芯片的位置设置有连通所述基板的上表面和下表面的第一窗口，所述基板在对应所述第二存储芯片的位置设置有连通所述基板的上表面和下表面的第二窗口；所述第一存储芯片的有源面上的触点通过所述第一窗口与所述第一基板的下表面引线连接，所述第二存储芯片的有源面上的触点通过所述第二窗口与所述第一基板的下表面引线连接；以有效降低封装结构的制作成本。
在一些可能实现的方式中，所述第三存储芯片和所述第四存储芯片的有源面上的触点与所述基板的上表面引线连接；以有效降低封装结构的制作成本。
在一些可能实现的方式中，所述第五存储芯片的有源面朝向背离所述基板的一侧，所述第五存储芯片的有源面上的触点与所述基板的上表面引线连接。也即，设置在第三层的存储芯片的有源面朝上，与基板的上表面引线连接；保证了封装结构中的所有存储芯片与基板之间的引线连接，以降低制作成本。
在一些可能实现的方式中，所述第五存储芯片的有源面朝向所述基板的上表面；所述基板在对应所述第一存储芯片和所述第二存储芯片之间的区域设置连通所述基板的上表面和下表面的有第三窗口；所述第三存储芯片、所述第四存储芯片在所述基板上的正投影与所述第三窗口不交叠；所述第五存储芯片的有源面上的触点通过所述第三窗口与所述基板的下表面引线连接。也即，设置在第三层的存储芯片的有源面朝下，通过基板上的窗口与基板的下表面引线连接；保证了封装结构中的所有存储芯片与基板之间的引线连接，以降低制作成本。
在一些可能实现的方式中，所述多层存储芯片还包括位于第四层的第六存储芯片；所述第六存储芯片的有源面朝向背离所述基板的一侧，且所述第六存储芯片的有源面上的触点与所述基板的上表面引线连接。也即，设置在第三层的存储芯片的有源面朝下，通过基板上的窗口与基板的下表面引线连接的基础上，设置位于第四层的第六存储芯片，并与基板的上表面引线连接；保证了封装结构中的所有存储芯片与基板之间的引线连接，以降低制作成本。
在一些可能实现的方式中，所述第三存储芯片与所述第一存储芯片在所述基板上的正投影重合，所述第四存储芯片与所述第二存储芯片在所述基板上的正投影重合；以减小封装结构的面积。
在一些可能实现的方式中，所述第六存储芯片与所述第五存储芯片在所述基板上的正投影重合，以避免第六存储芯片对下层的其他存储芯片在后续引线连接时，造成不必要的遮挡。
在一些可能实现的方式中，所述存储芯片堆叠封装中的所有存储芯片的规格相同，且每一存储芯片的触点位于有源面的中轴线上。
在一些可能实现的方式中，所述存储芯片堆叠封装中的所有存储芯片均为DRAM芯片。
在一些可能实现的方式中，所述依次堆叠在基板上的多层存储芯片形成一个存储模块，所述存储模块中的第一存储芯片和第二存储芯片沿第一方向并列设置；所述存储芯片堆叠封装包括沿第二方向并列设置的两个所述存储模块；所述第二方向与所述 第一方向垂直。
在此情况下，一方面，通过在封装结构中设置两个存储模块，能够使得整个封装结构接近正方形，保证封装结构在安装时第一方向和第二方向上的应力相对比较均衡，从而也就降低了封装结构出现翘曲的风险。另一方面，通过在封装结构中设置两个存储模块，相当于在一个封装结构中封装2个RANK，从而提高了封装结构的集成度。
在一些可能实现的方式中，所述基板的上表面设置有凹槽结构，位于第一层的所有存储芯片设置于所述凹槽结构中；以降低整个封装结构的厚度。
在一些可能实现的方式中，所述第一存储芯片、所述第二存储芯片、所述第三存储芯片、所述第四存储芯片和所述第五存储芯片中的四个用于提供并行的读写访问功能，剩余一个用于存放ECC实现纠错功能。
本申请实施例还提供一种电子设备，包括CPU以及如前述任一种可能实现的方式中的存储芯片堆叠封装；所述存储芯片堆叠封装与所述CPU连接。
在一些可能实现的方式中，所述CPU的位宽为64位，所述第一存储芯片、所述第二存储芯片、所述第三存储芯片、所述第四存储芯片、所述第五存储芯片中的四个分别用于提供16位的并行读写访问功能，剩余一个用于保存ECC实现纠错功能；从而保证即使有数据出现错误，ECC会自动进行改正，使得电子设备可以继续正常工作，不会因错误而中断。
在一些可能实现的方式中，所述存储芯片堆叠封装中的第六存储芯片用于实现chipkill功能；从而能够通过该存储芯片代替失效的存储芯，以解决ECC不能覆盖的纠错方法。
附图说明
图1为本申请实施例提供的一种存储芯片的结构示意图；
图2为本申请实施例提供的一种存储芯片堆叠封装的平面结构示意图；
图3为本申请实施例提供的一种存储芯片堆叠封装的侧面结构示意图；
图4为本申请实施例提供的一种存储芯片堆叠封装的侧面结构示意图；
图5为本申请实施例提供的一种存储芯片堆叠封装的侧面结构示意图；
图6为本申请实施例提供的一种存储芯片堆叠封装的侧面结构示意图；
图7为本申请实施例提供的一种存储芯片堆叠封装的平面结构示意图；
图8为本申请实施例提供的一种存储芯片堆叠封装的侧面结构示意图；
图9为本申请实施例提供的一种存储芯片堆叠封装的侧面结构示意图。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚，下面将结合本申请中的附图，对本申请中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请的说明书实施例和权利要求书及附图中的术语“第一”、“第二”等仅用于区 分描述的目的，而不能理解为指示或暗示相对重要性，也不能理解为指示或暗示顺序。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元。“上”、“下”、“水平”以及“竖直”等仅用于相对于附图中的部件的方位而言的，这些方向性术语是相对的概念，它们用于相对于的描述和澄清，其可以根据附图中的部件所放置的方位的变化而相应地发生变化。
本申请实施例提供一种电子设备，该电子设备可以为服务器、电脑、平板电脑(portable android device，Pad)、笔记本、车载电脑等电子产品。本申请实施例对该电子设备的具体形式不做特殊限制。
该电子设备包括印制电路板(printed circuit board，PCB)，以及设置在PCB上的存储芯片堆叠封装和CPU；该存储芯片堆叠封装与CPU通过PCB电连接，实现互连传输。示意的，存储芯片堆叠封装可以通过底部设置的连接结构(例如焊球)焊接在PCB的焊盘(pad)上。
本申请实施例提供的存储芯片堆叠封装中包括至少五颗存储芯片，能够在保证封装结构的面积满足需求的基础上，避免因采用微凸点(micro-bump)、硅通孔(TSV)、重布线层(redistribution layer，RDL)等技术造成成本高的问题。
在一些实施例中，该存储芯片堆叠封装中所有存储芯片的规格相同。示意的，所有的存储芯片可以均为DRAM芯片。
在一些可能实现的方式中，上述DRAM芯片可以采用DDR SDRAM(double data rate synchronous dynamic random access memory，双倍速率同步动态随机存储器)芯片，简称DDR；例如DDR4、DDR5等。以下实施例均是以存储芯片为DDR为例进行说明的。
本领域的技术人员可以理解到，随着存储单元(bit)面积的不断缩小，存储单元的容限(margin)也在不断减小，目前DRAM芯片的主流加工工艺为25nm/20nm/18nm等工艺节点，DRAM芯片中出现越来越多的弱存储单元，从而导致电子设备在工作过程中，由于温度应力、电应力等不可避免地出现存储信号跳变(bit跳变)，并且由于DRAM芯片的容量从8Gb演进到16Gb，软失效引起的存储信号跳变风险也在增加，因此，在高速应用的存储系统中必须增加纠错码(error correcting code，ECC)，才能保障存储系统的安全运行。应当理解的是，ECC是一种纠错技术，通过在数据中增添附加位来检测和改正数据操作中的错误。内存错误是引起系统故障的最主要原因之一，ECC技术能够容许内存运行中的错误，即使有数据出现错误，ECC会自动纠正这些错误，使得系统可以继续正常工作，不会因错误而中断。在将数据写入到ECC内存时，与写入数据相对应的纠错码会被存储在ECC内存的附加位中。读取数据时，内存控制器会将存储的纠错码与读取数据时生成的纠错码进行比较。如果读取的代码与存储的代码不匹配，可以根据纠错码确定出哪个位出错，然后立即纠正该位。
另外，目前常见的CPU位宽是64位，4个位宽为16位的DDR为一个RANK(也可以称为内存区块；即CPU能够同时访问的DRAM芯片组，或者说，CPU必须按这样的芯片组进行访问)，在此情况下，需要第5个(颗)DRAM芯片存放ECC(纠错码)，才能实现错误检查和纠正的功能。也就是说，需要采用至少包括5个DRAM芯片的存储封装结构。基于此，本申请实施例提供的存储芯片堆叠封装包括至少5个存 储芯片，能够很好的满足CPU到DRAM芯片的正常数据传输，并在提高存储系统的性能的同时，进一步实现存储系统的小型化。
此外，还可以理解的是，对于存储芯片本身而言，具有相对设置的有源面和非有源面(也可以称为无源面)；也可以将存储芯片的有源面称为正面，非有源面可以称为背面。其中，在芯片的有源面设置有触点(也即导电端子、pad)，芯片通过pad与基板之间电气连接。示意的，如图1中示出的芯片，在有源面的中轴线位置设置有多个触点p，以下实施例中涉及的存储芯片均是以此规格为例进行说明的。
以下通过具体实施例对本申请提供的存储芯片堆叠封装做进一步的说明。
实施例一
如图2和图3(图2的侧面示意图)所示，本申请实施例提供一种存储芯片堆叠封装，包括基板1以及依次堆叠在基板1的五个存储芯片。五个存储芯片分别为第一存储芯片10、第二存储芯片20、第三存储芯片30、第四存储芯片40、第五存储芯片50，且五个存储芯片(10、20、30、40、50)分布在三层，并且五个存储芯片(10、20、30、40、50)在有源面分别设置有触点。图2中仅是为了清楚对多层芯片的层间相对位置进行示意，将芯片示意的采用错位的方式示出，对于各层芯片在水平方向的实际相对位置关系可以参考图3以及下文的文字描述部分。
如图3所示，第一存储芯片10和第二存储芯片20沿第一方向AA’并列设置于基板1的上表面，也即，第一存储芯片10和第二存储芯片20位于依次堆叠的多层存储芯片中的第一层。在一些可能实现的方式中，可以将第一存储芯片10和第二存储芯片20通过粘附层(attach film)F直接贴附在基板1的上表面。
此处需要说明的是，在本实施例中的存储芯片均采用图1中示出的触点位于中轴线上的DRAM芯片的情况下，对于前述第一方向AA’而言，该第一方向AA’可以与存储芯片的中轴线垂直(参考图2)。
如图3所示，第一存储芯片10和第二存储芯片20的有源面朝向基板1一侧；也即第一存储芯片10和第二存储芯片20的有源面朝下，非有源面朝上。其中，第一存储芯片10和第二存储芯片20的有源面上的触点与基板1连接。
可以理解的是，由于第一存储芯片10和第二存储芯片20位于基板1的上表面，且第一存储芯片10和第二存储芯片20的有源面朝向基板1，因此对于第一存储芯片10、第二存储芯片20与基板1的连接方式而言，无需采用TSV或者RDL等，通过常规的普通连接方式(例如引线连接、凸点连接)即可。
例如，在一些可能实现的方式中，如图3所示，基板1在对应第一存储芯片10和第二存储芯片20的位置分别设置有连通基板1的上表面和下表面的第一窗口11和第二窗口12；也即基板1在对应第一存储芯片10和第二存储芯片20的位置分别设置镂空区。第一存储芯片10的有源面上的触点通过第一窗口11与基板1的下表面引线连接(wire bonding)，第二存储芯片20的有源面上的触点通过第二窗口12与基板1的下表面引线连接；也即位于第一层的第一存储芯片10和第二存储芯片20采用倒装芯片引线连接(flip chip window wire bonding)的方式与基板1连接。
此处可以理解的是，第一窗口11应尽可能的位于第一存储芯片10的触点的正下方，以保证第一存储芯片10与基板1的引线连接；第二窗口12应尽可能的位于第二 存储芯片20的触点的正下方，以保证第二存储芯片20与基板1的引线连接。
又例如，在一些可能实现的方式中，如图4所示，第一存储芯片10和第二存储芯片20的有源面上的触点直接与基板1的上表面通过凸点B(bump)连接。
如图3所示，第三存储芯片30和第四存储芯片40位于依次堆叠的多层存储芯片中的第二层，第三存储芯片30堆叠贴附在第一存储芯片10上，第四存储芯片40堆叠贴附在第二存储芯片20上。当然，在此情况下，第三存储芯片30和第四存储芯片40同样在第一方向AA’上并列设置。在一些可能实现的方式中，可以将第三存储芯片30的非有源面通过粘附层F贴附在第一存储芯片10的上表面，将第四存储芯片40的非有源面通过粘附层F贴附在第二存储芯片20的上表面。
第三存储芯片30和第四存储芯片40的有源面朝向背离基板1的一侧；也即第三存储芯片30和第四存储芯片40的有源面朝上，非有源面朝下。第三存储芯片30、第四存储芯片40的有源面上的触点与基板1引线连接。
如图3所示，在一些可能实现的方式中，第三存储芯片30的有源面上的触点与基板1的上表面引线连接，第四存储芯片40的有源面上的触点与基板1的上表面引线连接。示意的，参考图2和图3所示，基板1的上表面可以在位于沿第一方向上两侧的边缘区域设置焊盘(pad)，从而保证第三存储芯片30和第四存储芯片40的触点分别与两侧的焊盘引线连接。
需要说明的是，图3以及后续附图中关于第三存储芯片30和第四存储芯片40的引线交错设置，仅是示意的表示引线在空间上的交错，引线间并不直接接触。
在一些可能实现的方式中，第三存储芯片30、第四存储芯片40的有源面上的触点可以通过位于基板1两侧边缘的窗口与基板1的下表面引线连接。
如图3所示，第五存储芯片50位于依次堆叠的多层芯片中的第三层，第五存储芯片50的有源面朝向背离基板1的一侧；也即第五存储芯片50的有源面朝上，非有源面朝下。该第五存储芯片50的无源面搭接在第三存储芯片30和第四存储芯片40的有源面上，第五存储芯片50有源面的触点与基板1的上表面引线连接。
当然，为了保证第三存储芯片30和第四存储芯片40与基板1的引线连接，第五存储芯片50不应覆盖第三存储芯片30和第四存储芯片40的有源面上的触点；示意的，可以设置第五存储芯片50位于第三存储芯片30和第四存储芯片40的有源面上的触点之间的区域，也即第五存储芯片50与第三存储芯片30和第四存储芯片40的触点之间的区域交叠。在一些可能实现的方式中，可以将第五存储芯片50通过粘附层F贴附在第三存储芯片30和第四存储芯片40的触点之间区域的上表面。
可以理解的是，为了尽可能的减小封装结构的面积，在工艺条件允许的情况下，可以尽量的减小第一存储芯片10和第二存储芯片20之间的间隙。并且在一些可能实现的方式中，还可以设置第三存储芯片30的边缘与第一存储芯片10的边缘平齐，第四存储芯片40的边缘与第二存储芯片20的边缘平齐；也即第三存储芯片30与第一存储芯片10在基板1上的正投影重合，第四存储芯片40与第二存储芯片20在基板1上的正投影重合。
综上所述，本实施例提供的存储芯片堆叠封装将五个存储芯片堆叠在三层，通过设置第一层的两个存储芯片有源面朝下，并与基板直接连接(例如，通过凸点与基板 的上表面连接，或者通过基板上的窗口与基板的下表面连接)；设置第二层的两个芯片的非有源面分别贴附在第一层的两个存储芯片的上表面，有源面与基板引线连接(例如可以与基板的上表面引线连接)；设置第三层的一个存储芯片非有源面搭接在第二层的两个存储芯片上，有源面与基板的上表面引线连接。也就是说，采用本申请的存储芯片堆叠封装，在保证封装结构的面积满足需求的基础上，避免了采用micro-bump结合TSV或者采用RDL等连接技术，即可实现五个存储芯片与基板之间的互连，从而大幅降低了存储芯片堆叠封装的制作成本。
实施例二
如图5所示，本实施例提供的存储芯片堆叠封装与实施例一的存储芯片堆叠封装的区别在于：
基板1在对应第一存储芯片10和第二存储芯片20之间的区域设置有连通基板1的上表面和下表面的第三窗口13，同时应保证第三存储芯片30、第四存储芯片40并不会延伸至第三窗口13的上方，也即第三存储芯片30、第四存储芯片40在基板1上的正投影与第三窗口13不交叠。
位于第三层的第五存储芯片50的有源面朝向基板1的一侧，也即第五存储芯片50的有源面朝下，非有源面朝上。第五存储芯片50的有源面上的触点通过第三窗口13与基板1的下表面引线连接。可以理解的是，在此情况下，应尽可能的保证第三窗口13位于第五存储芯片50的触点的正下方，以保证第五存储芯片50与基板1的引线连接。
本实施例提供的存储芯片堆叠封装将五个存储芯片堆叠在三层，通过设置第一层的两个存储芯片有源面朝下，并与基板直接连接(例如，通过凸点与基板的上表面连接，或者通过基板上的窗口与基板的下表面连接)；设置第二层的两个芯片的非有源面分别贴附在第一层的两个存储芯片的上表面，有源面与基板引线连接(例如可以与基板的上表面引线连接)；设置第三层的一个存储芯片的非有源面朝搭接在第二层的两个存储芯片之间，有源面通过位于基板上的窗口与基板的下表面引线连接。也就是说，采用本实施例的存储芯片堆叠封装，在保证封装结构的面积满足需求的基础上，避免了采用micro-bump结合TSV或者采用RDL等连接技术，即可实现五个存储芯片与基板之间的互连，从而大幅降低了存储芯片堆叠封装的制作成本。
需要说明的是，在该实施例二中，为了减小封装结构的，第一存储芯片10和第二存储芯片20之间的间隙，在满足第五存储芯片50与基板1的下表面的引线连接工艺的基础上，应尽可能的减小。
另外，需要说明的是，相比于实施例一中第五存储芯片50的有源面朝上，从而需要较长的引线与位于基板1的上表面两侧的边缘区域的焊盘连接，本实施例二中，通过设置第五存储芯片50的有源面朝下，能够采用较短的引线通过第三窗口13与基板1位于正下方的下表面连接，从而能够有效的提升传输信号的频率。
对于该实施例的存储芯片堆叠封装中的其他相关设置，例如，第一存储芯片10、第二存储芯片20、第三存储芯片30、第四存储芯片40的设置等，可以参考前述实施例一中的相关描述，此处不再赘述。
实施例三
如图6所示，本实施例提供的存储芯片堆叠封装与实施例二的存储芯片堆叠封装的区别在于：
该存储芯片堆叠封装还包括位于第四层的第六存储芯片60，第六存储芯片60的有源面朝向背离基板1的一侧，也即第六存储芯片60的有源面朝向上，非有源面朝下。第六存储芯片60的有源面上的触点与基板1的上表面引线连接。
在一些可能实现的方式中，如图6所示，可以将第六存储芯片60通过粘附层F粘附在第五存储芯片50的上表面。
当然，为了尽可能的避免第六存储芯片60对下层的其他存储芯片(30、40)在后续引线连接时，造成不必要的遮挡，可以设置第六存储芯片60的边缘与第五存储芯片50的边缘平齐，也即第六存储芯片60与第五存储芯片50在基板1上的正投影重合。
本实施例提供的存储芯片堆叠封装将六个存储芯片堆叠在四层，通过设置第一层的两个存储芯片有源面朝下，并与基板直接连接(例如，通过凸点与基板的上表面连接，或者通过基板上的窗口与基板的下表面连接)；设置第二层的两个芯片的非有源面分别贴附在第一层的两个存储芯片的上表面，有源面与基板引线连接(例如，可以与基板的上表面引线连接)；设置第三层的一个存储芯片的非有源面朝搭接在第二层的两个存储芯片的触点之间的区域，有源面通过位于基板上的窗口与基板的下表面引线连接；设置位于第四层的存储芯片的非有源面贴附在第三层的存储芯片的上表面，有源面与基板的上表面引线连接。也就是说，采用本实施例的存储芯片堆叠封装，在保证封装结构的面积满足需求的基础上，避免了采用micro-bump结合TSV或者采用RDL等连接技术，即可实现六个存储芯片与基板之间的互连，从而大幅降低了存储芯片堆叠封装的制作成本。
对于该实施例的存储芯片堆叠封装中的其他相关设置，例如，第一存储芯片10、第二存储芯片20、第三存储芯片30、第四存储芯片40的设置，可以参考前述实施例一中的相关描述，对于第五存储芯片50以及基板1的设置，可以参考前述实施例二中的相关描述，此处不再赘述。
基于此，对于前述实施例一和实施例二封装结构而言，其内部包括五个存储芯片中，四个存储芯片形成一个RANK，提供并行的读写访问功能；另一个存储芯片可以用来存放纠错码(即ECC)实现纠错功能，也即该存储芯片作为ECC存储芯片。对于实施例三的封装结构而言，其内部包括六颗存储芯片中，四个存储芯片形成一个RANK，提供并行的读写访问功能；一个存储芯片可以用来存放纠错码，实现纠错功能；另一个存储芯片可以代替失效芯片用，在其他任一存储芯片失效时对其进行替代，来解决ECC不能覆盖的纠错方法，也即实现chipkill功能。
示意的，在一些可能实现的方式中，针对电子设备中采用位宽为64位的CPU，存储芯片堆叠封装中包括五个采用16位的存储芯片(例如DDR芯片)的情况下，可以通过五个存储芯片中的四个分别提供16位的并行读写访问功能，另外一个用于保存ECC实现纠错功能。
对于前述任一种可能实现的方式(包括实施例一、实施例二、实施例三)中提供的存储芯片堆叠封装而言，参考图1所示，位与第一层的第一存储芯片10和第二存 储芯片20在第一方向AA’上并列设置，在此情况下，整个封装结构呈长条形(例如，一些实施例中封装结构的尺寸约为17.2mm×9.5mm)，从而使得封装结构在安装时第一方向AA’和垂直第一方向的第二方向上受到的应力不均衡，进而容易造成整个封装结构出现翘曲的风险。
基于此，将前述实施例中依次堆叠在基板1上的多层存储芯片定义为一个存储模块，如图7所示，本申请实施例还提供一种存储芯片堆叠封装，包括在与第一方向AA’垂直的第二方向上并列设置两个存储模块：第一存储模块U1和第二存储模块U2。
在此情况下，一方面，通过在封装结构中设置两个存储模块(U1、U2)，能够使得整个封装结构接近正方形(例如在一些实施例中封装结构的尺寸约为20mm×20mm)，保证了封装结构在安装时第一方向和第二方向上的应力相对比较均衡，从而也就降低了封装结构出现翘曲的风险。另一方面，通过在封装结构中设置两个存储模块(U1、U2)，相当于在一个封装结构中封装2个RANK，从而提高了封装结构的集成度。
另外，对于上述位于封装结构中的第一存储模块U1和第二存储模块U2而言：
在一些可能实现的方式中，第一存储模块U1和第二存储模块U2中存储芯片的设置可以完全相同。例如，第一存储模块U1和第二存储模块U2中存储芯片可以采用实施例一中的五个存储芯片的设置方式。
在一些可能实现的方式中，第一存储模块U1和第二存储模块U2中存储芯片的设置可以不完全相同。例如，第一存储模块U1可以采用实施例一中的五个存储芯片的设置方式，第二存储模块U2可以采用实施例三中六个存储芯片的设置方式。
另外，对于前述任一种可能实现的方式中提供的存储芯片堆叠封装而言，为了降低整个封装结构的厚度，并且降低位于上层(第三层、第四层)的存储芯片与基板之间的互连引线的长度，降低传输信号的延迟，保证高频信号的完整性；在一些可能实现的实施例中，参考图8、图9所示，可以在基板1的上表面设置有凹槽结构S，将位于第一层的存储芯片(例如10、20)设置于凹槽结构S中；也即位于第一层的存储芯片嵌入至基板1中。
需要说明的是，本申请中对于第一层的存储芯片嵌入至基板1中的深度不作具体限制。实际中可以根据第一层的存储芯片以及基板1的厚度，选择设置第一层的存储芯片在基板1中的嵌入方式。
例如，在一些可能实现的方式中，参考图8所示，第一层的存储芯片(例如10、20)可以部分嵌入至基板1中，也即基板1上的凹槽结构S的深度小于第一层的存储芯片的厚度，第一层的存储芯片的部分露出于凹槽结构S。
又例如，在另一些可能实现的方式中，参考图9所示，第一层的存储芯片(例如10、20)全部嵌入至基板1中，且第一层的存储芯片的上表面与基板1的上表面基本平齐，也即基板1上的凹槽结构S的深度与第一层的存储芯片的厚度基本相同。
示意的，在一些实施例中，第一层的存储芯片可以采用100μm左右的DRAM芯片，并且第一层的存储芯片完全嵌入至基板1中。在此情况下，对于整个封装结构而言，其厚度相当于减少了一层存储芯片的厚度。例如，对于实施例一和实施例二的存 储芯片堆叠封装而言，其厚度相当于在基板1上堆叠了两层存储芯片的厚度，同时能够减小最上层的存储芯片与基板之间的引线长度。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (15)

  1. 一种存储芯片堆叠封装，其特征在于，包括基板以及依次堆叠在所述基板上的多层存储芯片；
    所述多层存储芯片包括：位于第一层、并列设置的第一存储芯片和第二存储芯片，位于第二层、并列设置的第三存储芯片和第四存储芯片，以及位于第三层的第五存储芯片；
    所述第一存储芯片和所述第二存储芯片的有源面朝向所述基板的上表面，所述第三存储芯片和所述第四存储芯片的无源面分别贴在所述第一存储芯片和第二存储芯片的无源面上；
    所述第一存储芯片和所述第二存储芯片的有源面上的触点与所述基板连接；
    所述第三存储芯片和所述第四存储芯片的有源面上的触点与所述基板引线连接；
    所述第五存储芯片的无源面搭接在所述第三存储芯片和第四存储芯片的有源面上，所述第五存储芯片的有源面上的触点与所述基板引线连接。
  2. 根据权利要求1所述的存储芯片堆叠封装，其特征在于，
    所述基板在对应所述第一存储芯片的位置设置有连通所述基板的上表面和下表面的第一窗口，所述基板在对应所述第二存储芯片的位置设置有连通所述基板的上表面和下表面的第二窗口；
    所述第一存储芯片的有源面上的触点通过所述第一窗口与所述第一基板的下表面引线连接，所述第二存储芯片的有源面上的触点通过所述第二窗口与所述第一基板的下表面引线连接。
  3. 根据权利要求1或2所述的存储芯片堆叠封装，其特征在于，
    所述第三存储芯片和所述第四存储芯片的有源面上的触点与所述基板的上表面引线连接。
  4. 根据权利要求1-3任一项所述的存储芯片堆叠封装，其特征在于，所述第五存储芯片的有源面朝向背离所述基板的一侧，所述第五存储芯片的有源面上的触点与所述基板的上表面引线连接。
  5. 根据权利要求1-3任一项所述的存储芯片堆叠封装，其特征在于，所述第五存储芯片的有源面朝向所述基板的上表面；所述基板在对应所述第一存储芯片和所述第二存储芯片之间的区域设置连通所述基板的上表面和下表面的有第三窗口；
    所述第三存储芯片、所述第四存储芯片在所述基板上的正投影与所述第三窗口不交叠；
    所述第五存储芯片的有源面上触点通过所述第三窗口与所述基板的下表面引线连接。
  6. 根据权利要求5所述的存储芯片堆叠封装，其特征在于，
    所述多层存储芯片还包括位于第四层的第六存储芯片；
    所述第六存储芯片的有源面朝向背离所述基板的一侧，且所述第六存储芯片的有源面上触点与所述基板的上表面引线连接。
  7. 根据权利要求1-6任一项所述的存储芯片堆叠封装，其特征在于，所述第三存 储芯片与所述第一存储芯片在所述基板上的正投影重合，所述第四存储芯片与所述第二存储芯片在所述基板上的正投影重合。
  8. 根据权利要求6或7所述的存储芯片堆叠封装，其特征在于，所述第六存储芯片与所述第五存储芯片在所述基板上的正投影重合。
  9. 根据权利要求1-8任一项所述的存储芯片堆叠封装，其特征在于，
    所述存储芯片堆叠封装中的所有存储芯片的规格相同，且每一存储芯片的触点位于有源面的中轴线上。
  10. 根据权利要求1-9任一项所述的存储芯片堆叠封装，其特征在于，
    所述存储芯片堆叠封装中的所有存储芯片均为DRAM芯片。
  11. 根据权利要求1-10任一项所述的存储芯片堆叠封装，其特征在于，
    所述依次堆叠在基板上的多层存储芯片形成一个存储模块，所述存储模块中的第一存储芯片和第二存储芯片沿第一方向并列设置；
    所述存储芯片堆叠封装包括沿第二方向并列设置的两个所述存储模块；
    所述第二方向与所述第一方向垂直。
  12. 根据权利要求1-11任一项所述的存储芯片堆叠封装，其特征在于，所述基板的上表面设置有凹槽结构，位于第一层的所有存储芯片设置于所述凹槽结构中。
  13. 根据权利要求1-12任一项所述的存储芯片堆叠封装，其特征在于，所述第一存储芯片、所述第二存储芯片、所述第三存储芯片、所述第四存储芯片和所述第五存储芯片中的四个用于提供并行的读写访问功能，剩余一个用于存放ECC实现纠错功能。
  14. 一种电子设备，其特征在于，包括CPU，以及，如权利要求1-13中任一项所述的存储芯片堆叠封装；所述存储芯片堆叠封装与所述CPU连接。
  15. 如权利要求14所述的电子设备，其特征在于，所述CPU的位宽为64位，所述第一存储芯片、所述第二存储芯片、所述第三存储芯片、所述第四存储芯片、所述第五存储芯片中的四个分别用于提供16位的并行读写访问功能，剩余一个用于保存ECC实现纠错功能。
PCT/CN2020/081132 2020-03-25 2020-03-25 存储芯片堆叠封装及电子设备 WO2021189300A1 (zh)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101866915A (zh) * 2009-04-15 2010-10-20 三星电子株式会社 集成电路装置及其操作方法、存储器存储装置及电子系统
CN102944709A (zh) * 2011-08-16 2013-02-27 北京天中磊智能科技有限公司 多芯片系统级封装技术实现的电表模块结构及其封装方法
CN106409775A (zh) * 2015-07-31 2017-02-15 爱思开海力士有限公司 堆叠封装及其制造方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN2528109Y (zh) * 2002-01-18 2002-12-25 胜开科技股份有限公司 封装多个记忆体晶片的封装记忆体
SG127684A1 (en) * 2002-08-19 2006-12-29 Micron Technology Inc Packaged microelectronic component assemblies
KR20060028487A (ko) * 2004-09-24 2006-03-30 삼성전자주식회사 Ｂｏｃ 구조를 이용한 적층 칩 패키지
KR101070913B1 (ko) * 2005-05-19 2011-10-06 삼성테크윈 주식회사 반도체 칩 적층 패키지
EP3732711A4 (en) * 2017-12-30 2021-11-03 INTEL Corporation STACKED SILICON CHIP ARCHITECTURE WITH MIXED RETURN CHIP AND WIRE CONNECTION INTERCONNECT
KR102378819B1 (ko) * 2018-02-20 2022-03-25 삼성전자주식회사 메모리 장치

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101866915A (zh) * 2009-04-15 2010-10-20 三星电子株式会社 集成电路装置及其操作方法、存储器存储装置及电子系统
CN102944709A (zh) * 2011-08-16 2013-02-27 北京天中磊智能科技有限公司 多芯片系统级封装技术实现的电表模块结构及其封装方法
CN106409775A (zh) * 2015-07-31 2017-02-15 爱思开海力士有限公司 堆叠封装及其制造方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4123695A4 *

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