WO2021185037A1 - 显示基板及其制作方法、显示面板 - Google Patents

显示基板及其制作方法、显示面板 Download PDF

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Publication number
WO2021185037A1
WO2021185037A1 PCT/CN2021/077695 CN2021077695W WO2021185037A1 WO 2021185037 A1 WO2021185037 A1 WO 2021185037A1 CN 2021077695 W CN2021077695 W CN 2021077695W WO 2021185037 A1 WO2021185037 A1 WO 2021185037A1
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Prior art keywords
flat
layer
passivation
substrate
display
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PCT/CN2021/077695
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English (en)
French (fr)
Inventor
程磊磊
黄勇潮
王庆贺
张扬
周斌
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京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥鑫晟光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/432,462 priority Critical patent/US20230380215A1/en
Publication of WO2021185037A1 publication Critical patent/WO2021185037A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/32—Stacked devices having two or more layers, each emitting at different wavelengths
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/82—Interconnections, e.g. terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/20—Changing the shape of the active layer in the devices, e.g. patterning
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/20—Changing the shape of the active layer in the devices, e.g. patterning
    • H10K71/231—Changing the shape of the active layer in the devices, e.g. patterning by etching of existing layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10—Substrates, e.g. flexible substrates
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/1306—Details
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/873—Encapsulations

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display substrate, a manufacturing method thereof, and a display panel.
  • OLED Organic Light-Emtting Diode
  • the organic light-emitting layer EL needs to be fabricated on a film surface with good flatness to ensure the light-emitting efficiency of the device and the life of the light-emitting material.
  • the embodiments of the present disclosure provide a display substrate, a manufacturing method thereof, and a display panel.
  • a display substrate in one aspect, includes a display area and a non-display area at least on one side of the display area; the display substrate further includes a passivation layer and a passivation layer covering the passivation layer.
  • a flat layer, the passivation layer and the flat layer are located in the display area and the non-display area;
  • the flat layer includes a first flat via hole located in the non-display area and a plurality of second flat via holes located in the display area;
  • the passivation layer includes a first passivation via located in the non-display area, and the first flat via and the first passivation via form a first set of holes;
  • the hole depth of the first flat via is smaller than the hole depth of each of the second flat vias, and the hole depth of the first passivation via is greater than or equal to the largest hole in all the second flat vias The difference between the depth and the hole depth of the first flat via.
  • the passivation layer further includes a plurality of second passivation vias located in the display area;
  • the plurality of second flat vias and the plurality of second passivation vias form a plurality of second sets of holes
  • the passivation layer and the flat layer are formed with a step on the inner wall of each second set of holes, and a part of the flat layer is provided on the step.
  • the display substrate further includes a substrate; the passivation layer and the flat layer are disposed on the substrate.
  • each of the second flat vias includes: a first flat sub-via and a second flat sub-via that are connected, the first flat sub-via is far away from the substrate, and the second flat sub-via The sub-via is close to the substrate;
  • the step is located on a side of the first flat sub-via close to the substrate and adjacent to the second flat sub-via.
  • the cross-sections of the first flat sub-via and the second flat sub-via each include opposite first top edges and first bottom edges, so The first top side is far away from the substrate, and the first bottom side is close to the substrate; the length of the first top side is greater than the length of the first bottom side;
  • the length of the first bottom side of the first flat sub-via is greater than the length of the first top side of the second flat sub-via.
  • the display substrate further includes: a first metal layer, and the passivation layer covers the first metal layer;
  • the first metal layer includes: a first metal portion located in the non-display area and a second metal portion located in the display area; the first metal portion is located below the first set of holes; The second metal part is located below the plurality of second sets of holes.
  • the second metal part includes a source electrode and a drain electrode, and the source electrode and the drain electrode are respectively located under different second sets of holes.
  • the display substrate further includes an anode located on a side of the flat layer away from the passivation layer, and the anode is electrically connected to the second metal part through the second set of holes.
  • the display substrate further includes: a buffer layer, an active layer, a gate insulating layer, a gate metal layer, and an interlayer dielectric layer; wherein,
  • the active layer includes a semiconductor portion and conductive portions located on both sides of the semiconductor portion, and the gate metal layer includes a gate located in the display area and an electrode located in the non-display area.
  • a display panel including the above-mentioned display substrate.
  • the display panel includes a twisted nematic liquid crystal display panel, a vertical alignment liquid crystal display panel, a plane switching liquid crystal display panel, an advanced super dimensional field switching liquid crystal display panel, or an OLED display panel.
  • the method includes:
  • the first flat via area in the non-display area and the flat layer in the second flat via area in the display area are etched for the first time, and a second flat via area is formed in the first flat via area.
  • the passivation layer located in the first flat via area and the second flat via area and the flat layer located in the second flat via area are etched a second time to form a A passivation via and at least one second flat sub-via; the at least one first flat sub-via and the at least one second flat sub-via form at least one second flat via; the first blunt The first flat via hole and the first flat via hole form a first set of holes; the hole depth of the first flat via hole is smaller than the hole depth of each of the second flat via holes; wherein, the second etching The depth of the first passivation via is the depth of the first passivation via; the depth of the first passivation via is greater than or equal to the maximum depth of the second flat via and the depth of the first flat via The difference in hole depth.
  • the method further includes:
  • the passivation layer located in the second flat via area is etched a third time to form at least one second passivation via; the second passivation via and the second flat via are formed The second set of holes.
  • the material of the protective layer is photoresist.
  • the display substrate further includes a substrate, and the passivation layer and the flat layer are formed on the substrate;
  • the cross-sections of the first flat sub-via and the second flat sub-via each include a first top side and a first bottom side opposite to each other, and the first top side The side is far away from the substrate, the first bottom side is close to the substrate; the length of the first top side is greater than the length of the first bottom side;
  • the length of the first bottom side of the first flat sub-via is greater than the length of the first top side of the second flat sub-via.
  • the method before the forming the passivation layer and the flat layer covering the passivation layer, the method further includes:
  • the first metal layer includes: a first metal part located in the non-display area and a second metal part located in the display area.
  • the second etching further includes:
  • the first metal part is exposed.
  • the third etching further includes:
  • the second metal part is exposed.
  • the first metal layer is a source-drain metal layer
  • the second metal part includes a source electrode and a drain electrode.
  • the method further includes:
  • An anode is formed on the flat layer, and the anode is in contact with the source through the second set of holes located above the source.
  • the method before the forming the first metal layer, the method further includes:
  • the first metal layer is formed on the interlayer dielectric layer
  • the active layer includes a semiconductor part and a conductive part located on both sides of the semiconductor part, and the source electrode and the drain electrode are respectively It is electrically connected to the conductorization part.
  • the method further includes:
  • a buffer layer located in the display area and the non-display area is formed on the substrate.
  • FIG. 1 is a schematic diagram of the first display substrate in the related art
  • FIG. 2 is a schematic flow chart of a manufacturing method of a display substrate provided by an embodiment of the disclosure
  • FIG. 3 is a schematic diagram of a second display substrate provided by an embodiment of the disclosure.
  • FIG. 4 is a schematic diagram of a third display substrate provided by an embodiment of the disclosure.
  • FIG. 5 is a schematic diagram of a fourth display substrate provided by an embodiment of the disclosure.
  • FIG. 6 is a schematic diagram of a fifth display substrate provided by an embodiment of the disclosure.
  • FIG. 7 is a schematic diagram of a sixth display substrate provided by an embodiment of the disclosure.
  • FIG. 8 is a schematic diagram of a seventh display substrate provided by an embodiment of the disclosure.
  • FIG. 9 is a schematic diagram of an eighth display substrate provided by an embodiment of the disclosure.
  • FIG. 10 is a schematic diagram of a ninth display substrate provided by an embodiment of the disclosure.
  • FIG. 11 is a schematic diagram of a tenth display substrate provided by an embodiment of the disclosure.
  • words such as “first” and “second” are used to distinguish the same items or similar items that have basically the same function and effect. This is only to clearly describe the technical solutions of the embodiments of the present disclosure, and cannot be understood. To indicate or imply relative importance or implicitly indicate the number of technical features indicated.
  • plural means two or more, and “at least one” means one or more, unless otherwise specifically defined.
  • the embodiment of the present disclosure provides a display substrate, the display substrate includes: a display area and a non-display area at least on one side of the display area; as shown in FIG. 8, the display substrate includes: a passivation layer 28 and a cover passivation layer 28 The flat layer 29, the passivation layer and the flat layer are located in the display area and the non-display area.
  • the planarization layer includes a first planar via hole located in the non-display area and a plurality of second planar via holes located in the display area;
  • the passivation layer includes a first passivation via hole located in the non-display area, the first planar via hole and the first planar via hole Passivation via holes form a first set of holes 31.
  • the hole depth of the first flat via is smaller than the hole depth of each second flat via; the hole depth of the first passivation via is greater than or equal to the maximum hole depth of all the second flat vias and that of the first flat via The difference in hole depth.
  • the passivation layer further includes a plurality of second passivation vias located in the display area; a plurality of second flat vias and a plurality of second passivation vias form a plurality of second sets of holes 32; passivation layer 28 and the flat layer 29 are formed with a step (marked 70 in FIG. 9) on the inner wall of the second set of holes 32, and a partial flat layer (marked M area and N area in FIG. 10) is provided on the step.
  • the correspondence between the plurality of second flat vias and the plurality of second passivation vias is a one-to-one correspondence.
  • the display substrate can be used to form a liquid crystal display panel, and can also be used to form an Organic Light-Emitting Diode (OLED) display panel, which is not limited here.
  • OLED Organic Light-Emitting Diode
  • the display substrate has small differences in the via holes etched at different thicknesses of the flat layer, which can improve the metal oxidation problem caused by excessive etching, thereby reducing the impact on the subsequent metal film layer overlap and signal transmission; at the same time, the passivation
  • the stepped layer and the flat layer are formed on the inner wall of the second set of holes, and a part of the flat layer is provided on the step.
  • the metal structure provided below can be better protected from oxidation; on the other hand, the structure can be reversed.
  • the production method of the following embodiment is introduced.
  • the display substrate further includes a substrate 60, and a passivation layer 28 and a flat layer 29 are formed on the substrate 60.
  • each second flat via includes: a first flat sub-via 3021 and a second flat sub-via 3022 that are connected, the first flat sub-via 3021 is away from the substrate 60, and the second flat sub-via 3022 Close to the substrate 60; the step 70 is located on the side of the first flat sub-via 3021 close to the substrate 60 and adjacent to the second flat sub-via 3022.
  • the cross-sections of the first flat sub-via and the second flat sub-via each include a first top side and a first bottom side opposite to each other, and the first top side is away from the substrate , The first bottom side is close to the substrate; the length of the first top side is greater than the length of the first bottom side; the length of the first bottom side of the first flat sub-via is greater than the length of the first top side of the second flat sub-via .
  • the length t1 of the first top side of the first flat sub-via is greater than the length b1 of the first bottom side, and the second flat sub-via
  • the length t2 of the first top side is greater than the length b2 of the first bottom side
  • the length b1 of the first bottom side of the first flat sub-via is greater than the length t2 of the first top side of the second flat sub-via.
  • the second metal part (shown in Figure 10 The thickness above the source electrode 30 and the drain electrode 27) can better protect the second metal part from oxidation; on the other hand, the manufacturing method of the display substrate can be deduced from this structure, which is more conducive to product protection.
  • the display substrate further includes: a first metal layer, and the passivation layer covers the first metal layer.
  • the first metal layer includes: a first metal portion 26 located in the non-display area and a second metal portion (including the source electrode 30 and the drain electrode 27) located in the display area; the first metal portion 26 is located under the first set of holes 31; The second metal part is located under the plurality of second sets of holes, wherein the source 30 and the drain 27 are respectively located under different second sets of holes. Specifically, the source 30 in the second metal part is located on the right side of the second set of holes. Below the second set of holes 32 and the drain 27 are located below the second set of holes 32 on the left.
  • the display substrate further includes an anode 50.
  • the anode 50 is located on the side of the flat layer 29 away from the passivation layer 28.
  • the anode 50 passes through the second set of holes (not marked in FIG. 11) and the second metal part. Electric connection. In FIG. 11, the anode 50 and the source 30 are electrically connected.
  • the above-mentioned display substrate may further include: a buffer layer 20, an active layer, a gate insulating layer (GI layer) 22, a gate metal layer (including a gate 23 located in the display area and a gate 23 located in the non-display area).
  • An embodiment of the present disclosure provides a display panel including the display substrate of the above embodiment.
  • the display panel has small differences in via holes etched at different thicknesses of the flat layer, can improve the metal oxidation problem caused by excessive etching, and has the characteristics of high metal film layer bonding quality and stable signal transmission.
  • the display panel can be of Twisted Nematic (TN) type, Vertical Alignment (VA) type, In-Plane Switching (IPS) type or Advanced Super Dimension Switch (ADS) ) Type and other liquid crystal display panels can also be OLED display panels and any products or components with display functions such as televisions, digital cameras, mobile phones, and tablet computers including these display panels.
  • TN Twisted Nematic
  • VA Vertical Alignment
  • IPS In-Plane Switching
  • ADS Advanced Super Dimension Switch
  • the flat layer is exposed first, and then all the flat layer via holes are etched; Then, the passivation layer is exposed, and then all the passivation layer via holes are etched; thus, at least the flat layer via hole and the passivation layer via hole are formed at least in the region 201 and the region 200.
  • the existing etching processes all have excessive etching to ensure the uniformity of etching in different areas.
  • the flat layer vias at the region 200 located in the non-display area will be overetched, and then after the passivation layer vias are etched , Resulting in oxidation of the metal layer 15 below it, which in turn affects the bonding and signal transmission of the subsequent metal film layer.
  • the left side of the dotted line AB is the thin film transistor area (TFT area), which is located in the display area; the right side of the dotted line AB is the S/B area (Short Bar area), which is located in the non-display area.
  • TFT area thin film transistor area
  • S/B area Short Bar area
  • the dotted line AB between the TFT area and the S/B area in FIG. 1 indicates that the two areas are not directly adjacent to each other, and other areas are set in between. To illustrate the problem, the two are drawn together.
  • ⁇ H1, ⁇ H2, and ⁇ H3 respectively indicate that the planarization layer has different thicknesses in different regions
  • ⁇ H4 represents the thickness of the passivation layer in that region.
  • the 1 also includes a buffer layer 10, an active layer, a gate insulating layer (GI layer) 12, a gate metal layer (Gate layer) 13, an interlayer dielectric layer (ILD layer) 14, a source and drain metal layer (SD Layer) 15, where the active layer includes a semiconductor part (Act) 111 and a conductive part (conducted Act) 110 located on both sides of the semiconductor part 111.
  • GI layer gate insulating layer
  • ILD layer interlayer dielectric layer
  • SD Layer source and drain metal layer
  • the embodiment of the present disclosure provides a method for manufacturing a display substrate.
  • the display substrate includes a display area and a non-display area at least on one side of the display area.
  • the above-mentioned display area refers to the area used to achieve display; the non-display area refers to the area outside the display area, which can include the Short bar area (used to realize short-circuit protection), Fanout area (used to collect The metal wire in the display area) and so on.
  • the method includes:
  • the material of the flat layer here may be resin (Resin), for example: Silicon-Organic (SOG) and so on.
  • the forming method is not limited here, and it can be formed by a patterning process or an inkjet printing process. In order to improve the utilization of existing equipment, the former is often used.
  • the patterning process is a process of forming a thin film into a layer including at least one pattern. It usually includes: coating photoresist on the film, using a mask to expose the photoresist, then using a developer to wash away the photoresist that needs to be removed, and then etching off the part of the film that is not covered with the photoresist , And finally strip the remaining photoresist.
  • the above-mentioned passivation layer, also called PVX layer can be made of inorganic insulating materials, such as silicon dioxide and silicon oxynitride.
  • the first flat layer in the first flat via area in the non-display area and the flat layer in the second flat via area in the display area is etched for the first time, and a second flat via area is formed in the first flat via area.
  • a flat via 301 forms a first flat sub-via 3021 in the second flat via area; the depth of the first etching is the hole depth H1 of the first flat via.
  • the first flat via area may be located in the short bar area of the non-display area, and of course, it may also be other areas in the non-display area that need to be punched.
  • the embodiments of the present disclosure and the drawings are described using the former as an example.
  • the passivation layer located in the first flat via area and the second flat via area and the flat layer located in the second flat via area are etched a second time to form a first passivation.
  • a through hole 401 and at least one second flat sub-via (marked as 3022 in FIG. 9); at least one first flat sub-via and at least one second flat sub-via form at least one second flat via 302;
  • a passivation via 401 and a first flat via 301 form a first set of holes (31 marked in FIG. 8); referring to FIG.
  • the hole depth H1 of the first flat via is smaller than that of all the second flat vias Depth (H3 and H4 shown in Figure 3); where the depth of the second etch is the depth of the first passivation via (H2 shown in Figure 3); the depth of the first passivation via is greater than Or equal to the difference between the maximum hole depth of all the second flat vias and the hole depth of the first flat vias.
  • the depth of the second etch (that is, the hole depth of the first passivation via) is equal to the difference between the maximum hole depth in all the second flat vias and the hole depth of the first flat via Examples are drawn. If the depth of the second etch (that is, the depth of the first passivation via) is greater than the difference between the maximum hole depth of all the second flat vias and the depth of the first flat via, refer to Figure 5 Note, I won’t repeat it here.
  • the aforementioned at least one second flat via refers to one or more second flat vias.
  • the specific position and number of the second flat vias are not limited here, and the specific needs are determined according to actual conditions.
  • the thin film transistor includes a gate, a gate insulating layer, an active layer, a source and a drain; the anode is electrically connected to the source.
  • a second flat via and a second passivation via need to be provided in the area above the source to achieve electrical connection with the anode.
  • a second flat via hole and a second passivation via hole may also be provided above the drain to realize electrical connection between other film layers and the drain.
  • the hole depths of these second flat vias may be the same or different, and the specific needs to be determined according to the positions and functions.
  • the difference between the maximum hole depth in all the second flat vias and the hole depth of the first flat via refers to the maximum hole depth in all the second flat vias minus the hole depth of the first flat via Numerical value.
  • a protective layer is formed, and the protective layer covers the first set of holes.
  • the above-mentioned protective layer may only cover the first set of holes; of course, the protective layer may also cover areas other than the second flat via area in the display area, which is not limited here.
  • the embodiments of the present disclosure and the drawings are described later as examples.
  • the material of the protective layer may be photoresist.
  • a layer of photoresist 41 may be coated as a whole, and the photoresist covers the flat layer, the passivation layer, the second flat via hole, and the first set of holes. Then after the photoresist is exposed and developed, the photoresist above the second flat via is removed, and the photoresist above the flat layer in areas other than the second flat via area and the light above the first set of holes are retained. Resist; to obtain a display substrate as shown in Figure 7.
  • the passivation layer located in the second flat via area is etched a third time to form at least one second passivation via (not marked in FIG. 8); the second passivation via and The second flat vias form a second set of holes 32.
  • the correspondence between the second passivation via and the second flat via is a one-to-one correspondence.
  • the embodiment of the present disclosure provides a method for manufacturing a display substrate.
  • the display substrate includes: a display area and a non-display area at least on one side of the display area; the method includes: forming a passivation layer and a flat layer covering the passivation layer; and passivation.
  • the flat layer and the flat layer are located in the display area and the non-display area; the flat layer in the first flat via area in the non-display area and the flat layer in the second flat via area in the display area is etched for the first time, A first flat via is formed in the via area, and at least one first flat sub-via is formed in the second flat via area; the depth of the first etching is the depth of the first flat via;
  • the passivation layer in the hole region and the second flat via region, and the flat layer located in the second flat via region are etched a second time to form a first passivation via and at least one second flat sub-via; at least One first flat sub-via and at least one second flat sub-via form at least one second flat via; the first passivation via and the first flat via form a first set of holes; the hole of the first flat via The depth is less than the depth of the second flat via; where the depth of the second etch is the depth of the first passivation via; the depth of the first passivation via is greater
  • the etching depth of the flat via is used as the etching depth, so when the first flat via is formed, the first flat via will not be over-etched.
  • the etching depth is the hole depth of the first passivation via, and the hole depth of the first passivation via is greater than or equal to the maximum hole depth of all the second flat vias and the first flat via. The difference between the hole depths of the via holes prevents over-etching of the first passivation via when the first passivation via and the at least one second flat via are formed.
  • the protective layer is used to cover the first set of holes. Then, in the third etching, the first flat vias and the first passivation vias will not be etched again, thereby preventing the first set of vias. A flat via and the first passivation via are over-etched.
  • the above manufacturing method can improve the oxidation of the underlying metal layer caused by the over-etching of the first flat via, thereby reducing the impact on the subsequent metal film layer overlap and signal transmission.
  • the manufacturing method of the display substrate provided by the embodiments of the present disclosure can improve the etching difference caused by etching the via holes at different thicknesses of the flat layer, thereby improving the metal oxidation problem caused by excessive etching, thereby reducing the impact on the subsequent metal film layer.
  • the material of the protective layer is photoresist.
  • the display substrate further includes a substrate 60, and a passivation layer 28 and a flat layer 29 are formed on the substrate 60.
  • the cross-sections of the first flat sub-via and the second flat sub-via each include a first top side and a first bottom side opposite to each other.
  • the first top side is away from the substrate, and the first bottom The side is close to the substrate; the length of the first top side is greater than the length of the first bottom side.
  • the length of the first bottom side of the first flat sub-via is greater than the length of the first top side of the second flat sub-via.
  • the length t1 of the first top side of the first flat sub-via is greater than the length b1 of the first bottom side
  • the length t2 of the first top side of the second flat sub-via is greater than the length of the first bottom side.
  • the length b1 of the first bottom side of the first flat sub-via is greater than the length t2 of the first top side of the second flat sub-via.
  • the above method further includes:
  • the first metal layer includes: a first metal portion 26 located in the non-display area and a second metal portion (including the source 30 and the drain 27) located in the display area.
  • the material of the above-mentioned first metal layer is not limited, and it may be copper, silver, or the like.
  • the second etching further includes:
  • the first metal portion 26 is exposed.
  • the third etching further includes:
  • the second metal part (including the source 30 and the drain 27) is exposed.
  • the first metal layer may be a source-drain metal layer
  • the second metal part includes a source electrode and a drain electrode.
  • the material of the source electrode and the drain electrode is not limited.
  • a metal for example: copper
  • the above method further includes:
  • an anode 50 is formed on the flat layer 29, and the anode 50 is in contact with the source 30 through a second set of holes located above the source. At this time, the anode is electrically connected to the second metal part (that is, the source), and the second metal part can be used to supply power to the anode.
  • the second metal part that is, the source
  • the above method further includes:
  • an active layer, a gate insulating layer 22, a gate metal layer, and an interlayer dielectric layer are sequentially formed; wherein, the first metal layer is formed on the interlayer dielectric layer, and the active layer includes a semiconductor part 211 and the conductive portion 210 located on both sides of the semiconductor portion 211, the source 30 and the drain 27 are respectively electrically connected to the conductive portion 210.
  • the gate metal layer includes a gate 23 located in the display area and a non-display The electrode 24 in the Short bar (S/B) area of the area. In this way, after S07 and S04, thin film transistors can be formed.
  • the material of the above-mentioned active layer is an oxide semiconductor material, such as: indium gallium zinc oxide (Indium Gallium Zinc Oxide, IGZO), indium tin zinc oxide (Indium Tin Zinc Oxide, ITZO), indium zinc oxide (Indium Zinc Oxide, IZO) and so on.
  • oxide semiconductor material such as: indium gallium zinc oxide (Indium Gallium Zinc Oxide, IGZO), indium tin zinc oxide (Indium Tin Zinc Oxide, ITZO), indium zinc oxide (Indium Zinc Oxide, IZO) and so on.
  • the manufacturing method of the display substrate includes:
  • Buffer layer located in the display area and the non-display area on the substrate.
  • the gate metal layer includes a gate located in the display area and an electrode located in the short bar (S/B) area of the non-display area.
  • the active layer includes a semiconductor part (Act) and conductive parts (conducting Act) located on both sides of the semiconductor part (Act).
  • the active layer, the gate insulating layer (GI), and the gate are all located in the thin film transistor area (TFT area) of the display area.
  • the source-drain metal layer that is, the first metal layer, includes a source electrode and a drain electrode (ie, a second metal portion) located in the thin film transistor region, and a first metal portion located in the S/B region. Wherein, the source electrode and the drain electrode are respectively electrically connected to the conductive part.
  • the first flat via area in the S/B area and the second flat via area in the thin film transistor area in the flat layer are etched for the first time to form a first flat via 301 And the first flat sub-via 3021; the first etching depth is the hole depth H1 of the first flat via.
  • the second flat via area is etched a second time to form a first passivation via 401 and two second flat sub-vias (marked as 3022 in FIG. 9), two groups
  • the first flat sub-via and the second flat sub-via form two second flat vias 302 (source flat vias and drain flat vias); the first passivation via 301 and the first flat via 401
  • a first set of holes (marked as 31 in FIG. 8) is formed; at this time, the first metal portion 26 is exposed.
  • the hole depth of the first flat via is smaller than the hole depth of the two second flat vias.
  • the depth of the second etching is the hole depth of the first passivation via; the hole depth (H2) of the first passivation via is equal to the maximum hole depth (H4) and the first passivation via in the two second flat vias.
  • a photoresist 41 is coated, and the photoresist covers the flat layer, the passivation layer, the second flat via hole, and the first set of holes.
  • the passivation layer located in the second flat via area is etched a third time to form two second passivation vias (source passivation vias and drain passivation vias). ), and the second metal part (including the source 30 and the drain 27) is exposed; the second passivation via and the second flat via are corresponding to each other to form a second set of holes 32. That is, two second flat vias (source flat via and drain flat via) and two corresponding second passivation vias (source passivation via and drain passivation via) respectively Two second sets of holes (source sleeve holes and drain sleeve holes) are formed.
  • the display substrate shown in FIG. 8 is a structure after the remaining photoresist is stripped after the third etching.
  • an anode 50 is formed on the flat layer 29, and the anode 50 is in contact with the source 30 through a second set of holes located above the source (that is, the source set hole).

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Abstract

显示基板及其制作方法、显示面板，涉及显示技术领域。显示基板包括：钝化层(28)和覆盖钝化层(28)的平坦层(29)；平坦层(29)包括第一平坦过孔和多个第二平坦过孔；钝化层(28)包括第一钝化过孔；第一平坦过孔和第一钝化过孔形成第一套孔(31)；第一平坦过孔的孔深小于每一个第二平坦过孔的孔深；第一钝化过孔的孔深大于或等于所有第二平坦过孔中的最大孔深与第一平坦过孔的孔深的差值。

Description

显示基板及其制作方法、显示面板
相关申请的交叉引用
本公开要求在2020年03月20日提交中国专利局、申请号为202010202995.5、名称为“一种显示基板及其制作方法、显示面板”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及显示技术领域，尤其涉及一种显示基板及其制作方法、显示面板。
背景技术
有机发光二极管(Organic Light-Emtting Diode，OLED)是一种利用有机半导体材料制成的薄膜发光器件，其具有自发光的特性。
随着日益增长的显示需求，OLED在高精度和大尺寸电视显示技术中，受到了人们的广泛重视。现有OLED技术中，有机发光层EL需制作在平坦度较好的膜面，以保证器件的出光效率和发光材料的寿命。
概述
本公开的实施例提供一种显示基板及其制作方法、显示面板。
本公开的实施例采用如下技术方案：
一方面，提供了一种显示基板，所述显示基板包括：显示区和至少位于所述显示区一侧的非显示区；所述显示基板还包括：钝化层和覆盖所述钝化层的平坦层，所述钝化层和所述平坦层位于所述显示区和所述非显示区；
所述平坦层包括位于所述非显示区的第一平坦过孔和位于所述显示区的多个第二平坦过孔；
所述钝化层包括位于所述非显示区的第一钝化过孔，所述第一平坦过孔和所述第一钝化过孔形成第一套孔；
所述第一平坦过孔的孔深小于每一个所述第二平坦过孔的孔深，所述第一钝化过孔的孔深大于或等于所有所述第二平坦过孔中的最大孔深与所述第 一平坦过孔的孔深的差值。
可选地，所述钝化层还包括位于所述显示区的多个第二钝化过孔；
所述多个第二平坦过孔和所述多个第二钝化过孔形成多个第二套孔；
所述钝化层与所述平坦层在每一个所述第二套孔的内壁形成有台阶，所述台阶上设置有部分所述平坦层。
可选地，所述显示基板还包括衬底；所述钝化层和所述平坦层设置在所述衬底之上。
可选地，每一个所述第二平坦过孔包括：相连的第一平坦子过孔和第二平坦子过孔，所述第一平坦子过孔远离所述衬底，所述第二平坦子过孔靠近所述衬底；
所述台阶位于所述第一平坦子过孔中靠近所述衬底的一侧、且与所述第二平坦子过孔相邻。
可选地，在沿垂直于所述衬底的方向上，所述第一平坦子过孔和所述第二平坦子过孔的截面均包括相对的第一顶边和第一底边，所述第一顶边远离所述衬底，所述第一底边靠近所述衬底；所述第一顶边的长度大于所述第一底边的长度；
所述第一平坦子过孔的所述第一底边的长度大于所述第二平坦子过孔的所述第一顶边的长度。
可选地，所述显示基板还包括：第一金属层，所述钝化层覆盖所述第一金属层；
所述第一金属层包括：位于所述非显示区的第一金属部和位于所述显示区的第二金属部；所述第一金属部位于所述第一套孔的下方；所述第二金属部位于所述多个第二套孔的下方。
可选地，所述第二金属部包括源极和漏极，所述源极和所述漏极分别位于不同的所述第二套孔的下方。
可选地，所述显示基板还包括阳极，所述阳极位于所述平坦层远离所述钝化层的一侧，所述阳极通过所述第二套孔与所述第二金属部电连接。
可选地，所述显示基板还包括：缓冲层、有源层、栅绝缘层、栅极金属层，以及层间介质层；其中，
所述有源层包括半导体部和位于所述半导体部两侧的导体化部，所述栅 极金属层包括位于所述显示区的栅极和位于所述非显示区的电极。
另一方面，提供了一种显示面板，包括上述显示基板。
可选地，所述显示面板包括扭曲向列型液晶显示面板、垂直取向型液晶显示面板、平面转换型液晶显示面板、高级超维场转换型液晶显示面板或OLED显示面板。
再一方面，提供了一种显示基板的制作方法，
所述方法包括：
形成钝化层和覆盖所述钝化层的平坦层；所述钝化层和所述平坦层位于所述显示区和所述非显示区；
对位于所述非显示区的第一平坦过孔区域和位于所述显示区的第二平坦过孔区域的所述平坦层进行第一次刻蚀，在所述第一平坦过孔区域形成第一平坦过孔，在所述第二平坦过孔区域形成至少一个第一平坦子过孔；所述第一次刻蚀的深度为所述第一平坦过孔的孔深；
对位于所述第一平坦过孔区域和所述第二平坦过孔区域的所述钝化层、以及位于所述第二平坦过孔区域的所述平坦层进行第二次刻蚀，形成第一钝化过孔和至少一个第二平坦子过孔；所述至少一个第一平坦子过孔和所述至少一个第二平坦子过孔形成至少一个第二平坦过孔；所述第一钝化过孔和所述第一平坦过孔形成第一套孔；所述第一平坦过孔的孔深小于每一个所述第二平坦过孔的孔深；其中，所述第二次刻蚀的深度为所述第一钝化过孔的孔深；所述第一钝化过孔的孔深大于或等于所述第二平坦过孔中的最大孔深与所述第一平坦过孔的孔深的差值。
可选地，所述方法还包括：
形成保护层，所述保护层覆盖所述第一套孔；
对位于所述第二平坦过孔区域的所述钝化层进行第三次刻蚀，形成至少一个第二钝化过孔；所述第二钝化过孔和所述第二平坦过孔形成第二套孔。
可选地，所述保护层的材料为光刻胶。
可选地，所述显示基板还包括衬底，所述钝化层和所述平坦层形成在所述衬底之上；
在沿垂直于所述衬底的方向上，所述第一平坦子过孔和所述第二平坦子过孔的截面均包括相对的第一顶边和第一底边，所述第一顶边远离所述衬底， 所述第一底边靠近所述衬底；所述第一顶边的长度大于所述第一底边的长度；
所述第一平坦子过孔的所述第一底边的长度大于所述第二平坦子过孔的所述第一顶边的长度。
可选地，在所述形成钝化层和覆盖所述钝化层的平坦层之前，所述方法还包括：
形成第一金属层，所述钝化层覆盖所述第一金属层；
其中，所述第一金属层包括：位于所述非显示区的第一金属部和位于所述显示区的第二金属部。
可选地，所述第二次刻蚀还包括：
在所述第一钝化过孔形成之后，露出所述第一金属部。
可选地，所述第三次刻蚀还包括：
在至少一个所述第二钝化过孔形成之后，露出所述第二金属部。
可选地，所述第一金属层为源漏金属层，所述第二金属部包括源极和漏极。
可选地，在所述第三次刻蚀之后，所述方法还包括：
在所述平坦层之上形成阳极，所述阳极通过位于所述源极上方的所述第二套孔与所述源极接触。
可选地，在所述形成第一金属层之前，所述方法还包括：
依次形成有源层、栅绝缘层、栅极金属层和层间介质层；
其中，所述第一金属层形成于所述层间介质层之上，所述有源层包括半导体部和位于所述半导体部两侧的导体化部，所述源极和所述漏极分别与所述导体化部电连接。
可选地，在所述依次形成有源层、栅绝缘层和栅极金属层之前，所述方法还包括：
在所述衬底上形成位于所述显示区和所述非显示区的缓冲层。
上述说明仅是本公开技术方案的概述，为了能够更清楚了解本公开的技术手段，而可依照说明书的内容予以实施，并且为了让本公开的上述和其它目的、特征和优点能够更明显易懂，以下特举本公开的具体实施方式。
附图简述
为了更清楚地说明本公开实施例或相关技术中的技术方案，下面将对实施例或相关技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为相关技术中的第一种显示基板的示意图；
图2为本公开实施例提供的一种显示基板的制作方法的流程示意；
图3为本公开实施例提供的第二种显示基板的示意图；
图4为本公开实施例提供的第三种显示基板的示意图；
图5为本公开实施例提供的第四种显示基板的示意图；
图6为本公开实施例提供的第五种显示基板的示意图；
图7为本公开实施例提供的第六种显示基板的示意图；
图8为本公开实施例提供的第七种显示基板的示意图；
图9为本公开实施例提供的第八种显示基板的示意图；
图10为本公开实施例提供的第九种显示基板的示意图；并且
图11为本公开实施例提供的第十种显示基板的示意图。
详细描述
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
在本公开的实施例中，采用“第一”、“第二”等字样对功能和作用基本相同的相同项或相似项进行区分，仅为了清楚描述本公开实施例的技术方案，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。
在本公开的实施例中，“多个”的含义是两个或两个以上，“至少一个”的含义是一个或一个以上，除非另有明确具体的限定。
本公开实施例提供了一种显示基板，该显示基板包括：显示区和至少位于显示区一侧的非显示区；参考图8所示，显示基板包括：钝化层28和覆盖钝化层28的平坦层29，钝化层和平坦层位于显示区和非显示区。
平坦层包括位于非显示区的第一平坦过孔和位于显示区的多个第二平坦过孔；钝化层包括位于非显示区的第一钝化过孔，第一平坦过孔和第一钝化过孔形成第一套孔31。
第一平坦过孔的孔深小于每一个第二平坦过孔的孔深；第一钝化过孔的孔深大于或等于所有第二平坦过孔中的最大孔深与第一平坦过孔的孔深的差值。
可选地，钝化层还包括位于显示区的多个第二钝化过孔；多个第二平坦过孔和多个第二钝化过孔形成多个第二套孔32；钝化层28与平坦层29在第二套孔32的内壁形成有台阶(图9中标记70)，台阶上设置有部分平坦层(图10中标记的M区域和N区域)。
示例的，上述多个第二平坦过孔和多个第二钝化过孔的对应关系为一一对应关系。
该显示基板可用于形成液晶显示面板，也可用于形成有机发光二极管(Organic Light-Emitting Diode，OLED)显示面板，这里不做限定。
该显示基板在平坦层的不同厚度处刻蚀的过孔的差异小，能改善因刻蚀过量产生的金属氧化问题，从而减轻对后续金属膜层的搭接和信号传输的影响；同时，钝化层与平坦层在第二套孔的内壁形成有台阶，台阶上设置有部分平坦层，一方面可以更好地保护下方设置的金属结构，防止其氧化；另一方面，从该结构可以反推出下文实施例的制作方法。
可选地，参考图9所示，显示基板还包括衬底60，钝化层28和平坦层29形成在衬底60之上。
可选地，每一个第二平坦过孔包括：相连的第一平坦子过孔3021和第二平坦子过孔3022，第一平坦子过孔3021远离衬底60，第二平坦子过孔3022靠近衬底60；台阶70位于第一平坦子过孔3021中靠近衬底60的一侧、且与第二平坦子过孔3022相邻。
可选地，在沿垂直于衬底的方向上，第一平坦子过孔和第二平坦子过孔的截面均包括相对的第一顶边和第一底边，第一顶边远离衬底，第一底边靠近衬底；第一顶边的长度大于第一底边的长度；第一平坦子过孔的第一底边的长度大于第二平坦子过孔的第一顶边的长度。
示例的，参考图10所示，以左侧的第二平坦过孔为例，第一平坦子过孔 的第一顶边的长度t1大于第一底边的长度b1，第二平坦子过孔的第一顶边的长度t2大于第一底边的长度b2，第一平坦子过孔的第一底边的长度b1大于第二平坦子过孔的第一顶边的长度t2。那么，图10所示的M区域和N区域会保留部分未刻蚀的平坦层；这样，一方面可以保护下方设置的金属结构，示例的，可以增大第二金属部(图10所示的源极30和漏极27)上方的厚度，从而更好地保护第二金属部，防止其氧化；另一方面，从该结构可以反推出显示基板的制作方法，更有利于保护产品。
可选地，参考图8所示，显示基板还包括：第一金属层，钝化层覆盖第一金属层。
第一金属层包括：位于非显示区的第一金属部26和位于显示区的第二金属部(包括源极30和漏极27)；第一金属部26位于第一套孔31的下方；第二金属部位于多个第二套孔的下方，其中，源极30和漏极27分别位于不同的第二套孔的下方，具体地，第二金属部中的源极30位于右侧第二套孔32的下方、漏极27位于左侧第二套孔32的下方。
可选地，参考图11所示，显示基板还包括阳极50，阳极50位于平坦层29远离钝化层28的一侧，阳极50通过第二套孔(图11未标记)与第二金属部电连接。图11中绘示的是阳极50和源极30电连接。
当然，参考图11所示，上述显示基板还可以包括：缓冲层20、有源层、栅绝缘层(GI层)22、栅极金属层(包括位于显示区的栅极23和位于非显示区的电极24)、层间介质层(ILD层)25、其中，有源层包括半导体部(Act)211和位于半导体部211两侧的导体化部(导体化Act)210。
本公开实施例提供的显示基板的制作方法以及相关内容可以参考下文实施例，此处不再赘述。
本公开实施例提供了一种显示面板，包括上文实施例的显示基板。该显示面板在平坦层的不同厚度处刻蚀的过孔的差异小，能改善因刻蚀过量产生的金属氧化问题，具有金属膜层搭接质量高、信号传输稳定的特点。
该显示面板可以是扭曲向列(Twisted Nematic，TN)型、垂直取向(Vertical Alignment，VA)型、平面转换(In-Plane Switching，IPS)型或高级超维场转换(Advanced Super Dimension Switch，ADS)型等液晶显示面板，还可以是OLED显示面板以及包括这些显示面板的电视、数码相机、手机、平板电脑 等任何具有显示功能的产品或者部件。
对图1所示的显示基板的平坦层(Resin层)17钝化层(PVX层)16刻蚀时，相关技术中，先对平坦层进行曝光，然后进行平坦层过孔的全部刻蚀；接着对钝化层进行曝光，然后进行钝化层过孔的全部刻蚀；从而至少在区域201和区域200处分别形成平坦层过孔和钝化层过孔。但是，现有刻蚀工艺均存在过量刻蚀，以保证不同区域的刻蚀均一性。这样在平坦层的不同厚度处刻蚀过孔后，会造成位于非显示区(S/B区域)中的区域200处的平坦层过孔的过刻，进而在钝化层过孔刻蚀后，导致其下方的金属层15产生氧化的问题，进而影响后续金属膜层的搭接和信号传输。另外，在显示区中的区域201处的平坦层过孔和钝化层过孔形成的套孔处也存在金属氧化现象。
图1中，虚线AB的左侧为薄膜晶体管区域(TFT区域)，位于显示区域；虚线AB的右侧为S/B区域(Short bar区域)，位于非显示区。图1中TFT区域和S/B区域之间的虚线AB表示两个区域并不是直接相邻，中间还设置其它区域，为了说明问题，将两者绘示在一起。图1中，△H1、△H2、△H3分别表示平坦层在不同区域具有不同的厚度，△H4表示钝化层在该处区域的厚度。当然，图1中还包括缓冲层10、有源层、栅绝缘层(GI层)12、栅极金属层(Gate层)13、层间介质层(ILD层)14、源漏金属层(SD层)15，其中，有源层包括半导体部(Act)111和位于半导体部111两侧的导体化部(导体化Act)110。
本公开实施例提供了一种显示基板的制作方法，显示基板包括：显示区和至少位于显示区一侧的非显示区。
上述显示区(Active Area，AA)是指用于实现显示的区域；非显示区是指显示区以外的区域，其可以包括Short bar区域(用于实现短路保护)、Fanout区(用于归集显示区的金属线)等。
参考图2所示，该方法包括：
S01、形成如图3所示的钝化层28和覆盖钝化层28的平坦层29；钝化层中设置有位于非显示区的第一钝化过孔区域和位于显示区的第二钝化过孔区域；钝化层和平坦层位于显示区和非显示区。
这里平坦层的材料可以是树脂(Resin)，例如：有机硅氧烷树脂(Silicon-Organic，SOG)等。这里对于形成方法不做限定，其可以采用构图 工艺形成，还可以采用喷墨打印工艺形成。为了提高现有设备利用率，多采用前者。构图工艺是将薄膜形成包含至少一个图案的层的工艺。其通常包括：在薄膜上涂光刻胶，利用掩膜板对光刻胶进行曝光，再利用显影液将需去除的光刻胶冲蚀掉，再刻蚀掉未覆盖光刻胶的薄膜部分，最后将剩下的光刻胶剥离。上述钝化层，又称PVX层，其材料可以是无机绝缘材料，例如：二氧化硅和氮氧化硅等。
S02、参考图4所示，对位于非显示区的第一平坦过孔区域和位于显示区的第二平坦过孔区域的平坦层进行第一次刻蚀，在第一平坦过孔区域形成第一平坦过孔301，在第二平坦过孔区域形成第一平坦子过孔3021；第一次刻蚀的深度为第一平坦过孔的孔深H1。
这里第一平坦过孔区域可以位于非显示区的Short bar区域，当然，也可以是非显示区中其它需要打过孔的区域。本公开实施例以及附图均以前者为例进行说明。
S03、参考图5所示，对位于第一平坦过孔区域和第二平坦过孔区域的钝化层、以及位于第二平坦过孔区域的平坦层进行第二次刻蚀，形成第一钝化过孔401和至少一个第二平坦子过孔(图9中标记为3022)；至少一个第一平坦子过孔和至少一个第二平坦子过孔形成至少一个第二平坦过孔302；第一钝化过孔401和第一平坦过孔301形成第一套孔(图8标记的31)；参考图3所示，第一平坦过孔的孔深H1小于所有第二平坦过孔的孔深(图3所示的H3和H4)；其中，第二次刻蚀的深度为第一钝化过孔的孔深(图3所示的H2)；第一钝化过孔的孔深大于或等于所有第二平坦过孔中的最大孔深与第一平坦过孔的孔深的差值。
图5中，绘示了两个第二平坦过孔302；左侧的第二平坦过孔302的孔深对应图3中的H4，右侧的第二平坦过孔302的孔深对应图3中的H3，H4大于H3，H3大于H1；两个第二平坦过孔中的最大孔深为H4，而第一平坦过孔的孔深为H1，第一钝化过孔的孔深为H2；从图3中可以看出，H4-H1＝H2，因此，图5中以第二次刻蚀的深度是H2为例进行绘示。即图5中是以第二次刻蚀的深度(即第一钝化过孔的孔深)等于所有第二平坦过孔中的最大孔深与第一平坦过孔的孔深的差值为例进行绘示。第二次刻蚀的深度(即第一钝化过孔的孔深)大于所有第二平坦过孔中的最大孔深与第一平坦过孔的孔深 的差值的情况可以参考图5的说明，此处不再赘述。
上述至少一个第二平坦过孔是指一个或者多个第二平坦过孔。这里对于第二平坦过孔的具体位置和数量不做限定，具体需要根据实际情况而定。示例的，若将上述显示基板应用在OLED显示面板中，则在显示区内，平坦层的下方还会设置钝化层和薄膜晶体管，在平坦层的上方会设置阳极。其中，薄膜晶体管包括栅极、栅绝缘层、有源层、源极和漏极；阳极与源极电连接。若源极和漏极设置在钝化层的下方且分别与钝化层接触，则在源极上方区域需要设置第二平坦过孔和第二钝化过孔，以实现与阳极的电连接。当然，此时漏极上方也可以设置第二平坦过孔和第二钝化过孔，以实现其它膜层与漏极电连接。
若上述第二平坦过孔的数量大于或等于两个，则这些第二平坦过孔的孔深可以相同，也可以不同，具体需要根据位置和作用确定。
上述所有第二平坦过孔中的最大孔深与第一平坦过孔的孔深的差值是指所有第二平坦过孔中的最大孔深减去第一平坦过孔的孔深所得到的数值。
S04、形成保护层，保护层覆盖第一套孔。
需要说明的是，上述保护层可以仅覆盖第一套孔；当然，保护层还可以覆盖显示区域中除第二平坦过孔区域以外的区域，这里不做限定。本公开实施例以及附图以后者为例进行说明。
上述保护层的材料可以是光刻胶。为了简化工艺，参考图6所示，可以整体涂覆一层光刻胶41，光刻胶覆盖平坦层、钝化层、第二平坦过孔、第一套孔。然后在光刻胶曝光显影后，去除第二平坦过孔上方的光刻胶、并保留除位于第二平坦过孔区域以外的区域的平坦层上方的光刻胶以及第一套孔上方的光刻胶；从而得到如图7示的显示基板。
S05、参考图8所示，对位于第二平坦过孔区域的钝化层进行第三次刻蚀，形成至少一个第二钝化过孔(图8未标记)；第二钝化过孔和第二平坦过孔形成第二套孔32。
示例的，上述第二钝化过孔和第二平坦过孔的对应关系为一一对应关系。
本公开的实施例提供了一种显示基板的制作方法，显示基板包括：显示区和至少位于显示区一侧的非显示区；方法包括：形成钝化层和覆盖钝化层的平坦层；钝化层和平坦层位于显示区和非显示区；对位于非显示区的第一 平坦过孔区域和位于显示区的第二平坦过孔区域的平坦层进行第一次刻蚀，在第一平坦过孔区域形成第一平坦过孔，在第二平坦过孔区域形成至少一个第一平坦子过孔；第一次刻蚀的深度为第一平坦过孔的孔深；对位于第一平坦过孔区域和第二平坦过孔区域的钝化层、以及位于第二平坦过孔区域的平坦层进行第二次刻蚀，形成第一钝化过孔和至少一个第二平坦子过孔；至少一个第一平坦子过孔和至少一个第二平坦子过孔形成至少一个第二平坦过孔；第一钝化过孔和第一平坦过孔形成第一套孔；第一平坦过孔的孔深小于第二平坦过孔的孔深；其中，第二次刻蚀的深度为第一钝化过孔的孔深；第一钝化过孔的孔深大于或等于第二平坦过孔中的最大孔深与第一平坦过孔的孔深的差值；形成保护层，保护层覆盖第一套孔；对位于第二平坦过孔区域的钝化层进行第三次刻蚀，形成至少一个第二钝化过孔；第二钝化过孔和第二平坦过孔形成第二套孔。
对平坦层不同厚度处刻蚀过孔时，由于第一平坦过孔的孔深的深度小，第二平坦过孔的孔深的深度大；这样，在第一次刻蚀中，采用第一平坦过孔的孔深作为刻蚀深度，则在形成第一平坦过孔时，不会造成第一平坦过孔的过刻。在第二次刻蚀中，刻蚀深度为第一钝化过孔的孔深，而第一钝化过孔的孔深大于或等于所有第二平坦过孔中的最大孔深与第一平坦过孔的孔深的差值，则在形成第一钝化过孔和至少一个第二平坦过孔时，不会对第一钝化过造成过刻。在第三次刻蚀之前，采用保护层覆盖第一套孔，那么，在第三次刻蚀中，不会对第一平坦过孔和第一钝化过孔进行再次刻蚀，从而防止第一平坦过孔和第一钝化过孔过刻。综上，上述制作方法可以改善因第一平坦过孔过刻导致的其下方的金属层产生氧化的问题，从而减轻对后续金属膜层的搭接和信号传输的影响。即本公开实施例提供的显示基板的制作方法可以改善在平坦层的不同厚度处刻蚀过孔产生的刻蚀差异，进而改善因刻蚀过量产生的金属氧化问题，从而减轻对后续金属膜层的搭接和信号传输的影响。
可选地，为了最大程度地利用现有工艺和材料，保护层的材料为光刻胶。
可选地，参考图10所示，显示基板还包括衬底60，钝化层28和平坦层29形成在衬底60之上。
在沿垂直于衬底的方向上，第一平坦子过孔和第二平坦子过孔的截面均包括相对的第一顶边和第一底边，第一顶边远离衬底，第一底边靠近衬底； 第一顶边的长度大于第一底边的长度。
第一平坦子过孔的第一底边的长度大于第二平坦子过孔的第一顶边的长度。
参考图10所示，第一平坦子过孔的第一顶边的长度t1大于第一底边的长度b1，第二平坦子过孔的第一顶边的长度t2大于第一底边的长度b2，第一平坦子过孔的第一底边的长度b1大于第二平坦子过孔的第一顶边的长度t2。
参考图10所示，以左侧的第二平坦过孔为例，在第二次刻蚀中，按照第二平坦子过孔的第一顶边的长度t2进行开孔刻蚀，则在经过第二次刻蚀后，图10所示的M区域和N区域会保留部分未刻蚀的平坦层；这样，一方面可以增大第二金属部上方的厚度，从而更好地保护第二金属部，防止其氧化；另一方面，从该结构可以反推出上述的制作方法，更有利于保护产品。
可选地，在S01、形成钝化层和覆盖钝化层的平坦层之前，上述方法还包括：
S06、形成第一金属层，钝化层覆盖第一金属层。
其中，参考图3所示，第一金属层包括：位于非显示区的第一金属部26和位于显示区的第二金属部(包括源极30和漏极27)。
上述第一金属层的材料不做限定，其可以是铜、银等。
进一步可选地，S03、第二次刻蚀还包括：
参考图5所示，在第一钝化过孔401形成之后，露出第一金属部26。
进一步可选地，S05、第三次刻蚀还包括：
参考图8所示，在至少一个第二钝化过孔形成之后，露出第二金属部(包括源极30和漏极27)。
可选地，第一金属层可以为源漏金属层，第二金属部包括源极和漏极，这里，对于源极和漏极的材料不做限定，示例的，可以采用金属(例如：铜)制作。
进一步可选地，在S05、第三次刻蚀之后，上述方法还包括：
S07、参考图11所示，在平坦层29之上形成阳极50，阳极50通过位于源极上方的第二套孔与源极30接触。此时，阳极与第二金属部(即源极)电连接，第二金属部可用于向阳极供电。
进一步可选地，在S06、形成第一金属层之前，上述方法还包括：
S08、参考图3所示，依次形成有源层、栅绝缘层22、栅极金属层和层间介质层；其中，第一金属层形成于层间介质层之上，有源层包括半导体部211和位于半导体部211两侧的导体化部210，源极30和漏极27分别与导体化部210电连接，图3中，栅极金属层包括位于显示区的栅极23和位于非显示区的Short bar(S/B)区域的电极24。这样，在经过S07和S04之后，可以形成薄膜晶体管。上述有源层的材料是氧化物半导体材料，例如：铟镓锌氧化物(Indium Gallium Zinc Oxide，IGZO)、铟锡锌氧化物(Indium Tin Zinc Oxide，ITZO)、氧化铟锌(Indium Zinc Oxide，IZO)等。
下面提供一具体实施例以详细说明本公开，这里以在第二平坦过孔区域形成两个第二平坦过孔为例进行说明。该显示基板的制作方法包括：
S101、在衬底上形成位于显示区和非显示区的缓冲层(Buffer层)。
S102、在缓冲层之上依次形成有源层、栅绝缘层(GI)、栅极金属层(Gate)和层间介质层(ILD)。其中，栅极金属层包括位于显示区的栅极和位于非显示区的Short bar(S/B)区域的电极。有源层包括半导体部(Act)、以及位于半导体部(Act)两侧的导体化部(导体化Act)。有源层、栅绝缘层(GI)、栅极均位于显示区的薄膜晶体管区域(TFT区域)。
S103、在层间介质层(ILD)之上形成源漏金属层(S/D层)。源漏金属层，即第一金属层，包括位于薄膜晶体管区域的源极和漏极(即第二金属部)、以及位于S/B区域的第一金属部。其中，源极和漏极分别与导体化部电连接。
S104、形成钝化层和覆盖钝化层的平坦层；钝化层覆盖上述源漏金属层；钝化层和平坦层位于显示区和非显示区。从而形成如图3所示的显示基板。
S105、参考图4所示，对平坦层中位于S/B区域的第一平坦过孔区域和位于薄膜晶体管区域的第二平坦过孔区域进行第一次刻蚀，形成第一平坦过孔301和第一平坦子过孔3021；第一次刻蚀的深度为第一平坦过孔的孔深H1。
S106、参考图5所示，对第二平坦过孔区域进行第二次刻蚀，形成第一钝化过孔401和两个第二平坦子过孔(图9中标记为3022)，两组第一平坦子过孔和第二平坦子过孔形成两个第二平坦过孔302(源极平坦过孔和漏极平坦过孔)；第一钝化过孔301和第一平坦过孔401形成第一套孔(图8标记为31)；此时，第一金属部26露出。第一平坦过孔的孔深小于两个第二平坦过孔的孔深。
其中，第二次刻蚀的深度为第一钝化过孔的孔深；第一钝化过孔的孔深(H2)等于两个第二平坦过孔中的最大孔深(H4)与第一平坦过孔的孔深(H1)的差值。从而形成如图5所示的显示基板。
S107、参考图6所示，涂覆光刻胶41，光刻胶覆盖平坦层、钝化层、第二平坦过孔、第一套孔。
S108、在光刻胶曝光显影后，去除第二平坦过孔上方的光刻胶、并保留除位于第二平坦过孔区域以外的区域的平坦层上方的光刻胶以及第一套孔上方的光刻胶；得到如图7示的显示基板。
S109、参考图8所示，对位于第二平坦过孔区域的钝化层进行第三次刻蚀，形成两个第二钝化过孔(源极钝化过孔和漏极钝化过孔)，并露出第二金属部(包括源极30和漏极27)；第二钝化过孔和第二平坦过孔一一对应形成第二套孔32。即两个第二平坦过孔(源极平坦过孔和漏极平坦过孔)和与之对应的两个第二钝化过孔(源极钝化过孔和漏极钝化过孔)分别形成两个第二套孔(源极套孔和漏极套孔)。图8所示的显示基板是在第三次刻蚀之后，将剩余的光刻胶剥离之后的结构。
S110、参考图11所示，在平坦层29之上形成阳极50，阳极50通过位于源极上方的第二套孔(即源极套孔)与源极30接触。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (22)

  1. 一种显示基板，其中，所述显示基板包括：显示区和至少位于所述显示区一侧的非显示区；所述显示基板还包括：钝化层和覆盖所述钝化层的平坦层，所述钝化层和所述平坦层位于所述显示区和所述非显示区；
    所述平坦层包括位于所述非显示区的第一平坦过孔和位于所述显示区的多个第二平坦过孔；
    所述钝化层包括位于所述非显示区的第一钝化过孔，所述第一平坦过孔和所述第一钝化过孔形成第一套孔；
    所述第一平坦过孔的孔深小于每一个所述第二平坦过孔的孔深，所述第一钝化过孔的孔深大于或等于所有所述第二平坦过孔中的最大孔深与所述第一平坦过孔的孔深的差值。
  2. 根据权利要求1所述的显示基板，其中，所述钝化层还包括位于所述显示区的多个第二钝化过孔；
    所述多个第二平坦过孔和所述多个第二钝化过孔形成多个第二套孔；
    所述钝化层与所述平坦层在每一个所述第二套孔的内壁形成有台阶，所述台阶上设置有部分所述平坦层。
  3. 根据权利要求2所述的显示基板，其中，所述显示基板还包括衬底；所述钝化层和所述平坦层设置在所述衬底之上。
  4. 根据权利要求3所述的显示基板，其中，每一个所述第二平坦过孔包括：相连的第一平坦子过孔和第二平坦子过孔，所述第一平坦子过孔远离所述衬底，所述第二平坦子过孔靠近所述衬底；
    所述台阶位于所述第一平坦子过孔中靠近所述衬底的一侧、且与所述第二平坦子过孔相邻。
  5. 根据权利要求4所述的显示基板，其中，在沿垂直于所述衬底的方向上，所述第一平坦子过孔和所述第二平坦子过孔的截面均包括相对的第一顶边和第一底边，所述第一顶边远离所述衬底，所述第一底边靠近所述衬底；所述第一顶边的长度大于所述第一底边的长度；
    所述第一平坦子过孔的所述第一底边的长度大于所述第二平坦子过孔的所述第一顶边的长度。
  6. 根据权利要求2所述的显示基板，其中，所述显示基板还包括：第一 金属层，所述钝化层覆盖所述第一金属层；
    所述第一金属层包括：位于所述非显示区的第一金属部和位于所述显示区的第二金属部；所述第一金属部位于所述第一套孔的下方；所述第二金属部位于所述多个第二套孔的下方。
  7. 根据权利要求6所述的显示基板，其中，所述第二金属部包括源极和漏极，所述源极和所述漏极分别位于不同的所述第二套孔的下方。
  8. 根据权利要求6所述的显示基板，其中，所述显示基板还包括阳极，所述阳极位于所述平坦层远离所述钝化层的一侧，所述阳极通过所述第二套孔与所述第二金属部电连接。
  9. 根据权利要求1所述的显示基板，其中，所述显示基板还包括：缓冲层、有源层、栅绝缘层、栅极金属层，以及层间介质层；其中，
    所述有源层包括半导体部和位于所述半导体部两侧的导体化部，所述栅极金属层包括位于所述显示区的栅极和位于所述非显示区的电极。
  10. 一种显示面板，其中，包括权利要求1-9任一项所述的显示基板。
  11. 根据权利要求10所述的显示面板，其中，所述显示面板包括扭曲向列型液晶显示面板、垂直取向型液晶显示面板、平面转换型液晶显示面板、高级超维场转换型液晶显示面板或OLED显示面板。
  12. 一种显示基板的制作方法，其中，所述方法包括：
    形成钝化层和覆盖所述钝化层的平坦层；所述钝化层和所述平坦层位于所述显示区和所述非显示区；
    对位于所述非显示区的第一平坦过孔区域和位于所述显示区的第二平坦过孔区域的所述平坦层进行第一次刻蚀，在所述第一平坦过孔区域形成第一平坦过孔，在所述第二平坦过孔区域形成至少一个第一平坦子过孔；所述第一次刻蚀的深度为所述第一平坦过孔的孔深；
    对位于所述第一平坦过孔区域和所述第二平坦过孔区域的所述钝化层、以及位于所述第二平坦过孔区域的所述平坦层进行第二次刻蚀，形成第一钝化过孔和至少一个第二平坦子过孔；所述至少一个第一平坦子过孔和所述至少一个第二平坦子过孔形成至少一个第二平坦过孔；所述第一钝化过孔和所述第一平坦过孔形成第一套孔；所述第一平坦过孔的孔深小于每一个所述第二平坦过孔的孔深；其中，所述第二次刻蚀的深度为所述第一钝化过孔的孔 深；所述第一钝化过孔的孔深大于或等于所述第二平坦过孔中的最大孔深与所述第一平坦过孔的孔深的差值。
  13. 根据权利要求12所述的制作方法，其中，所述方法还包括：
    形成保护层，所述保护层覆盖所述第一套孔；
    对位于所述第二平坦过孔区域的所述钝化层进行第三次刻蚀，形成至少一个第二钝化过孔；所述第二钝化过孔和所述第二平坦过孔形成第二套孔。
  14. 根据权利要求12所述的制作方法，其中，所述保护层的材料为光刻胶。
  15. 根据权利要求13所述的制作方法，其中，所述显示基板还包括衬底，所述钝化层和所述平坦层形成在所述衬底之上；
    在沿垂直于所述衬底的方向上，所述第一平坦子过孔和所述第二平坦子过孔的截面均包括相对的第一顶边和第一底边，所述第一顶边远离所述衬底，所述第一底边靠近所述衬底；所述第一顶边的长度大于所述第一底边的长度；
    所述第一平坦子过孔的所述第一底边的长度大于所述第二平坦子过孔的所述第一顶边的长度。
  16. 根据权利要求15所述的制作方法，其中，在所述形成钝化层和覆盖所述钝化层的平坦层之前，所述方法还包括：
    形成第一金属层，所述钝化层覆盖所述第一金属层；
    其中，所述第一金属层包括：位于所述非显示区的第一金属部和位于所述显示区的第二金属部。
  17. 根据权利要求16所述的制作方法，其中，所述第二次刻蚀还包括：
    在所述第一钝化过孔形成之后，露出所述第一金属部。
  18. 根据权利要求16所述的制作方法，其中，所述第三次刻蚀还包括：
    在所述至少一个第二钝化过孔形成之后，露出所述第二金属部。
  19. 根据权利要求18所述的制作方法，其中，所述第一金属层为源漏金属层，所述第二金属部包括源极和漏极。
  20. 根据权利要求19所述的制作方法，其中，在所述第三次刻蚀之后，所述方法还包括：
    在所述平坦层之上形成阳极，所述阳极通过位于所述源极上方的所述第二套孔与所述源极接触。
  21. 根据权利要求20所述的制作方法，其中，在所述形成第一金属层之前，所述方法还包括：
    依次形成有源层、栅绝缘层、栅极金属层和层间介质层；
    其中，所述第一金属层形成于所述层间介质层之上，所述有源层包括半导体部和位于所述半导体部两侧的导体化部，所述源极和所述漏极分别与所述导体化部电连接。
  22. 根据权利要求21所述的制作方法，其中，在所述依次形成有源层、栅绝缘层和栅极金属层之前，所述方法还包括：
    在所述衬底上形成位于所述显示区和所述非显示区的缓冲层。
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