WO2021181468A1 - Module semi-conducteur - Google Patents

Module semi-conducteur Download PDF

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Publication number
WO2021181468A1
WO2021181468A1 PCT/JP2020/010059 JP2020010059W WO2021181468A1 WO 2021181468 A1 WO2021181468 A1 WO 2021181468A1 JP 2020010059 W JP2020010059 W JP 2020010059W WO 2021181468 A1 WO2021181468 A1 WO 2021181468A1
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WO
WIPO (PCT)
Prior art keywords
insulating layer
layer
adhesive
semiconductor component
metal layer
Prior art date
Application number
PCT/JP2020/010059
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English (en)
Japanese (ja)
Inventor
夏目真志
中島邦彦
Original Assignee
太陽誘電株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 太陽誘電株式会社 filed Critical 太陽誘電株式会社
Priority to PCT/JP2020/010059 priority Critical patent/WO2021181468A1/fr
Publication of WO2021181468A1 publication Critical patent/WO2021181468A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks

Definitions

  • the present invention relates to a semiconductor module, for example, a semiconductor module for mounting a semiconductor component.
  • a semiconductor module in which an adhesive is applied on an insulating layer, a semiconductor component is placed on the insulating layer, and a metal layer is provided which connects to the semiconductor component through a through hole penetrating the adhesive and the insulating layer (for example, a patent).
  • Document 1 A semiconductor module is known in which an adhesive is applied on an insulating layer, a semiconductor component is placed on the insulating layer, and a metal layer is provided which connects to the semiconductor component through a through hole penetrating the adhesive and the insulating layer (for example, a patent). Document 1).
  • the present invention has been made in view of the above problems, and an object of the present invention is to improve heat dissipation from semiconductor parts.
  • the present invention is provided on a first insulating layer, a semiconductor component that is bonded to the upper surface of the first insulating layer via a first adhesive and has an electrode on the lower surface, and the lower surface of the first insulating layer.
  • It is a semiconductor module including a first insulating layer and a high thermal conductivity layer having a thermal conductivity higher than that of the first adhesive, which is not connected to a semiconductor component.
  • the high thermal conductive layer may overlap the region between the two electrodes on the lower surface of the semiconductor component in a plan view, and the region may be in contact with the first adhesive.
  • the planar shape of the first insulating layer is rectangular, and the two electrodes can be configured to extend in the stretching direction of the pair of opposite sides of the first insulating layer.
  • the width of the high thermal conductive layer in the arrangement direction of the two electrodes may be equal to or larger than the distance between the first metal layer and the high thermal conductive layer.
  • the semiconductor component is a bare chip having a transistor, and at least a part of the transistor may be provided in the region.
  • the high thermal conductive layer can be thicker than the total thickness of the first insulating layer and the first adhesive.
  • the first insulating layer, the first metal layer, the second insulating layer bonded to the high thermal conductive layer via a second adhesive, and the second insulating layer provided on the lower surface of the second insulating layer.
  • the second metal layer connected to the first metal layer through the insulating layer and the second through hole penetrating the second adhesive, and the second insulating layer and the second insulating layer provided on the lower surface of the second insulating layer.
  • the configuration may include a third metal layer connected to the high thermal conductive layer through a third through hole penetrating the adhesive.
  • the distance between the first metal layer and the high thermal conductive layer can be narrower than the distance between the second metal layer and the third metal layer in the second insulating layer.
  • the high thermal conductive layer can be made of a metal material.
  • heat dissipation from semiconductor parts can be improved.
  • FIG. 1 is a cross-sectional view of the semiconductor module according to the first embodiment.
  • 2 (a) and 2 (b) are plan views of the semiconductor module according to the first embodiment.
  • FIG. 3 is a plan view of the semiconductor module according to the first embodiment.
  • FIG. 4 is a cross-sectional view of the semiconductor module according to Comparative Example 1.
  • FIG. 5 is a cross-sectional view of the semiconductor module according to the first embodiment.
  • FIG. 6 is a cross-sectional view of the semiconductor module according to the first modification of the first embodiment.
  • FIG. 7 is a cross-sectional view of the semiconductor module according to the second embodiment.
  • 8 (a) to 8 (e) are cross-sectional views (No. 1) showing a method of manufacturing a semiconductor module according to the second embodiment.
  • FIG. 1 is a cross-sectional view of the semiconductor module according to the first embodiment.
  • 2 (a) and 2 (b) are plan views of the semiconductor module according to the first embodiment.
  • FIG. 3 is a plan
  • FIG. 9 is a cross-sectional view (No. 2) showing a method of manufacturing the semiconductor module according to the second embodiment.
  • 10 (a) to 10 (d) are cross-sectional views (No. 3) showing a method of manufacturing a semiconductor module according to the second embodiment.
  • FIG. 1 is a cross-sectional view of the semiconductor module according to the first embodiment.
  • 2 (a) to 3 are plan views of the semiconductor module according to the first embodiment.
  • FIG. 1 corresponds to a cross-sectional view taken along the line AA of FIGS. 2A to 3A.
  • FIG. 2A shows the insulating layer 10, the through hole 16, the semiconductor component 40, and the electrode 42.
  • FIG. 2B shows the insulating layer 10, the metal layers 14, 14a and the through hole 16.
  • FIG. 3 shows the metal layers 14, 14a, the insulating layer 20, the metal layers 24, 24a, and the through holes 26 and 26a.
  • an adhesive 12 (first adhesive) is provided on the upper surface of the insulating layer 10 (first insulating layer).
  • the insulating layer 10 is a resin insulating layer whose main material is a resin such as a polyimide resin, and has flexibility.
  • the thickness of the insulating layer 10 is, for example, 10 ⁇ m to 100 ⁇ m.
  • the adhesive 12 is a resin adhesive such as an epoxy resin adhesive.
  • the thickness of the adhesive 12 is, for example, 5 ⁇ m to 100 ⁇ m after curing.
  • the adhesive 12 is thinner than, for example, the insulating layer 10.
  • the adhesive 12 is preferably a resin material having excellent heat resistance and low dielectric properties.
  • the adhesive 12 may be selectively provided only in the region overlapping the semiconductor component 40 and in the vicinity thereof.
  • the semiconductor component 40 is adhered to the upper surface of the insulating layer 10 via an adhesive 12.
  • the lower surface of the semiconductor component 40 is a surface (front surface) provided with an active portion such as a transistor 44.
  • An electrode 42 is provided on the lower surface of the semiconductor component 40.
  • the semiconductor component 40 is, for example, a power transistor such as an IGBT (Insulated Gate Bipolar Transistor), a bipolar transistor, or a FET (Field Effect Transistor).
  • a semiconductor material such as Si, GaN or SiC is used for the transistor.
  • the semiconductor component 40 is, for example, a bare chip or a package in which a bare chip is sealed and mounted.
  • the package on which the bare chip is mounted is a package such as WLP (Wafer Level Package) or SIP (Single Inline Package).
  • the semiconductor component 40 is a bare chip of a horizontal transistor such as a GaN FET.
  • a transistor 44 is provided between the electrodes 42 on the lower surface of the semiconductor component 40.
  • the thickness of the semiconductor component 40 is, for example, 10 ⁇ m to 900 ⁇ m, for example, several hundred ⁇ m.
  • the electrode 42 is mainly made of, for example, copper, silver, gold or aluminum.
  • a through hole 16 (via) penetrating the insulating layer 10 and the adhesive 12 is provided, and a metal layer 14 is provided on the inner surface of the through hole 16 and the lower surface of the insulating layer 10.
  • the metal layer 14 (first metal layer) is electrically connected to the electrode 42 of the semiconductor component 40 via the through hole 16 (first through hole).
  • a metal layer 14a (high thermal conductive layer) is provided on the lower surface of the insulating layer 10.
  • the metal layer 14a is provided so as to overlap the semiconductor component 40 in a plan view.
  • the metal layers 14 and 14a are formed, for example, at the same time, and the materials and thicknesses are substantially the same as each other.
  • the metal layers 14 and 14a are mainly made of copper, for example.
  • the thickness of the metal layers 14 and 14a is, for example, 10 ⁇ m to several hundred ⁇ m, which is the thickness at which the through hole 16 is embedded.
  • the metal layers 14 and 14a are thicker than the insulating layer 10.
  • the metal layers 14 and 14a may be thinner than the insulating layer 10.
  • the metal layers 14 and 14a are not electrically connected.
  • the size of the through hole 16 is, for example, 50 ⁇ m to several mm, and is appropriately set depending on the size of the electrode 42.
  • An adhesive 22 (second adhesive) is provided under the insulating layer 10 so as to cover the metal layers 14 and 14a.
  • the insulating layer 20 (second insulating layer) is adhered to the insulating layer 10, the metal layers 14 and 14a via an adhesive 22.
  • the insulating layer 20 is a resin insulating layer whose main material is a resin such as a polyimide resin, and has flexibility.
  • the thickness of the insulating layer 20 is, for example, 10 ⁇ m to 100 ⁇ m.
  • the adhesive 22 is a resin adhesive such as an epoxy resin adhesive.
  • the thickness of the adhesive 12 is a thickness capable of covering the metal layers 14 and 14a from, for example, 5 ⁇ m after curing.
  • a metal layer 24 (second metal layer) is provided on the inner surface of the through hole 26 and the lower surface of the insulating layer 20, and a metal layer 24a (third metal layer) is provided on the inner surface of the through hole 26a and the lower surface of the insulating layer 20. There is.
  • the metal layers 24 and 24a are electrically connected to the metal layers 14 and 14a through the through holes 26 and 26a, respectively.
  • the metal layers 24 and 24a are formed, for example, at the same time, and the materials and thicknesses are substantially the same as each other.
  • the metal layers 24 and 24a are mainly made of copper, for example.
  • the thickness of the metal layers 24 and 24a is, for example, 10 ⁇ m to several hundred ⁇ m, which is the thickness at which the through holes 26 and 26a are embedded.
  • the size of the through holes 26 and 26a is, for example, 50 ⁇ m to several mm.
  • An insulating layer 28 is provided under the insulating layer 20 so as to cover the metal layers 24 and 24a. A part of the lower surfaces of the metal layers 24 and 24a is exposed from the opening 27 of the insulating layer 28.
  • the insulating layer 28 is, for example, a solder resist or a coverlay, and is a resin such as an epoxy resin.
  • the metal layers 24 and 24a exposed from the opening 27 function as terminals for connecting to the outside.
  • the thickness of the insulating layer 28 is, for example, several tens of ⁇ m.
  • a heat radiating plate 30 (heat radiating member) is bonded to the upper surface of the semiconductor component 40 via a bonding layer 34.
  • the bonding layer 34 is, for example, a sintered metal layer in which a conductive paste such as silver paste is sintered, or a brazing material such as solder.
  • the heat radiating plate 30 is a metal layer such as a copper layer or an aluminum layer, or an insulating layer such as aluminum oxide.
  • the heat radiating plate 30 may be a heat radiating plate in which an insulating layer such as DBC (Direct Bonded Cupper) or DBA (Direct Bonded Aluminum) is sandwiched between metal layers.
  • the thickness of the bonding layer 34 is, for example, several tens of ⁇ m, and the thickness of the heat radiating plate 30 is, for example, 100 ⁇ m to several mm.
  • a resin layer 32 is provided on the insulating layer 10 so as to surround the semiconductor component 40 and the heat radiating plate 30.
  • the upper surface of the heat radiating plate 30 is exposed from the resin layer 32.
  • the resin layer 32 is a thermosetting resin such as an epoxy resin or a thermoplastic resin.
  • the resin layer 32 may contain additives such as an inorganic filler. At least one of the heat radiating plate 30 and the resin layer 32 may not be provided.
  • the semiconductor component 40 is a horizontal transistor, and a source electrode SE, a drain electrode DE, and a gate electrode GE are provided as electrodes 42 on the lower surface (front surface) of the semiconductor component 40. ..
  • the sizes X1 and Y1 of the semiconductor component 40 are, for example, 4 mm and 6 mm.
  • the source electrode SE and the drain electrode DE are provided along the opposite sides of the lower surface of the semiconductor component 40, respectively.
  • the region 43 is a region between the drain electrode DE and the source electrode SE on the lower surface of the semiconductor component 40.
  • the distance L4 between the source electrode SE and the drain electrode DE in the region 43 is such that the voltage applied between the source electrode SE and the drain electrode DE does not cause dielectric breakdown between the source electrode SE and the drain electrode DE. Is set to.
  • the distance L4 is, for example, 100 ⁇ m to 10 mm.
  • the semiconductor component 40 is a GaN FET and 650 V is applied between the source electrode SE and the drain electrode DE, the distance L4 is, for example, 3 mm to 4 mm.
  • a through hole 16 is provided to connect to the electrode 42.
  • metal layers 14d, 14s, and 14g are provided as the metal layer 14.
  • the metal layers 14d, 14s, and 14g are connected to the drain electrode DE, the source electrode SE, and the gate electrode GE, respectively, via the through holes 16.
  • a metal layer 14a is provided between the metal layers 14d and 14s so as to overlap the region 43 (see FIG. 2A).
  • the distance L1 between the metal layers 14d and 14s and 14a is, for example, 0.1 ⁇ m or more. If the interval L1 is narrow, dielectric breakdown may occur between the metal layers 14d and 14s via the metal layer 14a.
  • the interval L1 is set in consideration of the voltage applied between the metal layers 14d and 14s (that is, the voltage applied between the drain electrode DE and the source electrode SE).
  • this voltage is 650 V
  • the total of the intervals L1 on both sides is, for example, 1.0 mm.
  • the width W1 of the metal layer 14a is, for example, 0.1 mm or more. It is preferable that the width of the metal layer 14a is wide after ensuring an interval L1 that does not cause dielectric breakdown.
  • the metal layer 24 functions as a drain terminal DT, a source terminal ST, and a gate terminal GT.
  • the drain terminal DT, the source terminal ST, and the gate terminal GT are connected to the metal layers 14d, 14s, and 14g, respectively, via the through holes 26.
  • the metal layer 24a functions as a thermal terminal TT and is connected to the metal layer 14a via a through hole 26a.
  • the distance L2 between the through holes 26 and 26a is narrower than the distance L1.
  • the distance L3 between the drain terminal DT and the source terminal ST and the thermal terminal TT is wider than the distance L2 and narrower than the distance L1.
  • the interval L3 is, for example, 0.1 mm or more.
  • the total of the intervals L3 on both sides is, for example, 1.8 mm.
  • the width W2 of the metal layer 24a is, for example, 0.1 mm or more. It is preferable that the width of the metal layer 24a is wide after ensuring an interval L2 that does not cause dielectric breakdown. When the interval L3 is wider than L1, the width W2 is narrower than W1.
  • FIG. 4 is a cross-sectional view of the semiconductor module according to Comparative Example 1.
  • the metal layers 14a and 24a and the through hole 26a are not provided.
  • a part of the heat generated in the semiconductor component 40 is released from the upper surface (back surface) of the semiconductor component 40 to the outside of the semiconductor module via the bonding layer 34 and the heat radiating plate 30 as shown by the arrow 50.
  • a part of the heat generated in the semiconductor component 40 is released from the electrode 42 on the lower surface (surface) of the semiconductor component 40 to the outside of the semiconductor module via the metal layers 14 and 24 as shown by the arrow 52.
  • heat dissipation may not be sufficient in the heat dissipation path of arrow 52.
  • the transistor 44 is provided between the electrodes 42, and it is difficult to provide an electrode for heat dissipation between the electrodes 42. If the heat dissipation is insufficient, the temperature of the lower surface of the semiconductor component 40 rises. For example, when the semiconductor component 40 is a power transistor, the on-resistance of the transistor increases as the temperature rises, and the efficiency decreases.
  • FIG. 5 is a cross-sectional view of the semiconductor module according to the first embodiment.
  • the metal layer 14a is provided on the lower surface of the insulating layer 10, overlaps the semiconductor component 40 in a plan view, and is not connected to the semiconductor component 40.
  • the semiconductor component 40 and the adhesive 12 are in contact with each other, the adhesive 12 and the insulating layer 10 are in contact with each other, and the insulating layer 10 and the metal layer 14a are in contact with each other. Therefore, the heat generated in the semiconductor component 40 is conducted to the metal layer 14a via the adhesive 12 and the insulating layer 10 as shown by the arrow 54, and is released to the outside through the metal layers 14a and 24a as shown by the arrow 56.
  • the heat of the semiconductor component 40 can be dissipated by the heat dissipation paths of arrows 54 and 56 in addition to the heat dissipation paths of arrows 50 and 52.
  • the temperature of the semiconductor component 40 can be lowered.
  • the metal layer 14a functions as a heat sink that stores heat. Therefore, the temperature of the semiconductor component 40 can be lowered.
  • the semiconductor component 40 is a power transistor, the temperature of the semiconductor component 40 can be lowered, so that the on-resistance can be lowered and the efficiency can be improved.
  • the metal layer 14a In order to more exert the function of the heat dissipation path of the metal layer 14a, it is necessary to reduce the thermal resistance between the region 43 between the drain electrode DE and the source electrode SE and the metal layer 14a on the lower surface of the semiconductor component 40. preferable. Further, in order to more exert the function of the metal layer 14a as a heat sink, it is preferable that the metal layer 14a has a large heat capacity.
  • the metal layer 14a overlaps the region 43 in a plan view. As a result, heat can be dissipated from the region 43 where a part of the transistor 44 is provided and the electrode 42 cannot be provided to the metal layer 14a via the adhesive 12 and the insulating layer 10. Further, it is preferable that the region 43 is in contact with the adhesive 22. Thereby, the thermal resistance between the region 43 and the metal layer 14a can be reduced.
  • the planar shape of the insulating layer 10 is rectangular, and the drain electrode DE and the source electrode SE are stretched in the stretching direction of the pair of opposite sides of the insulating layer 10.
  • the area of the metal layer 14a can be increased by providing the metal layer 14a so as to overlap the region 43. Therefore, the thermal resistance between the region 43 and the metal layer 14a can be lowered, and the heat capacity of the metal layer 14a can be increased.
  • the width W1 of the metal layer 14a is preferably the interval L1 or more, and more preferably 1.5 times or more the interval L1.
  • the metal layer 14a is preferably thicker than the total thickness of the insulating layer 10 and the adhesive 12. As a result, the thermal resistance between the region 43 and the metal layer 14a via the adhesive 12 and the insulating layer 10 can be reduced, and the heat capacity of the metal layer 14a can be increased.
  • the width W1 of the metal layer 14a is preferably not more than the width of the through hole 16 in contact with the electrode 42, and more preferably 1.5 times or more of this width.
  • the semiconductor component 40 is a bare chip having a transistor 44, and at least a part of the transistor 44 is provided between the drain electrode DE and the source electrode SE. At this time, the electrode for heat dissipation cannot be formed in the region 43, and the metal layer 14 cannot be brought into contact with the region 43. Therefore, a metal layer 14a is provided under the region 43 via the adhesive 12 and the insulating layer 10. As a result, the heat generated in the transistor 44 can be released to the metal layer 14a as shown by the arrow 54.
  • the volumes of the metal layers 14a and 24a can be made larger than the volume of the metal layer 14a having only one layer. Therefore, the function as a heat sink can be further improved.
  • the metal layer 14 can be used as a rewiring layer for rewiring the connection between the electrode 42 and the metal layer 24. This improves the degree of freedom in design.
  • the withstand voltage performance of the insulating layer 28 may be inferior to the withstand voltage performance of the adhesive 12.
  • the distance L1 between the metal layers 14 and 14a is made shorter than the distance L3 between the metal layers 24 and 24a.
  • the width W2 of the metal layer 24a is narrower than the width W1 of the metal layer 14a.
  • the adhesive 12, and the withstand voltage performance the interval L1 may be wider than L3.
  • the width W2 may be wider than W1.
  • Heat resistance is improved by using the insulating layers 10 and 20 as polyimide layers.
  • the semiconductor module can be applied to a high-speed switching or a high-frequency amplifier.
  • FIG. 6 is a cross-sectional view of the semiconductor module according to the first modification of the first embodiment.
  • the insulating layer 20, the adhesive 22, and the metal layers 24 and 24a are not provided.
  • the insulating layer 28 is provided under the insulating layer 10 so as to cover the metal layers 14 and 14a.
  • the lower surfaces of the metal layers 14 and 14a are exposed from the opening 27 of the insulating layer 28.
  • Other configurations are the same as those in the first embodiment, and the description thereof will be omitted.
  • the metal layer may be one layer.
  • FIG. 7 is a cross-sectional view of the semiconductor module according to the second embodiment.
  • an insulating layer 15 is provided instead of the metal layer 14a.
  • the insulating layer 15 is an inorganic insulator such as a high thermal conductive ceramic containing silicon carbide, aluminum nitride, alumina, or the like.
  • the thermal conductivity of the insulating layer 15 is greater than the thermal conductivity of the insulating layers 10, 20, and the adhesives 12 and 22.
  • the thickness of the insulating layer 15 is, for example, several tens of ⁇ m. Other configurations are the same as those in the first embodiment, and the description thereof will be omitted.
  • the high thermal conductive layer may be a metal layer 14a or an insulating layer 15.
  • the thermal conductivity of the polyimide used as the insulating layers 10 and 20 and the epoxy resin used as the adhesives 12 and 22 is 1 W / m ⁇ K or less.
  • the thermal conductivity of copper used as the high thermal conductive layer is 400 W / m ⁇ K, and the thermal conductivity of silicon carbide and aluminum nitride is 100 W / m ⁇ K or more.
  • the thermal conductivity of the high thermal conductive layer is preferably larger than the thermal conductivity of the insulating layers 10 and 20, and the adhesives 12 and 22.
  • the thermal conductivity of the layers 10, 20, and the adhesives 12 and 22 is preferably 10 times or more, more preferably 100 times or more.
  • the high thermal conductivity layer is preferably made of a metal material. Further, the heat radiating plate 30 may not be provided.
  • the adhesive 12 is applied to the upper surface of the insulating layer 10.
  • the adhesive 12 for example, a spin coating method, a spray coating method, an inkjet method or a screen printing method is used.
  • the adhesive 12 is applied to the entire surface on the insulating layer 10, but the adhesive 12 may be selectively applied to the region overlapping the semiconductor component 40 and its vicinity.
  • the semiconductor component 40 is brought into contact with the upper surface of the adhesive 12.
  • the adhesive 12 is cured and the semiconductor component 40 and the insulating layer 10 are adhered to each other.
  • the heat treatment is carried out at a temperature of, for example, 100 ° C to 300 ° C.
  • a through hole 16 penetrating the insulating layer 10 and the adhesive 12 is formed.
  • the through hole 16 is formed by, for example, irradiating a laser beam. As a result, the lower surface of the electrode 42 is exposed from the through hole 16.
  • the through hole 16 may be formed before mounting the semiconductor component 40 on the adhesive 12.
  • a metal layer 14 is formed on the lower surface of the insulating layer 10 and the inner surface of the through hole 16.
  • the metal layer 14 is connected to the electrode 42 via the through hole 16.
  • the metal layer 14 is formed by, for example, the following method.
  • a seed layer is formed on the lower surface of the insulating layer 10 and the inner surface of the through hole 16.
  • the seed layer is formed by, for example, a sputtering method or an electroless plating method.
  • the seed layer is used as an electrode, and a plating layer is formed on the lower surface of the seed layer by an electrolytic plating method.
  • the plating layer is processed into a desired conductive pattern using a photolithography method and an etching method.
  • the metal layer 14 forms the pad electrode, the wiring, and the wiring integrally formed with the pad electrode.
  • the adhesive 22a is applied to the lower surfaces of the insulating layer 10 and the metal layer 14 (upper surface in FIG. 8E).
  • the method of applying the adhesive 22a is the same as that shown in FIG. 8 (a).
  • the ring 64 to which the insulating layer 10 is attached is arranged on the table 60.
  • a jig 62 is provided between the table 60 and the semiconductor component 40.
  • the insulating layer 15 is pressed by the mounter 66 in the direction shown by the arrow. As a result, the insulating layer 15 is attached to the adhesive 22a. Since the insulating layer 10 has flexibility, the insulating layer 15 is embedded in the adhesive 22a by using the jig 62.
  • the insulating layer 15 is embedded in the adhesive 22a.
  • the adhesive 22a may or may not remain between the insulating layer 10 and the insulating layer 15.
  • an adhesive is additionally applied to the lower surface of the adhesive 22a and the insulating layer 15.
  • the adhesive 22 that covers the metal layer 14 and the insulating layer 15 is formed under the insulating layer 15.
  • the insulating layer 20 is attached under the adhesive 22.
  • the adhesive 22 is cured to bond the insulating layer 10, the metal layer 14, the insulating layer 15 and the insulating layer 20.
  • through holes 26 and 26a penetrating the insulating layer 20 and the adhesive 22 are formed in the same manner as in FIG. 8 (c). Similar to FIG. 8D, the metal layers 24 and 24a are formed on the lower surface of the insulating layer 20 and the inner surfaces of the through holes 26 and 26a. The metal layers 24 and 24a are connected to the metal layer 14 and the insulating layer 15 through the through holes 26 and 26a. An insulating layer 28 having an opening 27 is formed under the insulating layer 20.
  • a resin layer 32 for sealing the semiconductor component 40 is formed on the insulating layer 10.
  • a transfer molding method, an injection method, or a compression method is used for the formation of the resin layer 32.
  • the semiconductor module of the second embodiment shown in FIG. 7 is manufactured.
  • the metal layer 14a is formed at the same time as the metal layer 14 in FIG. 8 (d). Further, in FIG. 10D, the heat radiating plate 30 is joined to the upper surface of the semiconductor component 40. Other manufacturing methods are the same as those of Example 2.

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  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

La présente invention comprend : une première couche isolante 10; un composant semi-conducteur 40 qui est collé à une surface supérieure de la première couche isolante par l'intermédiaire d'un premier adhésif 12, et a une électrode 42 sur une surface inférieure; une première couche métallique 14 qui est disposée sur une surface inférieure de la première couche isolante et est connectée à l'électrode par l'intermédiaire d'un premier trou traversant 16 qui pénètre dans la première couche isolante et le premier adhésif; et une couche hautement thermoconductrice qui est disposée sur la surface inférieure de la première couche isolante, chevauche le composant semi-conducteur dans une vue en plan, n'est pas connectée au composant semi-conducteur, et a une conductivité thermique qui est supérieure à la conductivité thermique de la première couche isolante et du premier adhésif.　
PCT/JP2020/010059 2020-03-09 2020-03-09 Module semi-conducteur WO2021181468A1 (fr)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20220149020A1 (en) * 2020-11-10 2022-05-12 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure, semiconductor device and manufacturing method thereof

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