WO2021180120A1 - 静电保护电路、集成电路及静电泄放方法 - Google Patents

静电保护电路、集成电路及静电泄放方法 Download PDF

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Publication number
WO2021180120A1
WO2021180120A1 PCT/CN2021/079970 CN2021079970W WO2021180120A1 WO 2021180120 A1 WO2021180120 A1 WO 2021180120A1 CN 2021079970 W CN2021079970 W CN 2021079970W WO 2021180120 A1 WO2021180120 A1 WO 2021180120A1
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Prior art keywords
pad
electrostatic
transistor
detection unit
inverter
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English (en)
French (fr)
Inventor
许杞安
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to US17/595,464 priority Critical patent/US11721688B2/en
Publication of WO2021180120A1 publication Critical patent/WO2021180120A1/zh
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
    • H02H9/045—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere
    • H02H9/046—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere responsive to excess voltage appearing at terminals of integrated circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/811—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using FETs as protective elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/811—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using FETs as protective elements
    • H10D89/819—Bias arrangements for gate electrodes of FETs, e.g. RC networks or voltage partitioning circuits

Definitions

  • This application relates to the field of integrated circuits, in particular to an electrostatic protection circuit, an integrated circuit and an electrostatic discharge method.
  • the electrostatic discharge protection circuit (ESD circuit) is used to provide a low-impedance current path to discharge the electrostatic charge.
  • ESD circuit The electrostatic discharge protection circuit
  • main design considerations for the existing ESD protection include layout area, startup current, leakage current from VDD to VSS, and mechanism for avoiding false triggers in operation.
  • the purpose of the present invention is to provide an electrostatic protection circuit, an integrated circuit, and an electrostatic discharge method, which can discharge static electricity more thoroughly and improve the protection effect of the protected circuit.
  • an electrostatic protection circuit including: a pulse detection unit for detecting electrostatic pulses, the first end of which is connected to the first pad, the second end of which is connected to the second pad, and the output end Output a detection result signal; a bleeder transistor, the gate is connected to the pulse detection unit, the drain is connected to the first pad, and the source is connected to the second pad for connecting to the first pad Or when the second pad has static electricity, the source and the drain are connected to discharge the electrostatic charge; the processing unit is respectively connected to the pulse detection unit and the discharge transistor for detecting according to the detection
  • the result signal controls the on and off of the bleeder transistor, and the processing unit includes: a feedback delay circuit for extending the on time of the bleeder transistor when the electrostatic charge is discharged, the feedback delay circuit It includes: a first PMOS tube, a source connected to the first pad, and a gate connected to the pulse detection unit; a first NMOS tube, a source connected to the second pad, and
  • the processing unit further includes: an inverter group, including at least one inverter, arranged between the feedback delay circuit and the pulse detection unit.
  • the inverter group includes a first inverter connected to the pulse detection unit, and a second inverter connected to the feedback delay circuit.
  • the first inverter includes: a second PMOS transistor, a source is connected to the first pad, a gate is connected to the pulse detection unit, and a drain is connected to the input terminal of another inverter A second NMOS tube, the source is connected to the source of the second PMOS tube, the gate is connected to the pulse detection unit, and the drain is connected to the second pad;
  • the second inverter includes: Three PMOS transistors, the source is connected to the first pad, the gate is connected to the output of the previous inverter, and the drain is connected to the input of the feedback delay circuit; the third NMOS transistor, the source is connected to the The source and gate of the second PMOS transistor are connected to the output terminal of the previous inverter, and the drain is connected to the second pad.
  • the pulse detection unit includes: a second resistor, one end is connected to the first pad, and the other end is connected to the input terminal of the feedback delay circuit; a capacitor, one end is connected to the second pad , The other end is connected to the input end of the feedback delay circuit.
  • the product of the second resistance and the capacitance is at least 0.08 to 0.7, and the unit is microseconds.
  • the bleeder transistor includes a fourth NMOS transistor, the drain of the fourth NMOS transistor is connected to the first pad, the source is connected to the second pad, and the gate is connected to the output of the processing unit. end.
  • the on-time of the discharge transistor when discharging the electrostatic charge is at least 0.1 to 1 microsecond.
  • the following also provides an integrated circuit, including the electrostatic protection circuit, for discharging static electricity to the pads on the integrated circuit.
  • the electrostatic discharge method using the electrostatic protection circuit includes the following steps: providing a bleeder transistor, the bleeder transistors are respectively connected to the electrostatic discharge The first area and the second area of the bleeder protection; control the bleeder transistor to be turned on when there is electrostatic charge on the surface of the first area and the second area, and the conduction time is at least a preset time period; control the The bleeder transistor is turned off when there is no need to discharge static electricity.
  • the electrostatic protection circuit, integrated circuit, and electrostatic discharge method in this application ensure the conduction time of the discharge transistor when discharging electrostatic charge, ensure that the discharge of electrostatic charge is more thorough, and prevent electrostatic charge from acting on the victim. Protect the functional circuit, causing damage to the functional circuit.
  • the conduction time of the bleeder transistor can be prolonged through feedback, so the requirement on the pulse detection unit can be reduced, so that there is no need to provide a pulse detection unit with a larger time constant, which can have enough
  • the long conduction time ensures sufficient discharge of electrostatic charges.
  • the electrostatic protection circuit further includes an inverter group, which can amplify and buffer electrical signals, buffer some electrical signal noise, prevent noise from affecting the electrostatic protection circuit, and ensure that a sufficiently large voltage can drive the electrical signal.
  • the bleeder transistor is turned on.
  • FIG. 1 is a schematic diagram of the connection relationship of the electrostatic protection circuit in an embodiment of the application.
  • FIG. 2 is a schematic diagram of the connection relationship of the electrostatic protection circuit in an embodiment of the application.
  • FIG. 3 is a schematic diagram of the connection relationship of the electrostatic protection circuit in an embodiment of the application.
  • FIG. 4 is a schematic diagram of the process flow of the electrostatic discharge method in an embodiment of the application.
  • the bleed-on time of the bleeder transistor of the electrostatic protection circuit can be prolonged.
  • an excessively large RC time constant will lead to the required
  • the increase in capacitance or resistance directly leads to an increase in the size of the capacitance or resistance, which affects the layout design of the integrated circuit.
  • the time constant of the RC time constant is related to the product of the resistance and the capacitance in the pulse detection unit in the electrostatic protection circuit. It is necessary to set a large enough capacitance or resistance to make the bleeder transistor have enough turn-on time. However, the size of a sufficiently large capacitor or resistor is also large, which consumes a lot of layout space of the integrated circuit. For example, to set the time constant of the pulse detection unit to 0.1 to 1 microsecond, it is necessary to set the R of 50Kohm N+ diffusion resistance and C of 20pF NMOS capacitor on the surface of the circuit board, which will occupy a relatively large layout space and also cause static electricity. The protection circuit is easily affected by noise.
  • FIG. 1 is a schematic diagram of the connection relationship of the electrostatic protection circuit in an embodiment of the application.
  • an electrostatic protection circuit including: a pulse detection unit 105 for detecting electrostatic pulses, the first end of which is connected to the first pad 102, the second end of which is connected to the second pad 103, The output terminal outputs the detection result signal; the bleeder transistor 104, the gate is connected to the pulse detection unit 105, the drain is connected to the first pad 102, and the source is connected to the second pad 103, for When the first pad 102 or the second pad 103 has static electricity, the source and drain are connected to discharge the electrostatic charge; the processing unit 101 is respectively connected to the pulse detection unit 105, and the The bleeder transistor 104 is used to control the on and off of the bleeder transistor 104 according to the detection result signal. Referring to FIG.
  • the processing unit 101 includes: a feedback delay circuit 202 for extending the bleeder The turn-on time of the discharge transistor 104 when the electrostatic charge is discharged.
  • the feedback delay circuit 202 includes: a first PMOS tube M5, the source is connected to the first pad 102, and the gate is connected to the pulse detection unit 105; An NMOS transistor M6, the source is connected to the second pad 103, the drain is connected to the pulse detection unit 105, and the gate is connected to the drain of the first PMOS transistor M5; Between the gate of an NMOS transistor M6 and the second pad 103.
  • the electrostatic protection circuit in this embodiment has a feedback delay circuit 202, which can extend the on-time of the bleeder transistor 104 when the electrostatic charge is discharged, without the need to set a larger capacitor to extend the bleeder transistor 104
  • the electrostatic charge discharge time is longer, the layout space of the integrated circuit is less occupied, and the electrostatic charge is discharged more thoroughly.
  • the pulse detection unit 105 includes: a second resistor R1, one end is connected to the first pad 102, the other end is connected to the input terminal of the feedback delay circuit 202; a capacitor C1, one end It is connected to the second pad 103, and the other end is connected to the input terminal of the feedback delay circuit 202.
  • the equivalent resistance of the capacitor C1 when the two pads have static electricity will change, causing the potential change at point 1 in FIG. 2 to be output to the feedback delay circuit 202 as a detection result signal .
  • the feedback delay circuit 202 drives or does not drive the bleeder transistor MESD according to the detection result signal.
  • the product of the second resistance R1 and the capacitor C1 of the pulse detection unit 105 directly affects the electrostatic discharge time of the electrostatic protection circuit during a single electrostatic discharge process.
  • the product of the second resistance R1 and the capacitor C1 of the pulse detection unit 105 is equal to the time constant of the pulse detection unit 105, and the time constant is related to the conduction time of the discharge transistor 104 when discharging electrostatic charges, The larger the product of the second resistor R1 and the capacitor C1 of the pulse detection unit 105 is, the longer the conduction time of the bleeder transistor 104 is, and the more thoroughly the electrostatic charge on the pad is discharged.
  • the product of the second resistor R1 and the capacitor C1 is at least 0.08 to 0.7, and the unit is microseconds.
  • the feedback delay circuit 202 is provided to reduce the requirement on the time constant of the pulse detection unit 105.
  • the feedback delay circuit 202 can effectively prolong the conduction time of the two pads when the electrostatic charge needs to be discharged, so it can effectively reduce the requirements on the time constant of the pulse detection unit 105, and prevent the excessive capacitance C1 from affecting the integrated circuit. Occupation of layout space.
  • the on-time of the bleeder transistor 104 is large enough to ensure the full discharge of electrostatic charges.
  • the on-time of the discharge transistor 104 when discharging electrostatic charges is at least 0.1 to 1 microsecond.
  • the pulse detection unit 105, the feedback delay circuit 202 and the bleeder transistor 104 are connected in sequence.
  • the pulse detection unit 105 and the feedback delay circuit 202 control the bleeder transistor 104 to turn on when there is electrostatic charge on the first pad 102 or the second pad 103, and reduce the electrostatic charge of the first pad 102.
  • the electrostatic charge of the second pad 103 is discharged to the second pad 103 or the electrostatic charge of the second pad 103 is discharged to the first pad 102.
  • the electrostatic protection circuit can protect the functional circuit to which the first pad 102 and the second pad 103 are connected, release the electrostatic charge on the pad, and prevent the electrostatic charge from moving to the functional circuit. , Resulting in the failure of the functional circuit.
  • the bleeder transistor 104 includes a fourth NMOS tube MESD, the drain of the fourth NMOS tube MESD is connected to the first pad 102, the source is connected to the second pad 103, and the gate Connected to the output terminal of the processing unit 101.
  • the bleeder transistor 104 is an NMOS tube, which is suitable for high-level driving. Therefore, in this embodiment, the processing unit 101 should output a high level to drive the bleeder transistor 104 to turn on when there is static electricity.
  • a PMOS tube can also be used as the bleeder transistor 104.
  • the specific structure of the processing unit 101 needs to be modified so that the processing unit 101 outputs a low level to drive the bleeder transistor 104 to turn on.
  • the processing unit 101 further includes an inverter group 201 including at least one inverter, which is arranged between the feedback delay circuit 202 and the pulse detection unit 105.
  • the inverter group 201 arranged in the feedback delay circuit 202 and the pulse detection unit 105 can invert and amplify the detection result signal from the pulse detection unit 105, so that the signal finally output to the bleeder transistor 104 It is large enough to drive the bleeder transistor 104.
  • the number of inverters in the inverter group 201 is even, and the signal output from the inverter group 201 is in phase with the detection result signal. In another implementation, if the number of inverters in the inverter group 201 is singular, the signal output from the inverter group 201 is inverted from the detection result signal.
  • the inverter group 201 includes a first inverter connected to the pulse detection unit 105 and a second inverter connected to the feedback delay circuit 202. This makes the detection result signal need to be inverted and amplified at least twice before it can flow to the feedback delay circuit 202 and the bleeder transistor 104. Since the signal output to the inverter group 201 is inverted and amplified at least twice, the signal output to the inverter group 201 can be rectified, and some electrical noise can be filtered out to prevent some noise signals This affects the conduction state of the bleeder transistor 104. In other embodiments, the number of inverters in the inverter group 201 can be set as required.
  • the first inverter includes: a second PMOS transistor M1, a source is connected to the first pad 102, and a gate is connected to the pulse detection unit 105 as the first inverter.
  • the input terminal of the inverter, the drain as the output terminal of the first inverter, is connected to the input terminal of another inverter; the second NMOS transistor M2, the drain is connected to the drain of the second PMOS transistor M1
  • the gate is connected to the gate of the second PMOS transistor M1, and the source is connected to the second pad 103;
  • the second inverter includes: a third PMOS transistor M3, and the source is connected to the first A pad 102, the gate is used as the input terminal of the second inverter, connected to the output terminal of the previous inverter, and the drain is used as the output terminal of the second inverter, connected to the feedback delay
  • the input terminal of the circuit 202; the third NMOS tube M4, the drain is connected to the drain of the third PMOS tube M3, the gate is connected to the gate
  • the inverter group 201 only includes the first inverter and the second inverter.
  • the electrical signal input at point is inverted and amplified for the first time, the output terminal of the first inverter is connected to the input terminal of the second inverter, and the second inverter performs the first inverter on the first inverter.
  • the output of the phaser is inverted and amplified twice.
  • the pulse detection unit 105 is connected before the inverter group 201, and the feedback delay circuit 202 is connected after the inverter group 201.
  • the feedback delay circuit 202 realizes the delay effect on the bleeder conduction time of the bleeder transistor 104.
  • the fourth NMOS transistor MESD is a high-level conductive device. Therefore, when a high level is provided at the fourth point in FIG. 2, the fourth NMOS transistor MESD is turned on, and when a low voltage is provided at the fourth point in FIG. 2, the fourth NMOS transistor MESD is turned off.
  • the first pad 102 is used as a power supply terminal with VDD applied, and the second pad 103 is grounded.
  • the first point in FIG. 2 is at a high level. After the reverse of the two inverters of the inverter group 201, the third point in FIG. 2 is still high.
  • the input terminal of the feedback delay circuit 202 is connected to point 3 in FIG. 2 at high level, the gate voltage of the first PMOS tube M5 is at high level, and the first PMOS tube M5 is not conducting.
  • the equivalent resistance between the source and drain of the first PMOS tube M5 is much larger than the first resistance R2. Therefore, the 4 points in the figure are divided into low level (approximately VSS), and the first NMOS tube and the fourth The NMOS transistor MESD is turned off, and the first pad 102 and the second pad 103 are not connected through the fourth NMOS transistor MESD.
  • the first point in FIG. 2 is at a low level. After passing through two inverters, the level at the third point in FIG. 2 is also Is low level, therefore, the gate of the first PMOS tube M5 is connected to the low level and turned on. At this time, the equivalent resistance between the source and drain of the first PMOS tube is much smaller than the first resistance R2, Therefore, the 4 points in the figure are high level (approximately VDD) after voltage division, and then the fourth NMOS transistor MESD is turned on, and the electrostatic charge on the first pad 102 is discharged to the second pad 103 .
  • the gate of the first NMOS transistor M6 is also connected to the high level at point 4 in FIG. 2, so the first NMOS transistor M6 is turned on, and the first resistor R2 can maintain the first NMOS transistor. High level of M6 gate.
  • the drain of the first NMOS transistor M6 is also at low level and is connected to The gate of the first PMOS transistor of the drain of the first NMOS transistor M6 is also a low level VSS, the first PMOS transistor can continue to be turned on, and the gate of the fourth NMOS transistor MESD is supplied to the first The high level VDD on the pad 102 turns on the fourth NMOS transistor MESD, connects the first pad 102 and the second pad 103, and maintains the discharge of electrostatic charges. This can prolong the conduction time of the two pads when there is static electricity on the pads, and ensure that the electrostatic charge is fully discharged.
  • the capacitive reactance of the capacitor C1 gradually increases as the electrostatic charge is discharged
  • the voltage at the first point in FIG. 2 also gradually increases, but due to the use of the feedback delay circuit 202 Therefore, the conduction time of the two pads can be prolonged, and the electrostatic charge of the first pad 102 can be guaranteed to have enough time to flow to the second pad 103 to realize the discharge of the electrostatic charge.
  • the above embodiment is the working principle when the first pad 102 has static electricity.
  • FIG. 3 is the connection relationship of the electrostatic protection circuit in an embodiment of the application. Schematic.
  • the parasitic capacitance Dp of the fourth NMOS tube MESD can be used to realize the discharge of the electrostatic charge, which will not be analyzed here.
  • the on-time of the discharge transistor 104 when discharging the electrostatic charge is at least 0.1 to 1 microsecond. This ensures the electrostatic charge discharge effect of the electrostatic protection circuit.
  • the electrostatic protection circuit is connected to two pads at the same time, so the functional circuits connected to the two pads have a protective effect, whether it is the occurrence of static electricity on the first pad 102 or the second welding
  • the electrostatic protection capability of the electrostatic protection circuit is relatively strong.
  • an integrated circuit including the static electricity protection circuit, which is used to discharge static electricity for the pads on the integrated circuit.
  • the integrated circuit can protect the functional circuit from electrostatic damage.
  • the electrostatic protection circuit has a feedback delay circuit 202, the time of discharging static electricity can be prolonged, and the static electricity on the pads can be completely discharged as much as possible, thus ensuring the protection effect of the electrostatic protection circuit and improving The antistatic ability of the integrated circuit is improved.
  • FIG. 4 is a schematic flow chart of the steps of an electrostatic discharge method in an embodiment of the present application.
  • an electrostatic discharge method is provided.
  • the electrostatic discharge method using the electrostatic protection circuit includes the following steps: S41 provides a bleeder transistor 104, and the bleeder transistors 104 are respectively connected to The first area and the second area protected by electrostatic discharge; S42 controls the discharge transistor 104 to be turned on when there is electrostatic charge on the surface of the first area and the second area, and the conduction time is at least a preset time period; S43 controls the discharge transistor 104 to turn off when there is no need to discharge static electricity.
  • a sufficiently long turn-on duration of the bleeder transistor 104 can be set to ensure that the electrostatic charge in the first area can be sufficiently discharged to prevent the electrostatic charge connected to the first area and the second area.
  • the functional circuit is affected by the undischarged electrostatic charge.
  • the preset time length is 0.1 to 1 microsecond, so the on-time length of the bleeder transistor 104 when it needs to discharge static electricity is at least 0.1 to 1 microsecond.
  • the bleeder transistor 104 is also connected to the pulse detection unit 105 and the processing unit 101.
  • the first end of the pulse detection unit 105 is connected to the first area, the second end is connected to the second area, and the output end outputs
  • the detection result signal is sent to the processing unit 101, and the pulse detection unit 105 and the processing unit 101 ensure the conduction time.
  • the discharge transistor 104 is controlled to be turned off when there is no need to discharge static electricity. In this way, when there is no electrostatic charge on the surface of the first area and the second area to discharge, the first area and the second area The functional circuit connected to the second area can work normally.

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Abstract

该申请涉及一种静电保护电路、集成电路及静电泄放方法，其中所述静电保护电路包括脉冲检测单元，用于检测静电脉冲，其第一端连接第一焊盘，其第二端连接第二焊盘，其输出端输出检测结果信号；泄放晶体管，栅极连接至所述脉冲检测单元，漏极连接至所述第一焊盘，源极连接至所述第二焊盘，用于在所述第一焊盘或第二焊盘有静电时使源极、漏极之间导通，以泄放静电电荷；处理单元，分别连接至所述脉冲检测单元，以及所述泄放晶体管，用于根据所述检测结果信号控制所述泄放晶体管的导通和关断，所述处理单元包括：反馈延时电路，用于延长所述泄放晶体管泄放静电电荷时的导通时长。

Description

静电保护电路、集成电路及静电泄放方法
相关申请引用说明
本申请要求于2020年03月12日递交的中国专利申请号202010169211.3，申请名为“静电保护电路、集成电路及静电泄放方法”的优先权，其全部内容以引用的形式附录于此。
技术领域
本申请涉及集成电路领域，具体涉及一种静电保护电路、集成电路及静电泄放方法。
背景技术
静电放电防护电路(electrostatic discharge protection circuit,ESD circuit)是用以提供一低阻抗的电流路径，以将静电电荷导出。一般来说，现有静电放电防护的主要设计考虑包含有布局面积、启动电流、VDD至VSS的漏电流、以及操作上错误触发的避免机制。
现有技术中常出现静电电荷泄放不够彻底的问题，在这种情况下，静电保护电路的静电保护效果不佳，焊盘上未被泄放的静电电荷仍有可能作用到功能电路，毁损被静电保护电路保护的功能电路，严重影响集成电路的使用寿命。
发明内容
本发明的目的在于提供一种静电保护电路、集成电路及静电泄放方法，能够更彻底的泄放静电，提高对被保护的电路的保护效果。
为了解决上述技术问题，以下提供了一种静电保护电路，包括：脉冲检测单元，用于检测静电脉冲，其第一端连接第一焊盘，其第二端连接第二焊盘，其输出端输出检测结果信号；泄放晶体管，栅极连接至所述脉冲检测单元，漏极连接至所述第一焊盘，源极连接至所述第二焊盘，用于在所述第一焊盘或第二焊盘有静电时使源极、漏极之间导通，以泄放静电电荷；处理单元，分别连接至所述脉冲检测单元，以及所述泄放晶体管，用于根据所述检测结果信号控制所述泄放晶体管的导通和关断，所述处理单元包括：反馈延时电路，用于延长所述泄放晶体管泄放静电电荷时的导通时长，所述反馈延时电路包括：第一PMOS管，源极连接所述第一焊盘，栅极连接所述脉冲检测单元；第一NMOS管，源极连接所述第二焊盘，漏极连接所述脉冲检测单元，栅极连接所述第一 PMOS管的漏极；第一电阻，设置于所述第一NMOS管的栅极与所述第二焊盘之间。
可选的，所述处理单元还包括：反相器组，包括至少一个反相器，设置于所述反馈延时电路与所述脉冲检测单元之间。
可选的，所述反相器组包括连接到脉冲检测单元的第一反相器，以及连接至所述反馈延时电路的第二反相器。
可选的，所述第一反相器包括：第二PMOS管，源极连接所述第一焊盘，栅极连接至所述脉冲检测单元，漏极连接至另一反相器的输入端；第二NMOS管，源极连接所述第二PMOS管的源极，栅极连接至所述脉冲检测单元，漏极连接至所述第二焊盘；所述第二反相器包括：第三PMOS管，源极连接所述第一焊盘，栅极连接至上一反相器的输出端，漏极连接至所述反馈延时电路的输入端；第三NMOS管，源极连接所述第二PMOS管的源极，栅极连接至上一反相器的输出端，漏极连接至所述第二焊盘。
可选的，所述脉冲检测单元包括：第二电阻，一端连接至所述第一焊盘，另一端连接至所述反馈延时电路的输入端；电容，一端连接至所述第二焊盘，另一端连接至所述反馈延时电路的输入端。
可选的，所述第二电阻和电容的乘积至少为0.08到0.7，单位为微秒。
可选的，所述泄放晶体管包括第四NMOS管，所述第四NMOS管的漏极连接至第一焊盘，源极连接至第二焊盘，栅极连接至所述处理单元的输出端。
可选的，所述泄放晶体管泄放静电电荷时的导通时长至少为0.1至1微秒。
为了解决上述技术问题，以下还提供了一种集成电路，包括所述的静电保护电路，用于为所述集成电路上的焊盘泄放静电。
为了解决上述技术问题，以下还提供了一种静电泄放方法，利用所述的静电保护电路进行静电泄放，包括以下步骤：提供一泄放晶体管，所述泄放晶体管分别连接到需进行静电泄放保护的第一区域以及第二区域；控制所述泄放晶体管在所述第一区域和第二区域表面有静电电荷时导通，且导通时长至少为一预设时长；控制所述泄放晶体管在无需泄放静电时关断。
本申请中的静电保护电路、集成电路及静电泄放方法保证了所述泄放晶体管在泄放静电电荷时的导通时长，尽可能保证静电电荷泄放的更加彻底，防止 静电电荷作用到被保护的功能电路，造成功能电路的毁损。
并且，由于具有反馈延时电路，能够通过反馈延长所述泄放晶体管的导通时间，因此可以降低对脉冲检测单元的要求，使得无需设置具有较大时间常数的脉冲检测单元，即可具有足够长的导通时长，保证对静电电荷的泄放充分。这样，在保证所述泄放晶体管的导通时长的同时，还能够减小脉冲检测单元中的元器件对集成电路的布图空间的占用。进一步的，所述静电保护电路还包括反相器组，能够对电信号进行放大缓冲，缓冲掉部分电信号噪声，防止噪声对所述静电保护电路的影响，并保证能够足够大的电压驱动所述泄放晶体管导通。
附图说明
为了更清楚地说明本申请实施例的技术方案，下面将对本申请实施例中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请的一种实施例中静电保护电路的连接关系示意图。
图2为本申请的一种实施例中静电保护电路的连接关系示意图。
图3为本申请的一种实施例中静电保护电路的连接关系示意图。
图4为本申请的一种实施例中静电泄放方法的步骤流程示意图。
具体实施方式
为了使本申请的目的、技术手段及其效果更加清楚明确，以下将结合附图对本申请作进一步地阐述。应当理解，此处所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例，并不用于限定本申请。基于本申请中的实施例，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
研究发现，焊盘的静电泄放不够彻底的原因在于，静电保护电路的泄放晶体管在泄放静电电荷时，泄放晶体管必须保持导通状态，然而泄放晶体管的时间却不够长，这将直接导致所述静电保护电路在泄放晶体管时，不能将焊盘表面的静电电荷完全泄放出去。
在一些实施例中，可以通过增大RC时间常数的方法，来延长所述静电保 护电路的泄放晶体管的泄放导通时长，然而，过大的RC时间常数要求，则会导致所需的电容或电阻增大，直接导致电容或电阻的尺寸增大，影响集成电路的布图设计。
在一种实施例中，所述RC时间常数的时间常数由静电保护电路中的脉冲检测单元中的电阻和电容的乘积有关。要设置足够大的电容或电阻，使泄放晶体管有足够的导通时长。然而足够大的电容或电阻的尺寸也很大，这非常占用集成电路的布图空间。例如设置脉冲检测单元的时间常数为0.1到1微秒，需要在电路板表面设置R为50Kohm的N+扩散电阻，C为20pF的NMOS电容，这会占用比较大的布图空间，同时还使得静电保护电路很容易受到噪声的影响。
以下结合附图和实施例对本申请提出的一种静电保护电路、集成电路及静电泄放方法作进一步详细说明。
请参阅图1，为本申请的一种实施例中静电保护电路的连接关系示意图。
在该实施例中，提供了一种静电保护电路，包括：脉冲检测单元105，用于检测静电脉冲，其第一端连接第一焊盘102，其第二端连接第二焊盘103，其输出端输出检测结果信号；泄放晶体管104，栅极连接至所述脉冲检测单元105，漏极连接至所述第一焊盘102，源极连接至所述第二焊盘103，用于在所述第一焊盘102或第二焊盘103有静电时使源极、漏极之间导通，以泄放静电电荷；处理单元101，分别连接至所述脉冲检测单元105，以及所述泄放晶体管104，用于根据所述检测结果信号控制所述泄放晶体管104的导通和关断，参考图2，所述处理单元101包括：反馈延时电路202，用于延长所述泄放晶体管104泄放静电电荷时的导通时长，所述反馈延时电路202包括：第一PMOS管M5，源极连接所述第一焊盘102，栅极连接所述脉冲检测单元105；第一NMOS管M6，源极连接所述第二焊盘103，漏极连接所述脉冲检测单元105，栅极连接所述第一PMOS管M5的漏极；第一电阻R2，设置于所述第一NMOS管M6的栅极与所述第二焊盘103之间。
在该实施例中的静电保护电路具有反馈延时电路202，能够延长所述泄放晶体管104泄放静电电荷时的导通时长，而无需通过设置更大的电容来延长所述泄放晶体管104的静电荷泄放时长，对集成电路的布图空间占用更少，静电 电荷释放的也更加彻底。
在一种实施例中，所述脉冲检测单元105包括：第二电阻R1，一端连接至所述第一焊盘102，另一端连接至所述反馈延时电路202的输入端；电容C1，一端连接至所述第二焊盘103，另一端连接至所述反馈延时电路202的输入端。
在该实施例中，所述电容C1在两个焊盘有静电时的等效电阻会发生变化，引起图2中1点的电位变化，作为检测结果信号输出到所述反馈延时电路202中。所述反馈延时电路202根据所述检测结果信号驱动或者不驱动所述泄放晶体管MESD。
在图2所示的实施例中，若第一焊盘102上有静电电荷累积，且第二焊盘接地，第一焊盘102和第二焊盘103之间的电容C1的等效电阻会发生变化，在静电电荷积累的一瞬间，图1中的1点为低电平，因此，此时，图1中的3点为低电平。
在该实施例中，所述脉冲检测单元105的第二电阻R1和电容C1的乘积直接影响所述静电保护电路在一次静电泄放过程中的静电泄放时长。所述脉冲检测单元105的第二电阻R1和电容C1的乘积与该脉冲检测单元105的时间常数相等，所述时间常数与所述泄放晶体管104在泄放静电电荷时的导通时长相关，所述脉冲检测单元105的第二电阻R1和电容C1的乘积越大，所述泄放晶体管104的导通时间越长，对焊盘上的静电电荷的泄放就越彻底。
在一些实施例中，所述第二电阻R1和电容C1的乘积至少为0.08到0.7，单位为微秒。
在该实施例中，通过设置所述反馈延时电路202来减小对所述脉冲检测单元105的时间常数的要求。所述反馈延时电路202能够有效延长需要泄放静电电荷时两个焊盘的导通时长，因此能够有效降低对所述脉冲检测单元105时间常数的要求，防止过大的电容C1对集成电路的布图空间的占用。
在该实施例中，应当保证所述泄放晶体管104的导通时长足够大，从而保证静电电荷的充分泄放。在一些实施例中，所述泄放晶体管104泄放静电电荷时的导通时长至少为0.1至1微秒。
在图2所示的实施例中，所述脉冲检测单元105、反馈延时电路202和泄放晶体管104依次连接。所述脉冲检测单元105、反馈延时电路202控制所述 泄放晶体管104在所述第一焊盘102或第二焊盘103上存在静电电荷时导通，将第一焊盘102的静电电荷泄放到第二焊盘103，或将第二焊盘103的静电电荷泄放到第一焊盘102。在该实施例中，所述静电保护电路能够保护所述第一焊盘102和第二焊盘103连接到的功能电路，将焊盘上的静电电荷释放掉，防止静电电荷运动到功能电路上，造成功能电路的失效。
在一种实施例中，所述泄放晶体管104包括第四NMOS管MESD，所述第四NMOS管MESD的漏极连接至第一焊盘102，源极连接至第二焊盘103，栅极连接至所述处理单元101的输出端。
在该实施例中，所述泄放晶体管104为NMOS管，适用于高电平驱动的情形。因此，在该实施例中，所述处理单元101应当在有静电时输出一高电平驱动所述泄放晶体管104导通。实际上，也可使用PMOS管来作为泄放晶体管104。在这种情况下，需要对所述处理单元101的具体结构进行更改，使所述处理单元101输出低电平来驱动所述泄放晶体管104导通。
在一种实施例中，所述处理单元101还包括：反相器组201，包括至少一个反相器，设置于所述反馈延时电路202与所述脉冲检测单元105之间。设置在反馈延时电路202与所述脉冲检测单元105的反相器组201能够对来自所述脉冲检测单元105的检测结果信号进行反相放大，使得最后输出到所述泄放晶体管104的信号足够大，能够驱动所述泄放晶体管104。
在一种实施例中，所述反相器组201中反相器的数目是双数，则从所述反相器组201输出的信号与所述检测结果信号同相，在一种其他的实施例中，所述反相器组201中反相器的数目是单数，则从所述反相器组201输出的信号与所述检测结果信号反相。
在一种实施例中，所述反相器组201包括连接到脉冲检测单元105的第一反相器，以及连接至所述反馈延时电路202的第二反相器。这使得所述检测结果信号至少需要经过两次反相放大，才能够流至所述反馈延时电路202，以及所述泄放晶体管104。由于输出至所述反相器组201的信号至少都会经过两次反相放大，因此能够对输出至所述反相器组201的信号进行整波，以及滤除一些电噪声，防止一些噪声信号对所述泄放晶体管104的导通状态造成影响。在其他的实施例中，可以根据需要设置反相器组201中反相器的个数。
在一种实施例中，所述第一反相器包括：第二PMOS管M1，源极连接所述第一焊盘102，栅极连接至所述脉冲检测单元105，作为所述第一反相器的输入端，漏极作为所述第一反相器的输出端，连接至另一反相器的输入端；第二NMOS管M2，漏极连接至所述第二PMOS管M1的漏极，栅极连接至所述第二PMOS管M1的栅极，源极连接至所述第二焊盘103；所述第二反相器包括：第三PMOS管M3，源极连接所述第一焊盘102，栅极作为所述第二反相器的输入端，连接至上一反相器的输出端，漏极作为所述第而反相器的输出端，连接至所述反馈延时电路202的输入端；第三NMOS管M4，漏极连接所述第三PMOS管M3的漏极，栅极连接所述第三PMOS管M3的栅极，源极连接至所述第二焊盘103。
在图2所示的实施例中，所述反相器组201只包括所述第一反相器以及所述第二反相器，由所述第一反相器对自图2中第1点输入的电信号进行第一次反相放大，所述第一反相器的输出端连接至所述第二反相器的输入端，由所述第二反相器对所述第一反相器的输出进行二次反相放大。
在图2所示的实施例中，所述脉冲检测单元105连接在所述反相器组201之前，所述反馈延时电路202连接在所述反相器组201之后。通过所述反馈延时电路202来实现对泄放晶体管104的泄放导通时长的延时作用。
在该实施例中，所述第四NMOS管MESD属于高电平导通的器件。因此，在图2的第4点提供高电平时，所述第四NMOS管MESD导通，在图2的第4点提供低电压时，所述第四NMOS管MESD关断。
在一种实施例中，所述第一焊盘102作为电源端施加有VDD，第二焊盘103接地。当所述第一焊盘102、第二焊盘103均无静电电荷的累积时，图2中第1点为高电平。经所述反相器组201的两个反相器的反向，图2中的第3点仍为高电平。
此时，所述反馈延时电路202的输入端连接图2中第3点为高电平，所述第一PMOS管M5的栅极电压为高电平，第一PMOS管M5不导通，第一PMOS管M5源漏之间的等效电阻远大于第一电阻R2，因此，图中4点经过分压后为低电平(近似为VSS)，进而所述第一NMOS管和第四NMOS管MESD管关断，所述第一焊盘102和第二焊盘103之间不通过所述第四NMOS管MESD 连通。
在该实施例中，若所述第一焊盘102有静电电荷累积时，图2的第1点是低电平，在经过两个反相器后，图2的第3点的电平也为低电平，因此，所述第一PMOS管M5的栅极连接到低电平并导通，此时，所述第一PMOS管源漏之间的等效电阻远小于第一电阻R2，因此，图中4点经过分压后为高电平(近似为VDD)，进而所述第四NMOS管MESD导通，所述第一焊盘102上的静电电荷向第二焊盘103泄放。
此时，所述第一NMOS管M6的栅极连接的也是图2中4点的高电平，因此所述第一NMOS管M6导通，所述第一电阻R2可以维持该第一NMOS管M6栅极的高电平。由于所述第一NMOS管M6的源极连接到的是第二焊盘103的连接到的地，即低电平VSS，这使得第一NMOS管M6的漏极也为低电平，连接到所述第一NMOS管M6漏极的所述第一PMOS管的栅极也是低电平VSS，所述第一PMOS管得以继续导通，供给所述第四NMOS管MESD的栅极以第一焊盘102上的高电平VDD，使所述第四NMOS管MESD导通，连通所述第一焊盘102和第二焊盘103，保持静电电荷的泄放。这能够延长焊盘上存在静电时两个焊盘的导通时长，保证静电电荷的充分泄放。
因此，在该实施例中，即使随着静电电荷的泄放，电容C1的容抗逐渐增大，图2中的第1点的电压也逐渐升高，但由于使用所述反馈延时电路202，能够延长两个焊盘的导通时长，保证所述第一焊盘102的静电电荷能够有足够时间流向所述第二焊盘103，实现静电电荷的泄放。
上述实施例是第一焊盘102有静电时的工作原理，实际上，当第二焊盘103上有静电时，请参阅图3，为本申请的一种实施例中静电保护电路的连接关系示意图。此时可以通过所述第四NMOS管MESD的寄生电容Dp来实现对静电电荷的泄放，在此并不再做分析。
在该实施例中，所述泄放晶体管104泄放静电电荷时的导通时长至少为0.1至1微秒。这保证了所述静电保护电路的静电电荷泄放效果。
在该实施例中，所述静电保护电路同时连接到了两个焊盘，因此对连接到两个焊盘的功能电路都有保护作用，无论是第一焊盘102上发生静电，还是第二焊盘103上发生静电，都能实现较好的静电泄放保护，因此所述静电保护电 路的静电保护能力也比较强。
在该实施例中，还提供了一种集成电路，包括所述的静电保护电路，用于为所述集成电路上的焊盘泄放静电。
在该实施例中，所述集成电路能够保护功能电路不受静电的损伤。并且，由于所述静电保护电路具有反馈延时电路202，能够延长泄放静电的时长，尽可能的保证焊盘上的静电被泄放完全，因此保证了所述静电保护电路的保护效果，提高了所述集成电路的抗静电能力。
请看图4，为本申请的一种实施例中的静电泄放方法的步骤流程示意图。
在该实施例中，提供了一种静电泄放方法，利用所述的静电保护电路进行静电泄放，包括以下步骤：S41提供一泄放晶体管104，所述泄放晶体管104分别连接到需进行静电泄放保护的第一区域以及第二区域；S42控制所述泄放晶体管104在所述第一区域和第二区域表面有静电电荷时导通，且导通时长至少为一预设时长；S43控制所述泄放晶体管104在无需泄放静电时关断。
在该实施例中，可通过设置足够长的泄放晶体管104的导通时长，来保证所述第一区域的静电电荷能够得到充分的泄放，以防止连接到第一区域和第二区域的功能电路受到未泄放完全的静电电荷的影响。
在一种实施例中，所述预设时长为0.1到1微秒，因此所述泄放晶体管104在需要泄放静电时的导通时长至少为0.1至1微秒。在该实施例中，所述泄放晶体管104还连接到脉冲检测单元105和处理单元101，所述脉冲检测单元105的第一端连接第一区域，第二端连接第二区域，输出端输出检测结果信号至所述处理单元101，由所述脉冲检测单元105和处理单元101来保证所述导通时长。
在该实施例中，控制所述泄放晶体管104在无需泄放静电时关断，这样，在所述第一区域和第二区域表面没有静电电荷需要泄放时，所述第一区域和第二区域上连接的功能电路可以正常工作。
以上所述仅是本申请的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本申请原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本申请的保护范围。

Claims (10)

  1. 一种静电保护电路，其中，包括：
    脉冲检测单元，用于检测静电脉冲，其第一端连接第一焊盘，其第二端连接第二焊盘，其输出端输出检测结果信号；
    泄放晶体管，栅极连接至所述脉冲检测单元，漏极连接至所述第一焊盘，源极连接至所述第二焊盘，用于在所述第一焊盘或第二焊盘有静电时使源极、漏极之间导通，以泄放静电电荷；
    处理单元，分别连接至所述脉冲检测单元以及所述泄放晶体管，用于根据所述检测结果信号控制所述泄放晶体管的导通和关断，所述处理单元包括：
    反馈延时电路，用于延长所述泄放晶体管泄放静电电荷时的导通时长，所述反馈延时电路包括：
    第一PMOS管，源极连接所述第一焊盘，栅极连接所述脉冲检测单元；
    第一NMOS管，源极连接所述第二焊盘，漏极连接所述脉冲检测单元，栅极连接所述第一PMOS管的漏极；
    第一电阻，设置于所述第一NMOS管的栅极与所述第二焊盘之间。
  2. 根据权利要求1所述的静电保护电路，其中，所述处理单元还包括：
    反相器组，包括至少一个反相器，设置于所述反馈延时电路与所述脉冲检测单元之间。
  3. 根据权利要求2所述的静电保护电路，其中，所述反相器组包括连接到脉冲检测单元的第一反相器，以及连接至所述反馈延时电路的第二反相器。
  4. 根据权利要求3所述的静电保护电路，其中，所述第一反相器包括：
    第二PMOS管，源极连接所述第一焊盘，栅极连接至所述脉冲检测单元，漏极连接至另一反相器的输入端；
    第二NMOS管，源极连接所述第二PMOS管的源极，栅极连接至所述脉冲检测单元，漏极连接至所述第二焊盘；
    所述第二反相器包括：
    第三PMOS管，源极连接所述第一焊盘，栅极连接至上一反相器的输出端，漏极连接至所述反馈延时电路的输入端；
    第三NMOS管，源极连接所述第二PMOS管的源极，栅极连接至上一反相器的输出端，漏极连接至所述第二焊盘。
  5. 根据权利要求1所述的静电保护电路，其中，所述脉冲检测单元包括：
    第二电阻，一端连接至所述第一焊盘，另一端连接至所述反馈延时电路的输入端；
    电容，一端连接至所述第二焊盘，另一端连接至所述导通延时电路的输入端。
  6. 根据权利要求5所述的静电保护电路，其中，所述第二电阻和电容的乘积至少为0.08到0.7，单位为微秒。
  7. 根据权利要求1所述的静电保护电路，其中，所述泄放晶体管包括第四NMOS管，所述第四NMOS管的漏极连接至第一焊盘，源极连接至第二焊盘，栅极连接至所述处理单元的输出端。
  8. 根据权利要求1所述的静电保护电路，其中，所述泄放晶体管泄放静电电荷时的导通时长至少为0.1至1微秒。
  9. 一种集成电路，其中，包括如权利要求1所述的静电保护电路，用于为所述集成电路上的焊盘泄放静电。
  10. 一种静电泄放方法，其中，利用如权利要求1所述的静电保护电路进行静电泄放，包括以下步骤：
    提供一泄放晶体管，所述泄放晶体管分别连接到需进行静电泄放保护的第一区域以及第二区域；
    控制所述泄放晶体管在所述第一区域和第二区域表面有静电电荷时导通，且导通时长至少为一预设时长；
    控制所述泄放晶体管在无需泄放静电时关断。
PCT/CN2021/079970 2020-03-12 2021-03-10 静电保护电路、集成电路及静电泄放方法 Ceased WO2021180120A1 (zh)

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