WO2021174643A1 - 一种像素驱动电路、 oled 显示面板及显示装置 - Google Patents

一种像素驱动电路、 oled 显示面板及显示装置 Download PDF

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Publication number
WO2021174643A1
WO2021174643A1 PCT/CN2020/084244 CN2020084244W WO2021174643A1 WO 2021174643 A1 WO2021174643 A1 WO 2021174643A1 CN 2020084244 W CN2020084244 W CN 2020084244W WO 2021174643 A1 WO2021174643 A1 WO 2021174643A1
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Prior art keywords
thin film
node
film transistor
electrically connected
scan signal
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PCT/CN2020/084244
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English (en)
French (fr)
Inventor
薛炎
周帅
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深圳市华星光电半导体显示技术有限公司
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Publication of WO2021174643A1 publication Critical patent/WO2021174643A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix

Definitions

  • This application relates to the field of display technology, and in particular to pixel drive circuits, OLED display panels and display devices.
  • Organic light emitting diode (Organic Light Emitting Diode, OLED) panels have self-luminous characteristics, due to OLED devices and thin film transistors (Thin Film Transistor) Transistor, TFT) device performance is closely related to the temperature of the panel. If the device characteristics change, the display screen is prone to abnormalities. Therefore, reducing the overall power consumption of the panel is extremely important.
  • OLED Organic Light Emitting Diode
  • the data signal voltage of the 2T1C pixel circuit of the general organic light emitting diode is relatively high, so the dynamic power consumption of the panel is relatively large, which is not conducive to the practical use of the display panel.
  • the present invention provides a pixel circuit, which can significantly reduce the data voltage of an organic light emitting diode panel, thereby reducing dynamic power consumption, and finally achieving the purpose of reducing total power consumption.
  • An embodiment of the application provides a pixel driving circuit
  • the pixel driving circuit includes a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, a first storage capacitor, a second storage capacitor, and an organic light emitting diode
  • the gate of the first thin film transistor is electrically connected to the first node
  • its source is electrically connected to the anode of the organic light emitting diode
  • its drain is electrically connected to the positive power supply voltage (VDD)
  • the gate of the second thin film transistor is connected to the first row scan signal, the source is connected to the second data signal, and the drain is electrically connected to the first node
  • the gate of the third thin film transistor is connected to The source of the scan signal in the first row is connected to the negative power supply voltage (VSS), and the drain is electrically connected to the second node
  • the gate of the fourth thin film transistor is connected to the scan signal in the second row, and the source is The pole is electrically connected to the second node, and
  • the second row of scan signal WR2 and the first row of scan signal WR1 have different timings, but the number of peripheral drive signals will not be increased. It is only necessary to move the scan signal from the previous row when wiring the pixels. Among the lines, it is sufficient to pull one of the lines to control the timing of the drive signal by an individual switch.
  • the first thin film transistor, the second thin film transistor, the third thin film transistor, and the fourth thin film transistor are low temperature polysilicon thin film transistors, and the low temperature polysilicon thin film transistors are all P-type thin film transistors; or A thin film transistor, a second thin film transistor, a third thin film transistor, and a fourth thin film transistor are oxide thin film transistors, and the oxide thin film transistors are all N-type oxide thin film transistors.
  • the working process of the pixel driving circuit from low gray scale to high gray scale is as follows:
  • the pixel driving circuit works, when the first row scan signal is at a high potential, the second thin film transistor and the third thin film transistor are turned on, and the potentials of the first node and the second node are reset to V1 and V2;
  • the second row scan signal When the second row scan signal is at a high level, the first row scan signal drops to a low level, a first data signal is written into the second node, and the second node rises from a low level V2 to a high level V1, at this time, the potential of the first node rises by (V1-V2)*C2/(C1+C2), becoming: V1 +[(V1-V2)*C2/(C1+C2)], where , V1-V2 is the potential difference of the second node, C2 is the capacitance value of the second storage capacitor, and C1 is the capacitance value of the first storage capacitor;
  • the pixel driving circuit switches from a low gray scale to a high gray scale, and the data voltage of the second node rises from V1 to V3.
  • the first The potential of the node rises (V3-V1)*C2/(C1+C2) and becomes: V1+[(V1-V2)*C2/(C1+C2)]+[ (V3-V1)*C2/(C1 +C2)].
  • the working process of the pixel driving circuit from high gray scale to low gray scale is as follows:
  • the pixel driving circuit switches from a low and high gray scale to a low gray scale, and the data voltage of the second node is reduced from V3 to V1.
  • the first The potential of a node drops (V3-V1)*C2/(C1+C2) and becomes: [(V3-V2)*C2/(C1+C2)]+V2-[ (V3-V1)*C2/ (C1+C2)].
  • the pixel design structure can reduce the dynamic power consumption of the pixel driving circuit, and finally achieve the goal of reducing the total power consumption.
  • An embodiment of the application also provides an OLED display panel including a pixel driving circuit, the pixel driving circuit includes a first thin film transistor, a second thin film transistor, a third thin film transistor, and a fourth thin film transistor , A first storage capacitor, a second storage capacitor and an organic light emitting diode; wherein the gate of the first thin film transistor is electrically connected to the first node, and the source is electrically connected to the anode of the organic light emitting diode, and The drain is electrically connected to the positive power supply voltage (VDD); the gate of the second thin film transistor is connected to the first row scan signal, the source is connected to the second data signal, and the drain is electrically connected to the first row scan signal.
  • VDD positive power supply voltage
  • the gate of the third thin film transistor is connected to the first row scan signal, its source is connected to the negative power supply voltage (VSS), and its drain is electrically connected to the second node;
  • the fourth thin film The gate of the transistor is connected to the second row scan signal, its source is electrically connected to the second node, and its drain is connected to the first data signal; one end of the first storage capacitor is electrically connected to the first A node, the other end of which is electrically connected to the first ground line; one end of the second storage capacitor is electrically connected to the second node, and the other end of the second storage capacitor is electrically connected to the first node;
  • the organic light emitting The anode of the diode is electrically connected to the source of the first thin film transistor, and the cathode of the diode is electrically connected to the second ground line; the timing of the second row scan signal and the first row scan signal are different, but not To increase the number of peripheral driving signals, it is only necessary to pull one of the traces from the traces of the scan signal
  • the first thin film transistor, the second thin film transistor, the third thin film transistor, and the fourth thin film transistor of the OLED display panel are low temperature polysilicon thin film transistors, and the low temperature polysilicon thin film transistors are all P-type thin films.
  • Transistor; or the first thin film transistor, the second thin film transistor, the third thin film transistor, and the fourth thin film transistor are oxide thin film transistors, and the oxide thin film transistors are all N-type oxide thin film transistors.
  • the working process of the pixel driving circuit of the OLED display panel from a low gray level to a high gray level is as follows:
  • the pixel driving circuit works, when the first row scan signal is at a high potential, the second thin film transistor and the third thin film transistor are turned on, and the potentials of the first node and the second node are reset to V1 and V2;
  • the second row scan signal When the second row scan signal is at a high level, the first row scan signal drops to a low level, a first data signal is written into the second node, and the second node rises from a low level V2 to a high level V1, at this time, the potential of the first node rises by (V1-V2)*C2/(C1+C2), becoming: V1 +[(V1-V2)*C2/(C1+C2)], where , V1-V2 is the potential difference of the second node, C2 is the capacitance value of the second storage capacitor, and C1 is the capacitance value of the first storage capacitor;
  • the pixel driving circuit switches from a low gray scale to a high gray scale, and the data voltage of the second node rises from V1 to V3.
  • the first The potential of the node rises (V3-V1)*C2/(C1+C2) and becomes: V1+[(V1-V2)*C2/(C1+C2)]+[ (V3-V1)*C2/(C1 +C2)].
  • the process of switching the pixel driving circuit of the OLED display panel from a high gray level to a low gray level is as follows:
  • the pixel driving circuit switches from a low and high gray scale to a low gray scale, and the data voltage of the second node is reduced from V3 to V1.
  • the first The potential of a node drops (V3-V1)*C2/(C1+C2) and becomes: [(V3-V2)*C2/(C1+C2)]+V2-[ (V3-V1)*C2/ (C1+C2)].
  • the pixel design structure can reduce the dynamic power consumption of the pixel driving circuit, and finally achieve the goal of reducing the total power consumption.
  • An embodiment of the present application further provides a display device, including the above-mentioned display panel, the display panel including a pixel driving circuit, and the pixel driving circuit includes a first thin film transistor, a second thin film transistor, a third thin film transistor, and a fourth thin film transistor.
  • the first thin film transistor, the second thin film transistor, the third thin film transistor, and the fourth thin film transistor of the display device are low temperature polysilicon thin film transistors, and the low temperature polysilicon thin film transistors are all P-type thin film transistors.
  • the first thin film transistor, the second thin film transistor, the third thin film transistor, and the fourth thin film transistor are oxide thin film transistors, and the oxide thin film transistors are all N-type oxide thin film transistors.
  • the working process of switching the pixel driving circuit of the display device from a low gray level to a high gray level is as follows:
  • the pixel driving circuit works, when the first row scan signal is at a high potential, the second thin film transistor and the third thin film transistor are turned on, and the potentials of the first node and the second node are reset to V1 and V2;
  • the second row scan signal When the second row scan signal is at a high level, the first row scan signal drops to a low level, a first data signal is written into the second node, and the second node rises from a low level V2 to a high level V1, at this time, the potential of the first node rises by (V1-V2)*C2/(C1+C2), becoming: V1 +[(V1-V2)*C2/(C1+C2)], where , V1-V2 is the potential difference of the second node, C2 is the capacitance value of the second storage capacitor, and C1 is the capacitance value of the first storage capacitor;
  • the pixel driving circuit switches from a low gray scale to a high gray scale, and the data voltage of the second node rises from V1 to V3.
  • the first The potential of the node rises (V3-V1)*C2/(C1+C2) and becomes: V1+[(V1-V2)*C2/(C1+C2)]+[ (V3-V1)*C2/(C1 +C2)].
  • the process of switching the pixel driving circuit of the display device from a high gray level to a low gray level is as follows:
  • the pixel driving circuit switches from a low and high gray scale to a low gray scale, and the data voltage of the second node is reduced from V3 to V1.
  • the first The potential of a node drops (V3-V1)*C2/(C1+C2) and becomes: [(V3-V2)*C2/(C1+C2)]+V2-[ (V3-V1)*C2/ (C1+C2)].
  • the pixel design structure can reduce the dynamic power consumption of the pixel driving circuit, and finally achieve the goal of reducing the total power consumption.
  • An embodiment of the application provides a pixel driving circuit
  • the pixel driving circuit includes a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, a first storage capacitor, a second storage capacitor, and an organic light emitting diode
  • the gate of the first thin film transistor is electrically connected to the first node
  • its source is electrically connected to the anode of the organic light emitting diode
  • its drain is electrically connected to the positive power supply voltage (VDD)
  • the gate of the second thin film transistor is connected to the first row scan signal, the source is connected to the second data signal, and the drain is electrically connected to the first node
  • the gate of the third thin film transistor is connected to The source of the scan signal in the first row is connected to the negative power supply voltage (VSS), and the drain is electrically connected to the second node
  • the gate of the fourth thin film transistor is connected to the scan signal in the second row, and the source is The pole is electrically connected to the second node, and
  • FIG. 1 is a schematic structural diagram of a pixel driving circuit provided by an embodiment of the application.
  • FIG. 2 is a schematic diagram of the working process of the pixel driving circuit structure of the present application when the low gray scale is switched to the high gray scale.
  • FIG. 3 is a schematic diagram of the working process of the pixel driving circuit structure of the present application when the high gray scale is switched to the low gray scale.
  • each pixel has a 4T2C pixel structure
  • the 4T2C pixel structure includes a first thin film transistor T1, a second thin film transistor T2, and a third thin film transistor.
  • T3, the fourth thin film transistor T4 the first storage capacitor C1, the second storage capacitor C2 and the organic light emitting diode OLED.
  • the gate of the first thin film transistor T1 is electrically connected to the first node G, its source is electrically connected to the anode S of the organic light emitting diode OLED, and its drain is electrically connected to the positive power supply voltage VDD.
  • the gate of the second thin film transistor T2 is connected to the first row scan signal WR1, the source thereof is connected to the second data signal line Data2, and the drain is electrically connected to the first node G.
  • the gate of the third thin film transistor T3 is connected to the first row scan signal WR1, the source is connected to VSS, and the drain is connected to the second node M.
  • the gate of the fourth thin film transistor T4 is connected to the second row scan signal WR2, its source is electrically connected to the second node M, and its drain is connected to the first data signal line Data1.
  • One end of the first storage capacitor C1 is electrically connected to the first node G, and the other end thereof is electrically connected to the first ground line GND1.
  • One end of the second storage capacitor C2 is electrically connected to the second node M, and the other end of the second storage capacitor C2 is electrically connected to the first node G.
  • the anode S of the organic light emitting diode OLED is electrically connected to the source of the first thin film transistor T1, and the cathode thereof is electrically connected to the second ground line GND2.
  • the second row scan signal WR2 has a different timing from the first row scan signal WR1, but it does not increase the number of peripheral drive signals. It only needs to draw one of the scan signal wires from the previous row when wiring the pixels. It is sufficient to control the timing of the drive signal with individual switches.
  • the first row scan signal WR1 controls the third thin film transistor T3 and the second thin film transistor T2 to turn on, and the second data signal Data2 enters the gate of the first thin film transistor T1 and the first thin film transistor T1 through the second thin film transistor T2.
  • the storage capacitor C1, the second storage capacitor C2, and the first thin film transistor T1 are turned on, and the organic light emitting diode OLED emits light.
  • the scan signal WR1 of the first row is turned off
  • the second thin film transistor T2 and the third thin film transistor T3 are turned off.
  • the scan signal WR2 of the second row is turned on, and the fourth thin film transistor T4 is turned on.
  • the gate voltage of the first thin film transistor T1 can still continue to maintain the data signal voltage, so that the first thin film transistor T1 is in the on state and the driving current
  • the first thin film transistor T1 enters the organic light emitting diode OLED, and drives the organic light emitting diode OLED to emit light.
  • the first storage capacitor C1 and the second storage capacitor C2 are electrically connected at the first node G, which is beneficial to maintain the voltage balance of the first node G and stably supply the data signal to T1.
  • stage 1 the first row scan signal WR1 rises to a high potential, the third thin film transistor T3 and the second thin film transistor T2 are turned on, the voltage of the second data signal Data2 is 15 volts, and the potentials of the first node G and the second node M are reset respectively 1 volt and -10 volts;
  • stage 2 the second row scan signal WR2 rises to a high potential, the first row scan signal WR1 will be a low potential, the first data signal Data1 is written into the second node M, and the potential of the second node M rises from -10 ⁇ to 1 volt, at this time, the potential of the first node G rises by 11*C2/(C1+C2), therefore, the potential of the first node G is 1+11*C2/(C1+C2);
  • stage 3 the second row of scanning signal WR2 continues to maintain a high level, the screen is switched from low gray level to high gray level, and the data signal rises from 1 volt to 10 volts.
  • the potential of the first node G rises by 9*C2/ (C1+C2), therefore, the potential of the first node G is 1+20*C2/(C1+C2), and the current of the organic light emitting diode OLED is 1.5 mA.
  • stage 1 the scan signal WR1 of the first row rises to a high potential, the third thin film transistor T3 and the second thin film transistor T2 are turned on, and the potentials of the first node G and the second node M are reset to 10 volts and -10 volts, respectively;
  • stage 2 the second row scan signal WR2 rises to a high potential, the first row scan signal WR1 will be a low potential, the first data signal Data1 is written into the second node M, and the potential of the second node M rises from -10 volts to 10 volts, at this time, the potential of the first node G rises by 20*C2/(C1+C2), therefore, the potential of the first node G is [20*C2/(C1+C2)]-10;
  • stage 3 the second row of scanning signal WR2 continues to maintain a high level, the screen is switched from high gray scale to low gray scale, and the data signal drops from 10 volts to 1 volt.
  • the potential of the first node G drops by 9*C2/ (C1+C2), therefore, the potential of the first node G is [11*C2/(C1+C2)]-10, the current of the organic light emitting diode OLED is 200 nA, and the screen displays a low gray scale.
  • the first thin film transistor T1, the second thin film transistor T2, the third thin film transistor T3, and the fourth thin film transistor T4 are low temperature polysilicon thin film transistors, and the low temperature polysilicon thin film transistors are all P-type thin film transistors; or the first thin film transistors
  • the transistor T1, the second thin film transistor T2, the third thin film transistor T3, and the fourth thin film transistor T4 are oxide thin film transistors, and the oxide thin film transistors are all N-type oxide thin film transistors.
  • An embodiment of the application also provides an OLED display panel including a pixel driving circuit.
  • each pixel has a 4T2C pixel structure, and the 4T2C pixel structure includes a first thin film transistor T1 and a second thin film.
  • the gate of the first thin film transistor T1 is electrically connected to the first node G, its source is electrically connected to the anode S of the organic light emitting diode OLED, and its drain is electrically connected to the positive power supply voltage VDD.
  • the gate of the second thin film transistor T2 is connected to the first row scan signal WR1, the source thereof is connected to the second data signal line Data2, and the drain is electrically connected to the first node G.
  • the gate of the third thin film transistor T3 is connected to the first row scan signal WR1, the source is connected to the negative power supply voltage VSS, and the drain is connected to the second node M.
  • the gate of the fourth thin film transistor T4 is connected to the second row scan signal WR2, its source is electrically connected to the second node M, and its drain is connected to the first data signal line Data1.
  • One end of the first storage capacitor C1 is electrically connected to the first node G, and the other end thereof is electrically connected to the first ground line GND1.
  • One end of the second storage capacitor C2 is electrically connected to the second node M, and the other end of the second storage capacitor C2 is electrically connected to the first node G.
  • the anode S of the organic light emitting diode OLED is electrically connected to the source of the first thin film transistor T1, and the cathode thereof is electrically connected to the second ground line GND2.
  • the second row scan signal WR2 has a different timing from the first row scan signal WR1, but it does not increase the number of peripheral drive signals. It only needs to draw one of the scan signal wires from the previous row when wiring the pixels. It is sufficient to control the timing of the drive signal with individual switches.
  • the first row scan signal WR1 controls the third thin film transistor T3 and the second thin film transistor T2 to turn on, and the second data signal Data2 enters the gate of the first thin film transistor T1 and the first thin film transistor T1 through the second thin film transistor T2.
  • the storage capacitor C1, the second storage capacitor C2, and the first thin film transistor T1 are turned on, and the organic light emitting diode OLED emits light.
  • the scan signal WR1 of the first row is turned off
  • the second thin film transistor T2 and the third thin film transistor T3 are turned off.
  • the fourth thin film transistor T4 is turned on, and the first data signal Data1 is written into the first data signal.
  • the gate voltage of the first thin film transistor T1 can still maintain the data signal voltage, so that the first thin film transistor T1 is in the on state and the driving current
  • the first thin film transistor T1 enters the organic light emitting diode OLED, and drives the organic light emitting diode OLED to emit light.
  • the first storage capacitor C1 and the second storage capacitor C2 are electrically connected at the first node G, which is beneficial to maintain the voltage balance of the first node G and stably supply data signals to T1.
  • stage 1 the first row scan signal WR1 rises to a high potential, the third thin film transistor T3 and the second thin film transistor T2 are turned on, the voltage of the second data signal Data2 is 15 volts, and the potentials of the first node G and the second node M are reset respectively 1 volt and -10 volts;
  • stage 2 the second row scan signal WR2 rises to a high potential, the first row scan signal WR1 will be a low potential, the first data signal Data1 is written into the second node M, and the potential of the second node M rises from -10 volts to 1 volt, at this time, the potential of the first node G rises by 11*C2/(C1+C2), therefore, the potential of the first node G is 1+11*C2/(C1+C2);
  • stage 3 the second row of scanning signal WR2 continues to maintain a high level, the screen is switched from low gray level to high gray level, and the data signal rises from 1 volt to 10 volts.
  • the potential of the first node G rises by 9*C2/ (C1+C2), therefore, the potential of the first node G is 1+20*C2/(C1+C2), and the current of the organic light emitting diode OLED is 1.5 mA.
  • stage 1 the scan signal WR1 of the first row rises to a high potential, the third thin film transistor T3 and the second thin film transistor T2 are turned on, and the potentials of the first node G and the second node M are reset to 10 volts and -10 volts, respectively;
  • stage 2 the second row scan signal WR2 rises to a high potential, the first row scan signal WR1 will be a low potential, the first data signal Data1 is written into the second node M, and the potential of the second node M rises from -10 volts to 10 volts, at this time, the potential of the first node G rises by 20*C2/(C1+C2), therefore, the potential of the first node G is [20*C2/(C1+C2)]-10;
  • stage 3 the second row of scanning signal WR2 continues to maintain a high level, the screen is switched from high gray scale to low gray scale, and the data signal drops from 10 volts to 1 volt.
  • the potential of the first node G drops by 9*C2/ (C1+C2), therefore, the potential of the first node G is [11*C2/(C1+C2)]-10, the current of the organic light emitting diode OLED is 200 nA, and the screen displays a low gray scale.
  • the dynamic power consumption of the data line I fCV data 2 , where f is the refresh rate of the panel, and C is the capacitance of the panel. It can be found that the dynamic power consumption of the panel is reduced by more than half.
  • the first thin film transistor T1, the second thin film transistor T2, the third thin film transistor T3, and the fourth thin film transistor T4 are low temperature polysilicon thin film transistors, and the low temperature polysilicon thin film transistors are all P-type thin film transistors; or the first thin film transistors
  • the transistor T1, the second thin film transistor T2, the third thin film transistor T3, and the fourth thin film transistor T4 are oxide thin film transistors, and the oxide thin film transistors are all N-type oxide thin film transistors.
  • An embodiment of the present application also provides a display device, including the above-mentioned display panel, the display panel including a pixel driving circuit, referring to FIG. 1, in the pixel driving circuit, each pixel has a 4T2C pixel structure, and the 4T2C pixel structure It includes a first thin film transistor T1, a second thin film transistor T2, a third thin film transistor T3, a fourth thin film transistor T4, a first storage capacitor C1, a second storage capacitor C2, and an organic light emitting diode OLED.
  • the gate of the first thin film transistor T1 is electrically connected to the first node G, its source is electrically connected to the anode S of the organic light emitting diode OLED, and its drain is electrically connected to the positive power supply voltage VDD.
  • the gate of the second thin film transistor T2 is connected to the first row scan signal WR1, the source thereof is connected to the second data signal line Data2, and the drain is electrically connected to the first node G.
  • the gate of the third thin film transistor T3 is connected to the first row scan signal WR1, the source is connected to the negative power supply voltage VSS, and the drain is connected to the second node M.
  • the gate of the fourth thin film transistor T4 is connected to the second row scan signal WR2, its source is electrically connected to the second node M, and its drain is connected to the first data signal line Data1.
  • One end of the first storage capacitor C1 is electrically connected to the first node G, and the other end thereof is electrically connected to the first ground line GND1.
  • One end of the second storage capacitor C2 is electrically connected to the second node M, and the other end of the second storage capacitor C2 is electrically connected to the first node G.
  • the anode S of the organic light emitting diode OLED is electrically connected to the source of the first thin film transistor T1, and the cathode thereof is electrically connected to the second ground line GND2.
  • the timing of WR2 is different from that of the first row of scanning signal WR1, but it will not increase the number of peripheral drive signals. It only needs to pull one of the wires from the previous row of scanning signal wires to individually switch the drive signals when doing pixel wiring.
  • the timing can be.
  • the first row scan signal WR1 controls the third thin film transistor T3 and the second thin film transistor T2 to turn on, and the second data signal Data2 enters the gate of the first thin film transistor T1 and the first thin film transistor T1 through the second thin film transistor T2.
  • the storage capacitor C1, the second storage capacitor C2, and the first thin film transistor T1 are turned on, and the organic light emitting diode OLED emits light.
  • the scan signal WR1 of the first row is turned off
  • the second thin film transistor T2 and the third thin film transistor T3 are turned off.
  • the fourth thin film transistor T4 is turned on, and the first data signal Data1 is written into the first data signal.
  • the gate voltage of the first thin film transistor T1 can still maintain the data signal voltage, so that the first thin film transistor T1 is in the on state and the driving current
  • the first thin film transistor T1 enters the organic light emitting diode OLED, and drives the organic light emitting diode OLED to emit light.
  • the first storage capacitor C1 and the second storage capacitor C2 are electrically connected at the first node G, which is beneficial to maintain the voltage balance of the first node G and stably supply data signals to T1.
  • stage 1 the first row scan signal WR1 rises to a high potential, the third thin film transistor T3 and the second thin film transistor T2 are turned on, the voltage of the second data signal Data2 is 15 volts, and the potentials of the first node G and the second node M are reset respectively 1 volt and -10 volts;
  • stage 2 the second row scan signal WR2 rises to a high potential, the first row scan signal WR1 will be a low potential, the first data signal Data1 is written into the second node M, and the potential of the second node M rises from -10 volts to 1 volt, at this time, the potential of the first node G rises by 11*C2/(C1+C2), therefore, the potential of the first node G is 1+11*C2/(C1+C2);
  • stage 3 the second row of scanning signal WR2 continues to maintain a high level, the screen is switched from low gray level to high gray level, and the data signal rises from 1 volt to 10 volts.
  • the potential of the first node G rises by 9*C2/ (C1+C2), therefore, the potential of the first node G is 1+20*C2/(C1+C2), and the current of the organic light emitting diode OLED is 1.5 mA.
  • stage 1 the scan signal WR1 of the first row rises to a high potential, the third thin film transistor T3 and the second thin film transistor T2 are turned on, and the potentials of the first node G and the second node M are reset to 10 volts and -10 volts, respectively;
  • stage 2 the second row scan signal WR2 rises to a high potential, the first row scan signal WR1 will be a low potential, the first data signal Data1 is written into the second node M, and the potential of the second node M rises from -10 volts to 10 volts, at this time, the potential of the first node G rises by 20*C2/(C1+C2), therefore, the potential of the first node G is [20*C2/(C1+C2)]-10;
  • stage 3 the second row of scanning signal WR2 continues to maintain a high level, the screen is switched from high gray scale to low gray scale, and the data signal drops from 10 volts to 1 volt.
  • the potential of the first node G drops by 9*C2/ (C1+C2), therefore, the potential of the first node G is [11*C2/(C1+C2)]-10, the current of the organic light emitting diode OLED is 200 nA, and the screen displays a low gray scale.
  • the dynamic power consumption of the data line I fCV data 2 , where f is the refresh rate of the panel, and C is the capacitance of the panel. It can be found that the dynamic power consumption of the panel is reduced by more than half.
  • the first thin film transistor T1, the second thin film transistor T2, the third thin film transistor T3, and the fourth thin film transistor T4 are low temperature polysilicon thin film transistors, and the low temperature polysilicon thin film transistors are all P-type thin film transistors; or the first thin film transistors
  • the transistor T1, the second thin film transistor T2, the third thin film transistor T3, and the fourth thin film transistor T4 are oxide thin film transistors, and the oxide thin film transistors are all N-type oxide thin film transistors.
  • the embodiments of the present application provide a pixel drive circuit
  • the pixel drive circuit includes a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, a first A storage capacitor, a second storage capacitor and an organic light emitting diode; wherein the gate of the first thin film transistor is electrically connected to the first node, the source is electrically connected to the anode of the organic light emitting diode, and the drain is electrically connected
  • the gate of the second thin film transistor is connected to the first row scan signal, the source of the second thin film transistor is connected to the second data signal, and the drain of the second thin film transistor is electrically connected to the first node;
  • the gate of the third thin film transistor is connected to the scan signal of the first row, its source is connected to the negative power supply voltage (VSS), and the drain is electrically connected to the second node;
  • the gate of the fourth thin film transistor The electrode is connected to the second row of scanning signals, the source of which is electrical

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Abstract

一种像素驱动电路、OLED显示面板、显示装置。像素驱动电路包括第一薄膜晶体管（T1）、第二薄膜晶体管（T2）、第三薄膜晶体管（T3）、第四薄膜晶体管（T4）、第一存储电容（C1）、第二存储电容（C2）及有机发光二极管（OLED）。通过新的4T2C像素驱动电路结构，能够显著降低AMOLED面板的数据电压，从而降低动态功耗，最终达到降低总功耗的目的。

Description

一种像素驱动电路、OLED显示面板及显示装置 技术领域
本申请涉及显示技术领域，尤其涉及像素驱动电路、OLED显示面板及显示装置。
 背景技术
有机发光二极管(Organic Light Emitting Diode, OLED)面板具有自发光特性，由于OLED器件以及薄膜晶体管（Thin Film Transistor，TFT）器件的性能与面板的温度息息相关，如果器件特性发生变化，显示画面易出现反常。因此，降低面板的整体功耗极为重要。
通用的有机发光二极管的2T1C像素电路数据信号电压较高，因此面板的动态功耗较大，不利于显示面板的实用化。
 技术问题
本发明提出一种像素电路，能够显著降低有机发光二极管面板的数据电压，从而降低动态功耗，最终达到降低总功耗的目的。
 技术解决方案
本申请实施例提供一种像素驱动电路，所述像素驱动电路包括第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第一存储电容、第二存储电容及有机发光二极管；其中，所述第一薄膜晶体管的栅极电性连接至第一节点，其源极电性连接至所述有机发光二极管的阳极，其漏极电性连接至电源正电压（VDD）；所述第二薄膜晶体管的栅极接入第一行扫描信号，其源极接入第二数据信号，其漏极电性连接至所述第一节点；所述第三薄膜晶体管的栅极接入所述第一行扫描信号，其源极接入电源负电压（VSS），其漏极电性连接至第二节点；所述第四薄膜晶体管的栅极接入第二行扫描信号，其源极电性连接至所述第二节点，其漏极接入第一数据信号；所述第一存储电容的一端电性连接至所述第一节点，其另一端电性连接至第一接地线；所述第二存储电容的一端电性连接至所述第二节点，其另一端电性连接至所述第一节点；所述有机发光二极管的阳极电性连接至所述第一薄膜晶体管的源极，其阴极电性连接至第二接地线。
在一些实施例中，第二行扫描信号WR２与所述第一行扫描信号WR1的时序不同，但不会额外增加外围驱动信号数量，仅需在做像素布线时，从上一行扫描信号的走线中，牵引其中一条走线以个别开关控制驱动信号的时序即可。
在一些实施例中，所述第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管为低温多晶硅薄膜晶体管，所述低温多晶硅薄膜晶体管均为P型薄膜晶体管；或所述第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管为氧化物薄膜晶体管，所述氧化物薄膜晶体管均为N型氧化物薄膜晶体管。
在一些实施例中，所述像素驱动电路由低灰阶切为高灰阶的工作过程如下：
像素驱动电路工作时，当所述第一行扫描信号为高电位时，所述第二薄膜晶体管、所述第三薄膜晶体管开启，所述第一节点与所述第二节点的电位分别复位为V1及V2；
当所述第二行扫描信号为高电位时，所述第一行扫描信号降为低电位，第一数据信号写入所述第二节点，所述第二节点由低电位V2升为高电位V1，此时，所述第一节点的电位上升了（V1-V2）*C2/（C1+C2），变为：V1 +[（V1-V2）*C2/（C1+C2）],其中，V1-V2为所述第二节点的电位差，C2是所述第二存储电容的电容值，C1是所述第一存储电容的电容值；
当所述第二行扫描信号维持为高电位时，所述像素驱动电路由低灰阶切为高灰阶，所述第二节点的数据电压由V1升为V3，此时，所述第一节点的电位上升了（V3-V1）*C2/（C1+C2），变为: V1+[（V1-V2）*C2/（C1+C2）]+[ （V3-V1）*C2/（C1+C2）]。
在一些实施例中，所述像素驱动电路由高灰阶切为低灰阶的工作过程如下：
像素驱动电路工作时，当所述第一行扫描信号为高电位时，所述第二薄膜晶体管、所述第二薄膜晶体管开启，所述第一节点与所述第二节点的电位分别复位为V3及V2；。
当所述第二行扫描信号为高电位时，所述第一行扫描信号降为低电位，第一数据信号写入所述第二节点，所述第二节点由低电位V2升为高电位V3，此时，所述第一节点的电位上升了了（V3-V2）*C2/（C1+C2），变为：[（V3-V2）*C2/（C1+C2）]+V2，其中，V3-V2是所述第二节点的电位差，C2是所述第二存储电容的电容值，C1是所述第一存储电容的电容值；
当所述第二行扫描信号维持为高电位时，所述像素驱动电路由低高灰阶切为低灰阶，所述第二节点的数据电压由V3降低为V1，此时，所述第一节点的电位下降了（V3-V1）*C2/（C1+C2），变为: [（V3-V2）*C2/（C1+C2）]+V2-[ （V3-V1）*C2/（C1+C2）]。
从而，该像素设计结构可降低像素驱动电路的动态功耗，最终达到降低总功耗的目的。
本申请实施例还提供一种OLED显示面板，包括像素驱动电路，所述一种像素驱动电路，所述像素驱动电路包括第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第一存储电容、第二存储电容及有机发光二极管；其中，所述第一薄膜晶体管的栅极电性连接至第一节点，其源极电性连接至所述有机发光二极管的阳极，其漏极电性连接至电源正电压（VDD）；所述第二薄膜晶体管的栅极接入第一行扫描信号，其源极接入第二数据信号，其漏极电性连接至所述第一节点；所述第三薄膜晶体管的栅极接入所述第一行扫描信号，其源极接入电源负电压（VSS），其漏极电性连接至第二节点；所述第四薄膜晶体管的栅极接入第二行扫描信号，其源极电性连接至所述第二节点，其漏极接入第一数据信号；所述第一存储电容的一端电性连接至所述第一节点，其另一端电性连接至第一接地线；所述第二存储电容的一端电性连接至所述第二节点，其另一端电性连接至所述第一节点；所述有机发光二极管的阳极电性连接至所述第一薄膜晶体管的源极，其阴极电性连接至第二接地线；所述第二行扫描信号与所述第一行扫描信号的时序不同，但不会额外增加外围驱动信号数量，仅需在做像素布线时，从上一行扫描信号的走线中，牵引其中一条走线以个别开关控制驱动信号的时序即可。
在一些实施例中，所述OLED显示面板的所述第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管为低温多晶硅薄膜晶体管，所述低温多晶硅薄膜晶体管均为P型薄膜晶体管；或所述第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管为氧化物薄膜晶体管，所述氧化物薄膜晶体管均为N型氧化物薄膜晶体管。
在一些实施例中，所述OLED显示面板的所述像素驱动电路由低灰阶切为高灰阶的工作过程如下：
像素驱动电路工作时，当所述第一行扫描信号为高电位时，所述第二薄膜晶体管、所述第三薄膜晶体管开启，所述第一节点与所述第二节点的电位分别复位为V1及V2；
当所述第二行扫描信号为高电位时，所述第一行扫描信号降为低电位，第一数据信号写入所述第二节点，所述第二节点由低电位V2升为高电位V1，此时，所述第一节点的电位上升了（V1-V2）*C2/（C1+C2），变为：V1 +[（V1-V2）*C2/（C1+C2）],其中，V1-V2为所述第二节点的电位差，C2是所述第二存储电容的电容值，C1是所述第一存储电容的电容值；
当所述第二行扫描信号维持为高电位时，所述像素驱动电路由低灰阶切为高灰阶，所述第二节点的数据电压由V1升为V3，此时，所述第一节点的电位上升了（V3-V1）*C2/（C1+C2），变为: V1+[（V1-V2）*C2/（C1+C2）]+[ （V3-V1）*C2/（C1+C2）]。
在一些实施例中，所述OLED显示面板的所述像素驱动电路由高灰阶切为低灰阶的工作过程如下：
像素驱动电路工作时，当所述第一行扫描信号为高电位时，所述第二薄膜晶体管、所述第二薄膜晶体管开启，所述第一节点与所述第二节点的电位分别复位为V3及V2；
当所述第二行扫描信号为高电位时，所述第一行扫描信号降为低电位，第一数据信号写入所述第二节点，所述第二节点由低电位V2升为高电位V3，此时，所述第一节点的电位上升了了（V3-V2）*C2/（C1+C2），变为：[（V3-V2）*C2/（C1+C2）]+V2，其中，V3-V2是所述第二节点的电位差，C2是所述第二存储电容的电容值，C1是所述第一存储电容的电容值；
当所述第二行扫描信号维持为高电位时，所述像素驱动电路由低高灰阶切为低灰阶，所述第二节点的数据电压由V3降低为V1，此时，所述第一节点的电位下降了（V3-V1）*C2/（C1+C2），变为: [（V3-V2）*C2/（C1+C2）]+V2-[ （V3-V1）*C2/（C1+C2）]。
从而，该像素设计结构可降低像素驱动电路的动态功耗，最终达到降低总功耗的目的。
本申请实施例还提供一种显示装置，包括上述的显示面板，所述显示面板包括像素驱动电路，所述像素驱动电路包括第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第一存储电容、第二存储电容及有机发光二极管；其中，所述第一薄膜晶体管的栅极电性连接至第一节点，其源极电性连接至所述有机发光二极管的阳极，其漏极电性连接至电源正电压（VDD）；所述第二薄膜晶体管的栅极接入第一行扫描信号，其源极接入第二数据信号，其漏极电性连接至所述第一节点；所述第三薄膜晶体管的栅极接入所述第一行扫描信号，其源极接入电源负电压（VSS），其漏极连接至第二节点；所述第四薄膜晶体管的栅极接入第二行扫描信号，其源极电性连接至所述第二节点，其漏极接入第一数据信号；所述第一存储电容的一端电性连接至所述第一节点，其另一端电性连接至第一接地线；所述第二存储电容的一端电性连接至所述第二节点，其另一端电性连接至所述第一节点；所述有机发光二极管的阳极电性连接至所述第一薄膜晶体管的源极，其阴极电性连接至第二接地线；所述第二行扫描信号与所述第一行扫描信号的时序不同，但不会额外增加外围驱动信号数量，仅需在做像素布线时，从上一行扫描信号的走线中，牵引其中一条走线以个别开关控制驱动信号的时序即可。
在一些实施例中，所述显示装置的所述第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管为低温多晶硅薄膜晶体管，所述低温多晶硅薄膜晶体管均为P型薄膜晶体管；或所述第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管为氧化物薄膜晶体管，所述氧化物薄膜晶体管均为N型氧化物薄膜晶体管。
在一些实施例中，所述显示装置的所述像素驱动电路由低灰阶切为高灰阶的工作过程如下：
像素驱动电路工作时，当所述第一行扫描信号为高电位时，所述第二薄膜晶体管、所述第三薄膜晶体管开启，所述第一节点与所述第二节点的电位分别复位为V1及V2；
当所述第二行扫描信号为高电位时，所述第一行扫描信号降为低电位，第一数据信号写入所述第二节点，所述第二节点由低电位V2升为高电位V1，此时，所述第一节点的电位上升了（V1-V2）*C2/（C1+C2），变为：V1 +[（V1-V2）*C2/（C1+C2）],其中，V1-V2为所述第二节点的电位差，C2是所述第二存储电容的电容值，C1是所述第一存储电容的电容值；
当所述第二行扫描信号维持为高电位时，所述像素驱动电路由低灰阶切为高灰阶，所述第二节点的数据电压由V1升为V3，此时，所述第一节点的电位上升了（V3-V1）*C2/（C1+C2），变为: V1+[（V1-V2）*C2/（C1+C2）]+[ （V3-V1）*C2/（C1+C2）]。
在一些实施例中，所述显示装置的所述像素驱动电路由高灰阶切为低灰阶的工作过程如下：
像素驱动电路工作时，当所述第一行扫描信号为高电位时，所述第二薄膜晶体管、所述第二薄膜晶体管开启，所述第一节点与所述第二节点的电位分别复位为V3及V2；
当所述第二行扫描信号为高电位时，所述第一行扫描信号降为低电位，第一数据信号写入所述第二节点，所述第二节点由低电位V2升为高电位V3，此时，所述第一节点的电位上升了了（V3-V2）*C2/（C1+C2），变为：[（V3-V2）*C2/（C1+C2）]+V2，其中，V3-V2是所述第二节点的电位差，C2是所述第二存储电容的电容值，C1是所述第一存储电容的电容值；
当所述第二行扫描信号维持为高电位时，所述像素驱动电路由低高灰阶切为低灰阶，所述第二节点的数据电压由V3降低为V1，此时，所述第一节点的电位下降了（V3-V1）*C2/（C1+C2），变为: [（V3-V2）*C2/（C1+C2）]+V2-[ （V3-V1）*C2/（C1+C2）]。
从而，该像素设计结构可降低像素驱动电路的动态功耗，最终达到降低总功耗的目的。
 有益效果
本申请实施例提供一种像素驱动电路，所述像素驱动电路包括第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第一存储电容、第二存储电容及有机发光二极管；其中，所述第一薄膜晶体管的栅极电性连接至第一节点，其源极电性连接至所述有机发光二极管的阳极，其漏极电性连接至电源正电压（VDD）；所述第二薄膜晶体管的栅极接入第一行扫描信号，其源极接入第二数据信号，其漏极电性连接至所述第一节点；所述第三薄膜晶体管的栅极接入所述第一行扫描信号，其源极接入电源负电压（VSS），其漏极电性连接至第二节点；所述第四薄膜晶体管的栅极接入第二行扫描信号，其源极电性连接至所述第二节点，其漏极接入第一数据信号；所述第一存储电容的一端电性连接至所述第一节点，其另一端电性连接至第一接地线；所述第二存储电容的一端电性连接至所述第二节点，其另一端电性连接至所述第一节点；所述有机发光二极管的阳极电性连接至所述第一薄膜晶体管的源极，其阴极电性连接至第二接地线；所述第二行扫描信号与所述第一行扫描信号的时序不同。本申请实施例通过4T2C像素驱动电路结构，能够显著降低OLED面板的数据电压，从而降低动态功耗，最终达到降低总功耗的目的。
 附图说明
图1为本申请实施例提供的像素驱动电路结构示意图。
图2为本申请的像素驱动电路结构在低灰阶切为高灰阶时的工作过程示意图。
图3为本申请的像素驱动电路结构在高灰阶切为低灰阶时的工作过程示意图。
 本发明的实施方式
具体的，请参阅图1，本申请实施例提供的像素驱动电路中，每个像素都具有4T2C像素结构，所述4T2C像素结构包括第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3、第四薄膜晶体管T4、第一存储电容C1、第二存储电容C2及有机发光二极管OLED。
第一薄膜晶体管T1的栅极电性连接至第一节点G，其源极电性连接至有机发光二极管OLED的阳极S，其漏极电性连接至电源正电压VDD。
第二薄膜晶体管T2的栅极接入第一行扫描信号WR1，其源极接入第二数据信号线Data2，其漏极电性连接至第一节点G。
第三薄膜晶体管T3的栅极接入第一行扫描信号WR1，其源极接入VSS，其漏极连接至第二节点M。
第四薄膜晶体管T4的栅极接入第二行扫描信号WR2，其源极电性连接至所述第二节点M，其漏极接入第一数据信号线Data1。
第一存储电容C1的一端电性连接至第一节点G，其另一端电性连接至第一接地线GND1。
第二存储电容C2的一端电性连接至第二节点M，其另一端电性连接至第一节点G。
有机发光二极管OLED的阳极S电性连接至第一薄膜晶体管T1的源极，其阴极电性连接至第二接地线GND２。
第二行扫描信号WR２与所述第一行扫描信号WR1的时序不同, 但不会额外增加外围驱动信号数量，仅需在做像素布线时，从上一行扫描信号走线中，牵引其中一条走线以个别开关控制驱动信号的时序即可。
在驱动时，首先，第一行扫描信号WR１控制第三薄膜晶体管T３、第二薄膜晶体管T2开启，第二数据信号Data2经过第二薄膜晶体管T2进入到第一薄膜晶体管T1的栅极及第一存储电容C1、第二存储电容C2，然后第一薄膜晶体管T1开启，有机发光二级管OLED发光。其次，第一行扫描信号WR１关闭，则第二薄膜晶体管T2与第三薄膜晶体管T３关闭，同时，第二行扫描信号WR２开启，则第四薄膜晶体管T４开启，第一数据信号Data1写入第二节点M，由于第一存储电容C1与第二存储电容C2的存储作用，第一薄膜晶体管T1的栅极电压仍可继续保持数据信号电压，使得第一薄膜晶体管T1处于导通状态，驱动电流通过第一薄膜晶体管T1进入有机发光二级管OLED，驱动有机发光二级管OLED发光。
在本申请的结构中，第一存储电容C1与第二存储电容C2在第一节点G处电性连接，这有利于保持第一节点G的电压的平衡，稳定地向T1供应数据信号。
如图2所示,像素低灰阶切为高灰阶的过程如下：
阶段1，第一行扫描信号WR１升为高电位,第三薄膜晶体管T３、第二薄膜晶体管T2开启，第二数据信号Data2电压15伏特，第一节点G与第二节点M的电位分别被复位为1伏特及-10伏特；
阶段2，第二行扫描信号WR2升为高电位，第一行扫描信号WR１将为低电位，第一数据信号Data1信号写入第二节点M，第二节点M的电位由-10茯升为1伏特，此时，第一节点G的电位上升了11*C2/(C1+C2),因此，第一节点G的电位为1+11*C2/(C1+C2)；
阶段3，第二行扫描信号WR2持续维持高电位，画面由低灰阶切换为高灰阶，数据信号由1伏特升为10伏特，这时，第一节点G的电位上升了9*C2/(C1+C2)，因此，第一节点G的电位为1+20*C2/(C1+C2)，有机发光二级管OLED的电流为1.5mA。
如图3所示，像素高灰阶切为低灰阶的过程如下：
阶段1，第一行扫描信号WR１升为高电位,第三薄膜晶体管T３、第二薄膜晶体管T2开启，第一节点G与第二节点M的电位分别被复位为10伏特及-10伏特；
阶段2，第二行扫描信号WR2升为高电位，第一行扫描信号WR１将为低电位，第一数据信号Data1信号写入第二节点M，第二节点M的电位由-10伏特升为10伏特，此时，第一节点G的电位上升了20*C2/(C1+C2),因此，第一节点G的电位为[20*C2/(C1+C2)]-10；
阶段3，第二行扫描信号WR2持续维持高电位，画面由高灰阶切换为低灰阶，数据信号由10伏特降为1伏特，这时，第一节点G的电位下降了9*C2/(C1+C2)，因此，第一节点G的电位为[11*C2/(C1+C2)]-10，有机发光二级管OLED的电流为200 nA，画面显示低灰阶。
而，数据线的动态功耗I=fcV data 2，面板的动态功耗降低一半以上。
在一些实施例中，第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3、第四薄膜晶体管T4为低温多晶硅薄膜晶体管，低温多晶硅薄膜晶体管均为P型薄膜晶体管；或第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3、第四薄膜晶体管T4为氧化物薄膜晶体管，氧化物薄膜晶体管均为N型氧化物薄膜晶体管。
本申请实施例还提供一种OLED显示面板，包括像素驱动电路，参考图1，像素驱动电路中，每个像素都具有4T2C像素结构，所述4T2C像素结构包括第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3、第四薄膜晶体管T4、第一存储电容C1、第二存储电容C2及有机发光二极管OLED。
第一薄膜晶体管T1的栅极电性连接至第一节点G，其源极电性连接至有机发光二极管OLED的阳极S，其漏极电性连接至电源正电压VDD。
第二薄膜晶体管T2的栅极接入第一行扫描信号WR1，其源极接入第二数据信号线Data2，其漏极电性连接至第一节点G。
第三薄膜晶体管T3的栅极接入第一行扫描信号WR1，其源极接入电源负电压VSS，其漏极连接至第二节点M。
第四薄膜晶体管T4的栅极接入第二行扫描信号WR2，其源极电性连接至所述第二节点M，其漏极接入第一数据信号线Data1。
第一存储电容C1的一端电性连接至第一节点G，其另一端电性连接至第一接地线GND1。
第二存储电容C2的一端电性连接至第二节点M，其另一端电性连接至第一节点G。
有机发光二极管OLED的阳极S电性连接至第一薄膜晶体管T1的源极，其阴极电性连接至第二接地线GND２。
第二行扫描信号WR２与所述第一行扫描信号WR1的时序不同, 但不会额外增加外围驱动信号数量，仅需在做像素布线时，从上一行扫描信号走线中，牵引其中一条走线以个别开关控制驱动信号的时序即可。
在驱动时，首先，第一行扫描信号WR１控制第三薄膜晶体管T３、第二薄膜晶体管T2开启，第二数据信号Data2经过第二薄膜晶体管T２进入到第一薄膜晶体管T１的栅极及第一存储电容C1、第二存储电容C2，然后第一薄膜晶体管T1开启，有机发光二级管OLED发光。其次，第一行扫描信号WR１关闭，则第二薄膜晶体管T２与第三薄膜晶体管T３关闭，同时，第二行扫描信号WR２开启，则第四薄膜晶体管T４开启，第一数据信号Data1写入第二节点M，由于第一存储电容C1与第二存储电容C2的存储作用，第一薄膜晶体管T１的栅极电压仍可继续保持数据信号电压，使得第一薄膜晶体管T１处于导通状态，驱动电流通过第一薄膜晶体管T１进入有机发光二级管OLED，驱动有机发光二级管OLED发光。
在本申请的结构中，第一存储电容C1与第二存储电容C2在第一节点G处电性连接，这有利于保持第一节点G的电压的平衡，稳定地向T１供应数据信号。
如图2所示,像素低灰阶切为高灰阶的过程如下：
阶段1，第一行扫描信号WR１升为高电位,第三薄膜晶体管T３、第二薄膜晶体管T2开启，第二数据信号Data2电压15伏特，第一节点G与第二节点M的电位分别被复位为1伏特及-10伏特；
阶段2，第二行扫描信号WR2升为高电位，第一行扫描信号WR１将为低电位，第一数据信号Data1信号写入第二节点M，第二节点M的电位由-10伏特升为1伏特，此时，第一节点G的电位上升了11*C2/(C1+C2),因此，第一节点G的电位为1+11*C2/(C1+C2)；
阶段3，第二行扫描信号WR2持续维持高电位，画面由低灰阶切换为高灰阶，数据信号由1伏特升为10伏特，这时，第一节点G的电位上升了9*C2/(C1+C2)，因此，第一节点G的电位为1+20*C2/(C1+C2)，有机发光二级管OLED的电流为1.5mA。
如图3所示，像素高灰阶切为低灰阶的过程如下：
阶段1，第一行扫描信号WR１升为高电位,第三薄膜晶体管T３、第二薄膜晶体管T2开启，第一节点G与第二节点M的电位分别被复位为10伏特及-10伏特；
阶段2，第二行扫描信号WR2升为高电位，第一行扫描信号WR１将为低电位，第一数据信号Data1信号写入第二节点M，第二节点M的电位由-10伏特升为10伏特，此时，第一节点G的电位上升了20*C2/(C1+C2),因此，第一节点G的电位为[20*C2/(C1+C2)]-10；
阶段3，第二行扫描信号WR2持续维持高电位，画面由高灰阶切换为低灰阶，数据信号由10伏特降为1伏特，这时，第一节点G的电位下降了9*C2/(C1+C2)，因此，第一节点G的电位为[11*C2/(C1+C2)]-10，有机发光二级管OLED的电流为200 nA，画面显示低灰阶。
而，数据线的动态功耗I=fCV data 2，这里，f是面板的刷新率，C是面板的电容，可以发现，面板的动态功耗降低了一半以上。
在一些实施例中，第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3、第四薄膜晶体管T4为低温多晶硅薄膜晶体管，低温多晶硅薄膜晶体管均为P型薄膜晶体管；或第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3、第四薄膜晶体管T4为氧化物薄膜晶体管，氧化物薄膜晶体管均为N型氧化物薄膜晶体管。
本申请实施例还提供一种的显示装置，包括上述的显示面板，所述显示面板包括像素驱动电路，参考图1，像素驱动电路中，每个像素都具有4T2C像素结构，所述4T2C像素结构包括第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3、第四薄膜晶体管T4、第一存储电容C1、第二存储电容C2及有机发光二极管OLED。
第一薄膜晶体管T1的栅极电性连接至第一节点G，其源极电性连接至有机发光二极管OLED的阳极S，其漏极电性连接至电源正电压VDD。
第二薄膜晶体管T2的栅极接入第一行扫描信号WR1，其源极接入第二数据信号线Data2，其漏极电性连接至第一节点G。
第三薄膜晶体管T3的栅极接入第一行扫描信号WR1，其源极接入电源负电压VSS，其漏极连接至第二节点M。
第四薄膜晶体管T4的栅极接入第二行扫描信号WR2，其源极电性连接至所述第二节点M，其漏极接入第一数据信号线Data1。
第一存储电容C1的一端电性连接至第一节点G，其另一端电性连接至第一接地线GND1。
第二存储电容C2的一端电性连接至第二节点M，其另一端电性连接至第一节点G。
有机发光二极管OLED的阳极S电性连接至第一薄膜晶体管T1的源极，其阴极电性连接至第二接地线GND２。
WR２与所述第一行扫描信号WR1的时序不同, 但不会额外增加外围驱动信号数量，仅需在做像素布线时，从上一行扫描信号走线牵引其中一条走线以个别开关控制驱动信号的时序即可。
在驱动时，首先，第一行扫描信号WR１控制第三薄膜晶体管T３、第二薄膜晶体管T2开启，第二数据信号Data2经过第二薄膜晶体管T２进入到第一薄膜晶体管T１的栅极及第一存储电容C1、第二存储电容C2，然后第一薄膜晶体管T1开启，有机发光二级管OLED发光。其次，第一行扫描信号WR１关闭，则第二薄膜晶体管T２与第三薄膜晶体管T３关闭，同时，第二行扫描信号WR２开启，则第四薄膜晶体管T４开启，第一数据信号Data1写入第二节点M，由于第一存储电容C1与第二存储电容C2的存储作用，第一薄膜晶体管T１的栅极电压仍可继续保持数据信号电压，使得第一薄膜晶体管T１处于导通状态，驱动电流通过第一薄膜晶体管T１进入有机发光二级管OLED，驱动有机发光二级管OLED发光。
在本申请的结构中，第一存储电容C1与第二存储电容C2在第一节点G处电性连接，这有利于保持第一节点G的电压的平衡，稳定地向T１供应数据信号。
如图2所示,像素低灰阶切为高灰阶的过程如下：
阶段1，第一行扫描信号WR１升为高电位,第三薄膜晶体管T３、第二薄膜晶体管T2开启，第二数据信号Data2电压15伏特，第一节点G与第二节点M的电位分别被复位为1伏特及-10伏特；
阶段2，第二行扫描信号WR2升为高电位，第一行扫描信号WR１将为低电位，第一数据信号Data1信号写入第二节点M，第二节点M的电位由-10伏特升为1伏特，此时，第一节点G的电位上升了11*C2/(C1+C2),因此，第一节点G的电位为1+11*C2/(C1+C2)；
阶段3，第二行扫描信号WR2持续维持高电位，画面由低灰阶切换为高灰阶，数据信号由1伏特升为10伏特，这时，第一节点G的电位上升了9*C2/(C1+C2)，因此，第一节点G的电位为1+20*C2/(C1+C2)，有机发光二级管OLED的电流为1.5mA。
如图3所示，像素高灰阶切为低灰阶的过程如下：
阶段1，第一行扫描信号WR１升为高电位,第三薄膜晶体管T３、第二薄膜晶体管T2开启，第一节点G与第二节点M的电位分别被复位为10伏特及-10伏特；
阶段2，第二行扫描信号WR2升为高电位，第一行扫描信号WR１将为低电位，第一数据信号Data1信号写入第二节点M，第二节点M的电位由-10伏特升为10伏特，此时，第一节点G的电位上升了20*C2/(C1+C2),因此，第一节点G的电位为[20*C2/(C1+C2)]-10；
阶段3，第二行扫描信号WR2持续维持高电位，画面由高灰阶切换为低灰阶，数据信号由10伏特降为1伏特，这时，第一节点G的电位下降了9*C2/(C1+C2)，因此，第一节点G的电位为[11*C2/(C1+C2)]-10，有机发光二级管OLED的电流为200 nA，画面显示低灰阶。
而，数据线的动态功耗I=fCV data 2，这里，f是面板的刷新率，C是面板的电容，可以发现，面板的动态功耗降低一半以上。
在一些实施例中，第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3、第四薄膜晶体管T4为低温多晶硅薄膜晶体管，低温多晶硅薄膜晶体管均为P型薄膜晶体管；或第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3、第四薄膜晶体管T4为氧化物薄膜晶体管，氧化物薄膜晶体管均为N型氧化物薄膜晶体管。
以上各个操作的具体实施可参见前面的实施例，在此不再赘述。
综上所述，本申请实施例提供的本申请实施例提供一种像素驱动电路，所述像素驱动电路包括第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第一存储电容、第二存储电容及有机发光二极管；其中，所述第一薄膜晶体管的栅极电性连接至第一节点，其源极电性连接至所述有机发光二极管的阳极，其漏极电性连接至电源正电压（VDD）；所述第二薄膜晶体管的栅极接入第一行扫描信号，其源极接入第二数据信号，其漏极电性连接至所述第一节点；所述第三薄膜晶体管的栅极接入所述第一行扫描信号，其源极接入电源负电压（VSS），其漏极电性连接至第二节点；所述第四薄膜晶体管的栅极接入第二行扫描信号，其源极电性连接至所述第二节点，其漏极接入第一数据信号；所述第一存储电容的一端电性连接至所述第一节点，其另一端电性连接至第一接地线；所述第二存储电容的一端电性连接至所述第二节点，其另一端电性连接至所述第一节点；所述有机发光二极管的阳极电性连接至所述第一薄膜晶体管的源极，其阴极电性连接至第二接地线；所述第二行扫描信号借用所述第一行扫描信号。本申请实施例通过4T2C像素驱动电路结构，能够显著降低AMOLED面板的数据电压，从而降低动态功耗，最终达到降低总功耗的目的。
可以理解的是，对本领域普通技术人员来说，可以根据本申请的技术方案及其发明构思加以等同替换或改变，而所有这些改变或替换都应属于本申请所附的权利要求的保护范围。

Claims (13)

  1. 一种像素驱动电路，其中，包括第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第一存储电容、第二存储电容及有机发光二极管；
    其中，所述第一薄膜晶体管的栅极电性连接至第一节点，其源极电性连接至所述有机发光二极管的阳极，其漏极电性连接至VDD；
    所述第二薄膜晶体管的栅极接入第一行扫描信号，其源极接入第二数据信号，其漏极电性连接至所述第一节点；
    所述第三薄膜晶体管的栅极接入所述第一行扫描信号，其源极接入VSS，其漏极电性连接至第二节点；
    所述第四薄膜晶体管的栅极接入第二行扫描信号，其源极电性连接至所述第二节点，其漏极接入第一数据信号；
    所述第一存储电容的一端电性连接至所述第一节点，其另一端电性连接至第一接地线；
    所述第二存储电容的一端电性连接至所述第二节点，其另一端电性连接至所述第一节点；
    所述有机发光二极管的阳极电性连接至所述第一薄膜晶体管的源极，其阴极电性连接至第二接地线。
  2. 根据权利要求1所述的像素驱动电路，其中，所述第二行扫描信号与所述第一行扫描信号的时序不同。
  3. 根据权利要求1所述的像素驱动电路，其中，所述第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管为低温多晶硅薄膜晶体管，所述低温多晶硅薄膜晶体管均为P型薄膜晶体管；或所述第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管为氧化物薄膜晶体管，所述氧化物薄膜晶体管均为N型氧化物薄膜晶体管。
  4. 根据权利要求2所述的像素驱动电路，其中，所述像素驱动电路由低灰阶切为高灰阶的工作过程如下：
    像素驱动电路工作时，当所述第一行扫描信号为高电位时，所述第二薄膜晶体管、所述第三薄膜晶体管开启，所述第一节点与所述第二节点的电位分别复位为V1及V2；
    当所述第二行扫描信号为高电位时，所述第一行扫描信号降为低电位，第一数据信号写入所述第二节点，所述第二节点由低电位V2升为高电位V1，此时，所述第一节点的电位上升了（V1-V2）*C2/（C1+C2），变为：V1 +[（V1-V2）*C2/（C1+C2）],其中，V1-V2为所述第二节点的电位差，C2是所述第二存储电容的电容值，C1是所述第一存储电容的电容值；
    当所述第二行扫描信号维持为高电位时，所述像素驱动电路由低灰阶切为高灰阶，所述第二节点的数据电压由V1升为V3，此时，所述第一节点的电位上升了（V3-V1）*C2/（C1+C2），变为: V1+[（V1-V2）*C2/（C1+C2）]+[ （V3-V1）*C2/（C1+C2）]。
  5. 根据权利要求4所述的像素驱动电路，其中，所述像素驱动电路由高灰阶切为低灰阶的工作过程如下：
    像素驱动电路工作时，当所述第一行扫描信号为高电位时，所述第二薄膜晶体管、所述第二薄膜晶体管开启，所述第一节点与所述第二节点的电位分别复位为V3及V2；
    当所述第二行扫描信号为高电位时，所述第一行扫描信号降为低电位，第一数据信号写入所述第二节点，所述第二节点由低电位V2升为高电位V3，此时，所述第一节点的电位上升了（V3-V2）*C2/（C1+C2），变为：[（V3-V2）*C2/（C1+C2）]+V2，其中，V3-V2是所述第二节点的电位差，C2是所述第二存储电容的电容值，C1是所述第一存储电容的电容值；
    当所述第二行扫描信号维持为高电位时，所述像素驱动电路由低高灰阶切为低灰阶，所述第二节点的数据电压由V3降低为V1，此时，所述第一节点的电位下降了（V3-V1）*C2/（C1+C2），变为: [（V3-V2）*C2/（C1+C2）]+V2-[ （V3-V1）*C2/（C1+C2）]。
  6. 一种OLED显示面板，包括像素驱动电路，其中，所述像素驱动电路包括第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第一存储电容、第二存储电容及有机发光二极管；
    其中，所述第一薄膜晶体管的栅极电性连接至第一节点，其源极电性连接至所述有机发光二极管的阳极，其漏极电性连接至VDD；
    所述第二薄膜晶体管的栅极接入第一行扫描信号，其源极接入第二数据信号线，其漏极电性连接至所述第一节点；
    所述第三薄膜晶体管的栅极接入所述第一行扫描信号，其源极接入VSS，其漏极电性连接至第二节点；
    所述第四薄膜晶体管的栅极接入第二行扫描信号，其源极电性连接至所述第二节点，其漏极接入第一数据信号线；
    所述第一存储电容的一端电性连接至所述第一节点，其另一端电性连接至第一接地线；
    所述第二存储电容的一端电性连接至所述第二节点，其另一端电性连接至所述第一节点；
    所述有机发光二极管的阳极电性连接至所述第一薄膜晶体管的源极，其阴极电性连接至第二接地线；
    所述第二行扫描信号与所述第一行扫描信号的时序不同。
  7. 根据权利要求6所述的OLED显示面板，其中，所述第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管为低温多晶硅薄膜晶体管，所述低温多晶硅薄膜晶体管均为P型薄膜晶体管；或所述第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管为氧化物薄膜晶体管，所述氧化物薄膜晶体管均为N型氧化物薄膜晶体管。
  8. 根据权利要求6所述的OLED显示面板，其中，所述像素驱动电路由低灰阶切为高灰阶的工作过程如下：
    像素驱动电路工作时，当所述第一行扫描信号为高电位时，所述第二薄膜晶体管、所述第二薄膜晶体管开启，所述第一节点与所述第二节点的电位分别复位为V1及V2；
    当所述第二行扫描信号为高电位时，所述第一行扫描信号降为低电位，第一数据信号写入所述第二节点，所述第二节点由低电位V2升为高电位V1，此时，所述第一节点的电位上升了（V1-V2）*C2/（C1+C2），变为：V1 +[（V1-V2）*C2/（C1+C2）],其中，V1-V2为所述第二节点的电位差，C2是所述第二存储电容的电容值，C1是所述第一存储电容的电容值；
    当所述第二行扫描信号维持为高电位时，所述像素驱动电路由低灰阶切为高灰阶，所述第二节点的数据电压由V1升为V3，此时，所述第一节点的电位上升了（V3-V1）*C2/（C1+C2），变为: V1+[（V1-V2）*C2/（C1+C2）]+[ （V3-V1）*C2/（C1+C2）]。
  9. 根据权利要求8所述的OLED显示面板，其中，所述像素驱动电路由高灰阶切为低灰阶的工作过程如下：
    像素驱动电路工作时，当所述第一行扫描信号为高电位时，所述第二薄膜晶体管、所述第二薄膜晶体管开启，所述第一节点与所述第二节点的电位分别复位为V3及V2；
    当所述第二行扫描信号为高电位时，所述第一行扫描信号降为低电位，第一数据信号写入所述第二节点，所述第二节点由低电位V2升为高电位V3，此时，所述第一节点的电位上升了了（V3-V2）*C2/（C1+C2），变为：[（V3-V2）*C2/（C1+C2）]+V2，其中，V3-V2是所述第二节点的电位差，C2是所述第二存储电容的电容值，C1是所述第一存储电容的电容值；
    当所述第二行扫描信号维持为高电位时，所述像素驱动电路由低高灰阶切为低灰阶，所述第二节点的数据电压由V3降低为V1，此时，所述第一节点的电位下降了（V3-V1）*C2/（C1+C2），变为: [（V3-V2）*C2/（C1+C2）]+V2-[ （V3-V1）*C2/（C1+C2）]。
  10. 一种显示装置，包括显示面板，所述显示面板包括像素驱动电路，其中，所述像素驱动电路包括第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第一存储电容、第二存储电容及有机发光二极管；
    其中，所述第一薄膜晶体管的栅极电性连接至第一节点，其源极电性连接至所述有机发光二极管的阳极，其漏极电性连接至VDD；
    所述第二薄膜晶体管的栅极接入第一行扫描信号，其源极接入第二数据信号线，其漏极电性连接至所述第一节点；
    所述第三薄膜晶体管的栅极接入所述第一行扫描信号，其源极接入VSS，其漏极电性连接至第二节点；
    所述第四薄膜晶体管的栅极接入第二行扫描信号，其源极电性连接至所述第二节点，其漏极接入第一数据信号线；
    所述第一存储电容的一端电性连接至所述第一节点，其另一端电性连接至第一接地线；
    所述第二存储电容的一端电性连接至所述第二节点，其另一端电性连接至所述第一节点；
    所述有机发光二极管的阳极电性连接至所述第一薄膜晶体管的源极，其阴极电性连接至第二接地线；
    所述第二行扫描信号与所述第一行扫描信号的时序不同。
  11. 根据权利要求10所述的显示装置，其中，所述第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管为低温多晶硅薄膜晶体管，所述低温多晶硅薄膜晶体管均为P型薄膜晶体管；或所述第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管为氧化物薄膜晶体管，所述氧化物薄膜晶体管均为N型氧化物薄膜晶体管。
  12. 根据权利要求10所述的显示装置，其中，所述像素驱动电路由低灰阶切为高灰阶的工作过程如下：
    像素驱动电路工作时，当所述第一行扫描信号为高电位时，所述第二薄膜晶体管、所述第二薄膜晶体管开启，所述第一节点与所述第二节点的电位分别复位为V1及V2；
    当所述第二行扫描信号为高电位时，所述第一行扫描信号降为低电位，第一数据信号写入所述第二节点，所述第二节点由低电位V2升为高电位V1，此时，所述第一节点的电位上升了（V1-V2）*C2/（C1+C2），变为：V1 +[（V1-V2）*C2/（C1+C2）],其中，V1-V2为所述第二节点的电位差，C2是所述第二存储电容的电容值，C1是所述第一存储电容的电容值；
    当所述第二行扫描信号维持为高电位时，所述像素驱动电路由低灰阶切为高灰阶，所述第二节点的数据电压由V1升为V3，此时，所述第一节点的电位上升了（V3-V1）*C2/（C1+C2），变为: V1+[（V1-V2）*C2/（C1+C2）]+[ （V3-V1）*C2/（C1+C2）]。
  13. 根据权利要求12所述的显示装置，其中，所述像素驱动电路由高灰阶切为低灰阶的工作过程如下：
    像素驱动电路工作时，当所述第一行扫描信号为高电位时，所述第二薄膜晶体管、所述第二薄膜晶体管开启，所述第一节点与所述第二节点的电位分别复位为V3及V2；
    当所述第二行扫描信号为高电位时，所述第一行扫描信号降为低电位，第一数据信号写入所述第二节点，所述第二节点由低电位V2升为高电位V3，此时，所述第一节点的电位上升了了（V3-V2）*C2/（C1+C2），变为：[（V3-V2）*C2/（C1+C2）]+V2，其中，V3-V2是所述第二节点的电位差，C2是所述第二存储电容的电容值，C1是所述第一存储电容的电容值；
    当所述第二行扫描信号维持为高电位时，所述像素驱动电路由低高灰阶切为低灰阶，所述第二节点的数据电压由V3降低为V1，此时，所述第一节点的电位下降了（V3-V1）*C2/（C1+C2），变为: [（V3-V2）*C2/（C1+C2）]+V2-[ （V3-V1）*C2/（C1+C2）]。
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