WO2021169044A1 - 蓝相液晶像素电路、其驱动方法及显示装置 - Google Patents

蓝相液晶像素电路、其驱动方法及显示装置 Download PDF

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Publication number
WO2021169044A1
WO2021169044A1 PCT/CN2020/089425 CN2020089425W WO2021169044A1 WO 2021169044 A1 WO2021169044 A1 WO 2021169044A1 CN 2020089425 W CN2020089425 W CN 2020089425W WO 2021169044 A1 WO2021169044 A1 WO 2021169044A1
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Prior art keywords
electric switch
scan signal
switch
terminal
pixel circuit
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PCT/CN2020/089425
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English (en)
French (fr)
Inventor
薛炎
Original Assignee
深圳市华星光电半导体显示技术有限公司
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Priority to US16/767,502 priority Critical patent/US11257453B2/en
Publication of WO2021169044A1 publication Critical patent/WO2021169044A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3659—Control of matrices with row and column drivers using an active matrix the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/3406—Control of illumination source
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3655—Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/043—Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0469—Details of the physics of pixel operation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0814—Several active elements per pixel in active matrix panels used for selection purposes, e.g. logical AND for partial update
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen

Definitions

  • the present invention relates to the technical field of liquid crystal display, in particular to a blue phase liquid crystal pixel circuit, a driving method thereof, and a display device.
  • blue phase liquid crystal display Due to the rise of the global information society and the development of science and technology, the field of display technology is changing with each passing day, and there are more and more types of display technologies, such as traditional liquid crystal display technology, blue phase liquid crystal display technology, and organic electroluminescent diodes (Organic Light Emitting Diode, OLED) display technology, electrophoretic display technology, etc.
  • OLED Organic Light Emitting Diode
  • the blue phase liquid crystal display has the advantages of sub-millimeter response time, simple preparation process, wide viewing angle, etc., and has attracted the attention of the industry and more and more researchers worldwide.
  • the most important feature of blue-phase liquid crystals is that they generally require a higher data voltage to drive liquid crystal molecules.
  • the data signal voltage is generally not less than 30V
  • the present invention provides a blue phase liquid crystal pixel circuit, a driving method thereof, and a display device to reduce the data signal voltage of the liquid crystal panel, thereby reducing the power consumption of the panel.
  • a blue phase liquid crystal pixel circuit which adopts a 5T2C structure (5 electric switches and 2 capacitors), and is applied to a liquid crystal display device to drive light-emitting diodes to emit light, including:
  • the first end of the first electrical switch is connected to the second end of the fourth electrical switch, and the second end of the first electrical switch is connected to the second end of the third electrical switch at the first node, The first end of the fifth electric switch, the second end of the first capacitor,
  • the control terminal of the second electric switch is connected to the first scan line to receive the first scan signal, the first terminal of the second electric switch is connected to the data line to receive the data signal voltage, and the second terminal of the second electric switch is at The second node is connected to the control terminal of the first electrical switch and the first terminal of the first capacitor,
  • the control terminal of the third electric switch is connected to the second scan line to receive the second scan signal, and the first terminal of the third electric switch is connected to the initial potential line to receive a preset initial voltage,
  • the control terminal of the fourth electric switch is connected to the third scan signal line to receive the third scan signal, and is connected to the control terminal of the fifth electric switch, and the first terminal of the fourth electric switch is connected to the power line to receive power Signal,
  • the second terminal of the fifth electrical switch is connected to the first terminal of the second capacitor and the anode of the light emitting diode at the third node, and the cathode of the light emitting diode is connected to the first reference potential line to receive the first reference voltage ,
  • the second end of the second capacitor is connected to the common ground.
  • the third scan signal line is a row scan signal line
  • the third scan signal is a row scan signal.
  • first to fifth electrical switches are all NPN type field effect transistors.
  • first to fifth electrical switches are all NPN-type field effect transistors, and the control terminals, first terminals, and second terminals of the first to fifth electrical switches are gates, drains, and sources, respectively .
  • first to fifth electrical switches are all thin film transistors.
  • first to fifth electrical switches are all IGZO thin film transistors.
  • the third scan signal is a row scan signal.
  • the first reference voltage is 0V.
  • a driving method of a blue phase liquid crystal pixel circuit which is applied to the above-mentioned blue phase liquid crystal pixel circuit, and includes the following steps:
  • the first stage the first scan signal rises to a high potential, the second scan signal rises to a high potential, the third scan signal falls to a low potential, and the first terminal of the second electrical switch is loaded with a preset Reference voltage (Vref), the second electrical switch and the third electrical switch are turned on, the fourth electrical switch and the fifth electrical switch are turned off, and the first node and the second node are reset to The preset initial voltage (Vini) and the preset reference voltage (Vref);
  • the second stage the third scan signal rises to a high level, the fourth electric switch and the fifth electric switch are turned on, the first terminal of the first electric switch maintains a high level, and the second scan signal Drops to a low potential, the third electric switch is closed, and the first node voltage is raised to the difference (Vref-Vth) of the preset reference voltage minus the threshold voltage of the first electric switch;
  • the third stage the third scan signal drops to a low level, the fourth electric switch and the fifth electric switch are closed, the first scan signal maintains a high level, and the first end of the second electric switch Load a data signal voltage, and the second node potential is written into the data signal voltage;
  • the third scan signal rises to a high potential
  • the fourth electrical switch and the fifth electrical switch are turned on
  • the first node and the third node rise in potential
  • the second node rises To a high potential
  • the first electrical switch maintains an on state
  • the potentials of the first node and the third node are raised to a high potential.
  • time sequence of the first scan signal and the second scan signal are different but the absolute value of the maximum voltage value is the same.
  • a display device including the above-mentioned pixel circuit.
  • the pixel circuit used in the present invention due to the pixel circuit used in the present invention, it is not necessary to use a higher data voltage, which can significantly reduce the data voltage used by the liquid crystal panel. Since the data dynamic power consumption is proportional to the square of the data voltage, the data voltage is reduced. Can significantly reduce panel power consumption.
  • the circuit, method and device provided by the present invention both have a threshold voltage (Vth) compensation effect, which is beneficial to improve the uniformity of display brightness.
  • Vth threshold voltage
  • FIG. 1 shows a schematic structural diagram of a blue phase liquid crystal pixel circuit according to an embodiment of the present invention.
  • FIG. 2 shows a timing diagram of key signals of a blue phase liquid crystal pixel circuit and a driving method thereof according to an embodiment of the present invention.
  • FIG. 3 shows an example diagram of the value or amplitude of the key signal of the blue phase liquid crystal pixel circuit according to an embodiment of an embodiment of the present invention.
  • FIG. 4 shows a schematic diagram of a threshold voltage compensation effect of a blue phase liquid crystal pixel circuit according to an embodiment of an embodiment of the present invention.
  • FIG. 5 shows a schematic diagram of a circuit working state in the first stage of a driving method of a blue phase liquid crystal pixel circuit according to an embodiment of the present invention.
  • FIG. 6 shows a schematic diagram of the circuit working state in the second stage of the driving method of the blue phase liquid crystal pixel circuit according to an embodiment of the present invention.
  • FIG. 7 shows a schematic diagram of the circuit working state in the third stage of the driving method of the blue phase liquid crystal pixel circuit according to an embodiment of the present invention.
  • FIG. 8 shows a schematic diagram of the circuit working state in the fourth stage of the driving method of the blue phase liquid crystal pixel circuit according to an embodiment of the present invention.
  • FIG. 9 shows an example diagram of the working state and key parameters of the key components of the blue phase liquid crystal pixel circuit and the driving method thereof according to an embodiment of the present invention.
  • FIG. 10 shows a timing diagram of key parameters of a blue phase liquid crystal pixel circuit and a driving method thereof according to an embodiment of the present invention. .
  • FIG. 1 shows a schematic structural diagram of a blue phase liquid crystal pixel circuit according to an embodiment of the present invention. As shown in Figure 1, the circuit includes:
  • the first terminal of the first electric switch T1 is connected to the second terminal of the fourth electric switch T4, and the second terminal of the first electric switch T1 is connected to the third electric switch T3 at the first node S
  • the control terminal of the second electric switch T2 is connected to the first scan line to receive the first scan signal Scan1
  • the first terminal of the second electric switch T2 is connected to the data line to receive the data signal voltage Data
  • the second electric switch T2 The second terminal of is connected to the control terminal of the first electrical switch T1 and the first terminal of the first capacitor C1 at the second node G,
  • the control end of the third electrical switch T3 is connected to the second scan line to receive the second scan signal Scan2, and the first end of the third electrical switch T3 is connected to the initial potential line to receive the preset initial voltage Vini,
  • the control terminal of the fourth electric switch T4 is connected to the third scan signal line to receive the third scan signal EM, and is connected to the control terminal of the fifth electric switch T5, and the first terminal of the fourth electric switch T4 is connected
  • the power line receives the power signal VDD
  • the second terminal of the fifth electrical switch T5 is connected to the first terminal of the second capacitor C2 and the anode of the light emitting diode at the third node M, and the cathode of the light emitting diode is connected to the first reference potential line to receive the first Reference voltage Tcom,
  • the second terminal of the second capacitor C2 is connected to the common ground VSS.
  • the third scan signal line is a horizontal scan signal line
  • the third scan signal EM is a horizontal scan signal
  • the first to fifth electrical switches T5 are all NPN type field effect transistors.
  • the first to fifth electrical switches T5 are all NPN type field effect transistors, and the control terminals, first terminals, and second terminals of the first to fifth electrical switches T5 are gates, Drain and source.
  • the first to fifth electrical switches T5 are all IGZO thin film transistors.
  • the third scan signal EM is a horizontal scan signal.
  • the cathode of the light emitting diode is grounded, and the first reference voltage Tcom is 0V.
  • the schematic diagram of the pixel circuit structure in Figure 1 is a circuit structure corresponding to a light-emitting element.
  • the above description is based on a pixel circuit corresponding to a light-emitting element.
  • the actual display is a pixel array with multiple pixels and corresponding circuit units. Multiple.
  • the value or value range of the key signal of the pixel circuit in an embodiment is shown.
  • the maximum value of the data signal voltage Data is 10V, which is generally not less than 30V compared to the data signal voltage in some prior art, which significantly reduces the data signal voltage.
  • the dynamic power consumption is proportional to the square of the data signal voltage.
  • the power consumption of the liquid crystal panel is reduced.
  • the working process of the pixel circuit is as follows:
  • First stage A1 The first scan signal Scan1 rises to a high level, the second scan signal Scan2 rises to a high level, the third scan signal EM falls to a low level, and the first scan signal of the second electrical switch A preset reference voltage (Vref) is applied to the terminal, the second electrical switch T2 and the third electrical switch T3 are turned on, the fourth electrical switch T4 and the fifth electrical switch T5 are turned off, and the first node S And the second node G are respectively reset to the preset initial voltage (Vini) and the preset reference voltage (Vref);
  • Second stage A2 The third scan signal EM rises to a high potential, the fourth electrical switch T4 and the fifth electrical switch T5 are turned on, and the first terminal of the first electrical switch T1 maintains a high potential, so The second scan signal Scan2 drops to a low level, the third electric switch T3 is closed, and the voltage at the first node S is raised to the difference between the preset reference voltage minus the threshold voltage of the first electric switch T1 (Vref-Vth);
  • the third stage A3 the third scan signal EM drops to a low level, the fourth electrical switch T4 and the fifth electrical switch T5 are closed, the first scan signal Scan1 maintains a high level, and the second electrical switch The first terminal of the switch T2 is loaded with the data signal voltage Data, and the second node G is written with the data signal voltage Data;
  • Fourth stage A4 The third scan signal EM rises to a high potential, the fourth electrical switch T4 and the fifth electrical switch T5 are turned on, and the first node S and the third node M rise in electrical potential.
  • the second node G rises to a high potential, the first electrical switch T1 maintains an on state, and finally the potentials of the first node S and the third node M are raised to a high potential.
  • FIG. 4 shows a schematic diagram of the threshold voltage compensation effect of the pixel circuit in an embodiment.
  • the threshold voltage Vth of the first electrical switch T1 is positively biased by 2V, negatively biased by -2V, and unbiased
  • the changes in the potential of the first node G, the second node S, and the third node M can be seen from the figure.
  • the potential at point M remains the same eventually, regardless of the threshold voltage Vth of the first electrical switch T1.
  • a driving method of a blue phase liquid crystal pixel circuit is provided, which is applied to the above blue phase liquid crystal pixel circuit:
  • the driving method of the blue phase liquid crystal pixel circuit includes the following steps:
  • First stage A1 The first scan signal Scan1 rises to a high level, the second scan signal Scan2 rises to a high level, the third scan signal EM falls to a low level, and the first scan signal of the second electrical switch A preset reference voltage (Vref) is applied to the terminal, the second electrical switch T2 and the third electrical switch T3 are turned on, the fourth electrical switch T4 and the fifth electrical switch T5 are turned off, and the first node S And the second node G are respectively reset to the preset initial voltage (Vini) and the preset reference voltage (Vref);
  • Second stage A2 The third scan signal EM rises to a high potential, the fourth electrical switch T4 and the fifth electrical switch T5 are turned on, and the first terminal of the first electrical switch T1 maintains a high potential, so The second scan signal Scan2 drops to a low level, the third electric switch T3 is closed, and the voltage at the first node S is raised to the difference between the preset reference voltage minus the threshold voltage of the first electric switch T1 (Vref-Vth);
  • the third stage A3 the third scan signal EM drops to a low level, the fourth electrical switch T4 and the fifth electrical switch T5 are closed, the first scan signal Scan1 maintains a high level, and the second electrical switch The first terminal of the switch T2 is loaded with the data signal voltage Data, and the second node G is written with the data signal voltage Data;
  • Fourth stage A4 The third scan signal EM rises to a high potential, the fourth electrical switch T4 and the fifth electrical switch T5 are turned on, and the first node S and the third node M rise in potential.
  • the second node G rises to a high potential, the first electrical switch T1 maintains an on state, and finally the potentials of the first node S and the third node M are raised to a high potential.
  • the driving method of the blue phase liquid crystal pixel circuit includes the following steps:
  • the first stage A1 the first scan signal Scan1 rises to a high potential +15V, the second scan signal Scan2 rises to a high potential +15V, the third scan signal EM falls to a low potential -6V, and the first
  • Fourth stage A4 The third scan signal EM rises to a high potential +40V, the fourth electrical switch T4 and the fifth electrical switch T5 are turned on, and the first node S and the third node M are at potential Raised, the second node G rises to a high potential +35V, the first electrical switch T1 remains in an on state, and finally the potentials of the first node S and the third node M are raised to a high potential +30V.
  • the first stage A1 is the reset stage
  • the second stage A2 is the threshold voltage extraction stage
  • the third stage A3 is the data writing stage
  • the fourth stage A4 is the light-emitting stage.
  • the first scan signal Scan1 may also fall to a low level in the late stage of the first stage A1 after the first scan signal Scan1 rises to a high potential +15V.
  • the potential is -6V (but A2 still rises to a high potential +15V in the second stage).
  • the data signal voltage Data +10V in the early stage of the fourth stage A4
  • the data signal voltage Data +5V in the later stage of the fourth stage A4.
  • a display device including a blue phase liquid crystal pixel circuit, wherein a single liquid crystal pixel circuit includes:
  • the first end of the first electrical switch T1 is connected to the second end of the fourth electrical switch T4, and the second end of the first electrical switch T1 is connected to the third electrical switch T3 at the first node S
  • the second end of the fifth electrical switch T5 the second end of the first capacitor C1
  • the control terminal of the second electric switch T2 is connected to the first scan line to receive the first scan signal Scan1
  • the first terminal of the second electric switch T2 is connected to the data line to receive the data signal voltage Data
  • the second electric switch T2 The second terminal of is connected to the control terminal of the first electrical switch T1 and the first terminal of the first capacitor C1 at the second node G,
  • the control end of the third electrical switch T3 is connected to the second scan line to receive the second scan signal Scan2, and the first end of the third electrical switch T3 is connected to the initial potential line to receive the preset initial voltage Vini,
  • the control terminal of the fourth electric switch T4 is connected to the third scan signal line to receive the third scan signal EM, and is connected to the control terminal of the fifth electric switch T5, and the first terminal of the fourth electric switch T4 is connected
  • the power line receives the power signal VDD
  • the second end of the fifth electrical switch T5 is connected to the first end of the second capacitor C2 and the anode of the light emitting diode at the third node M, and the cathode of the light emitting diode is connected to the first reference potential line to receive the first Reference voltage Tcom,
  • the second terminal of the second capacitor C2 is connected to the common ground VSS.
  • the third scan signal line is a horizontal scan signal line
  • the third scan signal EM is a horizontal scan signal
  • the first to fifth electrical switches T5 are all NPN type field effect transistors.
  • the first to fifth electrical switches T5 are all NPN field effect transistors, and the control terminals, first terminals, and second terminals of the first to fifth electrical switches T5 are gates, Drain and source.
  • the first to fifth electrical switches T5 are all IGZO thin film transistors.
  • the third scan signal EM is a horizontal scan signal.
  • the cathode of the light emitting diode is grounded, and the first reference voltage Tcom is 0V.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features.
  • features defined with “first” and “second” may explicitly or implicitly include one or more features.
  • “multiple” means two or more than two, unless otherwise specifically defined.
  • the terms “include”, “include” or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device including a series of elements not only includes those elements, but also includes those elements that are not explicitly listed. Other elements of, or also include elements inherent to this process, method, article or equipment.
  • the pixel circuit used in the present invention due to the pixel circuit used in the present invention, it is not necessary to use a higher data voltage, which can significantly reduce the data voltage used by the liquid crystal panel. Since the data dynamic power consumption is proportional to the square of the data voltage, the data voltage is reduced. Can significantly reduce panel power consumption.
  • the circuit, method and device provided by the present invention both have a threshold voltage (Vth) compensation effect, which is beneficial to improve the uniformity of display brightness.

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Abstract

一种蓝相液晶像素电路、蓝相液晶像素电路的驱动方法及包含像素电路的显示装置，蓝相液晶像素电路包括第一到第五电开关(T1-T5)、第一到第二电容(C1-C2)。本技术方案能够显著降低面板的数据信号电压(Data)，从而实现降低功耗的目的，同时具有阈值电压(Vth)补偿效果。

Description

蓝相液晶像素电路、其驱动方法及显示装置 技术领域
本发明涉及液晶显示技术领域，具体地涉及一种蓝相液晶像素电路、其驱动方法及显示装置。
 背景技术
由于全球信息社会的兴起，以及科技的发展，显示技术领域日新月异，显示技术种类也越来越多，例如包括传统的液晶显示技术，蓝相液晶显示技术，有机电致发光二极管(Organic Light Emitting Diode，OLED)显示技术，电泳显示技术等。蓝相液晶显示具有亚毫米级的响应时间、制备工艺简单、视角广等优点，在全球范围内受到产业界和越来越多研究人员的关注。然而蓝相液晶的最主要特点是一般需要较高的数据电压才能驱动液晶分子，比如传统采用1T1C结构（1个晶体管1个电容）的像素电路的液晶面板，数据信号电压一般不少于30V,根据动态功耗计算公式p=fcV2，动态功耗与数据信号电压的平方成正比，在数据信号电压较高的情况下，面板的功耗也较大。。
 技术问题
有鉴于此，本发明提供一种蓝相液晶像素电路、其驱动方法及显示装置，以降低液晶面板的数据信号电压，从而降低面板功耗。
 技术解决方案
本发明实施例提供如下技术方案：
根据本发明一方面，提供一种蓝相液晶像素电路，采用5T2C结构（5个电开关2个电容），应用于液晶显示设备中以驱动发光二极管发光，包括：
第一电开关、第二电开关、第三电开关、第四电开关、第五电开关、第一电容、第二电容，
所述第一电开关的第一端连接至所述第四电开关的第二端，所述第一电开关的第二端在第一节点连接至所述第三电开关的第二端、所述第五电开关的第一端、所述第一电容的第二端，
所述第二电开关的控制端连接至第一扫描线接收第一扫描信号，所述第二电开关的第一端连接数据线接收数据信号电压，所述第二电开关的第二端在第二节点连接至所述第一电开关的控制端、所述第一电容器的第一端，
所述第三电开关的控制端连接至第二扫描线接收第二扫描信号，所述第三电开关的第一端连接初始电位线接收预设初始电压，
所述第四电开关的控制端连接至第三扫描信号线收第三扫描信号，并连接至所述第五电开关的控制端，所述第四电开关的第一端连接电源线接收电源信号，
所述第五电开关的第二端在第三节点连接所述第二电容电的第一端、发光二极管的阳极，所述发光二级管的阴极连接第一参考电位线接收第一参考电压，
所述第二电容的第二端连接至公共接地。
进一步的，所述第三扫描信号线为行扫描信号线，第三扫描信号为行扫描信号。
进一步的，所述第一至第五电开关均为NPN型场效应管。
进一步的，所述第一至第五电开关均为NPN型场效应管，所述第一至第五电开关的控制端、第一端及第二端分别为栅极、漏极及源极。
进一步的，所述第一至第五电开关均为薄膜晶体管。
进一步的，所述第一至第五电开关均为IGZO薄膜晶体管。
进一步的，所述第三扫描信号为行扫描信号。
进一步的，所述第一参考电压为0V。
根据本发明另一方面，提供了一种蓝相液晶像素电路的驱动方法，应用于上述所述的蓝相液晶像素电路，包括以下步骤：
第一阶段：所述第一扫描信号升为高电位，所述第二扫描信号升为高电位，所述第三扫描信号降为低电位，所述第二电开关的第一端加载预设参考电压（Vref），所述第二电开关、所述第三电开关打开，所述第四电开关、所述第五电开关关闭，所述第一节点和所述第二节点分别复位至所述预设初始电压（Vini）和所述预设参考电压（Vref）；
第二阶段：所述第三扫描信号升为高电位，所述第四电开关、所述第五电开关打开，所述第一电开关的第一端维持高电位，所述第二扫描信号降为低电位，所述第三电开关关闭，所述第一节点电压被抬升至所述预设参考电压减所述第一电开关的阈值电压的差值（Vref-Vth）；
 第三阶段：所述第三扫描信号降为低电位，所述第四电开关、所述第五电开关关闭，所述第一扫描信号维持高电位，所述第二电开关的第一端加载数据信号电压，所述第二节点电位写入数据信号电压；
第四阶段：所述第三扫描信号升为高电位，所述第四电开关、所述第五电开关打开，所述第一节点、所述第三节点电位抬升，所述第二节点抬升至高电位，所述第一电开关维持开启状态，最终所述第一节点、所述第三节点电位被抬升至高电位。
进一步的，所述的第一扫描信号和第二扫描信号的时序不同但最大电压值的绝对值相同。
根据本发明另一方面，提供了一种显示装置，该显示装置，包括上述的像素电路。
 有益效果
根据本发明的技术方案，由于本发明采用的像素电路，可以不必采用较高的数据电压，可显著降低液晶面板使用的数据电压，由于数据动态功耗与数据电压的平方成正比，降低数据电压可以显著降低面板功耗。同时，本发明提供的电路、方法及装置兼具阈值电压（Vth）补偿效果，有利于提升显示亮度的均匀性。当然，实施本发明的任一产品或方法并不一定需要同时达到以上所述的所有优点。
 附图说明
为了更清楚地说明本发明具体实施方式或现有技术中的技术方案，下面将对具体实施方式或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图是本发明的一些实施方式，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
附图中的部件不是成比例绘制的，而只是为了示出本发明的原理。为了便于示出和描述本发明的一些部分，附图中对应部分可能被放大，即，使其相对于在依据本发明实际制造的示例性装置中的其它部件变得更大。在附图中，相同的或类似的技术特征或部件将采用相同或类似的附图标记来表示。
图1示出了根据本发明的一个实施方式的蓝相液晶像素电路的结构示意图。
图2示出了根据本发明的一个实施方式的蓝相液晶像素电路及其驱动方法的关键信号的时序示意图。
图3示出了根据本发明一个实施方式的一个实施例的蓝相液晶像素电路的关键信号的值或幅值示例图。
图4示出了根据本发明一个实施方式的一个实施例的蓝相液晶像素电路的阈值电压补偿效果示意图。
图5示出了根据本发明一个实施方式的蓝相液晶像素电路的驱动方法的第一阶段的电路工作状态示意图。
图6示出了根据本发明一个实施方式的蓝相液晶像素电路的驱动方法的第二阶段的电路工作状态示意图。
图7示出了根据本发明一个实施方式的蓝相液晶像素电路的驱动方法的第三阶段的电路工作状态示意图。
图8示出了根据本发明一个实施方式的蓝相液晶像素电路的驱动方法的第四阶段的电路工作状态示意图。
图9示出了根据本发明一个实施方式的蓝相液晶像素电路及其驱动方法的电路关键元器件工作状态和关键参数示例图。
图10示出了根据本发明一个实施方式的蓝相液晶像素电路及其驱动方法的关键参数的时序示意图。。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
第一实施方式
根据本发明第一实施方式，提供一种蓝相液晶像素电路，采用5T2C结构。图1示出了根据本发明的一个实施方式的蓝相液晶像素电路的结构示意图。如图1所示，该电路包括：
第一电开关T1、第二电开关T2、第三电开关T3、第四电开关T4、第五电开关T5、第一电容C1、第二电容C2，
所述第一电开关T1的第一端连接至所述第四电开关T4的第二端，所述第一电开关T1的第二端在第一节点S连接至所述第三电开关T3的第二端、所述第五电开关T5的第一端、所述第一电容C1的第二端，
所述第二电开关T2的控制端连接至第一扫描线接收第一扫描信号Scan1，所述第二电开关T2的第一端连接数据线接收数据信号电压Data，所述第二电开关T2的第二端在第二节点G连接至所述第一电开关T1的控制端、所述第一电容器C1的第一端，
所述第三电开关T3的控制端连接至第二扫描线接收第二扫描信号Scan2，所述第三电开关T3的第一端连接初始电位线接收预设初始电压Vini，
所述第四电开关T4的控制端连接至第三扫描信号线收第三扫描信号EM，并连接至所述第五电开关T5的控制端，所述第四电开关T4的第一端连接电源线接收电源信号VDD，
所述第五电开关T5的第二端在第三节点M连接所述第二电容C2的第一端、发光二极管的阳极，所述发光二级管的阴极连接第一参考电位线接收第一参考电压Tcom，
所述第二电容C2的第二端连接至公共接地VSS。
在一个实施例中，所述第三扫描信号线为行扫描信号线，第三扫描信号EM为行扫描信号。
在一个实施例中，所述第一至第五电开关T5均为NPN型场效应管。
在一个实施例中，所述第一至第五电开关T5均为NPN型场效应管，所述第一至第五电开关T5的控制端、第一端及第二端分别为栅极、漏极及源极。
在一个实施例中，所述第一至第五电开关T5均为IGZO薄膜晶体管。
在一个实施例中，所述第三扫描信号EM为行扫描信号。
在一个实施例中，所述发光二极管的阴极接地，第一参考电压Tcom为0V。
需要说明的是，图1像素电路结构示意图是以一个发光元件对应的电路结构，以上是以一个发光元件对应的像素电路来说明，实际显示器为像素阵列，有多个像素，对应的电路单元也有多个。
参见图3，示出了一个实施例中像素电路的关键信号的取值或取值范围。该实施例中，数据信号电压Data的最大值为10v，相较于一些现有技术中的数据信号电压一般不少于30V，显著降低了数据信号电压，根据动态功耗计算公式p=fcV2，动态功耗与数据信号电压的平方成正比，在数据信号电压降低的情况下，降低了液晶面板的功耗。采用采用本发明的电路驱动液晶像素，可以使用相对较低的数据信号电压驱动液晶像素，从而可以降低液晶面板的功耗。
在一个实施例中，参见图1和图2，像素电路工作过程如下：
第一阶段A1：所述第一扫描信号Scan1升为高电位，所述第二扫描信号Scan2升为高电位，所述第三扫描信号EM降为低电位，所述第二电开关的第一端加载预设参考电压（Vref），所述第二电开关T2、所述第三电开关T3打开，所述第四电开关T4、所述第五电开关T5关闭，所述第一节点S和所述第二节点G分别复位至所述预设初始电压（Vini）和所述预设参考电压（Vref）；
第二阶段A2：所述第三扫描信号EM升为高电位，所述第四电开关T4、所述第五电开关T5打开，所述第一电开关T1的第一端维持高电位，所述第二扫描信号Scan2降为低电位，所述第三电开关T3关闭，所述第一节点S电压被抬升至所述预设参考电压减所述第一电开关T1的阈值电压的差值（Vref-Vth）；
第三阶段A3：所述第三扫描信号EM降为低电位，所述第四电开关T4、所述第五电开关T5关闭，所述第一扫描信号Scan1维持高电位，所述第二电开关T2的第一端加载数据信号电压Data，所述第二节点G电位写入数据信号电压Data；
第四阶段A4：所述第三扫描信号EM升为高电位，所述第四电开关T4、所述第五电开关T5打开，所述第一节点S、所述第三节点M电位抬升，所述第二节点G抬升至高电位，所述第一电开关T1维持开启状态，最终所述第一节点S、所述第三节点M电位被抬升至高电位。
第四阶段A4，第一节点G和第二节点S的电位差VGS= Data-(Vref-Vth),则对于第一电开关T1，VGS-Vth=Data-(Vref-Vth)-Vth=Data-Vref。可见，通过第一电开关的电流与第一电开关的阈值电压Vth无关。故根据本发明的一个实施方式的像素电路具有阈值电压补偿效果。
参见图4，示出了一个实施例中像素电路阈值电压补偿效果示意图。图中可见，第一电开关T1的阈值电压Vth正偏2V、负偏-2V、不偏时，第一节点G和第二节点S，以及第三节点M点电位的变化情况，从图中可知，M点电位最终保持一致，与第一电开关T1的阈值电压Vth无关。
第二实施方式
根据本发明第二实施方式，提供了一种蓝相液晶像素电路的驱动方法，应用于上述的蓝相液晶像素电路：
在一个实施例中，参见图1-3、图5-8，蓝相液晶像素电路的驱动方法包括以下步骤：
第一阶段A1：所述第一扫描信号Scan1升为高电位，所述第二扫描信号Scan2升为高电位，所述第三扫描信号EM降为低电位，所述第二电开关的第一端加载预设参考电压（Vref），所述第二电开关T2、所述第三电开关T3打开，所述第四电开关T4、所述第五电开关T5关闭，所述第一节点S和所述第二节点G分别复位至所述预设初始电压（Vini）和所述预设参考电压（Vref）；
第二阶段A2：所述第三扫描信号EM升为高电位，所述第四电开关T4、所述第五电开关T5打开，所述第一电开关T1的第一端维持高电位，所述第二扫描信号Scan2降为低电位，所述第三电开关T3关闭，所述第一节点S电压被抬升至所述预设参考电压减所述第一电开关T1的阈值电压的差值（Vref-Vth）；
第三阶段A3：所述第三扫描信号EM降为低电位，所述第四电开关T4、所述第五电开关T5关闭，所述第一扫描信号Scan1维持高电位，所述第二电开关T2的第一端加载数据信号电压Data，所述第二节点G电位写入数据信号电压Data；
第四阶段A4：所述第三扫描信号EM升为高电位，所述第四电开关T4、所述第五电开关T5打开，所述第一节点S、所述第三节点M电位抬升，所述第二节点G抬升至高电位，所述第一电开关T1维持开启状态，最终所述第一节点S、所述第三节点M电位被抬升至高电位。
在一个实施例中，参见图1-3、图5-10，蓝相液晶像素电路的驱动方法包括以下步骤：
第一阶段A1：所述第一扫描信号Scan1升为高电位+15V，所述第二扫描信号Scan2升为高电位+15V，所述第三扫描信号EM降为低电位-6V，所述第二电开关的第一端加载预设参考电压（Vref=+5V），所述第二电开关T2、所述第三电开关T3打开，所述第四电开关T4、所述第五电开关T5关闭，所述第一节点S和所述第二节点G分别复位至所述预设初始电压（Vini=+1V）和所述预设参考电压（Vref=+5V）；
第二阶段A2：所述第三扫描信号EM升为高电位+40V，所述第四电开关T4、所述第五电开关T5打开，所述第一电开关T1的第一端维持高电位+30V，所述第二扫描信号Scan2降为低电位-6V，所述第三电开关T3关闭，所述第一节点S电压被抬升至所述预设参考电压减所述第一电开关T1的阈值电压的差值（Vref-Vth=5V-Vth）；
第三阶段A3：所述第三扫描信号EM降为低电位-6V，所述第四电开关T4、所述第五电开关T5关闭，所述第一扫描信号Scan1维持高电位+15V，所述第二电开关T2的第一端加载数据信号电压Data=10V，所述第二节点G电位写入数据信号电压Data=+10V；
第四阶段A4：所述第三扫描信号EM升为高电位+40V，所述第四电开关T4、所述第五电开关T5打开，所述第一节点S、所述第三节点M电位抬升，所述第二节点G抬升至高电位+35V，所述第一电开关T1维持开启状态，最终所述第一节点S、所述第三节点M电位被抬升至高电位+30V。
其中，第一阶段A1为复位阶段，第二阶段A2为阈值电压提取阶段，第三阶段A3为数据写入阶段，第四阶段A4为发光阶段。
需要说明的是，在一些实施例中，在第一阶段A1，所述第一扫描信号Scan1也可在升为高电位+15V后，在第一阶段A1的后期第一扫描信号Scan1降为低电位-6V（但在第二阶段A2仍然升为高电位+15V）。在一些实施例中，在第四阶段A4，也可在第四阶段A4的前期数据信号电压Data=+10V，在第四阶段A4的后期数据信号电压Data=+5V。
第三实施方式
根据本发明第三实施方式，提供一种显示装置，包括蓝相液晶像素电路，其中单个液晶像素电路包括：
第一电开关T1、第二电开关T2、第三电开关T3、第四电开关T4、第五电开关T5、第一电容C1、第二电容C2，
所述第一电开关T1的第一端连接至所述第四电开关T4的第二端，所述第一电开关T1的第二端在第一节点S连接至所述第三电开关T3的第二端、所述第五电开关T5的第一端、所述第一电容C1的第二端，
所述第二电开关T2的控制端连接至第一扫描线接收第一扫描信号Scan1，所述第二电开关T2的第一端连接数据线接收数据信号电压Data，所述第二电开关T2的第二端在第二节点G连接至所述第一电开关T1的控制端、所述第一电容器C1的第一端，
所述第三电开关T3的控制端连接至第二扫描线接收第二扫描信号Scan2，所述第三电开关T3的第一端连接初始电位线接收预设初始电压Vini，
所述第四电开关T4的控制端连接至第三扫描信号线收第三扫描信号EM，并连接至所述第五电开关T5的控制端，所述第四电开关T4的第一端连接电源线接收电源信号VDD，
所述第五电开关T5的第二端在第三节点M连接所述第二电容C2的第一端、发光二极管的阳极，所述发光二级管的阴极连接第一参考电位线接收第一参考电压Tcom，
所述第二电容C2的第二端连接至公共接地VSS。
在一个实施例中，所述第三扫描信号线为行扫描信号线，第三扫描信号EM为行扫描信号。
在一个实施例中，所述第一至第五电开关T5均为NPN型场效应管。
在一个实施例中，所述第一至第五电开关T5均为NPN型场效应管，所述第一至第五电开关T5的控制端、第一端及第二端分别为栅极、漏极及源极。
在一个实施例中，所述第一至第五电开关T5均为IGZO薄膜晶体管。
在一个实施例中，所述第三扫描信号EM为行扫描信号。
在一个实施例中，所述发光二极管的阴极接地，第一参考电压Tcom为0V。
本领域技术人员可以理解，以上描述并不构成对电子设备的限定，可以包括比更多或更少的部件，或者组合某些部件，或者不同的部件布置。
需要说明的是，在本申请的描述中，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。而且，术语“ 包括”、“ 包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个 ......”限定的要素，并不排除在包括上述要素的过程、方法、物品或者设备中还存在另外的相同要素。本说明书中的各个实施例均采用相关的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。尤其，对于装置和电子设备实施例而言，由于其基本相似于方法实施例，所以描述的比较简单，相关之处参见方法实施例的部分说明即可。以上仅为本发明的实施例而已，并非用于限定本发明的保护范围。凡在本发明的精神和原则之内所作的任何修改、等同替换、改进等，均包含在本发明的保护范围内。 在上面对本发明具体实施例的描述中，针对一种实施方式描述和/或示出的特征可以以相同或类似的方式在一个或更多个其它实施方式中使用，与其它实施方式中的特征相组合，或替代其它实施方式中的特征。
在本申请中，“示例性”一词用来表示“用作例子、例证或说明”。本申请中被描述为“示例性”的任何实施例不一定被解释为比其它实施例更优选或更具优势。为了使本领域任何技术人员能够实现和使用本申请，给出了以下描述。在以下描述中，为了解释的目的而列出了细节。应当明白的是，本领域普通技术人员可以认识到，在不使用这些特定细节的情况下也可以实现本申请。在其它实例中，不会对公知的结构和过程进行详细阐述，以避免不必要的细节使本申请的描述变得晦涩。因此，本申请并非旨在限于所示的实施例，而是与符合本申请所公开的原理和特征的最广范围相一致。
应该强调，术语“包括/包含”在本文使用时指特征、要素、步骤或组件的存在，但并不排除一个或更多个其它特征、要素、步骤或组件的存在或附加。涉及序数的术语或下标“一”“二”“1”“2”“n”“n-”等并不必然表示这些术语所限定的特征、要素、步骤或组件的实施顺序或者重要性程度，而仅仅是为了描述清楚起见而用于在这些特征、要素、步骤或组件之间进行标识。
虽然结合附图描述了本发明的实施例，但是本领域技术人员可以在不脱离本发明的精神和范围的情况下作出各种修改和变型，这样的修改和变型均落入由所附权利要求所限定的范围之内。
 工业实用性
根据本发明的技术方案，由于本发明采用的像素电路，可以不必采用较高的数据电压，可显著降低液晶面板使用的数据电压，由于数据动态功耗与数据电压的平方成正比，降低数据电压可以显著降低面板功耗。同时，本发明提供的电路、方法及装置兼具阈值电压（Vth）补偿效果，有利于提升显示亮度的均匀性。

Claims (20)

  1. 一种蓝相液晶像素电路，包括：
    第一电开关、第二电开关、第三电开关、第四电开关、第五电开关、第一电容、第二电容，
    所述第一电开关的第一端连接至所述第四电开关的第二端，所述第一电开关的第二端在第一节点连接至所述第三电开关的第二端、所述第五电开关的第一端、所述第一电容的第二端，
    所述第二电开关的控制端连接至第一扫描线接收第一扫描信号，所述第二电开关的第一端连接数据线接收数据信号电压，所述第二电开关的第二端在第二节点连接至所述第一电开关的控制端、所述第一电容器的第一端，
    所述第三电开关的控制端连接至第二扫描线接收第二扫描信号，所述第三电开关的第一端连接初始电位线接收预设初始电压，
    所述第四电开关的控制端连接至第三扫描信号线收第三扫描信号，并连接至所述第五电开关的控制端，所述第四电开关的第一端连接电源线接收电源信号，
    所述第五电开关的第二端在第三节点连接所述第二电容电的第一端、发光二极管的阳极，所述发光二级管的阴极连接第一参考电位线接收第一参考电压，
    所述第二电容的第二端连接至公共接地。
  2. 根据权利要求1所述的蓝相液晶像素电路，其特征在于，所述第一至第五电开关均为薄膜晶体管。
  3. 根据权利要求2所述的蓝相液晶像素电路，其特征在于，所述第一至第五电开关均为IGZO薄膜晶体管。
  4. 根据权利要求1所述的蓝相液晶像素电路，其特征在于，所述第一至第五电开关均为NPN型场效应管。
  5. 根据权利要求4所述的蓝相液晶像素电路，其特征在于，所述第一至第五电开关的控制端、第一端及第二端分别为栅极、漏极及源极。
  6. 根据权利要求1所述的蓝相液晶像素电路，其特征在于，所述第三扫描信号为行扫描信号。
  7. 根据权利要求2所述的蓝相液晶像素电路，其特征在于，所述第三扫描信号为行扫描信号。
  8. 根据权利要求5所述的蓝相液晶像素电路，其特征在于，所述第三扫描信号为行扫描信号。
  9. 根据权利要求1所述的蓝相液晶像素电路，其特征在于，所述第一参考电压为0V。
  10. 根据权利要求3所述的蓝相液晶像素电路，其特征在于，所述第一参考电压为0V。
  11. 根据权利要求5所述的蓝相液晶像素电路，其特征在于，所述第一参考电压为0V。
  12. 一种蓝相液晶像素电路的驱动方法，其特征在于，应用于如权利要求1所述的蓝相液晶像素电路，包括以下步骤：
    第一阶段：所述第一扫描信号升为高电位，所述第二扫描信号升为高电位，所述第三扫描信号降为低电位，所述第二电开关的第一端加载预设参考电压，所述第二电开关、所述第三电开关打开，所述第四电开关、所述第五电开关关闭，所述第一节点和所述第二节点分别复位至所述预设初始电压和所述预设参考电压；
    第二阶段：所述第三扫描信号升为高电位，所述第四电开关、所述第五电开关打开，所述第一电开关的第一端维持高电位，所述第二扫描信号降为低电位，所述第三电开关关闭，所述第一节点电压被抬升至所述预设参考电压减所述第一电开关的阈值电压的差值；
     第三阶段：所述第三扫描信号降为低电位，所述第四电开关、所述第五电开关关闭，所述第一扫描信号维持高电位，所述第二电开关的第一端加载数据信号电压，所述第二节点电位写入数据信号电压；
    第四阶段：所述第三扫描信号升为高电位，所述第四电开关、所述第五电开关打开，所述第一节点、所述第三节点电位抬升，所述第二节点抬升至高电位，所述第一电开关维持开启状态，最终所述第一节点、所述第三节点电位被抬升至高电位。
  13. 根据权利要求12所述的像素电路的驱动方法，其特征在于，所述的第一扫描信号和第二扫描信号的时序不同、最大电压值的绝对值相同。
  14. 一种显示装置，其特征在于，包括蓝相液晶像素电路，所述蓝相液晶像素电路包括：
    第一电开关、第二电开关、第三电开关、第四电开关、第五电开关、第一电容、第二电容，
    所述第一电开关的第一端连接至所述第四电开关的第二端，所述第一电开关的第二端在第一节点连接至所述第三电开关的第二端、所述第五电开关的第一端、所述第一电容的第二端，
    所述第二电开关的控制端连接至第一扫描线接收第一扫描信号，所述第二电开关的第一端连接数据线接收数据信号电压，所述第二电开关的第二端在第二节点连接至所述第一电开关的控制端、所述第一电容器的第一端，
    所述第三电开关的控制端连接至第二扫描线接收第二扫描信号，所述第三电开关的第一端连接初始电位线接收预设初始电压，
    所述第四电开关的控制端连接至第三扫描信号线收第三扫描信号，并连接至所述第五电开关的控制端，所述第四电开关的第一端连接电源线接收电源信号，
    所述第五电开关的第二端在第三节点连接所述第二电容电的第一端、发光二极管的阳极，所述发光二级管的阴极连接第一参考电位线接收第一参考电压，
    所述第二电容的第二端连接至公共接地。
  15. 根据权利要求14所述的显示装置，其特征在于，所述第一至第五电开关均为薄膜晶体管。
  16. 根据权利要求15所述的显示装置，其特征在于，所述第一至第五电开关均为IGZO薄膜晶体管。
  17. 根据权利要求14所述的显示装置，其特征在于，所述第一至第五电开关均为NPN型场效应管。
  18. 根据权利要求17所述的显示装置，其特征在于，所述第一至第五电开关的控制端、第一端及第二端分别为栅极、漏极及源极。
  19. 根据权利要求14所述的显示装置，其特征在于，所述第三扫描信号为行扫描信号。
  20. 根据权利要求14所述的显示装置，其特征在于，所述第一参考电压为0V。
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