WO2021163924A1 - 一种用于多结led的隧穿结、多结led及其制备方法 - Google Patents

一种用于多结led的隧穿结、多结led及其制备方法 Download PDF

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WO2021163924A1
WO2021163924A1 PCT/CN2020/075867 CN2020075867W WO2021163924A1 WO 2021163924 A1 WO2021163924 A1 WO 2021163924A1 CN 2020075867 W CN2020075867 W CN 2020075867W WO 2021163924 A1 WO2021163924 A1 WO 2021163924A1
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junction
heavily doped
layer
doped
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French (fr)
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萧至宏
彭钰仁
蔡坤煌
王笃祥
张家宏
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天津三安光电有限公司
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Priority to CN202080002688.0A priority Critical patent/CN112219286B/zh
Priority to PCT/CN2020/075867 priority patent/WO2021163924A1/zh
Priority to JP2021568384A priority patent/JP7309920B2/ja
Publication of WO2021163924A1 publication Critical patent/WO2021163924A1/zh
Priority to US17/655,097 priority patent/US20220209049A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/08—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a plurality of light emitting regions, e.g. laterally discontinuous light emitting layer or photoluminescent region integrated within the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/025—Physical imperfections, e.g. particular concentration or distribution of impurities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of group III and group V of the periodic system
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of group III and group V of the periodic system
    • H01L33/305—Materials of the light emitting region containing only elements of group III and group V of the periodic system characterised by the doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0093—Wafer bonding; Removal of the growth substrate

Definitions

  • the invention relates to a tunnel junction for a multi-junction LED, a multi-junction LED and a preparation method thereof, and belongs to the technical field of semiconductor optoelectronics.
  • Infrared light-emitting diodes are a kind of diodes that emit infrared rays, which are used in security monitoring, wearable devices, infrared communications, infrared remote control devices, light sources for sensors, and night lighting, especially in the field of gas detection.
  • security monitoring and night lighting systems have higher requirements for the brightness of infrared light-emitting diodes.
  • the commonly used solution is multi-junction LED series, that is, the tunneling junction is used to connect each sub-device in series during the epitaxial growth process.
  • the key technology is high peak value.
  • the infrared light-emitting diode is mainly an AlGaAs material system, it will have a light absorption effect and will also produce a larger series resistance, so the selection of the tunnel junction material for the multi-junction LED is very important.
  • the thickness of the p-region and n-region of the tunnel junction should be as thin as possible (less than 15nm).
  • the material band gap of the p-zone and n-zone of the tunnel junction must be greater than the main peak wavelength (Eg>hv) to avoid light absorption.
  • the concentration of the p-zone and n-zone of the tunnel junction must be greater than 1E10 19 cm -3 .
  • the injection current of the device is getting larger and larger, and the peak current density of the tunnel junction is required Also getting higher and higher. Due to the light absorption phenomenon of the low band gap tunnel junction, the light-emitting brightness of the device is seriously affected. Therefore, the method of increasing the peak current density by reducing the band gap of the tunnel junction semiconductor material is not feasible.
  • the present invention aims to provide a tunnel junction for a multi-junction LED, a multi-junction LED, and a method for manufacturing the same.
  • a tunnel junction for a multi-junction LED includes in sequence: heavily doped P-type Al X1 Ga 1-X1 As; Al X2 Ga 1-X2 As graded layer one; heavily doped Hetero N-type Ga Y In 1-Y P; Al X3 Ga 1-X3 As graded layer two.
  • the range of X1 of the heavily doped P-type Al X1 Ga 1-X1 As is 0-0.8.
  • the doping concentration of the heavily doped P-type Al X1 Ga 1-X1 As is 1E19 cm -3 or more.
  • the heavily doped P-type Al X1 Ga 1-X1 As is C-doped P-type Al X1 Ga 1-X1 As, and its doping concentration is 1E19-2E20 cm -3 .
  • the thickness of the heavily doped P-type Al X1 Ga 1-X1 As ranges from 10 to 100 nm.
  • the Y range of the heavily doped N-type Ga Y In 1-Y P is 0.45 to 0.7.
  • the doping concentration of the heavily doped N-type Ga Y In 1-Y P is 1E19 cm ⁇ 3 or more.
  • the heavily doped N-type Ga Y In 1-Y P is a Te-doped N-type Ga Y In 1-Y P with a Te doping concentration of 1E19-2E20 cm -3 .
  • the heavily doped N-type Ga Y In 1-Y P is an N-type Ga Y In 1-Y P doped with Te and Si, and its Te doped
  • the concentration is 1E19-2E20cm -3
  • the Si doping concentration is 5E18-2E19cm -3
  • the doping concentration ratio of Te and Si is 5:3 to 2:1.
  • the thickness of the heavily doped N-type Ga Y In 1-Y P ranges from 10 to 100 nm.
  • the Al X2 Ga 1-X2 As graded layer is between the heavily doped P-type Al X1 Ga 1-X1 As and the heavily doped N-type Ga Y In 1-Y P, and the Al X2 Ga 1
  • the relative content of Al in the first -X2 As graded layer is gradually decreasing in the direction of heavily doped P-type Al X1 Ga 1-X1 As toward heavily doped N-type Ga Y In 1-Y P. More preferably, the relative content of Al in the Al X2 Ga 1-X2 As graded layer 1 decreases linearly from the heavily doped P-type Al X1 Ga 1-X1 As toward the heavily doped N-type Ga Y In 1-Y P .
  • the first Al X2 Ga 1-X2 As graded layer is a C-doped P-type Al X2 Ga 1-X2 As graded layer with a doping concentration of 1E19 to 5E19 cm -3 .
  • the thickness of the first Al X2 Ga 1-X2 As graded layer is in the range of 10-50 nm.
  • the second Al X3 Ga 1-X3 As graded layer is located on the heavily doped N-type Ga Y In 1-Y P, and the relative content of Al in the Al X3 Ga 1-X3 As graded layer two is far from heavy.
  • the direction of doped N-type Ga Y In 1-Y P is gradually increasing. More preferably, the relative content of Al in the Al X3 Ga 1-X3 As graded layer two increases linearly from the direction away from the heavily doped N-type Ga Y In 1-Y P.
  • the second Al X3 Ga 1-X3 As graded layer is a Te-doped N-type Al X3 Ga 1-X3 As graded layer with a doping concentration of 1E19 to 5E19 cm -3 .
  • the thickness of the Al X3 Ga 1-X3 As graded layer two ranges from 10 to 50 nm.
  • a multi-junction LED structure includes at least a first LEDI epitaxial structure and a second LEDII epitaxial structure, characterized in that: between the first LEDI epitaxial structure and the second LEDII epitaxial structure It has a tunneling junction that satisfies the preceding claims.
  • the first LEDI epitaxial structure and the second LEDII epitaxial structure radiate infrared light with a wavelength of 760 nm to 1100 nm.
  • the present invention also provides a method for preparing a multi-junction LED structure, which includes the steps of: forming a first LEDI epitaxial structure; forming a tunnel junction above the first LEDI epitaxial structure, which includes heavily doped P-type Al X1 Ga 1-X1 As; Al X2 Ga 1-X2 As graded layer one; heavily doped N-type Ga Y In 1-Y P; Al X3 Ga 1-X3 As graded layer two; formed above the tunnel junction structure The second LEDII epitaxial structure. So far, the double-junction LED structure is formed, and the multi-junction LED device structure can be epitaxially grown according to this method.
  • Each LED epitaxial substructure generally includes an n-type semiconductor layer, an active layer, and a P-type semiconductor layer, but it may also include functional layers such as a corrosion stop layer, an ohmic contact layer, and a transparent conductive layer.
  • the tunnel junction and the multi-junction LED designed by the present invention for the multi-junction LED include the following beneficial effects:
  • Ga Y In 1-Y P has a large band gap, it can effectively reduce the invisible light absorption effect, improve the brightness of the device, and effectively reduce the series resistance and reduce Voltage;
  • AlGaAs coating layer is continuously grown on the heavily doped N-type Ga Y In 1-Y P to prevent the formation of convex and water-point (Ga-rich or Al-rich) mismatched epitaxial layers during the synthesis of high Al composition , Al composition and the growth rate and temperature changes should be effectively controlled.
  • the present invention adds Al X3 Ga 1-X3 As graded layer two to make the relative content of Al composition self-heavy doped N-type Ga Y In 1-Y P
  • the direction of the AlGaAs covering layer gradually increases to improve the crystal growth quality of the AlGaAs covering layer, reduce the series resistance, and lower the operating voltage;
  • N-type Ga Y In 1-Y P with high Te and low Si mixed doping can effectively grow highly doped N++GaInP and produce high luminous efficiency invisible red LED light-emitting elements.
  • Fig. 1 is a schematic diagram of the structure of a multi-junction LED implemented according to the present invention.
  • FIG. 2 is an enlarged schematic diagram of the tunnel junction area of the multi-junction LED structure shown in FIG. 1.
  • FIG. 3 is a schematic diagram of forming a first LEDI epitaxial structure on a growth substrate in the first embodiment.
  • FIG. 4 is a schematic diagram of forming a tunnel junction on the first LEDI epitaxial structure in the first embodiment.
  • FIG. 5 is a schematic diagram of forming a second LEDII epitaxial structure on the tunnel junction in the first embodiment.
  • FIG. 6 is a schematic diagram of the structure obtained after the double-junction LED epitaxial structure is transferred to the conductive substrate through the bonding process in the manufacturing method of the first embodiment.
  • FIG. 7 is a structure obtained by removing the substrate of the double-junction LED epitaxial structure in the manufacturing method of the first embodiment, forming the first electrode, and exposing the AlGaAs window layer through an etching process and performing the surface roughening step of the AlGaAs window layer Schematic.
  • FIG. 8 is a schematic diagram of the structure obtained in the step of manufacturing the second electrode on the conductive substrate in the manufacturing method of the first embodiment.
  • 001 Growth substrate; 002: N-type layer of LED I; 003: Active layer of LED I; 004: P-type layer of LED I; 005: Tunnel junction; 006: N-type layer of LEDII; 007: LEDII 008: P-type layer of LEDII; 201: Buffer layer; 202: Corrosion stop layer; 203: N-type ohmic contact layer; 204: N-type AlGaAs window layer; 205, 601: N-type AlGaAs cover layer; 206, 602: undoped AlGaAs lower space isolation layer; 401, 801: undoped AlGaAs upper space isolation layer; 402, 802: P-type AlGaAs cover layer; 803: P-type AlGaAs window layer; 804: P-type GaInP current Barrier layer; 805: P-type GaP ohmic contact layer; 501: heavily doped P-type Al X1 Ga 1-X1 As
  • diagrams provided in this embodiment only illustrate the basic idea of the present invention in a schematic manner, so the diagrams only show the components related to the present invention instead of the number, shape, and shape of the components in actual implementation.
  • the type, quantity, and proportion of each component can be changed at will during actual implementation, and the component layout type may also be more complicated.
  • FIG. 1 is a schematic diagram of a multi-junction LED structure implemented according to the present invention, which includes at least a first LEDI structure and a second LEDII structure, and the first LEDI structure and the second LEDII structure are connected through a tunnel junction 005.
  • Figure 2 shows an enlarged schematic view of the tunnel junction 005, which in turn includes heavily doped P-type Al X1 Ga 1-X1 As 501, Al X2 Ga 1-X2 As graded layer 502; heavily doped N-type Ga Y In 1-Y P 503; Al X3 Ga 1-X3 As graded layer two 504.
  • the multi-junction LED structure in this embodiment will be described below in conjunction with the manufacturing method.
  • the N-type layer 002 may include an N-type GaAs ohmic contact layer, an N-type AlGaAs window layer, an N-type AlGaAs cover layer, and an undoped AlGaAs lower space isolation layer; the active layer 003 provides radiation from 760 nm to 1100 nm, which can be but not It is limited to a multi-quantum well structure without doping.
  • the multi-quantum well is a repeated stacked structure of a well layer and an epitaxial layer.
  • the well layer is made of InGaAs and InGaAsP materials with a thickness of 3-15 nm.
  • the barrier layer is AlGaAs, AlGaAsP, GaAsP, the thickness is 5-50nm, and the number of quantum wells is between 1 to 25 pairs, preferably 3-12 pairs.
  • the element content of the well layer can be adjusted.
  • the radiation band of the source layer; the P-type layer 004 may include a P-type AlGaAs cover layer and an undoped AlGaAs upper space isolation layer.
  • the present invention proposes the use of N-type GaInP high energy band gap and heavy doping The characteristic provides effective bonding of the first LEDI structure and the second LEDII structure and multiple LED epitaxial structures, which can effectively reduce the light absorption effect of the tunnel junction.
  • a tunnel junction 005 may be formed over the P-type layer 004 of the LED 1.
  • a tunnel junction 005 may be formed over the P-type layer 004 of the LED 1.
  • grow Al X1 Ga 1-X1 As: C or In z Al X1 Ga 1-X1 As: C (X1 0 ⁇ 0.8, Z ⁇ 0.05) as an ultra-thin heavily doped P-type layer 501, the thickness of which is 10nm-100nm, and the doping concentration can be between 1E19cm -3 and 2E20cm -3 .
  • the present invention introduces Al X2 Ga 1-X2 As into the heavily doped P-type Al X1 Ga 1-X1 As layer and the heavily doped N-type Ga Y In 1-Y P
  • the graded layer 502 can realize effective switching of As and P, effectively improve the interface quality and crystal growth quality, reduce the series resistance, thereby reduce the operating voltage, and improve the luminous efficiency of the light-emitting diode.
  • the relative content of Al in the Al X2 Ga 1-X2 As graded layer 502 gradually decreases from the heavily doped P-type Al X1 Ga 1-X1 As toward the heavily doped N-type Ga Y In 1-Y P direction. More preferably, the relative content of Al in the Al X2 Ga 1-X2 As graded layer 1 decreases linearly from the heavily doped P-type Al X1 Ga 1-X1 As toward the heavily doped N-type Ga Y In 1-Y P .
  • the first Al X2 Ga 1-X2 As graded layer is a C-doped P-type Al X2 Ga 1-X2 As graded layer with a doping concentration of 1E19-5E19 cm -3 .
  • the thickness of the first Al X2 Ga 1-X2 As graded layer is 10-50 nm.
  • a heavily doped N-type Ga Y In 1-Y P 503 is grown on the Al X2 Ga 1-X2 As graded layer 502, and the Y range of the heavily doped N-type Ga Y In 1-Y P is 0.45 ⁇ 0.7, the thickness is 10nm ⁇ 100nm; the heavily doped N-type Ga Y In 1-YP 503 can be Te-doped N-type Ga Y In 1-Y P, and its Te doping concentration is 1E19 ⁇ 2E20cm -3 .
  • AlGaAs coating layer needs to be grown on the heavily doped N-type Ga Y In 1-Y P.
  • Al The composition, growth rate, and temperature change should be effectively controlled.
  • the present invention grows Al X3 Ga 1-X3 As graded layer two 504 on the heavily doped N-type Ga Y In 1-Y P 503 to make the Al composition relative
  • the content of self-heavy doped N-type Ga Y In 1-Y P gradually increases toward the AlGaAs covering layer, which can effectively improve the relative aluminum content of the interface between the heavily doped N-type Ga Y In 1-Y P and the AlGaAs covering layer.
  • the problem of defects caused by lattice mismatch improves the crystal growth quality of the AlGaAs covering layer, reduces the series resistance, and reduces the operating voltage. More preferably, the relative content of Al in the Al X3 Ga 1-X3 As graded layer two increases linearly from the direction away from the heavily doped N-type Ga Y In 1-Y P.
  • the thickness of the second Al X3 Ga 1-X3 As graded layer 504 is 10-50 nm, and the doping concentration may be 11E19-5E19 cm -3 .
  • the N-type layer 006 may include an N-type AlGaAs cover layer and an undoped AlGaAs lower space isolation layer;
  • the active layer 007 may use InGaAs/AlGaAs as a multiple quantum well structure composed of quantum wells and barriers, respectively, by adjusting the MQW well
  • the composition of the barrier layer can emit infrared light with a peak wavelength of 760nm ⁇ 1100nm, the period of the well barrier layer of the active layer is 1 ⁇ 25, and the total thickness of the active layer is between 20 ⁇ 500nm;
  • P-type layer 008 may include a P-type GaP ohmic contact layer, a P-type GaInP current blocking layer, a P-type AlGaAs window layer, a P-type AlG
  • a first LED I epitaxial structure is grown on the bottom.
  • the first LED I epitaxial structure includes the following epitaxial layers stacked in sequence: a buffer layer 201 composed of Si-doped GaAs, and a corrosion preventing layer composed of GaInP 202.
  • N-type ohmic contact layer 203 composed of Si-doped GaAs, N-type AlGaAs window layer 204, N-type AlGaAs cover layer 205, undoped AlGaAs lower space isolation layer 206, composed of In 0.2 Ga 0.8 As well layer
  • An active layer 003 composed of a pair of /Al 0.2 Ga 0.8 As barrier layers, an undoped AlGaAs upper space isolation layer 401, and a P-type cladding layer 402 composed of C-doped AlGaAs.
  • an organic metal chemical vapor deposition device (MOCVD device) is used to epitaxially grow the first LED I epitaxial structure on a GaAs growth substrate with a diameter of 100 mm and a thickness of 350 microns.
  • MOCVD device organic metal chemical vapor deposition device
  • the epitaxial layer as the raw material of the group III constituent elements, trimethyl aluminum ((CH 3 ) 3 Al), trimethyl gallium ((CH 3 ) 3Ga), and trimethyl indium ((CH 3 ) 3 In).
  • the doping uses Carbon tetrabromide (Carbon tetrabromide) CBr4, Diethyl tellurium (Diethvl tellurium) Te (C 2 H 5 ) 2 , Disilane (Si 2 H 6 ), Diethylzinc (Diethylzinc) Zn (C 2 H 5 ) 2 is used as a raw material for doping.
  • Diethylzinc Diethylzinc Zn (C 2 H 5 ) 2 is used as raw material for doping.
  • phosphane (PH 3 ) and arsine (AsH 3 ) are used as raw materials of the group V constituent elements.
  • the buffer layer 201 made of GaAs can improve the problem of poor growth quality caused by the crystal lattice difference between the material of the substrate and the semiconductor epitaxial stack layer, and its thickness is about 0.3um.
  • the corrosion stop layer 202 made of GaInP has a thickness of about 100 nm and can provide an etching stop interface. For example, when transferring a semiconductor epitaxial stack layer to another substrate, the gallium arsenide substrate needs to be removed.
  • the etching stop layer can prevent etching The solution used in the process etches and destroys the ohmic contact layer.
  • the ohmic contact layer 203 made of Si-doped GaAs has a relatively high N-type doping concentration, for example, higher than 1E18 cm -3 , preferably higher than 2E18 cm -3 .
  • the thickness of the ohmic contact layer 203 is less than 200 nm, and the preferred thickness is 30-100 nm.
  • the N-type AlGaAs window layer 204 is a current spreading layer, with a doping concentration of 1E18 cm -3 and a layer thickness of about 4um-7um.
  • the N-type AlGaAs covering layer 205 has an N-type doping concentration of 5E17-2E18 cm -3 and a layer thickness of about 0.5 um.
  • the undoped AlGaAs lower space isolation layer 206 has a thickness of about 300 nm to 1 um.
  • the well layer is undoped In 0.2 Ga 0.8 As with a thickness of about 5.5 nm, and the barrier layer is undoped Al 0.2 Ga 0.8 As with a thickness of about 15 nm.
  • the number of pairs of well barriers of MQW is preferably 10 pairs.
  • the upper space isolation layer of the undoped AlGaAs 401 has a thickness of 300 nm to 1 um.
  • the P-type cladding layer 402 composed of C-doped AlGaAs has a carrier concentration of 1E18 cm -3 and a layer thickness of about 0.3um to 0.8um.
  • the tunnel junction includes the following sequentially stacked structures: heavily doped P-type Al 0.3 Ga 0.7 As 501, Al X2 Ga 1-X2 As graded layer one 502, heavily doped N-type Ga 0.6 In 0.4 P 503 and Al X3 Ga 1-X3 As graded layer two 504.
  • the epitaxial structure is grown on the first LEDI Al 0.3 Ga 0.7 As: C as a thin heavily doped P-type layer 501, a thickness of 50 nm, the doping concentration may be 8E19cm -3 cm -3.
  • an Al X2 Ga 1-X2 As graded layer 502 is grown on the heavily doped P-type Al 0.3 Ga 0.7 As layer.
  • the thickness of the Al X2 Ga 1-X2 As graded layer is 30 nm, and the Al X2 Ga 1
  • the relative content of Al in the first X2 As graded layer decreases linearly from the heavily doped P-type Al 0.3 Ga 0.7 As layer toward the heavily doped N-type Ga Y In 1-Y P direction.
  • the Al X2 Ga 1-X2 As graded layer 501 is a C-doped P-type Al X2 Ga 1-X2 As graded layer with a doping concentration of 3E19 cm ⁇ 3 .
  • a heavily doped N-type Ga 0.6 In 0.4 P503 is grown on the Al X2 Ga 1-X2 As graded layer one, the heavily doped N-type Ga 0.6 In 0.4 P 503 has a thickness of 50 nm; the heavily doped N-type Ga Y In 1-Y P can be Te-doped N-type Ga Y In 1-Y P, and its Te doping concentration is 8E19cm -3 .
  • an Al X3 Ga 1-X3 As graded layer 504 is grown on the heavily doped N-type Ga 0.6 In 0.4 P.
  • the Al relative content of the Al X3 Ga 1-X3 As graded layer two 504 increases linearly from the direction away from the heavily doped N-type Ga Y In 1-Y P.
  • the thickness of the second Al X3 Ga 1-X3 As graded layer 504 is 30 nm, and the doping concentration may be 3E19 cm ⁇ 3 .
  • the second LEDII epitaxial structure includes the following epitaxial growth layers stacked in sequence: N-type capping layer 601, undoped AlGaAs lower space isolation layer 602, composed of In 0.2 Ga 0.8 As well layer/Al 0.2 Ga 0.8 As An active layer 007 composed of a pair of barrier layers, an undoped AlGaAs upper space isolation layer 801, a P-type cladding layer 802 composed of C-doped AlGaAs, a P-type AlGaAs window layer 803, a P-type GaInP current blocking layer 804 and P-type GaP ohmic contact layer 805.
  • the N-type AlGaAs covering layer 601 has an N-type doping concentration of 5E17-2E18 cm -3 , preferably a doping concentration of 1E18 cm -3 , and a layer thickness of about 0.5 um.
  • the undoped AlGaAs is used as the space isolation layer 602, and its layer thickness is about 80 nm.
  • the well layer is undoped In 0.2 Ga 0.8 As with a thickness of about 5.5 nm
  • the barrier layer is undoped Al 0.2 Ga 0.8 As with a thickness of about 15 nm.
  • the number of pairs of well barriers of MQW is preferably 10 pairs.
  • the undoped AlGaAs is used as the space isolation layer 801, and the layer thickness is 0.2um.
  • the P-type cladding layer 802 composed of C-doped AlGaAs has a carrier concentration of 1.5E18cm -3 and a layer thickness of about 0.4um.
  • the thickness of the P-type AlGaAs window layer 803 is 1um, and the doping concentration is 5E17 ⁇ 1E18cm -3 ;
  • the thickness of the P-type GaInP current blocking layer 804 is about 10nm ⁇ 30nm, and the carrier concentration is 1E18 ⁇ 3E18cm -3 .
  • the thickness of the ohmic contact layer 805 is about 30-60 nm, and its carrier concentration is 6E19 cm -3 .
  • a reflective layer 009 is fabricated on the side of the P-type GaP ohmic contact layer 805; The process bonds the double-junction LED epitaxial structure to a conductive substrate 010; then, as shown in FIG.
  • the growth substrate 001 is removed by an etching process until the N-type ohmic contact layer 203 is exposed; on the N-type ohmic contact layer A first electrode 011 is formed, and the first electrode 011 forms a good ohmic contact with the N-type ohmic contact layer 203; then, a mask is formed to cover the first electrode 011; the ohmic contact layer 203 around the first electrode is etched away to expose AlG aAS window layer 204, then the AlGaAS window layer 204 is etched to form a patterned or roughened surface to increase the light extraction efficiency; finally, as shown in FIG. 8, a second electrode 012 is formed on the back side of the conductive substrate 010, Thereby, current can be conducted between the first electrode 011 and the second electrode 012 and the semiconductor epitaxial stack layer.
  • a unitized double-junction LED light-emitting element is obtained through processes such as etching and splitting.
  • Example 1 in this embodiment of the heavily doped N-type Ga Y In 1-Y P mix is Te and Si doped N-type Ga Y In 1-Y P, which doping concentration of 1E19 ⁇ Te 2E20cm -3 , and the Si doping concentration is 5E18 ⁇ 2E19cm -3 . More preferably, the doping concentration ratio of the Te and Si is 5:3-2:1. Otherwise, the tunneling combined multi-junction LED was fabricated under the same conditions as in Example 1.
  • the heavy doping of N-type Ga Y In 1-Y P is achieved by high Te and low Si mixed doping.
  • the tunnel junction uses heavily doped N-type Ga Y In 1-Y P, compared to the tunnel junction using heavily doped N-type AlGaAs, tested at 350mA Under current, the Vf value can be reduced by 0.43V and the brightness can be increased by 7.5%.
  • the use of heavily doped N-type Ga Y In 1-Y P can effectively reduce the light absorption effect of invisible light, improve the brightness of the device, and effectively reduce the series resistance and reduce the voltage; at the same time, the Al X2 Ga 1-X2 As graded layer is added One and Al X3 Ga 1-X3 As graded layer two, can effectively improve the quality of the interface and the quality of crystal growth, and can realize the effective switching of As and P, reduce the series resistance, reduce the working voltage, and thus improve the photoelectric conversion efficiency.

Abstract

本发明公开一种用于多结LED的隧穿结、多结LED及其制备方法，所述隧穿结包括：重掺杂P型AlX1Ga1-X1As； AlX2Ga1-X2As渐变层一；重掺杂N型GaYIn1-YP；AlX3Ga 1-X3As渐变层二。使用重掺杂N型GaYIn1-YP，能够有效减少长波长红外光的吸光效应，提升器件亮度，并且有效降低串联电阻降低电压；同时加入AlX2Ga1-X2As渐变层一和AlX3Ga1-X3As渐变层二，可以有效改善界面质量和晶体生长质量，并且可以实现As、P有效切换，减小串联电阻，降低工作电压，从而提升光电转换效率。

Description

一种用于多结LED的隧穿结、多结LED及其制备方法 技术领域
本发明涉及一种用于多结LED的隧穿结、多结LED及其制备方法，属于半导体光电技术领域。
背景技术
红外发光二极管是一种能发出红外线的二极管，应用于安全监控、穿戴式装置、红外线通信、红外线遥控装置、传感器用光源及夜间照明等领域，特别是气体检测领域。其中安全监控、夜间照明系统对于红外发光二极管的亮度要求较高，常用的解决方案是多结LED串联，即在外延生长过程中利用隧穿结将各个子器件串联起来，其关键技术是高峰值电流密度的隧穿结外延生长。为获得尽可能高的隧穿峰值电流，隧穿结材料的选择、掺杂源的选择、掺杂浓度及材料生长工艺等都是必须考虑的。
由于红外发光二极管主要为AlGaAs材料体系，自身会有吸光效应，同时还会产生较大的串联电阻，故多结LED隧穿结材料的选择相当重要。要完成高效率、低吸光、低电压隧穿结结构必须满足：1、隧穿结p区和n区的厚度应尽可能的薄(小于15nm)。2.隧穿结p区和n区的材料带隙必须大于主峰波长(Eg＞hv)，避免吸光。3.隧穿结p区和n区浓度必须要大于1E10 19cm -3。
在多结LED实际应用中，随着大尺寸高亮度产品的需求(例如车灯、舞台灯、虹膜识别等产品)，器件的注入电流越来越大，对隧穿结的峰值电流密度的要求也越来越高。由于低带隙隧穿结存在吸光现象，严重影响器件的发光亮度。因此通过降低隧穿结半导体材料的带隙来提高峰值电流密度的方法行不通。
发明概述
技术问题
问题的解决方案
技术解决方案
根据现有技术中存在的上述问题，本发明旨在提供一种用于多结LED的隧穿结 、多结LED及其制备方法。
根据本发明的第一个方面，一种用于多结LED的隧穿结，依次包括：重掺杂P型Al X1Ga 1-X1As；Al X2Ga 1-X2As渐变层一；重掺杂N型Ga YIn 1-YP；Al X3Ga 1-X3As渐变层二。
优选地，所述重掺杂P型Al X1Ga 1-X1As的X1的范围为0～0.8。
优选地，所述重掺杂P型Al X1Ga 1-X1As的掺杂浓度为1E19cm -3以上。
更优选地，所述重掺杂P型Al X1Ga 1-X1As为C掺杂的P型Al X1Ga 1-X1As，其掺杂浓度为1E19～2E20cm -3。
优选地，所述重掺杂P型Al X1Ga 1-X1As的厚度范围为10～100nm。
优选地，所述重掺杂N型Ga YIn 1-YP的Y的范围为0.45～0.7。
优选地，所述重掺杂N型Ga YIn 1-YP的掺杂浓度为1E19cm -3以上。
更优选地，所述重掺杂N型Ga YIn 1-YP为Te掺杂的N型Ga YIn 1-YP，其Te掺杂浓度为1E19～2E20cm -3。
作为本发明的另一种实施方式，更优选地，所述重掺杂N型Ga YIn 1-YP为Te和Si混掺杂的N型Ga YIn 1-YP，其Te掺杂浓度为1E19～2E20cm -3，Si掺杂浓度为5E18～2E19cm -3。更优选地，所述Te、Si的掺杂浓度比例为5∶3～2∶1。
优选地，所述重掺杂N型Ga YIn 1-YP的厚度范围为10～100nm。
优选地，所述Al X2Ga 1-X2As渐变层一介于重掺杂P型Al X1Ga 1-X1As与重掺杂N型Ga YIn 1-YP之间，所述Al X2Ga 1-X2As渐变层一的Al相对含量自重掺杂P型Al X1Ga 1-X1As往重掺杂N型Ga YIn 1-YP方向是逐渐递减的。更优选的，所述Al X2Ga 1-X2As渐变层一的Al相对含量自重掺杂P型Al X1Ga 1-X1As往重掺杂N型Ga YIn 1-YP方向是线性递减的。
优选地，所述Al X2Ga 1-X2As渐变层一为C掺杂的P型Al X2Ga 1-X2As渐变层，其掺杂浓度为1E19～5E19cm -3。
优选地，所述Al X2Ga 1-X2As渐变层一的厚度范围为10～50nm。
优选地，所述Al X3Ga 1-X3As渐变层二位于重掺杂N型Ga YIn 1-YP之上，所述Al X3Ga 1-X3As渐变层二的Al相对含量自远离重掺杂N型Ga YIn 1-YP方向是逐渐递增的。更优选的，所述Al X3Ga 1-X3As渐变层二的Al相对含量自远离重掺杂N型Ga YIn 1-YP 方向是线性递增的。
优选地，所述Al X3Ga 1-X3As渐变层二为Te掺杂的N型Al X3Ga 1-X3As渐变层，其掺杂浓度为1E19～5E19cm -3。
优选地，所述Al X3Ga 1-X3As渐变层二的厚度范围为10～50nm。
根据本发明的第二个方面，一种多结LED结构，至少包括第一LEDI外延结构和第二LEDII外延结构，其特征在于：在所述第一LEDI外延结构和第二LEDII外延结构之间具有满足前述权利要求的隧穿结。
优选地，所述第一LEDI外延结构和第二LEDII外延结构辐射波长为760nm～1100nm的红外光。
本发明同时还提供了一种多结LED结构的制备方法，包括步骤：形成第一LEDI外延结构；在所述第一LEDI外延结构的上方形成隧穿结，其包含重掺杂P型Al X1Ga 1-X1As；Al X2Ga 1-X2As渐变层一；重掺杂N型Ga YIn 1-YP；Al X3Ga 1-X3As渐变层二；在所述隧穿结结构上方形成第二LEDII外延结构。至此就形成了双结LED结构，可以依据此方法继续外延生长多结LED器件结构。各LED外延子结构一般包括n型半导体层、有源层和P型半导体层，但也可以包含腐蚀截止层、欧姆接触层、透明导电层等功能层。
发明的有益效果
有益效果
如上所述，本发明设计的用于多结LED的隧穿结及多结LED，包括以下有益效果：
(1)使用重掺杂N型Ga YIn 1-YP，因Ga YIn 1-YP带隙较大，可以有效减小不可见光吸光效应，提升器件亮度，并且有效降低串联电阻，降低电压；
(2)在重掺杂P型Al X1Ga 1-X1As和重掺杂N型Ga YIn 1-YP之间增加Al X2Ga 1-X2As渐变层一，可有效改善重掺杂P型Al X1Ga 1-X1As和重掺杂N型Ga YIn 1-YP之间界面的铝相对含量差异较大引起的晶格失配产生缺陷的问题，可有效改善界面质量和晶体生长质量，并且可以实现As、P有效切换，减小串联电阻，降低工作电压，从而提升光电转换效率；
(3)在重掺杂N型Ga YIn 1-YP上接续成长AlGaAs覆盖层，为了防止高Al组分合 成时产生凸状及水点(Ga-rich or Al-rich)失配外延层，Al组份及成长速率和温度的变化应有效控制，本发明通过加入Al X3Ga 1-X3As渐变层二，使Al组分的相对含量自重掺杂N型Ga YIn 1-YP往AlGaAs覆盖层方向逐渐递增，改善AlGaAs覆盖层晶体生长质量，减小串联电阻，降低工作电压；
(4)N型Ga YIn 1-YP搭配高Te，低Si混合掺杂，有效成长出高掺杂N++GaInP，制作出高发光效率不可见红光LED发光元件。
本发明的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本发明而了解。本发明的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
对附图的简要说明
附图说明
附图用来提供对本发明的进一步理解，并且构成说明书的一部分，与本发明的实施例一起用于解释本发明，并不构成对本发明的限制。此外，附图数据是描述概要，不是按比例绘制。
图1为根据本发明实施的一种多结LED的结构示意图。
图2为图1所示多结LED结构之隧穿结的区域放大示意图。
图3为实施例一中在生长衬底上形成第一LEDI外延结构的示意图。
图4为实施例一中在第一LEDI外延结构上形成隧穿结的示意图。
图5为实施例一中在隧穿结上成第二LEDII外延结构的示意图。
图6为在实施例一的制作方法中，双结LED外延结构经过键合工艺转移至导电基板后获得的结构示意图。
图7为在实施例一的制作方法中，双结LED外延结构经移除衬底，制作第一电极，并通过蚀刻工艺露出AlGaAs窗口层并进行AlGaAs窗口层的表面粗化步骤获得的结构的示意图。
图8为实施例一的制作方法中，在导电基板上制作第二电极的步骤获得的结构示意图。
图中元件标号说明：
001：生长衬底；002：LED I的N型层；003：LED I的有源层；004：LED I的P 型层；005：隧穿结；006：LEDII的N型层；007：LEDII的有源层；008：LEDII的P型层；201：缓冲层；202：腐蚀阻止层；203：N型欧姆接触层；204：N型AlGaAs窗口层；205、601：N型AlGaAs覆盖层；206、602：不掺杂AlGaAs下部空间隔离层；401、801：不掺杂AlGaAs上部空间隔离层；402、802：P型AlGaAs覆盖层；803：P型AlGaAs窗口层；804：P型GaInP电流阻挡层；805：P型GaP欧姆接触层；501：重掺杂P型Al X1Ga 1-X1As；502：Al X2Ga 1-X2As渐变层一；503：重掺杂N型Ga YIn 1-YP；504：Al X3Ga 1-X3As渐变层二；009：反射层；010：导电基板；011：第一电极；012：第二电极。
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施例加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。
需要说明的是，本实施例中所提供的图示仅以示意方式说明本发明的基本构想，遂图示中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。
发明实施例
本发明的实施方式
实施例一
图1为根据本发明实施的一种多结LED结构的示意图，其至少包括第一LEDI结构和第二LEDII结构，通过隧穿结005连接第一LEDI结构和第二LEDII结构。图2显示了隧穿结005的区域放大示意图，其依次包括重掺杂P型Al X1Ga 1-X1As 501，Al X2Ga 1-X2As渐变层一502；重掺杂N型Ga YIn 1-YP 503；Al X3Ga 1-X3As渐变层二504。
下面结合制作方法对本实施例中的多结LED结构进行说明。
首先，在MOCVD系统中，选用n型掺杂的向(100)晶面偏角为2 0GaAs作为生长衬底001，厚度在350微米左右，掺杂浓度在1 E18cm -3～3E18cm -3之间，在此衬底上生长第一LED I的N型层002、有源层003、P型层004，构成第一LED I外延 结构。其中N型层002可以包含N型GaAs欧姆接触层、N型AlGaAs窗口层、N型AlGaAs覆盖层、不掺杂AlGaAs下部空间隔离层；有源层003提供760nm～1100nm的辐射，可以是但不限于是不具有掺杂的多量子阱结构，作为一个实施例，多量子阱为阱层和磊层的重复堆叠结构，具体的，其中阱层为InGaAs，InGaAsP材料，其厚度为3～15nm，势垒层为AlGaAs、AlGaAsP，GaAsP，其厚度为5～50nm，量子阱对数介于1对到25对之间，优选对数为3～12对，通过调整阱层的元素含量可以调整有源层的辐射波段；P型层004可包括P型AlGaAs覆盖层、不掺杂AlGaAs上部空间隔离层。
目前传统隧穿结皆利用GaAs，AlGaAs材料做成，由于GaAs，AlGaAs材料自身具有吸光效应，故在不可见光无法达成双结LED特性，故本发明提出利用N型GaInP高能带隙及重掺杂特性，提供第一LEDI结构和第二LEDII结构及多个LED外延结构有效接合，可有效降低隧穿结的吸光作用。
接着，在LED I的P型层004上方可形成隧穿结005。如图2所示，首先，生长Al X1Ga 1-X1As：C或In zAl X1Ga 1-X1As：C(X1＝0～0.8，Z＜0.05)作为超薄重掺杂P型层501，其厚度为10nm～100nm，掺杂浓度可为1E19cm -3～2E20cm -3之间。
由于在重掺杂P型Al X1Ga 1-X1As层直接生长重掺杂N型Ga YIn 1-YP，As和P直接切换容易在界面处产生缺陷，影响界面质量和后续外延生长的晶体质量，从而影响发光二极管的工作电压，故本发明在重掺杂P型Al X1Ga 1-X1As层和重掺杂N型Ga YIn 1-YP中引入Al X2Ga 1-X2As渐变层一502，可实现As和P有效切换，有效改善界面质量和晶体生长质量，降低串联电阻，从而降低工作电压，提升发光二极管的发光效率。所述Al X2Ga 1-X2As渐变层一502的Al的相对含量自重掺杂P型Al X1Ga 1-X1As往重掺杂N型Ga YIn 1-YP方向是逐渐递减的。更优选的，所述Al X2Ga 1-X2As渐变层一的Al相对含量自重掺杂P型Al X1Ga 1-X1As往重掺杂N型Ga YIn 1-YP方向是线性递减的。所述Al X2Ga 1-X2As渐变层一为C掺杂的P型Al X2Ga 1-X2As渐变层，其掺杂浓度为1E19～5E19cm -3。所述Al X2Ga 1-X2As渐变层一的厚度为10～50nm。
接着，在Al X2Ga 1-X2As渐变层一502上生长重掺杂N型Ga YIn 1-YP 503，所述重掺杂N型Ga YIn 1-YP的Y的范围为0.45～0.7，厚度为10nm～100nm；所述重掺杂N 型Ga YIn 1-YP 503可为Te掺杂的N型Ga YIn 1-YP，其Te掺杂浓度为1E19～2E20cm -3。
在重掺杂N型Ga YIn 1-YP上需接续成长AlGaAs覆盖层，为了防止高Al组分合成时产生凸状及水点(Ga-rich or Al-rich)失配外延层，Al组份及成长速率和温度的变化应有效控制，本发明通过在重掺杂N型Ga YIn 1-YP 503上生长Al X3Ga 1-X3As渐变层二504，使Al组分的相对含量自重掺杂N型Ga YIn 1-YP往AlGaAs覆盖层方向逐渐递增，可有效改善重掺杂N型Ga YIn 1-YP和AlGaAs覆盖层之间界面的铝相对含量差异较大引起的晶格失配产生缺陷的问题，改善AlGaAs覆盖层的晶体生长质量，减小串联电阻，降低工作电压。更优选的，所述Al X3Ga 1-X3As渐变层二的Al相对含量自远离重掺杂N型Ga YIn 1-YP方向是线性递增的。所述Al X3Ga 1-X3As渐变层二504的厚度为10～50nm，掺杂浓度可为1 1E19～5E19cm -3。
然后，在隧穿结005的上方对称生长LED II的N型层006、有源层007和P型层008，构成第二LEDII外延结构。其中，N型层006可以包含N型AlGaAs覆盖层、不掺杂AlGaAs下部空间隔离层；有源层007可以采用InGaAs/AlGaAs分别作为量子阱和势垒构成的多量子阱结构，通过调整MQW阱垒层的组分，可发射峰值波长为760nm～1100nm的红外光，有源层的阱垒层的周期数为1～25个，有源层的总厚度为20～500nm之间；P型层008可包括P型GaP欧姆接触层、P型GaInP电流阻挡层、P型AlGaAs窗口层、P型AlGaAs覆盖层、不掺杂AlGaAs上部空间隔离层。
下面以850nm双结LED为例，结合工艺方法对双结LED结构进行具体的详细说明。
首先，选用n型掺杂的向(100)晶面偏角为2 0GaAs作为生长衬底001，厚度在350微米左右，掺杂浓度在1 E18cm -3～3E18cm -3之间，在此衬底上生长第一LED I外延结构，如图3所示，该第一LED I外延结构包含以下依次层叠的外延层：由掺杂Si的GaAs构成的缓冲层201、由GaInP构成的腐蚀阻止层202、由掺杂Si的GaAs构成的N型的欧姆接触层203、N型AlGaAs窗口层204、N型AlGaAs覆盖层205、不掺杂AlGaAs下部空间隔离层206，由In 0.2Ga 0.8As阱层/Al 0.2Ga 0.8As垒层的对构成的有源层003，不掺杂AlGaAs上部空间隔离层401，由掺杂C的AlGaAs构成的P 型覆盖层402。
在本实施例中，采用有机金属化学气相沉积装置(MOCVD装置)，在直径为100mm、厚度为350微米的GaAs生长衬底上外延生长第一LED I外延结构。在生长外延层时，作为III族构成元素的原料，使用三甲基铝((CH 3) 3Al)、三甲基镓((CH 3)3Ga)和三甲基铟((CH 3) 3In)。掺杂分别使用四溴化碳(Carbon tetrabromide)CBr4、二乙基碲(Diethvl tellurium)Te(C 2H 5) 2、乙硅烷(Si 2H 6)，二乙基锌(Diethylzinc)Zn(C 2H 5) 2作为掺杂的原料。另外，作为V族构成元素的原料，使用磷烷(PH 3)和砷烷(AsH 3)。
由GaAs构成的缓冲层201，可改善衬底与半导体外延堆叠层的材料之间的晶格差异导致的生长质量差的问题，其厚度约为0.3um。由GaInP构成的腐蚀阻止层202，其厚度约为100nm，可提供蚀刻截止界面，例如将半导体外延堆叠层转移至另一基板上时，需要去除砷化镓衬底，该蚀刻截止层能够防止蚀刻工艺用的溶液对欧姆接触层进行蚀刻破坏。
由掺杂Si的GaAs构成的欧姆接触层203具有比较高的N型掺杂浓度，例如高于1E18cm -3，较佳的高于2E18cm -3。欧姆接触层203的厚度低于200nm，较佳的厚度为30～100nm。N型AlGaAs窗口层204为电流扩展层，其掺杂浓度为1E18cm -3、层厚设为约4um～7um。N型AlGaAs覆盖层205，N型掺杂浓度为5E17～2E18cm -3，层厚约为0.5um。不掺杂AlGaAs下部空间隔离层206，其层厚约为300nm～1um。阱层是未掺杂且层厚约为5.5nm的In 0.2Ga 0.8As，垒层为未掺杂的且层厚约为15nm的Al 0.2Ga 0.8As。MQW的阱垒的对数优选为10对。不掺杂AlGaAs 401上部空间隔离层，层厚为300nm～1um。由掺杂C的AlGaAs构成的P型覆盖层402，其载流子浓度为1E18cm -3、层厚约为0.3um～0.8um。
接着，在第一LEDI外延结构上生长隧穿结005，如图4所示，该隧穿结包括以下依次层叠的结构：重掺杂P型Al 0.3Ga 0.7As 501，Al X2Ga 1-X2As渐变层一502，重掺杂N型Ga 0.6In 0.4P 503和Al X3Ga 1-X3As渐变层二504。首先，在第一LEDI外延结构上生长Al 0.3Ga 0.7As：C作为超薄重掺杂P型层501，其厚度为50nm，掺杂浓度可为8E19cm -3cm -3。接着，在重掺杂P型Al 0.3Ga 0.7As层上生长Al X2Ga 1-X2As渐变层一502，该Al X2Ga 1-X2As渐变层一的厚度为30nm，所述Al X2Ga 1-X2As渐变层一 的Al相对含量自重掺杂P型Al 0.3Ga 0.7As层往重掺杂N型Ga YIn 1-YP方向是线性递减的。所述Al X2Ga 1-X2As渐变层一501为C掺杂的P型Al X2Ga 1-X2As渐变层，其掺杂浓度为3E19cm -3。然后，在Al X2Ga 1-X2As渐变层一上生长重掺杂N型Ga 0.6In 0.4 P503，所述重掺杂N型Ga 0.6In 0.4P 503厚度为50nm；所述重掺杂N型Ga YIn 1-YP可为Te掺杂的N型Ga YIn 1-YP，其Te掺杂浓度为8E19cm -3。最后，在重掺杂N型Ga 0.6In 0.4P生长Al X3Ga 1-X3As渐变层二504。所述Al X3Ga 1-X3As渐变层二504的Al相对含量自远离重掺杂N型Ga YIn 1-YP方向是线性递增的。所述Al X3Ga 1-X3As渐变层二504的厚度为30nm，掺杂浓度可为3E19cm -3。
然后，在隧穿结005的上方对称生长第二LEDII外延结构。如图5所示，第二LEDII外延结构包括以下依次堆叠的外延生长层：N型覆盖层601，不掺杂AlGaAs下部空间隔离层602，由In 0.2Ga 0.8As阱层/Al 0.2Ga 0.8As垒层的对构成的有源层007，不掺杂AlGaAs上部空间隔离层801，由掺杂C的AlGaAs构成的P型覆盖层802，P型AlGaAs窗口层803、P型GaInP电流阻挡层804和P型GaP欧姆接触层805。
N型AlGaAs覆盖层601，N型掺杂浓度为5E17～2E18cm -3，优选掺杂浓度为1E18cm -3，层厚约为0.5um。不掺杂AlGaAs作为空间隔离层602，其层厚约为80nm。阱层是未掺杂且层厚约为5.5nm的In 0.2Ga 0.8As，垒层为未掺杂的且层厚约为15nm的Al 0.2Ga 0.8As。MQW的阱垒的对数优选为10对。不掺杂AlGaAs作为空间隔离层801，层厚为0.2um。由掺杂C的AlGaAs构成的P型覆盖层802，其载流子浓度为1.5E18cm -3、层厚约为0.4um。P型AlGaAs窗口层803厚度为1um，掺杂浓度为5E17～1E18cm -3；P型GaInP电流阻档层804厚约为10nm～30nm，其载流子浓度为1E18～3E18cm -3，P型GaP欧姆接触层805的厚度约30～60nm，其载流子浓度为6E19cm -3。
接着进行芯片工艺的制程，首先，如图6所示，在P型GaP欧姆接触层805一侧制作反射层009；反射层一侧设置键合层(示意图中未标出)，并通过键合工艺将双结LED外延结构键合至一导电性基板010；接着，如图7所示，通过蚀刻工艺移除生长衬底001，直至露出N型欧姆接触层203；在N型欧姆接触层上形成第一电极011，第一电极011与N型欧姆接触层203形成良好的欧姆接触；然后，形成掩膜覆盖在第一电极011上；蚀刻去除第一电极周围的欧姆接触层203，暴露AlG aAS窗口层204，接着蚀刻AlGaAS窗口层204以形成图形化或粗化面，以增大光的提取效率；最后，如图8所示，在导电性基板010的背面侧形成第二电极012，借此在第一电极011和第二电极012以及半导体外延堆叠层之间可以传导电流。
最后根据客户的尺寸需要，通过蚀刻、劈裂等工艺获得单元化的双结LED发光元件。
实施例二
与实施例1的区别在于，本实施例中重掺杂N型Ga YIn 1-YP为Te和Si混掺杂的N型Ga YIn 1-YP，其Te掺杂浓度为1E19～2E20cm -3，Si掺杂浓度为5E18～2E19cm -3。更优选地，所述所述Te、Si的掺杂浓度比例为5∶3～2∶1。除此之外以实施例1相同的条件进行隧穿结合多结LED的制作。
本实施例中，通过高Te、低Si混掺杂的方式实现N型Ga YIn 1-YP的重掺杂，经研究表明，通过高Te、低Si混掺杂可改善外延层的表面质量。
以42mil芯片为例，在其他结构和条件相同的情况下，隧穿结采用重掺杂N型Ga YIn 1-YP，相比于隧穿结使用重掺杂N型AlGaAs，在350mA测试电流下，Vf值可降低0.43V，亮度可增幅7.5％。这是因为使用重掺杂N型Ga YIn 1-YP，能够有效减小不可见光的吸光效应，提升器件亮度，并且有效降低串联电阻降低电压；同时加入Al X2Ga 1-X2As渐变层一和Al X3Ga 1-X3As渐变层二，可以有效改善界面质量和晶体生长质量，并且可以实现As、P有效切换，减小串联电阻，降低工作电压，从而提升光电转换效率。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，这样的修改和变型均落入由所附权利要求所限定的范围之内。

Claims (39)

  1. 一种用于多结LED的隧穿结，包括：
    重掺杂P型Al X1Ga 1-X1As；
    Al X2Ga 1-X2As渐变层一；
    重掺杂N型Ga YIn 1-YP；
    Al X3Ga 1-X3As渐变层二。
  2. 根据权利要求1所述的一种用于多结LED的隧穿结，其特征在于：所述重掺杂P型Al X1Ga 1-X1As的X1的范围为0～0.8。
  3. 根据权利要求1所述的一种用于多结LED的隧穿结，其特征在于：所述重掺杂P型Al X1Ga 1-X1As的掺杂浓度为1E19cm -3以上。
  4. 根据权利要求1所述的一种用于多结LED的隧穿结，其特征在于：所述重掺杂P型Al X1Ga 1-X1As为C掺杂的P型Al X1Ga 1-X1As，其掺杂浓度为1E19～2E20cm -3。
  5. 根据权利要求1所述的一种用于多结LED的隧穿结，其特征在于：所述重掺杂P型Al X1Ga 1-X1As的厚度范围为10～100nm。
  6. 根据权利要求1所述的一种用于多结LED的隧穿结，其特征在于：所述重掺杂N型Ga YIn 1-YP的Y的范围为0.45～0.7。
  7. 根据权利要求1所述的一种用于多结LED的隧穿结，其特征在于：所述重掺杂N型Ga YIn 1-YP的掺杂浓度为1E19cm -3以上。
  8. 根据权利要求1所述的一种用于多结LED的隧穿结，其特征在于：所述重掺杂N型Ga YIn 1-YP为Te掺杂的N型Ga YIn 1-YP，其Te掺杂浓度为1E19～2E20cm -3。
  9. 根据权利要求1所述的一种用于多结LED的隧穿结，其特征在于：所述重掺杂N型Ga YIn 1-YP为Te和Si混掺杂的N型Ga YIn 1-YP，其Te掺杂浓度为1E19～2E20cm -3，Si掺杂浓度为5E18～2E19cm -3。
  10. 根据权利要求9所述的一种用于多结LED的隧穿结，其特征在于：所述重掺杂N型Ga YIn 1-YP为Te和Si混掺杂的N型Ga YIn 1-YP，所述Te、Si的掺杂浓度比例为5∶3～2∶1。
  11. 根据权利要求1所述的一种用于多结LED的隧穿结，其特征在于：所述重掺杂N型Ga YIn 1-YP的厚度范围为10～100nm。
  12. 根据权利要求1所述的一种用于多结LED的隧穿结，其特征在于：所述Al X2Ga 1-X2As渐变层一介于重掺杂P型Al X1Ga 1-X1As与重掺杂N型Ga YIn 1-YP之间，所述Al X2Ga 1-X2As渐变层一的Al相对含量自重掺杂P型Al X1Ga 1-X1As往重掺杂N型Ga yIn 1-yP方向是逐渐递减的。
  13. 根据权利要求12所述的一种用于多结LED的隧穿结，其特征在于：所述Al X2Ga 1-X2As渐变层一的Al相对含量自重掺杂P型Al X1Ga 1-X1As往重掺杂N型Ga yIn 1-yP方向是线性递减的。
  14. 根据权利要求1所述的一种用于多结LED的隧穿结，其特征在于：所述Al X2Ga 1-X2As渐变层一为C掺杂的P型Al X2Ga 1-X2As渐变层，其掺杂浓度为1E19～5E19cm -3。
  15. 根据权利要求1所述的一种用于多结LED的隧穿结，其特征在于：所述Al X2Ga 1-X2As渐变层一的厚度范围为10～50nm。
  16. 根据权利要求1所述的一种用于多结LED的隧穿结，其特征在于：所述Al X3Ga 1-X3As渐变层二位于重掺杂N型Ga YIn 1-YP之上，所述Al X3Ga 1-X3As渐变层二的Al相对含量自远离重掺杂N型Ga YIn 1-YP方向是逐渐递增的。
  17. 根据权利要求16所述的一种用于多结LED的隧穿结，其特征在于：所述Al X3Ga 1-X3As渐变层二的Al相对含量自远离重掺杂N型Ga YIn 1-YP方向是线性递增的。
  18. 根据权利要求1所述的一种用于多结LED的隧穿结，其特征在于：所述Al X3Ga 1-X3As渐变层二为Te掺杂的N型Al X3Ga 1-X3As渐变层，其掺杂浓度为1E19～5E19cm -3。
  19. 根据权利要求1所述的一种用于多结LED的隧穿结，其特征在于：所述Al X3Ga 1-X3As渐变层二的厚度范围为10～50nm。
  20. 一种多结LED结构，至少包括第一LEDI外延结构和第二LEDII外延结构，其特征在于：在所述第一LEDI外延结构和第二LEDII外延 结构之间具有权利要求1～19所述的一种隧穿结。
  21. 根据权利要求20所述的一种多结LED结构，其特征在于：所述第一LEDI外延结构和第二LEDII外延结构辐射波长为760nm～1100nm的红外光。
  22. 一种多结LED结构的制备方法，包括步骤：
    形成第一LEDI外延结构；在所述第一LEDI外延结构的上方形成隧穿结，其包含重掺杂P型Al X1Ga 1-X1As；Al X2Ga 1-X2As渐变层一；
    重掺杂N型Ga YIn 1-YP；Al X3Ga 1-X3As渐变层二；
    在所述隧穿结结构上方形成第二LEDII外延结构。
  23. 根据权利要求22所述的一种多结LED的制备方法，其特征在于：所述重掺杂P型Al X1Ga 1-X1As的X1的范围为0～0.8。
  24. 根据权利要求22所述的一种多结LED的制备方法，其特征在于：所述重掺杂P型Al X1Ga 1-X1As为C掺杂的P型Al X1Ga 1-X1As，其掺杂浓度为1E19～2E20cm -3。
  25. 根据权利要求22所述的一种多结LED的制备方法，其特征在于：所述重掺杂P型Al X1Ga 1-X1As的厚度范围为10～100nm。
  26. 根据权利要求22所述的一种多结LED的制备方法，其特征在于：所述重掺杂N型Ga YIn 1-YP的Y的范围为0.45～0.7。
  27. 根据权利要求22所述的一种多结LED的制备方法，其特征在于：所述重掺杂N型Ga YIn 1-YP为Te掺杂的N型Ga YIn 1-YP，其Te掺杂浓度为1E19～2E20cm -3。
  28. 根据权利要求22所述的一种多结LED的制备方法，其特征在于：所述重掺杂N型Ga YIn 1-YP为Te和Si混掺杂的N型Ga YIn 1-YP，其Te掺杂浓度为1E19～2E20cm -3，Si掺杂浓度为5E18～2E19cm -3。
  29. 根据权利要求28所述的一种多结LED的制备方法，其特征在于：所述重掺杂N型Ga YIn 1-YP为Te和Si混掺杂的N型Ga YIn 1-YP，所述Te、Si的掺杂浓度比例为5∶3～2∶1。
  30. 根据权利要求22所述的一种多结LED的制备方法，其特征在于： 所述重掺杂N型Ga YIn 1-YP的厚度范围为10～100nm。
  31. 根据权利要求22所述的一种多结LED的制备方法，其特征在于：所述Al X2Ga 1-X2As渐变层一介于重掺杂P型Al X1Ga 1-X1As与重掺杂N型Ga YIn 1-YP之间，所述Al X2Ga 1-X2As渐变层一的Al相对含量自重掺杂P型Al X1Ga 1-X1As往重掺杂N型Ga yIn 1-yP方向是逐渐递减的。
  32. 根据权利要求31所述的一种多结LED的制备方法，其特征在于：所述Al X2Ga 1-X2As渐变层一的Al相对含量自重掺杂P型Al X1Ga 1-X1As往重掺杂N型Ga yIn 1-yP方向是线性递减的。
  33. 根据权利要求22所述的一种多结LED的制备方法，其特征在于：所述Al X2Ga 1-X2As渐变层一为C掺杂的P型Al X2Ga 1-X2As渐变层，其掺杂浓度为1E19～5E19cm -3。
  34. 根据权利要求22所述的一种多结LED的制备方法，其特征在于：所述Al X2Ga 1-X2As渐变层一的厚度范围为10～50nm。
  35. 根据权利要求22所述的一种多结LED的制备方法，其特征在于：所述Al X3Ga 1-X3As渐变层二位于重掺杂N型Ga YIn 1-YP之上，所述Al X3Ga 1-X3As渐变层二的Al相对含量自远离重掺杂N型Ga YIn 1-YP方向是逐渐递增的。
  36. 根据权利要求35所述的一种多结LED的制备方法，其特征在于：所述Al X3Ga 1-X3As渐变层二的Al相对含量自远离重掺杂N型Ga YIn 1-YP方向是线性递增的。
  37. 根据权利要求22所述的一种多结LED的制备方法，其特征在于：所述Al X3Ga 1-X3As渐变层二为Te掺杂的N型Al X3Ga 1-X3As渐变层，其掺杂浓度为1E19～5E19cm -3。
  38. 根据权利要求22所述的一种多结LED的制备方法，其特征在于：所述Al X3Ga 1-X3As渐变层二的厚度范围为10～50nm。
  39. 根据权利要求22所述的一种多结LED的制备方法，其特征在于：所述第一LEDI外延结构和第二LEDII外延结构辐射波长为760nm～1100nm的红外光。
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