WO2021161379A1 - Display panel and method for producing display device - Google Patents

Display panel and method for producing display device Download PDF

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Publication number
WO2021161379A1
WO2021161379A1 PCT/JP2020/005117 JP2020005117W WO2021161379A1 WO 2021161379 A1 WO2021161379 A1 WO 2021161379A1 JP 2020005117 W JP2020005117 W JP 2020005117W WO 2021161379 A1 WO2021161379 A1 WO 2021161379A1
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Prior art keywords
silicon island
display panel
substrate
line
panel according
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PCT/JP2020/005117
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French (fr)
Japanese (ja)
Inventor
克彦 岸本
徹 増野
幸也 西岡
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堺ディスプレイプロダクト株式会社
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Priority to PCT/JP2020/005117 priority Critical patent/WO2021161379A1/en
Publication of WO2021161379A1 publication Critical patent/WO2021161379A1/en

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    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09FDISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09FDISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements

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  • the present invention relates to a method for manufacturing a display panel and a display device, and more particularly to a display panel capable of efficiently repairing defects in an active matrix type display panel and a method for manufacturing a display device using such a display panel.
  • an organic EL display panel for mobile use has, for example, a total of six or more TFTs including one switching TFT for each pixel (for example, Patent Documents 1 to 3). All of the disclosures of Patent Documents 1 to 3 are incorporated herein by reference.
  • Patent Document 4 describes a method of irradiating a predetermined layer of an organic layer of a pixel having a bright spot defect with a laser beam to cause multiphoton absorption to form a non-light emitting portion composed of the defective portion. It is disclosed.
  • JP-A-2007-279655 Japanese Unexamined Patent Publication No. 2010-0264888 Japanese Unexamined Patent Publication No. 2019-74729 Japanese Unexamined Patent Publication No. 2008-235178
  • Patent Document 4 cannot deal with the emission line defect. According to the study of the present inventor, when the signal line connected to the TFT of each pixel is short-circuited with the power supply line, a series of pixels (pixel strings) connected to the signal line become bright spots and are recognized as bright line defects. .. Short circuits between signal lines and power lines are often caused, for example, by poor patterning of these wirings. The emission line defect caused by such a short circuit of the wiring can be repaired by blocking the path for supplying the current or voltage to the pixel which is abnormally operating due to the poor patterning.
  • a method of cutting off the path for supplying current or voltage to the pixel As a method of cutting off the path for supplying current or voltage to the pixel, a method of cutting the wiring by irradiating a laser beam is known.
  • this method is effective for aluminum wiring and aluminum alloy wiring, it is formed of a refractory metal (for example, W, Mo, Ta, etc. having a melting point exceeding 2000 ° C.). It is not easy to cut the wire by irradiating the laser beam.
  • the organic EL display panel is often provided with a sealing structure that covers the organic EL element (which constitutes each pixel), and in such a case, one of the laser beams.
  • the portion is absorbed or reflected by the sealing structure, it may be difficult to cut even the aluminum wiring and the aluminum alloy wiring. Even if the laser beam is irradiated from the substrate side instead of from the sealing structure side, there is absorption or reflection by the substrate, so that there is a similar problem. Since the liquid crystal display panel has a pair of substrates facing each other via the liquid crystal layer, there is a problem that it becomes difficult to cut the wiring due to absorption by the substrates or the like.
  • the wiring is easily cut by the laser beam irradiation even if the wiring is made of a refractory metal or when the laser beam is irradiated through the sealing structure or the substrate. It is an object of the present invention to provide a display panel capable of the present invention and a method for manufacturing a display device using such a display panel.
  • a display panel having a switching TFT the display panel further A plurality of scanning lines, each of which is connected to any one of the plurality of scanning lines, and a plurality of scanning lines.
  • a plurality of signal lines each of which is connected to any one of the plurality of signal lines, and a plurality of signal lines.
  • Each of the plurality of pixels has a first silicon island formed between the scanning line and the substrate and / or a second silicon island formed between the signal line and the substrate.
  • the first silicon island has a portion protruding in the width direction of the scanning line when viewed from the normal direction of the substrate, and the second silicon island has the signal when viewed from the normal direction of the substrate.
  • a display panel that has a portion that protrudes in the width direction of the line.
  • [Item 5] It also has a plurality of power supply lines and a plurality of driving TFTs.
  • the gate electrode of the driving TFT is connected to the drain electrode of the switching TFT
  • the source electrode of the driving TFT is connected to the power supply line
  • the driving TFT has.
  • the drain electrode is connected to the pixel electrode and
  • a third is provided between the drain electrode of the switching TFT and the pixel electrode, and between the wiring between the drain electrode and the pixel electrode of the switching TFT and the substrate.
  • the display panel according to any one of items 1 to 4, further comprising a silicon island.
  • the thickness of the third silicon island is, for example, 10 nm or more and 500 nm or less.
  • the thickness of the third silicon island is Tsi and the thickness of the wiring on the third silicon island is Trm, the relationship of 0.05 ⁇ Tsi / Trm ⁇ 1.0 is satisfied.
  • the third silicon island may be formed of polysilicon or amorphous silicon.
  • the third silicon island is formed of, for example, the same semiconductor as the first silicon island and / or the second silicon island.
  • the thickness of the first silicon island or the second silicon island is independently Tsi, and the thickness of an arbitrary scanning line on the first silicon island or the thickness of an arbitrary signal line on the second silicon island is set as Tsi, respectively.
  • a method for manufacturing a display device comprising the step C of cutting the scanning line or the signal line by melting the first silicon island or the second silicon island.
  • step A the display panel according to item 5 is prepared.
  • step B a location where a short circuit occurs with any of the plurality of power supply lines in the plurality of signal lines is identified.
  • step C the signal line is cut by melting the two second silicon islands sandwiching the short-circuited portion of the signal line in which the short circuit occurs.
  • the gate electrode of the driving TFT and the switching TFT are formed by melting the third silicon island of the pixel connected to the power supply line through the short-circuited portion of the signal line.
  • the substrate contains a colored polyimide film.
  • the substrate contains a transparent polyimide film.
  • Step A is a step of preparing a top emission type organic EL display panel as the display panel.
  • the wiring can be easily provided by the laser beam irradiation.
  • a display panel that can be cut and a method for manufacturing a display device using such a display panel are provided.
  • the display panel according to the embodiment of the present invention can be easily cut even if the wiring is made of a metal other than the refractory metal (for example, aluminum, copper and alloys thereof).
  • an organic EL display panel (hereinafter, may be referred to as an OLED (Organic Light Emitting Diode) display panel) will be described as an example, but the embodiment according to the present invention is not limited to the OLED display panel and is a liquid crystal display panel. It can be widely applied to a display panel having a thin film transistor (TFT) for each pixel, such as a micro LED display panel having an arranged inorganic LED.
  • TFT thin film transistor
  • Such a display panel having a TFT for each pixel is called an active matrix type display panel or a TFT type display panel, but here, for the sake of simplicity, it may be simply referred to as a display panel.
  • multi-chamfering In mass production of TFT type display panels, so-called "multi-chamfering” is adopted. That is, individual display panels are manufactured by cutting a multi-chamfered display panel (sometimes referred to as a "mother display panel") including a plurality of display panels manufactured by using a mother substrate. An external circuit such as a power supply circuit or a control circuit is mounted on each display panel to manufacture a display device. Defect repair, such as cutting short-circuited parts of wiring, is performed in the state of the mother display panel or after cutting into individual display panels. In the present specification, for the sake of clarity, the step of repairing a defect in the display panel is described as being included in the process of manufacturing the display device, but the method of manufacturing the display panel may include the step of repairing the defect. good.
  • FIG. 1 is a schematic plan view of four pixels of the OLED display panel 100A according to the embodiment of the present invention.
  • the OLED display panel 100A has a plurality of pixels arranged in a matrix. Pixels are defined herein as follows.
  • the OLED display panel has a plurality of pixels, and each of the plurality of pixels has a pixel electrode, a switching TFT, and a driving TFT.
  • the display panel is a color display panel capable of performing color display, three or more pixels among the plurality of pixels constitute one color display pixel.
  • the color display pixel is composed of, for example, three pixels of R, G, and B (striped arrangement), or four pixels of, for example, R, G, G, and B (pentile arrangement and diamond pentile arrangement).
  • a definition is also known in the present specification in which a "pixel" is a sub-pixel and a "color display pixel" is a pixel.
  • the micro LED display panel also has a plurality of pixels, and each pixel has a switching TFT and a driving TFT, respectively.
  • the micro LED includes a pixel electrode.
  • a striped arrangement for example, three pixels constituting one color display pixel are selected by switching TFTs connected to a common scanning line, and display signals (data signals) are transmitted from different signal lines to the gate of the driving TFT.
  • a current of a magnitude corresponding to the signal is supplied from the power supply line via the driving TFT.
  • the signal line is typically provided corresponding to the color sequence. That is, for a certain signal line, for example, only R pixels are connected.
  • the four switching TFTs included in the four pixels constituting one color display pixel are connected to two or more scanning lines.
  • pixels that display different colors are connected to one signal line.
  • the connection relationship between the switching TFT for selecting pixels and the scanning line and the signal line may differ depending on the pixel arrangement (color arrangement).
  • the liquid crystal display panel typically has only a signal line (data line), a scanning line, and one switching TFT for each pixel, whereas the OLED display panel has at least one for each pixel.
  • One driving TFT is required in addition to the one switching TFT, and usually, a total of six or more TFTs including one switching TFT for each pixel are provided (Patent Documents 1 to 3).
  • the switching TFT, the driving TFT, the scanning line connected to the switching TFT, the signal line (including the main line and the branch line) and the power supply line connected to the driving TFT are referred to. I will explain only the relationship between.
  • the electrode directly connected to the driving TFT (drain) is referred to as a pixel electrode.
  • the pixel electrode can be a cathode or an anode.
  • the structures other than the one switching TFT provided for each pixel, the one driving TFT, the signal line connected to the driving TFT, the power supply line, and the pixel electrode, which will be described below, have the same structure as a known display panel. It can be widely applied.
  • the pixels Px of the OLED display panel 100A include a scanning line (SC) 22, a signal line (DA) 26, a power supply line (EL VDD) 28, one switching TFT Ts, and one. It has a driving TFT Te.
  • the scanning line 22 has a main line 22M extending in the row direction and a branch line 22B branched from the main line 22M
  • the signal line 26 has a main line 26M extending in the column direction and a branch line 26B branched from the main line 26M. doing.
  • the extension portion of the branch line 22B of the scanning line 22 constitutes the gate electrode TsG of the TFT Ts, and the extension portion of the branch line 26B of the signal line 26 constitutes the source electrode TsS of the TFT Ts, and the drain electrode TsD. Is formed of the same conductive layer as the signal line 26.
  • the drain electrode TsD of the TFT Ts is formed so as to be connected to the gate electrode TeG of the TFT Te via, for example, a contact hole Ch.
  • the source electrode TeS of the TFT Te is composed of a part of the power supply line 28, and the drain electrode TeD is formed of the same conductive layer as the power supply line 28.
  • the gate electrode TeG of the driving TFT Te is formed of the same conductive layer as the scanning line 22, and may be formed of a refractory metal.
  • the drain electrode TeD of the TFT Te is connected to the pixel electrode 32 (see FIG. 3A).
  • the semiconductor layer 20a included in the TFT Te and the semiconductor layer 20b included in the TFT Ts are formed of the same semiconductor layer.
  • the gate electrode, the source electrode, and the drain electrode may refer to a portion of the conductive layer constituting each of the conductive layers, which overlaps with the semiconductor layer.
  • the scanning line 22 is supplied with a scanning signal from the gate driver GD1 (not shown) connected to the terminal (gate terminal) of the scanning line 22 in the direction indicated by the arrow in FIG. 1 (from right to left). Further, a data signal is supplied to the signal line 26 from a source driver SD1 (not shown) connected to a terminal (source terminal) of the signal line 26 in the direction of the arrow in FIG. 1 (from top to bottom).
  • the driving TFT Te corresponds to, for example, the TFT T3 in FIG. 2 of Patent Document 2 shown in FIG. 6 and the TFT M1 in FIG. 5 of Patent Document 3 shown in FIG. Further, the switching TFT Ts in FIG. 1 corresponds to the TFT T4 in FIG. 2 of Patent Document 2 shown in FIG. 6 and the TFT M3 in FIG. 5 of Patent Document 3 shown in FIG.
  • the OLED display panel 100A includes a scanning line 22 and a switching TFT Ts (gate electrode TsG) when viewed from the gate terminal to which the gate driver GD1 is connected (that is, when viewed from the direction of the arrow GD1 in FIG. 1).
  • the first silicon island 20A formed between the branch line 22B branched from the main line 22M of the scanning line 22 toward the switching TFT Ts (gate electrode TsG) and the substrate is provided between the two.
  • the OLED display panel 100A is located between the signal line 26 and the switching TFT Ts when viewed from the source terminal to which the source driver SD1 is connected (that is, when viewed from the direction of the arrow SD1 in FIG. 1). It has a second silicon island 20B formed between the branch line 26B branched from the main line 26M of the signal line 26 toward the switching TFT Ts (source electrode TsS) and the substrate.
  • a state in which the pixel Px does not change the brightness according to the corresponding data signal and black cannot be displayed is referred to as a bright spot defect state, and a pixel in such a state is referred to as a bright spot defect.
  • a pixel in such a state is referred to as a bright spot defect.
  • the pixels of the bright spot defect are in a continuous state, such a pixel array is referred to as a bright line defect.
  • the signal line 26 is cut at the position of the second silicon island 20B, the data signal supplied from the source driver SD1 does not reach the switching TFT Ts. Therefore, in this case as well, the driving TFT Te does not operate. Therefore, since no current is supplied to the pixel electrode 32, the pixel Px does not emit light. By doing so, the pixel Px that was in the bright spot defect state can be always turned off (black display state).
  • the position where the first silicon island 20A and / or the second silicon island 20B is provided is not limited to the example shown in FIG. 1, and is driven by cutting the wiring on the first silicon island 20A and / or the second silicon island 20B. It is only necessary to prevent the voltage for turning on the driving TFT Te from being supplied to the gate electrode TeG of the driving TFT Te.
  • the first silicon island 20A and the second silicon island 20B are formed of polysilicon or amorphous silicon.
  • Polysilicon or amorphous silicon absorbs light more easily than metals and generates heat by absorbing light. The heat melts the polysilicon or amorphous silicon, thereby cutting the scanning line 22 formed on the first silicon island 20A and / or the signal line 26 formed on the second silicon island 20B.
  • the scanning lines 22 and / or the signal lines 26 are made of refractory metal, it is difficult to cut them by irradiating these wires directly with a laser beam, but the first silicon island 20A and the second silicon By using the island 20B, it is possible to cut these wirings efficiently and surely.
  • the first silicon island 20A and the second silicon island 20B can be formed from the same semiconductor film at the same time, for example, when forming the semiconductor layer 20a of the driving TFT Te and / or the semiconductor layer 20b of the switching TFT Ts.
  • the semiconductor layer of the driving TFT Te and / or the switching TFT Ts is formed of polysilicon
  • the first silicon island 20A and the second silicon island 20B may also be formed of polysilicon, or may not be crystallized. , May be formed of amorphous silicon.
  • the wavelength of the laser beam to be irradiated may be appropriately selected depending on polysilicon or amorphous.
  • the first silicon island 20A has a portion protruding in the width direction of the branch line 22B of the scanning line 22 when viewed from the normal direction of the substrate
  • the second silicon island 20B has a portion protruding in the width direction of the branch line 22B of the scanning line 22
  • the second silicon island 20B has a portion when viewed from the normal direction of the substrate. It has a portion protruding in the width direction of the branch line 26B of the signal line 26. If the first silicon island 20A and the second silicon island 20B have a portion protruding from these wirings, even if the laser beam is irradiated from above the substrate, the protruding portion absorbs the laser beam. Can be disconnected.
  • the length of the protruding portion is, for example, 0.5 ⁇ m or more and 1 ⁇ m or less. If it is less than 0.5 ⁇ m, it may be difficult to identify silicon islands with an optical camera using visible light attached to a device that irradiates a laser beam. Further, the length orthogonal to the width direction of the first silicon island 20A and / or the second silicon island 20B is 1 ⁇ m or more and 2 ⁇ m or less. The sizes and shapes of the first silicon island 20A and the second silicon island 20B will be described later with reference to FIGS. 4A, 4B, 5A, and 5B. The same applies to the second silicon islands 20C1 and 20C2 and the third silicon island 20D, which will be described later.
  • the thickness of the first silicon island 20A and / or the second silicon island 20B is independently, for example, 10 nm or more and 500 nm or less.
  • the thickness of the first silicon island 20A and / or the second silicon island 20B is independently, for example, 10 nm or more and 50 nm or less.
  • the thickness of the first silicon island 20A or the second silicon island 20B is independently set as Tsi, and the thickness of the scanning line 22 on the first silicon island 20A or the thickness of the signal line 26 on the second silicon island 20B is set respectively.
  • Trm is used independently, it is preferable to satisfy the relationship of 0.05 ⁇ Tsi / Trm ⁇ 1.0. If this relationship is satisfied, these wires can be cut efficiently.
  • FIG. 2 shows a schematic plan view of four pixels of another OLED display panel 100B according to the embodiment of the present invention.
  • the power supply line 28 (n-1 row) and the signal line 26 (n row) are short-circuited at the short-circuited portion DF1 shown in FIG.
  • a display signal (data signal) that changes corresponding to each pixel is supplied from the source driver SD1 via the signal line 26, it is higher than the display signal corresponding to the highest gradation from the power supply line 28.
  • gate drivers will be placed on both sides of the scanning line and source drivers will be placed on both sides of the signal line in order to suppress delays and distortions in the scanning signal and display signal due to the resistance of the wiring.
  • double-sided input structure a configuration in which each signal is supplied from both sides.
  • the OLED display panel 100B shown in FIG. 2 has a double-sided input structure. Therefore, in the OLED display panel 100B, the scanning signal (scan signal) and the display signal (data signal) are supplied to the switching TFT Ts and the driving TFT Te from the drivers arranged on both sides, respectively.
  • the OLED display panel 100B it is assumed that n rows of pixels Px connected to the signal line 26 have a emission line defect.
  • the cause (short-circuited portion) causing the emission line defect is the power supply line 28 of the pixel Px (m, n-1) adjacent to the signal line 26 in the pixel Px (m, n).
  • the high voltage (abnormal voltage) supplied from the power supply line 28 is higher than that of the pixel Px (m-1, n).
  • the pixels in the previous stage (upper row) are no longer reached, and the correct display signal is supplied to the pixels in the previous stage from the pixels Px (m-1, n) via the signal line 26.
  • the signal line 26 is cut at the position of the second silicon island 20C2 included in the pixel Px (m + 1, n)
  • the high voltage (abnormal voltage) supplied from the power supply line 28 is higher than that of the pixel Px (m + 1, n). Also does not reach the pixels in the latter stage (lower row), and the pixels in one vertical column (n columns) connected to the signal line 26 other than the pixels Px (m, n) return to the normal state.
  • the high voltage of the power supply line 28 continues to be applied to the source electrode TsS of the switching TFT Ts of the pixel Px (m, n), so when the switching TFT Ts is turned on, the gate electrode of the driving TFT Te As a result of applying a high voltage to the pixel Px (m, n), the pixel Px (m, n) becomes a bright spot defect.
  • This bright spot defect is cut at a position where the third silicon island 20D is provided between the drain electrode TsD of the switching TFT Ts and the gate electrode TeG of the driving TFT Te, and drives the pixel Px (m, n).
  • black spots can be formed by preventing current from being supplied from the power supply line 28 to the pixel electrode 32.
  • the organic material layer formed on the pixel electrode 32 is irradiated with a laser to locally make the organic material layer. It is also possible to make it non-luminous by heating it to about 100 ° C.
  • the second silicon island and / or the third silicon island is not limited to the example shown in FIG. 2, but is somewhere below the signal line 26, and the drain electrode TsD of the switching TFT Ts and the gate electrode TeG of the driving TFT Te. It may be provided somewhere between and.
  • FIG. 3A is a schematic cross-sectional view of a portion including the driving TFT Te
  • FIG. 3B is a schematic cross-sectional view of the portion including the first silicon island 20A provided below the scanning line 22.
  • FIG. 3C Includes a second silicon island 20B, a second silicon island 20C1, 20C2, and a third silicon island 20D provided under the drain electrode of the signal line 26 or the switching TFT Ts formed of the same conductive layer as the signal line 26. It is a schematic cross-sectional view of a part.
  • the switching TFT Ts is a signal line 26 instead of the source electrode TeS and the drain electrode TeD (formed by the same conductive layer as the power supply line 28) in the cross-sectional structure of the driving TFT Te shown in FIG. 3A.
  • the source electrode TsS and the drain electrode TsD may be formed using the same conductive layer.
  • the scanning line 22 is formed ahead of the signal line 26 (the side closer to the substrate 10)
  • only the scanning line 22 may be formed of the refractory metal.
  • the signal line 26 is formed ahead of the scanning line 22 (the side closer to the substrate 10)
  • only the signal line 26 may be formed of the refractory metal.
  • the silicon islands may be provided only under the wiring formed earlier (the side closer to the substrate 10).
  • the wiring formed earlier is often made of a refractory metal having high heat resistance because it undergoes a thermal history in a subsequent process.
  • the present invention is not limited to this, and both the scanning line 22 and the signal line 26 may be formed of a refractory metal.
  • the substrate 10 has, for example, a laminated structure of an inorganic insulating layer 15 / a polyimide film 14 / an inorganic insulating layer 13 / a polyimide film 12.
  • the thicknesses of the polyimide films 12 and 14 are, for example, about 6 ⁇ m, and the thicknesses of the inorganic insulating layers 13 and 15 are, for example, 0.5 ⁇ m and 2 ⁇ m, respectively.
  • the OLED display panel includes a lower electrode (pixel electrode) 32, an organic layer 34 formed on the lower electrode 32, and an upper electrode 36 formed on the organic layer 34.
  • the lower electrode 32 and the upper electrode 36 form, for example, an anode and a cathode, respectively.
  • the upper electrode 36 is a common electrode formed over a plurality of pixels in the display area.
  • the lower electrode (pixel electrode) 32 is formed for each pixel.
  • Each pixel of the OLED display panel has an OLED element.
  • the lower electrode 32 of the OLED element is formed on the flattening layer 27, and is connected to the drain electrode TeD in the through hole formed in the flattening layer 27.
  • the bank layer 33 is formed between the lower electrode 32 and the organic layer 34 so as to cover the peripheral portion of the lower electrode 32. If the bank layer 33 is present between the lower electrode 32 and the organic layer 34, holes are not injected from the lower electrode 32 into the organic layer 34. Therefore, since the region where the bank layer 33 exists does not function as a pixel, the bank layer 33 defines the outer edge of the pixel.
  • the driving TFT Te is a semiconductor layer 20a formed on the substrate 10, a gate insulating layer 21 formed on the semiconductor layer 20a, a gate electrode TeG formed on the gate insulating layer 21, and a gate electrode TeG. It has the interlayer insulating layers 23 and 25 formed in the above, and the source electrode TeS and the drain electrode TeD formed on the interlayer insulating layer 25.
  • the source electrode TeS and the drain electrode TeD are connected to the source region and the drain region of the semiconductor layer 20a, respectively, in the contact holes formed in the interlayer insulating layers 25 and 23 and the gate insulating layer 21.
  • the gate electrode TeG is included in the same metal layer as the scanning line 22 and the like, and the source electrode TeS and the drain electrode TeD are included in the same metal layer as the signal line 26.
  • the metal layer including the scanning line 22 (gate electrode TsG of the switching TFT Ts) is the first metal layer, the metal layer including the signal line 26 is the second metal layer, and the metal layer including the power supply line 28 is the third metal layer.
  • the OLED display panel may have a fourth metal layer in addition to these metal layers.
  • the fourth metal layer can be formed, for example, between the interlayer insulating layer 23 and the interlayer insulating layer 25. For example, in FIG.
  • a wiring (electrically connected to the signal line 26) formed by using the fourth metal layer may be used at least partially. That is, when the portion of the signal line 26 arranged so as to overlap the second silicon island 20B, the second silicon islands 20C1, 20C2, and the third silicon island 20D is formed by the fourth metal layer, the fourth metal layer is the first. Since it is closer to the second silicon island 20B, the second silicon island 20C1, 20C2, and the third silicon island 20D than the two metal layers, the second silicon island 20B, the second silicon island 20C1, 20C2, and the third silicon island 20D are melted. This makes it possible to cut more reliably.
  • each pixel has a first silicon island, a second silicon island, and a third silicon island, but in color display pixel units, the first silicon island, the second silicon island, and A third silicon island may be provided. That is, the color display pixels including the pixels in which the short-circuit defect has occurred may be hidden. For example, in a display panel having a resolution of 400 ppi, even if several pixels are continuously hidden, it is not noticeable.
  • the laser beam may irradiate the first silicon island, the second silicon island, and the third silicon island via the substrate.
  • the laser beam preferably has a wavelength of 500 nm or more.
  • YAG of 539 nm or 532 nm can be used.
  • the laser beam preferably has a wavelength of 300 nm or more and less than 500 nm, more preferably 400 nm or more and less than 500 nm.
  • Polysilicon can be destroyed even with the fundamental wave (1064 nm) of the YAG laser.
  • the fundamental wave (1064 nm) of the YAG laser in the case of visible light, it is possible to align by irradiating a laser beam with reduced output (the illuminated part can be visually recognized), whereas in the case of infrared light, an infrared sensor is used to do the same.
  • an infrared sensor is used to do the same.
  • a CCD sensor or a CMOS sensor that is sensitive not only in the visible light region but also in the near infrared region can be preferably used (however, the confirmation screen is a black and white image).
  • the wavelength is 500 nm or more, and the upper limit is about the oscillation wavelength of the YAG laser. If it is a transparent PI, a blue-violet laser having a wavelength of about 400 nm or a blue laser having a wavelength of about 450 nm can also be used. Since the transmittance of ultraviolet rays on a substrate (resin substrate) made of a resin such as PI is low, an ultraviolet laser is not suitable for laser irradiation through the substrate. However, for laser irradiation that does not pass through a substrate, an ultraviolet laser is preferable because it has a higher energy. Further, the shorter the wavelength, the more suitable for high-definition processing.
  • FIGS. 4A, 4B, 5A, 5B the size of the silicon islands used as the first silicon island 20A, the second silicon island 20B, the second silicon island 20C1, 20C2, the third silicon island 20D, and the like.
  • the shape will be described.
  • 4A, 4B, 5A, and 5B are plan views showing the silicon island and the wirings 22 and 26 formed on the silicon island, and the silicon island side (board) so that the outer shape of the silicon island can be easily understood. The figure seen from the side) is shown.
  • the silicon island 20E shown in FIG. 4A and the silicon island 20F shown in FIG. 4B have portions Sc and Sd protruding in the width direction of the wirings 22 and 26 when viewed from the normal direction of the substrate. If the protruding portion is provided, even if the laser beam is irradiated from above the substrate, the protruding portion absorbs the laser beam, so that the wiring can be cut. Further, if the protruding portion has an acute angle, there is an advantage that alignment when irradiating the laser beam becomes easy.
  • the lengths Lx and Ly of the protruding portion are, for example, 0.5 ⁇ m or more and 1 ⁇ m or less.
  • the length of the silicon island 20E orthogonal to the width direction is 1 ⁇ m or more and 2 ⁇ m or less.
  • the branch line 22B (see FIG. 1) branched from the main line 22M of the scanning line 22 toward the gate electrode TsG may be cut at the silicon island 20G or 20H. good. If the silicon islands 20G or 20H are arranged corresponding to the branch structure, the signal can be prevented from being supplied to the gate electrode TsG by cutting only one place (branch structure) regardless of the signal input direction.
  • the portions (three locations) protruding from the wiring preferably have an acute angle, and the lengths Lx and Ly of the protruding portions are, for example, 0.5 ⁇ m or more and 1 ⁇ m or less.
  • the portion where the source electrode TsS branches from the signal line 26 may be cut at the silicon island 20G or 20H.
  • the embodiment according to the present invention has been described by taking an OLED display panel as an example, but the present invention is not limited to this, and can be applied to, for example, an inorganic LED display panel and a micro LED display panel in which a large number of inorganic LED devices are arranged. .. Similar to the OLED display panel, these display panels have a power supply line in addition to the scanning line and the signal line, so that a bright line defect can occur like the OLED display panel. , The emission line defect can be repaired.
  • the liquid crystal display panel does not have a power supply line and a driving TFT like the OLED display panel, and the drain electrode of the switching TFT is directly connected to the pixel electrode. Even in the liquid crystal display panel, when a short circuit defect (for example, between the signal line and the common electrode) occurs in the signal line, a bright spot defect and / or a bright line defect may occur. Even in such a case, the bright spot defect and / or the bright line defect can be repaired by applying the present invention. That is, as shown in FIG. 1, a silicon island is formed between the branch line of the scanning line and the substrate between the scanning line and the gate electrode of the switching TFT, and / or the signal line and the switching are used.
  • a silicon island may be formed between the branch line of the signal line and the substrate between the source electrode of the TFT and the substrate.
  • a silicon island may be formed between the main line of the signal line and the substrate for each pixel, or a drain electrode may be formed between the drain electrode and the pixel electrode of the switching TFT. Silicon islands may be formed between the wiring between the pixel electrodes and the substrate.
  • the present invention can be used in an active matrix type display panel and a method for manufacturing a display device using such a display panel.
  • Substrate 12 Polygon film 13: Inorganic insulating layer 14: Polyethylene film 15: Inorganic insulating layer 20A: First silicon island 20B: Second silicon island (below the branch line) 20C1, 20C2: Second silicon island (main line) Bottom) 20D: Third silicon islands 20a, 20b: Semiconductor layer 21: Gate insulation layer 22: Scanning lines 23, 25: Thin film transistor insulation layer 26: Signal line 28: Power supply line 32: Pixel electrode (lower electrode) 33: Bank layer 34: Organic layer 36: Upper electrodes 100A, 100B: OLED display panel DF1: Short-circuited part DF2: Short-circuited part GD1: Gate driver SD1: Source driver Ts: Switching TFT Te: Driving TFT

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Abstract

A display panel (100A) having: a substrate (10); a plurality of pixel electrodes (32) supported by the substrate; a plurality of switching TFTs (Ts) connected one by one to each of the plurality of pixel electrodes; a plurality of scanning lines (22), with the plurality of switching TFTs being respectively connected to the plurality of scanning lines; a plurality of signal lines (26), with the plurality of switching TFTs being respectively connected to the plurality of signal lines; and, for each of a plurality of pixels, a first silicon island (20A) formed between the scanning lines and the substrate, and/or a second silicon island (20B) formed between the signal lines and the substrate. The first silicon island has a portion protruding in the width direction of the scanning lines when seen from a direction normal to the substrate, and the second silicon island has a portion protruding in the width direction of the signal lines when seen from the direction normal to the substrate.

Description

表示パネルおよび表示装置の製造方法Manufacturing method of display panel and display device
 本発明は表示パネルおよび表示装置の製造方法に関し、特に、アクティブマトリクス型表示パネルにおける欠陥を効率的に修復することができる表示パネルおよびそのような表示パネルを用いた表示装置の製造方法に関する。 The present invention relates to a method for manufacturing a display panel and a display device, and more particularly to a display panel capable of efficiently repairing defects in an active matrix type display panel and a method for manufacturing a display device using such a display panel.
 現在、液晶表示パネルおよび有機EL表示パネルなどの、画素毎にTFT(スイッチング用TFT)を有するアクティブマトリクス型表示パネル(以下、単に「表示パネル」という。)が広く用いられている。小型高精細化が進むにつれて、配線のパターニング不良による歩留りの低下が問題になっている。特に、モバイル用途の有機EL表示パネルは、例えば、画素毎に、1つのスイッチング用TFTを含む合計6つ以上のTFTを有している(例えば、特許文献1~3)。特許文献1~3の開示内容のすべてを参照により本明細書に援用する。 Currently, active matrix type display panels (hereinafter, simply referred to as "display panels") having TFTs (switching TFTs) for each pixel, such as liquid crystal display panels and organic EL display panels, are widely used. As the miniaturization and high definition progress, the decrease in yield due to poor patterning of wiring has become a problem. In particular, an organic EL display panel for mobile use has, for example, a total of six or more TFTs including one switching TFT for each pixel (for example, Patent Documents 1 to 3). All of the disclosures of Patent Documents 1 to 3 are incorporated herein by reference.
 そこで、表示パネルの歩留りを向上させるために、欠陥を修正する方法が種々検討されている。例えば、特許文献4には、輝点欠陥となった画素の有機層の所定の層にレーザビームを照射し、多光子吸収を生じさせて欠損部で構成された非発光部を形成する方法が開示されている。 Therefore, in order to improve the yield of the display panel, various methods for correcting defects are being studied. For example, Patent Document 4 describes a method of irradiating a predetermined layer of an organic layer of a pixel having a bright spot defect with a laser beam to cause multiphoton absorption to form a non-light emitting portion composed of the defective portion. It is disclosed.
特開2007-279655号公報JP-A-2007-279655 特開2010-026488号公報Japanese Unexamined Patent Publication No. 2010-0264888 特開2019-74729号公報Japanese Unexamined Patent Publication No. 2019-74729 特開2008-235178号公報Japanese Unexamined Patent Publication No. 2008-235178
 特許文献4に記載の方法では、輝線欠陥には対応できない。本発明者の検討によると、各画素のTFTに接続された信号線が電源線と短絡すると、当該信号線に接続された一連の画素(画素列)が輝点となり、輝線欠陥として認識される。信号線と電源線との短絡は、例えば、これらの配線のパターニング不良が原因で生じることが多い。このような配線の短絡に起因する輝線欠陥は、パターニング不良により異常動作している画素に電流または電圧を供給する経路を遮断することによって修復され得る。 The method described in Patent Document 4 cannot deal with the emission line defect. According to the study of the present inventor, when the signal line connected to the TFT of each pixel is short-circuited with the power supply line, a series of pixels (pixel strings) connected to the signal line become bright spots and are recognized as bright line defects. .. Short circuits between signal lines and power lines are often caused, for example, by poor patterning of these wirings. The emission line defect caused by such a short circuit of the wiring can be repaired by blocking the path for supplying the current or voltage to the pixel which is abnormally operating due to the poor patterning.
 画素に電流または電圧を供給する経路を遮断する方法として、レーザビームを照射することによって配線を切断する方法が知られている。しかしながら、本発明者の検討によると、この方法は、アルミニウム配線およびアルミニウム合金配線に対しては有効であるが、高融点金属(例えば、融点が2000℃を超えるW、Mo、Ta等)で形成された配線は、レーザビームの照射によって切断するのは容易ではない。また、有機EL表示パネルでは、信頼性を向上させるために、(個々の画素を構成する)有機EL素子を覆う封止構造が設けられることが多く、そのような場合には、レーザビームの一部が封止構造で吸収または反射されるために、アルミニウム配線およびアルミニウム合金配線であっても切断が困難となることがある。封止構造側からではなく、基板側からレーザビームを照射したとしても、基板による吸収または反射があるので、同様の問題がある。液晶表示パネルは液晶層を介して対向する一対の基板を有するので、基板による吸収等によって、配線の切断が困難になるという問題がある。 As a method of cutting off the path for supplying current or voltage to the pixel, a method of cutting the wiring by irradiating a laser beam is known. However, according to the study of the present inventor, although this method is effective for aluminum wiring and aluminum alloy wiring, it is formed of a refractory metal (for example, W, Mo, Ta, etc. having a melting point exceeding 2000 ° C.). It is not easy to cut the wire by irradiating the laser beam. Further, in order to improve reliability, the organic EL display panel is often provided with a sealing structure that covers the organic EL element (which constitutes each pixel), and in such a case, one of the laser beams. Since the portion is absorbed or reflected by the sealing structure, it may be difficult to cut even the aluminum wiring and the aluminum alloy wiring. Even if the laser beam is irradiated from the substrate side instead of from the sealing structure side, there is absorption or reflection by the substrate, so that there is a similar problem. Since the liquid crystal display panel has a pair of substrates facing each other via the liquid crystal layer, there is a problem that it becomes difficult to cut the wiring due to absorption by the substrates or the like.
 そこで、本発明は、高融点金属で形成された配線であっても、あるいは、封止構造または基板を介してレーザビームを照射する場合であっても、レーザビーム照射によって配線を容易に切断することができる表示パネルおよびそのような表示パネルを用いた表示装置の製造方法を提供することを目的とする。 Therefore, in the present invention, the wiring is easily cut by the laser beam irradiation even if the wiring is made of a refractory metal or when the laser beam is irradiated through the sealing structure or the substrate. It is an object of the present invention to provide a display panel capable of the present invention and a method for manufacturing a display device using such a display panel.
 本発明の実施形態によると、以下の項目に記載の解決手段が提供される。 According to an embodiment of the present invention, the solutions described in the following items are provided.
[項目1]
 基板と、前記基板に支持された複数の画素電極と、前記複数の画素電極のそれぞれに1つずつ接続された複数のスイッチング用TFTとを有し、複数の画素毎に、前記画素電極と前記スイッチング用TFTとを有する表示パネルであって、前記表示パネルはさらに、
 複数の走査線であって、前記複数のスイッチング用TFTのそれぞれが、前記複数の走査線のいずれか1つに接続されている、複数の走査線と、
 複数の信号線であって、前記複数のスイッチング用TFTのそれぞれが、前記複数の信号線のいずれか1つに接続されている、複数の信号線と、
 前記複数の画素毎に、前記走査線と前記基板との間に形成された第1シリコン島および/または前記信号線と前記基板との間に形成された第2シリコン島とを有し、
 前記第1シリコン島は、前記基板の法線方向からみたとき、前記走査線の幅方向にはみ出した部分を有し、前記第2シリコン島は、前記基板の法線方向からみたとき、前記信号線の幅方向にはみ出した部分を有する、表示パネル。
[Item 1]
It has a substrate, a plurality of pixel electrodes supported by the substrate, and a plurality of switching TFTs connected to each of the plurality of pixel electrodes, and the pixel electrodes and the said are described for each of the plurality of pixels. A display panel having a switching TFT, the display panel further
A plurality of scanning lines, each of which is connected to any one of the plurality of scanning lines, and a plurality of scanning lines.
A plurality of signal lines, each of which is connected to any one of the plurality of signal lines, and a plurality of signal lines.
Each of the plurality of pixels has a first silicon island formed between the scanning line and the substrate and / or a second silicon island formed between the signal line and the substrate.
The first silicon island has a portion protruding in the width direction of the scanning line when viewed from the normal direction of the substrate, and the second silicon island has the signal when viewed from the normal direction of the substrate. A display panel that has a portion that protrudes in the width direction of the line.
[項目2]
 前記走査線と前記スイッチング用TFTのゲート電極との間において、前記走査線の分岐線と前記基板との間に前記第1シリコン島を有する、項目1に記載の表示パネル。
[Item 2]
The display panel according to item 1, wherein the first silicon island is provided between the scanning line and the gate electrode of the switching TFT, and between the branch line of the scanning line and the substrate.
[項目3]
 前記信号線と前記スイッチング用TFTとの間において、前記信号線の分岐線と前記基板との間に前記第2シリコン島を有する、項目1に記載の表示パネル。
[Item 3]
The display panel according to item 1, wherein the second silicon island is provided between the signal line and the switching TFT, and between the branch line of the signal line and the substrate.
[項目4]
 前記複数の画素毎に、前記信号線の主線と前記基板との間に前記第2シリコン島を有する、項目1に記載の表示パネル。
[Item 4]
The display panel according to item 1, wherein the second silicon island is provided between the main line of the signal line and the substrate for each of the plurality of pixels.
[項目5]
 複数の電源線と複数の駆動用TFTとをさらに有し、
 前記複数の画素毎に、前記駆動用TFTのゲート電極は前記スイッチング用TFTのドレイン電極に接続されており、前記駆動用TFTのソース電極は前記電源線に接続されており、前記駆動用TFTのドレイン電極は前記画素電極に接続されており、
 前記駆動用TFTの前記ゲート電極と前記スイッチング用TFTの前記ドレイン電極とを接続する配線と前記基板との間に形成された第3シリコン島をさらに有する、項目1から4のいずれかに記載の表示パネル。
[Item 5]
It also has a plurality of power supply lines and a plurality of driving TFTs.
For each of the plurality of pixels, the gate electrode of the driving TFT is connected to the drain electrode of the switching TFT, the source electrode of the driving TFT is connected to the power supply line, and the driving TFT has. The drain electrode is connected to the pixel electrode and
The item according to any one of items 1 to 4, further comprising a third silicon island formed between the wiring connecting the gate electrode of the driving TFT and the drain electrode of the switching TFT and the substrate. Display panel.
[項目6]
 前記複数の画素毎に、前記スイッチング用TFTの前記ドレイン電極と前記画素電極との間において、前記スイッチング用TFTの前記ドレイン電極と前記画素電極との間の配線と前記基板との間に第3シリコン島をさらに有する、項目1から4のいずれかに記載の表示パネル。前記第3シリコン島の厚さは、例えば、10nm以上500nm以下である。前記第3シリコン島の厚さをTsiとし、前記第3シリコン島上の前記配線の厚さをTrmとするとき、0.05≦Tsi/Trm≦1.0の関係を満足する。前記第3シリコン島は、ポリシリコンで形成されてもよいし、アモルファスシリコンで形成されてよい。前記第3シリコン島は、例えば、前記第1シリコン島および/または前記第2シリコン島と同じ半導体で形成されている。
[Item 6]
For each of the plurality of pixels, a third is provided between the drain electrode of the switching TFT and the pixel electrode, and between the wiring between the drain electrode and the pixel electrode of the switching TFT and the substrate. The display panel according to any one of items 1 to 4, further comprising a silicon island. The thickness of the third silicon island is, for example, 10 nm or more and 500 nm or less. When the thickness of the third silicon island is Tsi and the thickness of the wiring on the third silicon island is Trm, the relationship of 0.05 ≦ Tsi / Trm ≦ 1.0 is satisfied. The third silicon island may be formed of polysilicon or amorphous silicon. The third silicon island is formed of, for example, the same semiconductor as the first silicon island and / or the second silicon island.
[項目7]
 前記複数の走査線および/または前記複数の信号線は高融点金属で形成されている、項目1から6のいずれかに記載の表示パネル。
[Item 7]
The display panel according to any one of items 1 to 6, wherein the plurality of scanning lines and / or the plurality of signal lines are made of a refractory metal.
[項目8]
 前記第1シリコン島および/または前記第2シリコン島の厚さは、それぞれ独立に、10nm以上500nm以下である、項目1から7のいずれかに記載の表示パネル 。
[Item 8]
The display panel according to any one of items 1 to 7, wherein the thickness of the first silicon island and / or the second silicon island is independently 10 nm or more and 500 nm or less.
[項目9]
 前記第1シリコン島または前記第2シリコン島の厚さをそれぞれ独立にTsiとし、前記第1シリコン島上の任意の走査線の厚さまたは前記第2シリコン島上の任意の信号線の厚さをそれぞれ独立にTrmとするとき、0.05≦Tsi/Trm≦1.0の関係を満足する、項目1から8のいずれかに記載の表示パネル。
[Item 9]
The thickness of the first silicon island or the second silicon island is independently Tsi, and the thickness of an arbitrary scanning line on the first silicon island or the thickness of an arbitrary signal line on the second silicon island is set as Tsi, respectively. The display panel according to any one of items 1 to 8, which satisfies the relationship of 0.05 ≦ Tsi / Trm ≦ 1.0 when Trm is used independently.
[項目10]
 前記第1シリコン島および/または前記第2シリコン島は、ポリシリコンで形成されている、項目1から9のいずれかに記載の表示パネル。
[Item 10]
The display panel according to any one of items 1 to 9, wherein the first silicon island and / or the second silicon island is formed of polysilicon.
[項目11]
 前記第1シリコン島および/または前記第2シリコン島は、アモルファスシリコンで形成されている、項目1から9のいずれかに記載の表示パネル。
[Item 11]
The display panel according to any one of items 1 to 9, wherein the first silicon island and / or the second silicon island is formed of amorphous silicon.
[項目12]
 前記はみ出した部分は、鋭角を有している、項目1から11のいずれかに記載の表示パネル。
[Item 12]
The display panel according to any one of items 1 to 11, wherein the protruding portion has an acute angle.
[項目13]
 前記はみ出した部分の長さは、0.5μm以上1μm以下である、項目1から12のいずれかに記載の表示パネル。
[Item 13]
The display panel according to any one of items 1 to 12, wherein the length of the protruding portion is 0.5 μm or more and 1 μm or less.
[項目14]
 前記第1シリコン島および/または前記第2シリコン島の前記幅方向に直交する長さは、1μm以上2μm以下である、項目1から13のいずれかに記載の表示パネル。
[Item 14]
The display panel according to any one of items 1 to 13, wherein the length of the first silicon island and / or the second silicon island orthogonal to the width direction is 1 μm or more and 2 μm or less.
[項目15]
 前記基板は、ポリイミドフィルムを含む、項目1から14のいずれかに記載の表示パネル。
[Item 15]
The display panel according to any one of items 1 to 14, wherein the substrate includes a polyimide film.
[項目16]
 前記ポリイミドフィルムは着色している、項目15に記載の表示パネル。
[Item 16]
The display panel according to item 15, wherein the polyimide film is colored.
[項目17]
 項目1から16のいずれかに記載の表示パネルを用意する工程Aと、
 前記複数の走査線または前記複数の信号線において短絡が発生している箇所を特定する工程Bと、
 前記短絡が発生している箇所を含む走査線または信号線の前記短絡が発生している箇所に最も近い前記第1シリコン島または前記第2シリコン島の少なくとも前記はみ出した部分にレーザビームを照射し、前記第1シリコン島または前記第2シリコン島を溶融させることによって、前記走査線または前記信号線を切断する工程Cと
を包含する、表示装置の製造方法。
[Item 17]
Step A to prepare the display panel according to any one of items 1 to 16 and
Step B for identifying a location where a short circuit occurs in the plurality of scanning lines or the plurality of signal lines, and
A laser beam is irradiated to at least the protruding portion of the first silicon island or the second silicon island closest to the location where the short circuit occurs in the scanning line or signal line including the location where the short circuit occurs. A method for manufacturing a display device, comprising the step C of cutting the scanning line or the signal line by melting the first silicon island or the second silicon island.
[項目18]
 前記工程Aにおいて、項目5に記載の前記表示パネルを用意し、
 前記工程Bにおいて、前記複数の信号線において前記複数の電源線のいずれかと短絡が発生している箇所を特定し、
 前記工程Cにおいて、前記短絡が発生している信号線の短絡箇所を挟む2つの前記第2シリコン島を溶融させることによって、前記信号線を切断する、項目17に記載の表示装置の製造方法。
[Item 18]
In the step A, the display panel according to item 5 is prepared.
In the step B, a location where a short circuit occurs with any of the plurality of power supply lines in the plurality of signal lines is identified.
The method for manufacturing a display device according to item 17, wherein in the step C, the signal line is cut by melting the two second silicon islands sandwiching the short-circuited portion of the signal line in which the short circuit occurs.
[項目19]
 前記工程Cにおいて、前記信号線の前記短絡箇所を介して前記電源線に接続されている画素の前記第3シリコン島を溶融させることによって、前記駆動用TFTの前記ゲート電極と前記スイッチング用TFTの前記ドレイン電極とを接続する前記配線を切断する、項目18に記載に表示装置の製造方法。
[Item 19]
In the step C, the gate electrode of the driving TFT and the switching TFT are formed by melting the third silicon island of the pixel connected to the power supply line through the short-circuited portion of the signal line. The method for manufacturing a display device according to item 18, wherein the wiring connecting the drain electrode is cut.
[項目20]
 前記工程Cにおいて、前記レーザビームは前記基板を介して、前記第1シリコン島または前記第2シリコン島に照射される、項目17から19のいずれかに記載の表示装置の製造方法。
[Item 20]
The method for manufacturing a display device according to any one of items 17 to 19, wherein in the step C, the laser beam is irradiated to the first silicon island or the second silicon island via the substrate.
[項目21]
 前記基板は、着色したポリイミドフィルムを含み、
 前記レーザビームは、500nm以上の波長を有する、項目20に記載の表示装置の製造方法。
[Item 21]
The substrate contains a colored polyimide film.
The method for manufacturing a display device according to item 20, wherein the laser beam has a wavelength of 500 nm or more.
[項目22]
 前記基板は、透明なポリイミドフィルムを含み、
 前記レーザビームは、300nm以上500nm未満の波長を有する、項目20に記載の表示装置の製造方法。
[Item 22]
The substrate contains a transparent polyimide film.
The method for manufacturing a display device according to item 20, wherein the laser beam has a wavelength of 300 nm or more and less than 500 nm.
[項目23]
 前記工程Aは、前記表示パネルとして、トップエミッション型の有機EL表示パネルを用意する工程である、項目17から22のいずれかに記載の表示装置の製造方法。
[Item 23]
The method for manufacturing a display device according to any one of items 17 to 22, wherein the step A is a step of preparing a top emission type organic EL display panel as the display panel.
 本発明の実施形態によると、高融点金属で形成された配線であっても、あるいは、封止構造または基板を介してレーザビームを照射する場合であっても、レーザビーム照射によって容易に配線を切断することができる表示パネルおよびそのような表示パネルを用いた表示装置の製造方法が提供される。本発明の実施形態による表示パネルは、もちろん、高融点金属以外の金属(例えば、アルミニウム、銅およびこれらの合金)で形成された配線であっても、容易に切断され得る。 According to an embodiment of the present invention, even if the wiring is made of a refractory metal, or if the laser beam is irradiated through the sealing structure or the substrate, the wiring can be easily provided by the laser beam irradiation. A display panel that can be cut and a method for manufacturing a display device using such a display panel are provided. The display panel according to the embodiment of the present invention can be easily cut even if the wiring is made of a metal other than the refractory metal (for example, aluminum, copper and alloys thereof).
本発明の実施形態によるOLED表示パネル100Aの1つの画素の模式的な平面図である。It is a schematic plan view of one pixel of the OLED display panel 100A according to the embodiment of the present invention. 本発明の実施形態によるOLED表示パネル100Bの1つの画素の模式的な平面図である。It is a schematic plan view of one pixel of the OLED display panel 100B according to the embodiment of the present invention. 本発明の実施形態によるOLED表示パネルの模式的な部分断面図である。It is a typical partial cross-sectional view of the OLED display panel according to the embodiment of the present invention. 本発明の実施形態によるOLED表示パネルの模式的な部分断面図である。It is a typical partial cross-sectional view of the OLED display panel according to the embodiment of the present invention. 本発明の実施形態によるOLED表示パネルの模式的な部分断面図である。It is a typical partial cross-sectional view of the OLED display panel according to the embodiment of the present invention. シリコン島の形状の例を示す図である。It is a figure which shows the example of the shape of a silicon island. シリコン島の形状の他の例を示す図である。It is a figure which shows another example of the shape of a silicon island. シリコン島の形状のさらに他の例を示す図である。It is a figure which shows still another example of the shape of a silicon island. シリコン島の形状のさらに他の例を示す図である。It is a figure which shows still another example of the shape of a silicon island. 特許文献2の図2に対応する図である。It is a figure corresponding to FIG. 2 of Patent Document 2. 特許文献3の図5に対応する図である。It is a figure corresponding to FIG. 5 of Patent Document 3.
 以下、図面を参照して、本発明の実施形態による表示パネルおよびそのような表示パネルを用いた表示装置の製造方法を説明する。ここでは、有機EL表示パネル(以下で、OLED(Organic Light Emitting Diode)表示パネルということがある。)を例に説明するが、本発明による実施形態は、OLED表示パネルに限られず、液晶表示パネルや配列された無機のLEDを有するマイクロLED表示パネルなど、画素毎に薄膜トランジスタ(Thin Film Transistor:TFT)を有する表示パネルに広く適用できる。このような画素毎にTFTを有する表示パネルは、アクティブマトリクス型表示パネルまたはTFT型表示パネルと呼ばれるが、ここでは、簡単のために単に表示パネルということがある。 Hereinafter, a display panel according to an embodiment of the present invention and a method for manufacturing a display device using such a display panel will be described with reference to the drawings. Here, an organic EL display panel (hereinafter, may be referred to as an OLED (Organic Light Emitting Diode) display panel) will be described as an example, but the embodiment according to the present invention is not limited to the OLED display panel and is a liquid crystal display panel. It can be widely applied to a display panel having a thin film transistor (TFT) for each pixel, such as a micro LED display panel having an arranged inorganic LED. Such a display panel having a TFT for each pixel is called an active matrix type display panel or a TFT type display panel, but here, for the sake of simplicity, it may be simply referred to as a display panel.
 TFT型表示パネルの量産では、いわゆる「多面取り」が採用されている。すなわち、マザー基板を用いて作製された複数の表示パネルを含む多面取り表示パネル(「マザー表示パネル」ということがある。)を切断することによって、個々の表示パネルが製造される。個々の表示パネルに、例えば、電源回路、制御回路などの外部回路を実装し、表示装置が製造される。配線の短絡箇所の切断などの欠陥修復は、マザー表示パネルの状態、または、個々の表示パネルに切断した後で行われる。本明細書では、分かりやすさのために、表示パネルの欠陥を修復する工程は、表示装置を製造するプロセスに含まれるとして説明するが、表示パネルの製造方法が欠陥を修復する工程を含んでもよい。 In mass production of TFT type display panels, so-called "multi-chamfering" is adopted. That is, individual display panels are manufactured by cutting a multi-chamfered display panel (sometimes referred to as a "mother display panel") including a plurality of display panels manufactured by using a mother substrate. An external circuit such as a power supply circuit or a control circuit is mounted on each display panel to manufacture a display device. Defect repair, such as cutting short-circuited parts of wiring, is performed in the state of the mother display panel or after cutting into individual display panels. In the present specification, for the sake of clarity, the step of repairing a defect in the display panel is described as being included in the process of manufacturing the display device, but the method of manufacturing the display panel may include the step of repairing the defect. good.
 図1は、本発明の実施形態によるOLED表示パネル100Aの4つの画素の模式的な平面図である。OLED表示パネル100Aは、マトリクス状に配列された複数の画素を有している。画素は本明細書において、画素を以下のように定義する。 FIG. 1 is a schematic plan view of four pixels of the OLED display panel 100A according to the embodiment of the present invention. The OLED display panel 100A has a plurality of pixels arranged in a matrix. Pixels are defined herein as follows.
 OLED表示パネルは、複数の画素を有し、複数の画素はそれぞれ画素電極とスイッチング用TFTおよび駆動用TFTとを有している。表示パネルがカラー表示を行えるカラー表示パネルのとき、複数の画素の内の3以上の画素が1つのカラー表示画素を構成する。カラー表示画素は、例えば、R、G、Bの3つの画素(ストライプ配列)、または、例えば、R、G、G、Bの4つの画素(ペンタイル配列、ダイヤモンドペンタイル配列)で構成される。本明細書における「画素」をサブ画素とし、「カラー表示画素」を画素とする定義も知られている。なお、マイクロLED表示パネルも、複数の画素を有し、各画素はそれぞれスイッチング用TFTと駆動用TFTとを有する。マイクロLEDは画素電極を備えている。 The OLED display panel has a plurality of pixels, and each of the plurality of pixels has a pixel electrode, a switching TFT, and a driving TFT. When the display panel is a color display panel capable of performing color display, three or more pixels among the plurality of pixels constitute one color display pixel. The color display pixel is composed of, for example, three pixels of R, G, and B (striped arrangement), or four pixels of, for example, R, G, G, and B (pentile arrangement and diamond pentile arrangement). A definition is also known in the present specification in which a "pixel" is a sub-pixel and a "color display pixel" is a pixel. The micro LED display panel also has a plurality of pixels, and each pixel has a switching TFT and a driving TFT, respectively. The micro LED includes a pixel electrode.
 ストライプ配列の場合、例えば1つのカラー表示画素を構成する3つの画素は共通の走査線に接続されたスイッチング用TFTによって選択され、互いに異なる信号線から表示信号(データ信号)が駆動用TFTのゲートに印加され、その信号に応じた大きさの電流が駆動用TFTを介して電源線から供給される。信号線は、典型的には色列に対応して設けられる。すなわち、ある信号線は例えばR画素だけが接続される。一方、ダイヤモンドペンタイル配列の場合、例えば1つのカラー表示画素を構成する4つの画素が有する4つのスイッチング用TFTは、2以上の走査線に接続される。また、1本の信号線に異なる色を表示する画素が接続される。このように、画素配列(カラー配列)によって、画素を選択するスイッチング用TFTと走査線および信号線との接続関係が異なり得る。 In the case of a striped arrangement, for example, three pixels constituting one color display pixel are selected by switching TFTs connected to a common scanning line, and display signals (data signals) are transmitted from different signal lines to the gate of the driving TFT. A current of a magnitude corresponding to the signal is supplied from the power supply line via the driving TFT. The signal line is typically provided corresponding to the color sequence. That is, for a certain signal line, for example, only R pixels are connected. On the other hand, in the case of the diamond pen tile arrangement, for example, the four switching TFTs included in the four pixels constituting one color display pixel are connected to two or more scanning lines. In addition, pixels that display different colors are connected to one signal line. As described above, the connection relationship between the switching TFT for selecting pixels and the scanning line and the signal line may differ depending on the pixel arrangement (color arrangement).
 また、液晶表示パネルは、典型的には信号線(データ線)と、走査線と、各画素に1つのスイッチング用TFTのみを有するのに対し、OLED表示パネルは、最低でも、画素毎に1つのスイッチング用TFTに加えて1つの駆動用TFTが必要であり、通常は、画素毎に1つのスイッチング用TFTを含む合計6つ以上のTFTを有している(特許文献1~3)。 Further, the liquid crystal display panel typically has only a signal line (data line), a scanning line, and one switching TFT for each pixel, whereas the OLED display panel has at least one for each pixel. One driving TFT is required in addition to the one switching TFT, and usually, a total of six or more TFTs including one switching TFT for each pixel are provided (Patent Documents 1 to 3).
 以下では、簡単のために、スイッチング用TFTと、駆動用TFTと、スイッチング用TFTに接続された走査線と、駆動用TFTに接続された信号線(主線および分岐線を含む)と電源線との関係だけを説明することにする。また、駆動用TFT(ドレイン)に直接接続された電極を画素電極ということにする。OLED表示パネルにおいて、画素電極は、陰極または陽極であり得る。OLED表示パネルにおいて、有機層(発光層を含む)を介して画素電極に対向する電極(陽極または陰極)および、液晶表示パネルにおいて、液晶層を介して画素電極に対向する電極(共通電極)、さらには画素毎に設けられた容量部分の説明は省略する。以下で説明する、画素毎に設けられた1つのスイッチング用TFT、1つの駆動用TFT、駆動用TFTに接続された信号線、電源線および画素電極以外の構造は、公知の表示パネルの構造を広く適用することができる。 In the following, for the sake of simplicity, the switching TFT, the driving TFT, the scanning line connected to the switching TFT, the signal line (including the main line and the branch line) and the power supply line connected to the driving TFT are referred to. I will explain only the relationship between. Further, the electrode directly connected to the driving TFT (drain) is referred to as a pixel electrode. In the OLED display panel, the pixel electrode can be a cathode or an anode. In the OLED display panel, an electrode (anode or cathode) facing the pixel electrode via an organic layer (including a light emitting layer), and in a liquid crystal display panel, an electrode facing the pixel electrode via a liquid crystal layer (common electrode). Furthermore, the description of the capacitance portion provided for each pixel will be omitted. The structures other than the one switching TFT provided for each pixel, the one driving TFT, the signal line connected to the driving TFT, the power supply line, and the pixel electrode, which will be described below, have the same structure as a known display panel. It can be widely applied.
 図1に示す様に、OLED表示パネル100Aの画素Pxは、走査線(SC)22と、信号線(DA)26と、電源線(ELVDD)28と、1つのスイッチング用TFT Tsと、1つの駆動用TFT Teとを有している。走査線22は、行方向に延びる主線22Mと主線22Mから分岐した分岐線22Bとを有しており、信号線26は、列方向に延びる主線26Mと主線26Mから分岐した分岐線26Bとを有している。走査線22の分岐線22Bの延長部分が、TFT Tsのゲート電極TsGを構成しており、信号線26の分岐線26Bの延長部分がTFT Tsのソース電極TsSを構成しており、ドレイン電極TsDは、信号線26と同じ導電層で形成されている。TFT Tsのドレイン電極TsDは、TFT Teのゲート電極TeGと例えばコンタクトホールChを介して接続するように形成されている。 As shown in FIG. 1, the pixels Px of the OLED display panel 100A include a scanning line (SC) 22, a signal line (DA) 26, a power supply line (EL VDD) 28, one switching TFT Ts, and one. It has a driving TFT Te. The scanning line 22 has a main line 22M extending in the row direction and a branch line 22B branched from the main line 22M, and the signal line 26 has a main line 26M extending in the column direction and a branch line 26B branched from the main line 26M. doing. The extension portion of the branch line 22B of the scanning line 22 constitutes the gate electrode TsG of the TFT Ts, and the extension portion of the branch line 26B of the signal line 26 constitutes the source electrode TsS of the TFT Ts, and the drain electrode TsD. Is formed of the same conductive layer as the signal line 26. The drain electrode TsD of the TFT Ts is formed so as to be connected to the gate electrode TeG of the TFT Te via, for example, a contact hole Ch.
 TFT Teのソース電極TeSは、電源線28の一部で構成されており、ドレイン電極TeDは電源線28と同じ導電層で形成されている。駆動用TFT Teのゲート電極TeGは、走査線22と同じ導電層で形成されており、高融点金属で形成されることがある。TFT Teのドレイン電極TeDは画素電極32に接続されている(図3A参照)。TFT Teが有する半導体層20aおよびTFT Tsが有する半導体層20bは、同じ半導体層から形成されている。なお、本明細書において、ゲート電極、ソース電極およびドレイン電極は、それぞれを構成する導電層のうち、半導体層と重なる部分を指すことがある。 The source electrode TeS of the TFT Te is composed of a part of the power supply line 28, and the drain electrode TeD is formed of the same conductive layer as the power supply line 28. The gate electrode TeG of the driving TFT Te is formed of the same conductive layer as the scanning line 22, and may be formed of a refractory metal. The drain electrode TeD of the TFT Te is connected to the pixel electrode 32 (see FIG. 3A). The semiconductor layer 20a included in the TFT Te and the semiconductor layer 20b included in the TFT Ts are formed of the same semiconductor layer. In the present specification, the gate electrode, the source electrode, and the drain electrode may refer to a portion of the conductive layer constituting each of the conductive layers, which overlaps with the semiconductor layer.
 ここで、走査線22には、走査線22の端子(ゲート端子)に接続された不図示のゲートドライバGD1から図1中の矢印で示す方向(右から左)に走査信号が供給される。また、信号線26には、信号線26の端子(ソース端子)に接続された不図示のソースドライバSD1から図1中の矢印の方向(上から下)にデータ信号が供給される。 Here, the scanning line 22 is supplied with a scanning signal from the gate driver GD1 (not shown) connected to the terminal (gate terminal) of the scanning line 22 in the direction indicated by the arrow in FIG. 1 (from right to left). Further, a data signal is supplied to the signal line 26 from a source driver SD1 (not shown) connected to a terminal (source terminal) of the signal line 26 in the direction of the arrow in FIG. 1 (from top to bottom).
 駆動用TFT Teは、例えば、図6に示す特許文献2の図2におけるTFT T3および図7に示す特許文献3の図5におけるTFT M1に相当する。また、図1中のスイッチング用TFT Tsは、図6に示す特許文献2の図2におけるTFT T4および図7に示す特許文献3の図5におけるTFT M3に相当する。 The driving TFT Te corresponds to, for example, the TFT T3 in FIG. 2 of Patent Document 2 shown in FIG. 6 and the TFT M1 in FIG. 5 of Patent Document 3 shown in FIG. Further, the switching TFT Ts in FIG. 1 corresponds to the TFT T4 in FIG. 2 of Patent Document 2 shown in FIG. 6 and the TFT M3 in FIG. 5 of Patent Document 3 shown in FIG.
 まず、輝点欠陥の修復について説明する。 First, the repair of bright spot defects will be explained.
 OLED表示パネル100Aは、ゲートドライバGD1が接続されたゲート端子から見たとき(すなわち、図1中の矢印GD1の方向から見たとき)、走査線22とスイッチング用TFT Ts(ゲート電極TsG)との間において、走査線22の主線22Mからスイッチング用TFT Ts(ゲート電極TsG)に向けて分岐された分岐線22Bと基板との間に形成された第1シリコン島20Aを有する。また、OLED表示パネル100Aは、ソースドライバSD1が接続されたソース端子から見たとき(すなわち、図1中の矢印SD1の方向から見たとき)、信号線26とスイッチング用TFT Tsとの間において、信号線26の主線26Mからスイッチング用TFT Ts(ソース電極TsS)に向けて分岐された分岐線26Bと基板との間に形成された第2シリコン島20Bを有している。 The OLED display panel 100A includes a scanning line 22 and a switching TFT Ts (gate electrode TsG) when viewed from the gate terminal to which the gate driver GD1 is connected (that is, when viewed from the direction of the arrow GD1 in FIG. 1). The first silicon island 20A formed between the branch line 22B branched from the main line 22M of the scanning line 22 toward the switching TFT Ts (gate electrode TsG) and the substrate is provided between the two. Further, the OLED display panel 100A is located between the signal line 26 and the switching TFT Ts when viewed from the source terminal to which the source driver SD1 is connected (that is, when viewed from the direction of the arrow SD1 in FIG. 1). It has a second silicon island 20B formed between the branch line 26B branched from the main line 26M of the signal line 26 toward the switching TFT Ts (source electrode TsS) and the substrate.
 ここで、画素Pxが対応するデータ信号に応じて輝度を変化させず、黒を表示できない状態を輝点欠陥状態であるといい、そのような状態にある画素を輝点欠陥ということにする。さらに、輝点欠陥の画素が連続している状態にあるときは、そのような画素列を輝線欠陥ということにする。第1シリコン島20Aの位置で走査線22を切断すると、ゲートドライバGD1から供給される走査信号がスイッチング用TFT Tsに到達しない。したがって、スイッチング用TFT Tsは常時オフ状態となり、その結果、駆動用TFT Teがオン状態にならないので画素電極32に電流が供給されることがなく、画素Pxは発光しない。また、第2シリコン島20Bの位置で信号線26を切断すると、ソースドライバSD1から供給されるデータ信号がスイッチング用TFT Tsに到達しないので、この場合もまた、駆動用TFT Teが動作せず、したがって、画素電極32に電流が供給されることがないので、画素Pxは発光しない。このようにすることによって、輝点欠陥状態にあった画素Pxを常時非点灯状態(黒表示状態)にできる。第1シリコン島20Aおよび/または第2シリコン島20Bを設ける位置は、図1に示した例に限られず、第1シリコン島20Aおよび/または第2シリコン島20B上で配線を切断することによって駆動用TFT Teのゲート電極TeGに駆動用TFT Teをオン状態にする電圧が供給されないようにできればよい。 Here, a state in which the pixel Px does not change the brightness according to the corresponding data signal and black cannot be displayed is referred to as a bright spot defect state, and a pixel in such a state is referred to as a bright spot defect. Further, when the pixels of the bright spot defect are in a continuous state, such a pixel array is referred to as a bright line defect. When the scanning line 22 is cut at the position of the first silicon island 20A, the scanning signal supplied from the gate driver GD1 does not reach the switching TFT Ts. Therefore, the switching TFT Ts is always off, and as a result, the driving TFT Te is not turned on, so that no current is supplied to the pixel electrode 32 and the pixel Px does not emit light. Further, if the signal line 26 is cut at the position of the second silicon island 20B, the data signal supplied from the source driver SD1 does not reach the switching TFT Ts. Therefore, in this case as well, the driving TFT Te does not operate. Therefore, since no current is supplied to the pixel electrode 32, the pixel Px does not emit light. By doing so, the pixel Px that was in the bright spot defect state can be always turned off (black display state). The position where the first silicon island 20A and / or the second silicon island 20B is provided is not limited to the example shown in FIG. 1, and is driven by cutting the wiring on the first silicon island 20A and / or the second silicon island 20B. It is only necessary to prevent the voltage for turning on the driving TFT Te from being supplied to the gate electrode TeG of the driving TFT Te.
 第1シリコン島20Aおよび第2シリコン島20Bは、ポリシリコンまたはアモルファスシリコンで形成される。ポリシリコンまたはアモルファスシリコンは、金属よりも光の吸収をし易く、光を吸収することによって発熱する。その熱によって、ポリシリコンまたはアモルファスシリコンが融解することによって、第1シリコン島20Aに形成されている走査線22および/または第2シリコン島20B上に形成されている信号線26が切断される。走査線22および/または信号線26が高融点金属で形成されている場合、これらの配線に直接レーザビームを照射することによって切断することは困難であるが、第1シリコン島20Aおよび第2シリコン島20Bを利用することによって、効率的かつ確実にこれらの配線を切断することが可能になる。 The first silicon island 20A and the second silicon island 20B are formed of polysilicon or amorphous silicon. Polysilicon or amorphous silicon absorbs light more easily than metals and generates heat by absorbing light. The heat melts the polysilicon or amorphous silicon, thereby cutting the scanning line 22 formed on the first silicon island 20A and / or the signal line 26 formed on the second silicon island 20B. When the scanning lines 22 and / or the signal lines 26 are made of refractory metal, it is difficult to cut them by irradiating these wires directly with a laser beam, but the first silicon island 20A and the second silicon By using the island 20B, it is possible to cut these wirings efficiently and surely.
 第1シリコン島20Aおよび第2シリコン島20Bは、例えば、駆動用TFT Teの半導体層20aおよび/またはスイッチング用TFT Tsの半導体層20bを形成する際に、同じ半導体膜から同時に形成され得る。例えば、駆動用TFT Teおよび/またはスイッチング用TFT Tsの半導体層をポリシリコンで形成する場合、第1シリコン島20Aおよび第2シリコン島20Bもポリシリコンで形成してもよいし、結晶化せず、アモルファスシリコンで形成してもよい。照射するレーザビームの波長は、ポリシリコンまたはアモルファスに応じて適宜選択すればよい。 The first silicon island 20A and the second silicon island 20B can be formed from the same semiconductor film at the same time, for example, when forming the semiconductor layer 20a of the driving TFT Te and / or the semiconductor layer 20b of the switching TFT Ts. For example, when the semiconductor layer of the driving TFT Te and / or the switching TFT Ts is formed of polysilicon, the first silicon island 20A and the second silicon island 20B may also be formed of polysilicon, or may not be crystallized. , May be formed of amorphous silicon. The wavelength of the laser beam to be irradiated may be appropriately selected depending on polysilicon or amorphous.
 第1シリコン島20Aは、基板の法線方向からみたとき、走査線22の分岐線22Bの幅方向にはみ出した部分を有し、第2シリコン島20Bは、基板の法線方向からみたとき、信号線26の分岐線26Bの幅方向にはみ出した部分を有する。第1シリコン島20Aおよび第2シリコン島20Bがこれらの配線からはみ出した部分を有すると、基板の上方からレーザビームを照射しても、はみ出した部分がレーザビームを吸収するので、これらの配線を切断することができる。 The first silicon island 20A has a portion protruding in the width direction of the branch line 22B of the scanning line 22 when viewed from the normal direction of the substrate, and the second silicon island 20B has a portion protruding in the width direction of the branch line 22B of the scanning line 22, and the second silicon island 20B has a portion when viewed from the normal direction of the substrate. It has a portion protruding in the width direction of the branch line 26B of the signal line 26. If the first silicon island 20A and the second silicon island 20B have a portion protruding from these wirings, even if the laser beam is irradiated from above the substrate, the protruding portion absorbs the laser beam. Can be disconnected.
 また、はみ出した部分が、鋭角を有していると、レーザビームを照射する際のアライメントが容易になるという利点が得られる。はみ出した部分の長さは、例えば、0.5μm以上1μm以下である。0.5μm未満だと、レーザビームを照射する装置に併設された可視光を用いた光学カメラにおいてシリコン島の識別が困難になる場合がある。また、第1シリコン島20Aおよび/または第2シリコン島20Bの幅方向に直交する長さは、1μm以上2μm以下である。第1シリコン島20Aおよび第2シリコン島20Bの大きさや形状については、図4A、図4B、図5A、図5Bを参照して後述する。後述する第2シリコン島20C1、20C2、および第3シリコン島20Dも同様である。 Also, if the protruding part has an acute angle, there is an advantage that alignment when irradiating the laser beam becomes easy. The length of the protruding portion is, for example, 0.5 μm or more and 1 μm or less. If it is less than 0.5 μm, it may be difficult to identify silicon islands with an optical camera using visible light attached to a device that irradiates a laser beam. Further, the length orthogonal to the width direction of the first silicon island 20A and / or the second silicon island 20B is 1 μm or more and 2 μm or less. The sizes and shapes of the first silicon island 20A and the second silicon island 20B will be described later with reference to FIGS. 4A, 4B, 5A, and 5B. The same applies to the second silicon islands 20C1 and 20C2 and the third silicon island 20D, which will be described later.
 第1シリコン島20Aおよび/または第2シリコン島20Bの厚さは、それぞれ独立に、例えば10nm以上500nm以下である。例えば、駆動用TFT Teの半導体層20aと同時に形成する場合には、第1シリコン島20Aおよび/または第2シリコン島20Bの厚さは、それぞれ独立に、例えば10nm以上50nm以下である。第1シリコン島20Aまたは第2シリコン島20Bの厚さをそれぞれ独立にTsiとし、第1シリコン島20A上の走査線22の厚さまたは第2シリコン島20B上の信号線26の厚さをそれぞれ独立にTrmとするとき、0.05≦Tsi/Trm≦1.0の関係を満足することが好ましい。この関係を満足すると、効率的にこれらの配線を切断することができる。 The thickness of the first silicon island 20A and / or the second silicon island 20B is independently, for example, 10 nm or more and 500 nm or less. For example, when the semiconductor layer 20a of the driving TFT Te is formed at the same time, the thickness of the first silicon island 20A and / or the second silicon island 20B is independently, for example, 10 nm or more and 50 nm or less. The thickness of the first silicon island 20A or the second silicon island 20B is independently set as Tsi, and the thickness of the scanning line 22 on the first silicon island 20A or the thickness of the signal line 26 on the second silicon island 20B is set respectively. When Trm is used independently, it is preferable to satisfy the relationship of 0.05 ≦ Tsi / Trm ≦ 1.0. If this relationship is satisfied, these wires can be cut efficiently.
 図2に、本発明の実施形態による他のOLED表示パネル100Bの4つの画素の模式的な平面図を示す。例えば、図2中に示した短絡箇所DF1で電源線28(n-1列)と信号線26(n列)とが短絡しているとする。この場合、ソースドライバSD1から信号線26を介して、各画素に対応して変化する表示信号(データ信号)が供給されても、電源線28から、最高階調に対応する表示信号よりも高い電圧が供給されるので、短絡が発生した信号線26(n列)に接続されている一列の画素Pxのすべてが、最高階調またはそれ以上の階調に対応する輝度となり、表示する画像に拘わらず輝線として認識されることになる。なお、図2中の短絡箇所DF2で電源線28(n列)と信号線26(n列)とが短絡した場合には、画素Px(m、n)だけが、輝点となる。 FIG. 2 shows a schematic plan view of four pixels of another OLED display panel 100B according to the embodiment of the present invention. For example, it is assumed that the power supply line 28 (n-1 row) and the signal line 26 (n row) are short-circuited at the short-circuited portion DF1 shown in FIG. In this case, even if a display signal (data signal) that changes corresponding to each pixel is supplied from the source driver SD1 via the signal line 26, it is higher than the display signal corresponding to the highest gradation from the power supply line 28. Since the voltage is supplied, all of the pixels Px in the single row connected to the signal line 26 (n rows) in which the short circuit occurs have the brightness corresponding to the highest gradation or higher gradation, and the image to be displayed has the brightness corresponding to the highest gradation or higher. Regardless, it will be recognized as a bright line. When the power supply line 28 (n row) and the signal line 26 (n row) are short-circuited at the short-circuited portion DF2 in FIG. 2, only the pixel Px (m, n) becomes a bright spot.
 OLED表示パネルの高精細化が進むと、配線が有する抵抗等による走査信号および表示信号の遅延やひずみを抑制するために、走査線の両側にゲートドライバを、信号線の両側にソースドライバを配置し、それぞれの信号を両側から供給する構成(以下、「両側入力構造」と呼ぶことがある。)が採用されることがある。 As the definition of OLED display panels progresses, gate drivers will be placed on both sides of the scanning line and source drivers will be placed on both sides of the signal line in order to suppress delays and distortions in the scanning signal and display signal due to the resistance of the wiring. However, a configuration in which each signal is supplied from both sides (hereinafter, may be referred to as a "double-sided input structure") may be adopted.
 図2に示したOLED表示パネル100Bは、両側入力構造を有している。そのため、OLED表示パネル100Bは、走査信号(スキャン信号)および表示信号(データ信号)がそれぞれ、両側に配置されたドライバからスイッチング用TFT Tsと駆動用TFT Teとに供給される。OLED表示パネル100Bにおいて、信号線26に接続されているn列の画素Pxが輝線欠陥となっているとする。輝線欠陥を生じさせている原因(短絡箇所)は、画素Px(m、n)内の信号線26と隣接する画素Px(m、n-1)の電源線28である。 The OLED display panel 100B shown in FIG. 2 has a double-sided input structure. Therefore, in the OLED display panel 100B, the scanning signal (scan signal) and the display signal (data signal) are supplied to the switching TFT Ts and the driving TFT Te from the drivers arranged on both sides, respectively. In the OLED display panel 100B, it is assumed that n rows of pixels Px connected to the signal line 26 have a emission line defect. The cause (short-circuited portion) causing the emission line defect is the power supply line 28 of the pixel Px (m, n-1) adjacent to the signal line 26 in the pixel Px (m, n).
 このような輝線欠陥を生じているOLED表示パネル100Bの欠陥修復方法を説明する。 The defect repair method of the OLED display panel 100B in which such a bright line defect has occurred will be described.
 まず、画素Px(m、n)の第2シリコン島20C1の位置で信号線26を切断すると、電源線28から供給される高い電圧(異常電圧)は、画素Px(m-1、n)より前段(上の行)の画素には到達しなくなり、信号線26を介して正しい表示信号が画素Px(m-1、n)より前段の画素に供給される。さらに、画素Px(m+1、n)に含まれる第2シリコン島20C2の位置で信号線26を切断すると、電源線28から供給される高い電圧(異常電圧)は、画素Px(m+1、n)よりも後段(下の行)の画素にも到達しなくなり、画素Px(m、n)以外の信号線26に接続された縦一列(n列)の画素が正常状態に戻る。 First, when the signal line 26 is cut at the position of the second silicon island 20C1 of the pixel Px (m, n), the high voltage (abnormal voltage) supplied from the power supply line 28 is higher than that of the pixel Px (m-1, n). The pixels in the previous stage (upper row) are no longer reached, and the correct display signal is supplied to the pixels in the previous stage from the pixels Px (m-1, n) via the signal line 26. Further, when the signal line 26 is cut at the position of the second silicon island 20C2 included in the pixel Px (m + 1, n), the high voltage (abnormal voltage) supplied from the power supply line 28 is higher than that of the pixel Px (m + 1, n). Also does not reach the pixels in the latter stage (lower row), and the pixels in one vertical column (n columns) connected to the signal line 26 other than the pixels Px (m, n) return to the normal state.
 ただし、これだけでは画素Px(m、n)のスイッチング用TFT Tsのソース電極TsSに電源線28の高い電圧が印加され続けるので、スイッチング用TFT Tsがオン状態になると、駆動用TFT Teのゲート電極に高い電圧が印加される結果、画素Px(m、n)は、輝点欠陥となる。この輝点欠陥は、スイッチング用TFT Tsのドレイン電極TsDと駆動用TFT Teのゲート電極TeGとの間の、第3シリコン島20Dを設けた箇所で切断し、画素Px(m、n)の駆動用TFT Teを常にオフ状態とすることによって、電源線28から画素電極32へ電流が供給されないようにすることにより、黒点化できる。 However, with this alone, the high voltage of the power supply line 28 continues to be applied to the source electrode TsS of the switching TFT Ts of the pixel Px (m, n), so when the switching TFT Ts is turned on, the gate electrode of the driving TFT Te As a result of applying a high voltage to the pixel Px (m, n), the pixel Px (m, n) becomes a bright spot defect. This bright spot defect is cut at a position where the third silicon island 20D is provided between the drain electrode TsD of the switching TFT Ts and the gate electrode TeG of the driving TFT Te, and drives the pixel Px (m, n). By always turning off the TFT Te for use, black spots can be formed by preventing current from being supplied from the power supply line 28 to the pixel electrode 32.
 なお、1画素を黒点化する方法としては、上述の第3シリコン島20Dを切断する以外に、画素電極32上に形成された有機材料層に対してレーザ照射を行い、有機材料層を局所的に100℃程度に加熱して非発光化させることによっても可能である。 As a method of blackening one pixel, in addition to cutting the third silicon island 20D described above, the organic material layer formed on the pixel electrode 32 is irradiated with a laser to locally make the organic material layer. It is also possible to make it non-luminous by heating it to about 100 ° C.
 上述したように配線を適切な位置で切断することにより、輝線欠陥となっていた画素列について、短絡が生じていた1画素だけを黒点化し、その他の画素を正常に表示を行うようにできる。 By cutting the wiring at an appropriate position as described above, it is possible to blacken only one pixel in which a short circuit has occurred and display the other pixels normally in the pixel sequence having a bright line defect.
 第2シリコン島および/または第3シリコン島は、図2に示した例に限られず、信号線26の下のどこか、およびスイッチング用TFT Tsのドレイン電極TsDと駆動用TFT Teのゲート電極TeGとの間のどこかに設ければよい。 The second silicon island and / or the third silicon island is not limited to the example shown in FIG. 2, but is somewhere below the signal line 26, and the drain electrode TsD of the switching TFT Ts and the gate electrode TeG of the driving TFT Te. It may be provided somewhere between and.
 図1または図2に例示したOLED表示パネル100A、100Bは、例えば、図3A、図3Bおよび図3Cに示すような断面構造を有している。図3Aは駆動用TFT Teを含む部分の模式的な断面図であり、図3Bは走査線22の下に設けられた第1シリコン島20Aを含む部分の模式的な断面図であり、図3Cは信号線26または信号線26と同じ導電層で形成されたスイッチング用TFT Tsのドレイン電極の下に設けられた第2シリコン島20B、第2シリコン島20C1、20C2、第3シリコン島20Dを含む部分の模式的な断面図である。なお、スイッチング用TFT Tsは、図3Aに示した駆動用TFT Teの断面構造におけるソース電極TeSおよびドレイン電極TeD(電源線28と同じ導電層で形成されている)の代わりに、信号線26と同じ導電層を用いて、ソース電極TsSおよびドレイン電極TsDを形成すればよい。 The OLED display panels 100A and 100B illustrated in FIG. 1 or 2 have, for example, a cross-sectional structure as shown in FIGS. 3A, 3B and 3C. FIG. 3A is a schematic cross-sectional view of a portion including the driving TFT Te, and FIG. 3B is a schematic cross-sectional view of the portion including the first silicon island 20A provided below the scanning line 22. FIG. 3C. Includes a second silicon island 20B, a second silicon island 20C1, 20C2, and a third silicon island 20D provided under the drain electrode of the signal line 26 or the switching TFT Ts formed of the same conductive layer as the signal line 26. It is a schematic cross-sectional view of a part. The switching TFT Ts is a signal line 26 instead of the source electrode TeS and the drain electrode TeD (formed by the same conductive layer as the power supply line 28) in the cross-sectional structure of the driving TFT Te shown in FIG. 3A. The source electrode TsS and the drain electrode TsD may be formed using the same conductive layer.
 ここでは、走査線22が信号線26よりも先(基板10に近い側)に形成されているので、走査線22だけが高融点金属で形成されてもよい。また、この例とは逆に、信号線26が走査線22よりも先(基板10に近い側)に形成される場合には、信号線26だけが高融点金属で形成されてもよい。このような場合には、先(基板10に近い側)に形成される配線の下にだけシリコン島を設けてもよい。先に形成される配線は、後続する工程で熱履歴を受けるので、耐熱性の高い高融点金属で形成されることが多い。もちろん、これに限られず、走査線22および信号線26の両方を高融点金属で形成してもよい。 Here, since the scanning line 22 is formed ahead of the signal line 26 (the side closer to the substrate 10), only the scanning line 22 may be formed of the refractory metal. Further, contrary to this example, when the signal line 26 is formed ahead of the scanning line 22 (the side closer to the substrate 10), only the signal line 26 may be formed of the refractory metal. In such a case, the silicon islands may be provided only under the wiring formed earlier (the side closer to the substrate 10). The wiring formed earlier is often made of a refractory metal having high heat resistance because it undergoes a thermal history in a subsequent process. Of course, the present invention is not limited to this, and both the scanning line 22 and the signal line 26 may be formed of a refractory metal.
 基板10は、例えば、無機絶縁層15/ポリイミド膜14/無機絶縁層13/ポリイミド膜12の積層構造を有している。ポリイミド膜12、14の厚さは、例えば約6μm、無機絶縁層13、15の厚さはそれぞれ例えば、0.5μmおよび2μmである。 The substrate 10 has, for example, a laminated structure of an inorganic insulating layer 15 / a polyimide film 14 / an inorganic insulating layer 13 / a polyimide film 12. The thicknesses of the polyimide films 12 and 14 are, for example, about 6 μm, and the thicknesses of the inorganic insulating layers 13 and 15 are, for example, 0.5 μm and 2 μm, respectively.
 図3Aに示す様に、OLED表示パネルは、下部電極(画素電極)32と、下部電極32上に形成された有機層34と、有機層34上に形成された上部電極36とを含む。ここでは、下部電極32および上部電極36は、例えば、それぞれ陽極および陰極を構成する。上部電極36は、表示領域の複数の画素全体にわたって形成されている共通の電極である。一方、下部電極(画素電極)32は画素ごとに形成されている。OLED表示パネルの各画素は、OLED素子を有している。 As shown in FIG. 3A, the OLED display panel includes a lower electrode (pixel electrode) 32, an organic layer 34 formed on the lower electrode 32, and an upper electrode 36 formed on the organic layer 34. Here, the lower electrode 32 and the upper electrode 36 form, for example, an anode and a cathode, respectively. The upper electrode 36 is a common electrode formed over a plurality of pixels in the display area. On the other hand, the lower electrode (pixel electrode) 32 is formed for each pixel. Each pixel of the OLED display panel has an OLED element.
 OLED素子の下部電極32は、平坦化層27上に形成されており、平坦化層27に形成されたスルーホール内で、ドレイン電極TeDに接続されている。 The lower electrode 32 of the OLED element is formed on the flattening layer 27, and is connected to the drain electrode TeD in the through hole formed in the flattening layer 27.
 バンク層33は、下部電極32と有機層34との間に、下部電極32の周辺部分を覆う様に形成されている。下部電極32と有機層34との間にバンク層33が存在すると、下部電極32から有機層34に正孔が注入されない。従って、バンク層33が存在する領域は画素として機能しないので、バンク層33が画素の外縁を規定する。 The bank layer 33 is formed between the lower electrode 32 and the organic layer 34 so as to cover the peripheral portion of the lower electrode 32. If the bank layer 33 is present between the lower electrode 32 and the organic layer 34, holes are not injected from the lower electrode 32 into the organic layer 34. Therefore, since the region where the bank layer 33 exists does not function as a pixel, the bank layer 33 defines the outer edge of the pixel.
 駆動用TFT Teは、基板10上に形成された半導体層20aと、半導体層20a上に形成されたゲート絶縁層21と、ゲート絶縁層21上に形成されたゲート電極TeGと、ゲート電極TeG上に形成された層間絶縁層23、25と、層間絶縁層25上に形成されたソース電極TeSおよびドレイン電極TeDとを有している。ソース電極TeSおよびドレイン電極TeDは、層間絶縁層25、23およびゲート絶縁層21に形成されたコンタクトホール内で、半導体層20aのソース領域およびドレイン領域にそれぞれ接続されている。 The driving TFT Te is a semiconductor layer 20a formed on the substrate 10, a gate insulating layer 21 formed on the semiconductor layer 20a, a gate electrode TeG formed on the gate insulating layer 21, and a gate electrode TeG. It has the interlayer insulating layers 23 and 25 formed in the above, and the source electrode TeS and the drain electrode TeD formed on the interlayer insulating layer 25. The source electrode TeS and the drain electrode TeD are connected to the source region and the drain region of the semiconductor layer 20a, respectively, in the contact holes formed in the interlayer insulating layers 25 and 23 and the gate insulating layer 21.
 ゲート電極TeGは走査線22等と同じメタル層に含まれ、ソース電極TeSおよびドレイン電極TeDは信号線26と同じメタル層に含まれる。走査線22(スイッチング用TFT Tsのゲート電極TsG)を含むメタル層を第1メタル層とし、信号線26を含むメタル層を第2メタル層、電源線28を含むメタル層を第3メタル層とすると、OLED表示パネルは、これらのメタル層に加えて、第4メタル層を有し得る。第4メタル層は、例えば、層間絶縁層23と層間絶縁層25との間に形成され得る。例えば、図3Cにおいて、信号線26に代えて、第4メタル層を用いて形成された配線(信号線26に電気的に接続されている)を少なくとも部分的に用いてもよい。すなわち、第2シリコン島20B、第2シリコン島20C1、20C2、第3シリコン島20Dと重なるように配置される信号線26の部分を第4メタル層で形成すると、第4メタル層の方が第2メタル層よりも第2シリコン島20B、第2シリコン島20C1、20C2、第3シリコン島20Dに近いので、第2シリコン島20B、第2シリコン島20C1、20C2、第3シリコン島20Dを溶融することによって、より確実に切断することが可能になる。 The gate electrode TeG is included in the same metal layer as the scanning line 22 and the like, and the source electrode TeS and the drain electrode TeD are included in the same metal layer as the signal line 26. The metal layer including the scanning line 22 (gate electrode TsG of the switching TFT Ts) is the first metal layer, the metal layer including the signal line 26 is the second metal layer, and the metal layer including the power supply line 28 is the third metal layer. Then, the OLED display panel may have a fourth metal layer in addition to these metal layers. The fourth metal layer can be formed, for example, between the interlayer insulating layer 23 and the interlayer insulating layer 25. For example, in FIG. 3C, instead of the signal line 26, a wiring (electrically connected to the signal line 26) formed by using the fourth metal layer may be used at least partially. That is, when the portion of the signal line 26 arranged so as to overlap the second silicon island 20B, the second silicon islands 20C1, 20C2, and the third silicon island 20D is formed by the fourth metal layer, the fourth metal layer is the first. Since it is closer to the second silicon island 20B, the second silicon island 20C1, 20C2, and the third silicon island 20D than the two metal layers, the second silicon island 20B, the second silicon island 20C1, 20C2, and the third silicon island 20D are melted. This makes it possible to cut more reliably.
 ここでは、各画素が、第1シリコン島、第2シリコン島、および第3シリコン島を有している例を示したが、カラー表示画素単位で、第1シリコン島、第2シリコン島、および第3シリコン島を設けてもよい。すなわち、短絡欠陥が発生した画素を含むカラー表示画素を非表示としてもよい。例えば、400ppiの解像度の表示パネルでは、数画素が連続して非表示となっても目立たない。 Here, an example is shown in which each pixel has a first silicon island, a second silicon island, and a third silicon island, but in color display pixel units, the first silicon island, the second silicon island, and A third silicon island may be provided. That is, the color display pixels including the pixels in which the short-circuit defect has occurred may be hidden. For example, in a display panel having a resolution of 400 ppi, even if several pixels are continuously hidden, it is not noticeable.
 レーザビームは基板を介して、第1シリコン島、第2シリコン島、および第3シリコン島に照射されてもよい。例えば、基板が着色したポリイミドフィルムを含むとき、レーザビームは、500nm以上の波長を有することが好ましい。例えば、YAGの539nmまたは532nmを用いることができる。 The laser beam may irradiate the first silicon island, the second silicon island, and the third silicon island via the substrate. For example, when the substrate contains a colored polyimide film, the laser beam preferably has a wavelength of 500 nm or more. For example, YAG of 539 nm or 532 nm can be used.
 また、基板が透明なポリイミドフィルム(PI)を含むとき、レーザビームは、300nm以上500nm未満、さらに好ましくは400nm以上、500nm未満の波長を有することが好ましい。 Further, when the substrate contains a transparent polyimide film (PI), the laser beam preferably has a wavelength of 300 nm or more and less than 500 nm, more preferably 400 nm or more and less than 500 nm.
 YAGレーザの基本波(1064nm)でも、ポリシリコンを破壊することができる。ただし、可視光の場合、出力を弱めたレーザ光を照射した位置合わせができる(照射されている箇所を視認できる)のに対し、赤外線の場合は、同様のことを行うためには赤外線センサを使用しなければならない。例えば、可視光域だけでなく近赤外にも感度がある、CCDセンサまたはCMOSセンサを好適に用いることができる(ただし、確認画面は白黒画像となる)。 Polysilicon can be destroyed even with the fundamental wave (1064 nm) of the YAG laser. However, in the case of visible light, it is possible to align by irradiating a laser beam with reduced output (the illuminated part can be visually recognized), whereas in the case of infrared light, an infrared sensor is used to do the same. Must be used. For example, a CCD sensor or a CMOS sensor that is sensitive not only in the visible light region but also in the near infrared region can be preferably used (however, the confirmation screen is a black and white image).
 着色しているポリイミド(すなわち、透明でないポリイミド、典型的には茶色を呈する。)を介してレーザ光を照射する場合は、波長は500nm以上で、上限はYAGレーザの発振波長程度である。透明PIであれば、波長400nm程度の青紫色レーザや450nm程度の青色レーザも使用できる。PIなどの樹脂で形成された基板(樹脂基板)の紫外線の透過率は低いので、基板を介してのレーザ照射には、紫外線レーザは適さない。ただし、基板を介さないレーザ照射には、紫外線レーザの方がエネルギーが高いので好ましい。また、波長が短いほど、高精細な加工に好適である。 When irradiating a laser beam through a colored polyimide (that is, a non-transparent polyimide, typically exhibiting brown color), the wavelength is 500 nm or more, and the upper limit is about the oscillation wavelength of the YAG laser. If it is a transparent PI, a blue-violet laser having a wavelength of about 400 nm or a blue laser having a wavelength of about 450 nm can also be used. Since the transmittance of ultraviolet rays on a substrate (resin substrate) made of a resin such as PI is low, an ultraviolet laser is not suitable for laser irradiation through the substrate. However, for laser irradiation that does not pass through a substrate, an ultraviolet laser is preferable because it has a higher energy. Further, the shorter the wavelength, the more suitable for high-definition processing.
 図4A、図4B、図5A、図5Bを参照して、第1シリコン島20A、第2シリコン島20B、第2シリコン島20C1、20C2および第3シリコン島20Dなどとして用いられるシリコン島の大きさや形状について説明する。図4A、図4B、図5A、図5Bは、シリコン島と、シリコン島上に形成された配線22、26とを示す平面図であり、シリコン島の外形が分かりやすいように、シリコン島側(基板側)から見た図を示す。 With reference to FIGS. 4A, 4B, 5A, 5B, the size of the silicon islands used as the first silicon island 20A, the second silicon island 20B, the second silicon island 20C1, 20C2, the third silicon island 20D, and the like. The shape will be described. 4A, 4B, 5A, and 5B are plan views showing the silicon island and the wirings 22 and 26 formed on the silicon island, and the silicon island side (board) so that the outer shape of the silicon island can be easily understood. The figure seen from the side) is shown.
 図4Aに示すシリコン島20Eおよび図4Bに示すシリコン島20Fは、基板の法線方向からみたとき、配線22、26の幅方向にはみ出した部分Sc、Sdを有する。はみ出した部分を有すると、基板の上方からレーザビームを照射しても、はみ出した部分がレーザビームを吸収するので、配線を切断することができる。また、はみ出した部分が、鋭角を有していると、レーザビームを照射する際のアライメントが容易になるという利点が得られる。はみ出した部分の長さLx、Lyは、例えば、0.5μm以上1μm以下である。0.5μm未満だと、レーザビームを照射する装置に併設された可視光を用いた光学カメラにおいてシリコン島の識別が困難になる場合がある。また、シリコン島20Eの幅方向に直交する長さは、1μm以上2μm以下である。 The silicon island 20E shown in FIG. 4A and the silicon island 20F shown in FIG. 4B have portions Sc and Sd protruding in the width direction of the wirings 22 and 26 when viewed from the normal direction of the substrate. If the protruding portion is provided, even if the laser beam is irradiated from above the substrate, the protruding portion absorbs the laser beam, so that the wiring can be cut. Further, if the protruding portion has an acute angle, there is an advantage that alignment when irradiating the laser beam becomes easy. The lengths Lx and Ly of the protruding portion are, for example, 0.5 μm or more and 1 μm or less. If it is less than 0.5 μm, it may be difficult to identify silicon islands with an optical camera using visible light attached to a device that irradiates a laser beam. The length of the silicon island 20E orthogonal to the width direction is 1 μm or more and 2 μm or less.
 図5Aおよび図5Bに示す様に、例えば、走査線22の主線22Mからゲート電極TsGに向かって分岐している分岐線22B(図1参照)をシリコン島20Gまたは20Hで切断するようにしてもよい。分岐構造に対応して、シリコン島20Gまたは20Hを配置すれば、信号の入力方向に拘わらず、1か所(分岐構造)を切断するだけで、ゲート電極TsGへ信号で供給されないように出来る。配線からはみ出している部分(3ケ所)は、鋭角を有していることが好ましく、はみ出した部分の長さLx、Lyは、例えば、0.5μm以上1μm以下である。同様に、信号線26からソース電極TsSが分岐している部分(図1参照)をシリコン島20Gまたは20Hで切断するようにしてもよい。 As shown in FIGS. 5A and 5B, for example, the branch line 22B (see FIG. 1) branched from the main line 22M of the scanning line 22 toward the gate electrode TsG may be cut at the silicon island 20G or 20H. good. If the silicon islands 20G or 20H are arranged corresponding to the branch structure, the signal can be prevented from being supplied to the gate electrode TsG by cutting only one place (branch structure) regardless of the signal input direction. The portions (three locations) protruding from the wiring preferably have an acute angle, and the lengths Lx and Ly of the protruding portions are, for example, 0.5 μm or more and 1 μm or less. Similarly, the portion where the source electrode TsS branches from the signal line 26 (see FIG. 1) may be cut at the silicon island 20G or 20H.
 ここでは、OLED表示パネルを例に本発明による実施形態を説明したが、本発明はこれに限らず、例えば、無機LED表示パネル、多数の無機LED装置を配列したマイクロLED表示パネルにも適用できる。これらの表示パネルは、OLED表示パネルと同様に、走査線、信号線に加えて電源線を有するので、OLED表示パネルと同様に輝線欠陥を生じ得るが、本発明による実施形態を適用することによって、輝線欠陥を修復することができる。 Here, the embodiment according to the present invention has been described by taking an OLED display panel as an example, but the present invention is not limited to this, and can be applied to, for example, an inorganic LED display panel and a micro LED display panel in which a large number of inorganic LED devices are arranged. .. Similar to the OLED display panel, these display panels have a power supply line in addition to the scanning line and the signal line, so that a bright line defect can occur like the OLED display panel. , The emission line defect can be repaired.
 なお、液晶表示パネルは、OLED表示パネルのように電源線および駆動用TFTを有さず、スイッチング用TFTのドレイン電極が直接、画素電極に接続されている。液晶表示パネルにおいても、信号線に短絡不良(例えば共通電極との間)が発生した場合、輝点欠陥および/または輝線欠陥を生じ得る。このような場合でも、本発明を適用することによって、輝点欠陥および/または輝線欠陥を修復することができる。すなわち、図1に示したように、走査線とスイッチング用TFTのゲート電極との間において、走査線の分岐線と基板との間にシリコン島を形成する、および/または、信号線とスイッチング用TFTのソース電極との間において、信号線の分岐線と基板との間にシリコン島を形成すればよい。あるいは、図2に示したように、画素毎に信号線の主線と基板との間にシリコン島を形成してもよいし、スイッチング用TFTのドレイン電極と画素電極との間において、ドレイン電極と画素電極との間の配線と基板との間にシリコン島を形成してもよい。 The liquid crystal display panel does not have a power supply line and a driving TFT like the OLED display panel, and the drain electrode of the switching TFT is directly connected to the pixel electrode. Even in the liquid crystal display panel, when a short circuit defect (for example, between the signal line and the common electrode) occurs in the signal line, a bright spot defect and / or a bright line defect may occur. Even in such a case, the bright spot defect and / or the bright line defect can be repaired by applying the present invention. That is, as shown in FIG. 1, a silicon island is formed between the branch line of the scanning line and the substrate between the scanning line and the gate electrode of the switching TFT, and / or the signal line and the switching are used. A silicon island may be formed between the branch line of the signal line and the substrate between the source electrode of the TFT and the substrate. Alternatively, as shown in FIG. 2, a silicon island may be formed between the main line of the signal line and the substrate for each pixel, or a drain electrode may be formed between the drain electrode and the pixel electrode of the switching TFT. Silicon islands may be formed between the wiring between the pixel electrodes and the substrate.
 本発明は、アクティブマトリクス型表示パネルおよびそのような表示パネルを用いた表示装置の製造方法に用いることができる。 The present invention can be used in an active matrix type display panel and a method for manufacturing a display device using such a display panel.
  10   :基板  12   :ポリイミド膜  13   :無機絶縁層  14   :ポリイミド膜  15   :無機絶縁層  20A  :第1シリコン島  20B  :第2シリコン島(分岐線の下)  20C1、20C2 :第2シリコン島(主線の下)  20D  :第3シリコン島  20a、20b  :半導体層  21   :ゲート絶縁層  22   :走査線  23、25   :層間絶縁層  26   :信号線  28   :電源線  32   :画素電極(下部電極)  33   :バンク層  34   :有機層  36   :上部電極  100A、100B :OLED表示パネル  DF1  :短絡箇所  DF2  :短絡箇所  GD1  :ゲートドライバ  SD1  :ソースドライバ  Ts  :スイッチング用TFT  Te  :駆動用TFT
                                                                                                  
10: Substrate 12: Polygon film 13: Inorganic insulating layer 14: Polyethylene film 15: Inorganic insulating layer 20A: First silicon island 20B: Second silicon island (below the branch line) 20C1, 20C2: Second silicon island (main line) Bottom) 20D: Third silicon islands 20a, 20b: Semiconductor layer 21: Gate insulation layer 22: Scanning lines 23, 25: Thin film transistor insulation layer 26: Signal line 28: Power supply line 32: Pixel electrode (lower electrode) 33: Bank layer 34: Organic layer 36: Upper electrodes 100A, 100B: OLED display panel DF1: Short-circuited part DF2: Short-circuited part GD1: Gate driver SD1: Source driver Ts: Switching TFT Te: Driving TFT

Claims (23)

  1.  基板と、前記基板に支持された複数の画素電極と、前記複数の画素電極のそれぞれに1つずつ接続された複数のスイッチング用TFTとを有し、複数の画素毎に、前記画素電極と前記スイッチング用TFTとを有する表示パネルであって、前記表示パネルはさらに、
     複数の走査線であって、前記複数のスイッチング用TFTのそれぞれが、前記複数の走査線のいずれか1つに接続されている、複数の走査線と、
     複数の信号線であって、前記複数のスイッチング用TFTのそれぞれが、前記複数の信号線のいずれか1つに接続されている、複数の信号線と、
     前記複数の画素毎に、前記走査線と前記基板との間に形成された第1シリコン島および/または前記信号線と前記基板との間に形成された第2シリコン島とを有し、
     前記第1シリコン島は、前記基板の法線方向からみたとき、前記走査線の幅方向にはみ出した部分を有し、前記第2シリコン島は、前記基板の法線方向からみたとき、前記信号線の幅方向にはみ出した部分を有する、表示パネル。
    It has a substrate, a plurality of pixel electrodes supported by the substrate, and a plurality of switching TFTs connected to each of the plurality of pixel electrodes, and the pixel electrodes and the said are described for each of the plurality of pixels. A display panel having a switching TFT, the display panel further
    A plurality of scanning lines, each of which is connected to any one of the plurality of scanning lines, and a plurality of scanning lines.
    A plurality of signal lines, each of which is connected to any one of the plurality of signal lines, and a plurality of signal lines.
    Each of the plurality of pixels has a first silicon island formed between the scanning line and the substrate and / or a second silicon island formed between the signal line and the substrate.
    The first silicon island has a portion protruding in the width direction of the scanning line when viewed from the normal direction of the substrate, and the second silicon island has the signal when viewed from the normal direction of the substrate. A display panel that has a portion that protrudes in the width direction of the line.
  2.  前記走査線と前記スイッチング用TFTのゲート電極との間において、前記走査線の分岐線と前記基板との間に前記第1シリコン島を有する、請求項1に記載の表示パネル。 The display panel according to claim 1, wherein the first silicon island is provided between the scanning line and the gate electrode of the switching TFT, and between the branch line of the scanning line and the substrate.
  3.  前記信号線と前記スイッチング用TFTとの間において、前記信号線の分岐線と前記基板との間に前記第2シリコン島を有する、請求項1に記載の表示パネル。 The display panel according to claim 1, wherein the second silicon island is provided between the signal line and the switching TFT, and between the branch line of the signal line and the substrate.
  4.  前記複数の画素毎に、前記信号線の主線と前記基板との間に前記第2シリコン島を有する、請求項1に記載の表示パネル。 The display panel according to claim 1, wherein the second silicon island is provided between the main line of the signal line and the substrate for each of the plurality of pixels.
  5.  複数の電源線と複数の駆動用TFTとをさらに有し、
     前記複数の画素毎に、前記駆動用TFTのゲート電極は前記スイッチング用TFTのドレイン電極に接続されており、前記駆動用TFTのソース電極は前記電源線に接続されており、前記駆動用TFTのドレイン電極は前記画素電極に接続されており、
     前記駆動用TFTの前記ゲート電極と前記スイッチング用TFTの前記ドレイン電極とを接続する配線と前記基板との間に形成された第3シリコン島をさらに有する、請求項1から4のいずれかに記載の表示パネル。
    It also has a plurality of power supply lines and a plurality of driving TFTs.
    For each of the plurality of pixels, the gate electrode of the driving TFT is connected to the drain electrode of the switching TFT, the source electrode of the driving TFT is connected to the power supply line, and the driving TFT has. The drain electrode is connected to the pixel electrode and
    The invention according to any one of claims 1 to 4, further comprising a third silicon island formed between the wiring connecting the gate electrode of the driving TFT and the drain electrode of the switching TFT and the substrate. Display panel.
  6.  前記複数の画素毎に、前記スイッチング用TFTのドレイン電極と前記画素電極との間において、前記スイッチング用TFTの前記ドレイン電極と前記画素電極との間の配線と前記基板との間に第3シリコン島をさらに有する、請求項1から4のいずれかに記載の表示パネル。 For each of the plurality of pixels, between the drain electrode of the switching TFT and the pixel electrode, the third silicon between the wiring between the drain electrode and the pixel electrode of the switching TFT and the substrate. The display panel according to any one of claims 1 to 4, further comprising an island.
  7.  前記複数の走査線および/または前記複数の信号線は高融点金属で形成されている、請求項1から6のいずれかに記載の表示パネル。 The display panel according to any one of claims 1 to 6, wherein the plurality of scanning lines and / or the plurality of signal lines are made of a refractory metal.
  8.  前記第1シリコン島および/または前記第2シリコン島の厚さは、それぞれ独立に、10nm以上500nm以下である、請求項1から7のいずれかに記載の表示パネル。 The display panel according to any one of claims 1 to 7, wherein the thickness of the first silicon island and / or the second silicon island is independently 10 nm or more and 500 nm or less.
  9.  前記第1シリコン島または前記第2シリコン島の厚さをそれぞれ独立にTsiとし、前記第1シリコン島上の任意の走査線の厚さまたは前記第2シリコン島上の任意の信号線の厚さをそれぞれ独立にTrmとするとき、0.05≦Tsi/Trm≦1.0の関係を満足する、請求項1から8のいずれかに記載の表示パネル。 The thickness of the first silicon island or the second silicon island is independently set as Tsi, and the thickness of an arbitrary scanning line on the first silicon island or the thickness of an arbitrary signal line on the second silicon island is set as Tsi, respectively. The display panel according to any one of claims 1 to 8, which satisfies the relationship of 0.05 ≦ Tsi / Trm ≦ 1.0 when Trm is used independently.
  10.  前記第1シリコン島および/または前記第2シリコン島は、ポリシリコンで形成されている、請求項1から9のいずれかに記載の表示パネル。 The display panel according to any one of claims 1 to 9, wherein the first silicon island and / or the second silicon island is formed of polysilicon.
  11.  前記第1シリコン島および/または前記第2シリコン島は、アモルファスシリコンで形成されている、請求項1から9のいずれかに記載の表示パネル。 The display panel according to any one of claims 1 to 9, wherein the first silicon island and / or the second silicon island is made of amorphous silicon.
  12.  前記はみ出した部分は、鋭角を有している、請求項1から11のいずれかに記載の表示パネル。 The display panel according to any one of claims 1 to 11, wherein the protruding portion has an acute angle.
  13.  前記はみ出した部分の長さは、0.5μm以上1μm以下である、請求項1から12のいずれかに記載の表示パネル。 The display panel according to any one of claims 1 to 12, wherein the length of the protruding portion is 0.5 μm or more and 1 μm or less.
  14.  前記第1シリコン島および/または前記第2シリコン島の前記幅方向に直交する長さは、1μm以上2μm以下である、請求項1から13のいずれかに記載の表示パネル。 The display panel according to any one of claims 1 to 13, wherein the length of the first silicon island and / or the second silicon island orthogonal to the width direction is 1 μm or more and 2 μm or less.
  15.  前記基板は、ポリイミドフィルムを含む、請求項1から14のいずれかに記載の表示パネル。 The display panel according to any one of claims 1 to 14, wherein the substrate includes a polyimide film.
  16.  前記ポリイミドフィルムは着色している、請求項15に記載の表示パネル。 The display panel according to claim 15, wherein the polyimide film is colored.
  17.  請求項1から16のいずれかに記載の表示パネルを用意する工程Aと、
     前記複数の走査線または前記複数の信号線において短絡が発生している箇所を特定する工程Bと、
     前記短絡が発生している箇所を含む走査線または信号線の前記短絡が発生している箇所に最も近い前記第1シリコン島または前記第2シリコン島の少なくとも前記はみ出した部分にレーザビームを照射し、前記第1シリコン島または前記第2シリコン島を溶融させることによって、前記走査線または前記信号線を切断する工程Cと
    を包含する、表示装置の製造方法。
    A step of preparing the display panel according to any one of claims 1 to 16,
    Step B for identifying a location where a short circuit occurs in the plurality of scanning lines or the plurality of signal lines, and
    A laser beam is irradiated to at least the protruding portion of the first silicon island or the second silicon island closest to the location where the short circuit occurs in the scanning line or signal line including the location where the short circuit occurs. A method for manufacturing a display device, comprising the step C of cutting the scanning line or the signal line by melting the first silicon island or the second silicon island.
  18.  前記工程Aにおいて、請求項5に記載の前記表示パネルを用意し、
     前記工程Bにおいて、前記複数の信号線において前記複数の電源線のいずれかと短絡が発生している箇所を特定し、
     前記工程Cにおいて、前記短絡が発生している信号線の短絡箇所を挟む2つの前記第2シリコン島を溶融させることによって、前記信号線を切断する、請求項17に記載の表示装置の製造方法。
    In the step A, the display panel according to claim 5 is prepared.
    In the step B, a location where a short circuit occurs with any of the plurality of power supply lines in the plurality of signal lines is identified.
    The method for manufacturing a display device according to claim 17, wherein in the step C, the signal line is cut by melting the two second silicon islands sandwiching the short-circuited portion of the signal line in which the short circuit occurs. ..
  19.  前記工程Cにおいて、前記信号線の前記短絡箇所を介して前記電源線に接続されている画素の前記第3シリコン島を溶融させることによって、前記駆動用TFTの前記ゲート電極と前記スイッチング用TFTの前記ドレイン電極とを接続する前記配線を切断する、請求項18に記載に表示装置の製造方法。 In the step C, the gate electrode of the driving TFT and the switching TFT are formed by melting the third silicon island of the pixel connected to the power supply line through the short-circuited portion of the signal line. The method of manufacturing a display device according to claim 18, wherein the wiring connecting the drain electrode is cut.
  20.  前記工程Cにおいて、前記レーザビームは前記基板を介して、前記第1シリコン島または前記第2シリコン島に照射される、請求項17から19のいずれかに記載の表示装置の製造方法。 The method for manufacturing a display device according to any one of claims 17 to 19, wherein in the step C, the laser beam is irradiated to the first silicon island or the second silicon island via the substrate.
  21.  前記基板は、着色したポリイミドフィルムを含み、
     前記レーザビームは、500nm以上の波長を有する、請求項20に記載の表示装置の製造方法。
    The substrate contains a colored polyimide film.
    The method for manufacturing a display device according to claim 20, wherein the laser beam has a wavelength of 500 nm or more.
  22.  前記基板は、透明なポリイミドフィルムを含み、
     前記レーザビームは、300nm以上500nm未満の波長を有する、請求項20に記載の表示装置の製造方法。
    The substrate contains a transparent polyimide film.
    The method for manufacturing a display device according to claim 20, wherein the laser beam has a wavelength of 300 nm or more and less than 500 nm.
  23.  前記工程Aは、前記表示パネルとして、トップエミッション型の有機EL表示パネルを用意する工程である、請求項17から22のいずれかに記載の表示装置の製造方法。 The method for manufacturing a display device according to any one of claims 17 to 22, wherein the step A is a step of preparing a top emission type organic EL display panel as the display panel.
PCT/JP2020/005117 2020-02-10 2020-02-10 Display panel and method for producing display device WO2021161379A1 (en)

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