WO2021159601A1 - 一种显示面板 - Google Patents

一种显示面板 Download PDF

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Publication number
WO2021159601A1
WO2021159601A1 PCT/CN2020/085023 CN2020085023W WO2021159601A1 WO 2021159601 A1 WO2021159601 A1 WO 2021159601A1 CN 2020085023 W CN2020085023 W CN 2020085023W WO 2021159601 A1 WO2021159601 A1 WO 2021159601A1
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WO
WIPO (PCT)
Prior art keywords
layer
metal layer
display panel
active
overlap
Prior art date
Application number
PCT/CN2020/085023
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English (en)
French (fr)
Inventor
黄茜
Original Assignee
武汉华星光电半导体显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
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Application filed by 武汉华星光电半导体显示技术有限公司 filed Critical 武汉华星光电半导体显示技术有限公司
Priority to US16/966,163 priority Critical patent/US20210327922A1/en
Publication of WO2021159601A1 publication Critical patent/WO2021159601A1/zh

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/301—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements flexible foldable or roll-able electronic displays, e.g. thin LCD, OLED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/311—Flexible OLED
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10—Substrates, e.g. flexible substrates
    • H10K77/111—Flexible substrates

Definitions

  • the present invention relates to the field of display technology, and in particular to a display panel.
  • the active layer is used as the semiconductor device layer, and phosphorous or boron is doped at the same time as the wires in the circuit.
  • the traditionally designed active layer has a mesh structure, and this mesh structure is bending In the process, it is easy to cause the active layer to disconnect and cause poor display.
  • the traditionally designed active layer has a mesh structure, and this mesh structure is likely to cause the active layer to be disconnected during the bending process and cause technical problems of poor display.
  • the present application provides a display panel.
  • the display panel includes a base substrate and a film structure provided on the base substrate; the film structure includes active layers and laminates located on different layers. Connect the metal layer;
  • the active layer includes a plurality of active islands distributed in an array and arranged at intervals
  • the overlap metal layer includes a plurality of overlap wirings
  • two adjacent active islands pass through the overlap wirings Electric connection.
  • the film structure further includes:
  • a first gate insulating layer disposed on the base substrate and covering the active layer
  • a second gate insulating layer disposed on the first gate insulating layer and the first metal layer;
  • An interlayer dielectric layer disposed on the second metal layer and the second gate insulating layer;
  • Source and drain metal layers arranged on the interlayer dielectric layer are Source and drain metal layers arranged on the interlayer dielectric layer.
  • the overlap wiring and the first metal layer are provided in the same layer.
  • the overlap wiring and the second metal layer are provided in the same layer.
  • the overlapping wiring includes at least two connecting wires located in different layers, and all the connecting wires in each overlapping wiring are electrically connected.
  • connection line and one of the first metal layer, the second metal layer, and the source/drain metal layer are provided in the same layer.
  • the active island includes a body and connection terminals located on both longitudinal sides of the body and electrically connected to the body, and the lap wire is electrically connected to the connection terminal.
  • the first metal layer includes scan lines arranged in a lateral direction, and the projection of the overlap wiring on the base substrate is parallel to the scan line.
  • a trench is provided on the interlayer dielectric layer, an organic layer is provided in the trench, and the orthographic projection of the trench on the base substrate is at the same position as the active layer.
  • the orthographic projections on the base substrate do not overlap.
  • the trench includes a first trench and a second trench, and the first trench is located on the interlayer dielectric layer and corresponds to a gap between two adjacent rows of the active islands.
  • the second trench is located on the interlayer dielectric layer in an area corresponding to the gap between the active islands in two adjacent rows.
  • the present application also provides a display panel.
  • the display panel includes a base substrate and a film structure arranged on the base substrate; the base substrate is a single-layer or multi-layer structure, and The film structure includes active layers and bonding metal layers located in different layers;
  • the active layer includes a plurality of active islands distributed in an array and arranged at intervals
  • the overlap metal layer includes a plurality of overlap wirings
  • two adjacent active islands pass through the overlap wirings Electric connection.
  • the film structure further includes:
  • a first gate insulating layer disposed on the base substrate and covering the active layer
  • a second gate insulating layer disposed on the first gate insulating layer and the first metal layer;
  • An interlayer dielectric layer disposed on the second metal layer and the second gate insulating layer;
  • Source and drain metal layers arranged on the interlayer dielectric layer are Source and drain metal layers arranged on the interlayer dielectric layer.
  • the overlap wiring and the first metal layer are provided in the same layer.
  • the overlap wiring and the second metal layer are provided in the same layer.
  • the overlap wiring and the source-drain metal layer are provided in the same layer.
  • the overlapping wiring includes at least two connecting wires located in different layers, and all the connecting wires in each overlapping wiring are electrically connected.
  • connection line and one of the first metal layer, the second metal layer, and the source/drain metal layer are provided in the same layer.
  • the active island includes a body and connection terminals located on both longitudinal sides of the body and electrically connected to the body, and the lap wire is electrically connected to the connection terminal.
  • the first metal layer includes scan lines arranged in a lateral direction, and the projection of the overlap wiring on the base substrate is parallel to the scan line.
  • the meshed active layer is cut to form multiple independent active islands, and at the same time, electrical connections between different active traces are realized by overlapping traces located on different layers with the active layer, thereby realizing all the active traces.
  • the electrical connection between the source islands while trenching and filling the organic layer in the area of the interlayer dielectric layer that does not correspond to the active layer, so as to reduce the amount of bending during the process of ensuring that the active layer can work normally.
  • the bending stress on the source layer prevents poor display caused by disconnection of the active layer during the bending process.
  • FIG. 1 is a schematic diagram of the structure of the display panel when the overlap wiring and the first metal layer are arranged in the same layer in the present invention
  • FIG. 2 is a schematic diagram of the structure of the display panel when the overlap wiring and the second metal layer are arranged in the same layer in the present invention
  • FIG. 3 is a schematic diagram of the structure of the display panel when the overlap wiring and the source and drain metal layers are arranged in the same layer in the present invention
  • FIG. 4 is a schematic diagram of the first structure of the display panel when the overlapping wiring includes two connecting wires located in different layers in the present invention
  • FIG. 5 is a schematic diagram of the second structure of the display panel when the overlapping wiring includes two connecting wires located in different layers in the present invention
  • FIG. 6 is a schematic diagram of a third structure of the display panel when the overlap wiring includes two connecting lines located in different layers in the present invention.
  • FIG. 7 is a schematic diagram of the fourth structure of the display panel when the overlapping wiring includes two connecting wires located in different layers in the present invention.
  • FIG. 8 is a schematic diagram of a plane structure of a part of a film layer of a display panel in a specific embodiment of the present invention.
  • FIG. 9 is a schematic plan view of a partial film layer of a region corresponding to a sub-pixel on a display panel in a specific embodiment of the present invention.
  • 10 to 14 are schematic diagrams of the preparation steps of a part of the film layer in an embodiment of the present invention.
  • the present invention is aimed at the technical problem that the traditionally designed active layer in the existing display panel has a mesh structure, and this mesh structure is likely to cause the active layer to be disconnected during the bending process and cause the technical problem of poor display.
  • the present invention can solve the above-mentioned problems.
  • a display panel as shown in FIG. 1, the display panel includes a base substrate 11 and a film structure provided on the base substrate 11; the film structure includes active layers 13 located in different layers And overlap the metal layer.
  • the display panel may be a flexible OLED display panel;
  • the base substrate 11 may be a flexible glass substrate or a flexible transparent plastic substrate, etc., and the base substrate 11 may be a single-layer structure or a multilayer structure.
  • a laminated structure such as a substrate with at least two layers bonded by a transparent adhesive layer.
  • the active layer 13 includes a plurality of active islands 131 distributed in an array and arranged at intervals
  • the bonding metal layer includes a plurality of bonding wires 21, and two adjacent active islands 131 pass through the The overlapping wires 21 are electrically connected.
  • the display panel further includes a plurality of sub-pixels distributed in an array, and the active island 131 corresponds to the sub-pixels one-to-one.
  • the film structure further includes: a first gate insulating layer 14 disposed on the base substrate 11 and covering the active layer 13, and a first gate insulating layer 14 disposed on the first gate 1 insulating layer 14
  • Two metal layers 17, an interlayer dielectric layer 18 disposed on the second metal layer 17 and the second gate insulating layer 16 Two metal layers 17, an interlayer dielectric layer 18 disposed on the second metal layer 17 and the second gate insulating layer 16, and a source and drain metal layer 19 disposed on the interlayer dielectric layer 18 .
  • the display panel further includes a flat layer 23 disposed on the interlayer dielectric layer 18, a pixel definition layer 24 and an anode metal layer 25 disposed on the flat layer 23, and the flat layer 23 covers all The source and drain metal layer 19.
  • a buffer layer 12 may be further provided between the base substrate 11 and the active layer 13, the active layer 13 is provided on the buffer layer 12, and the buffer layer 12 may It is a single-layer or multi-layer structure.
  • the overlapping metal layer has a single-layer structure, that is, all the overlapping wires 21 are located on the same film layer.
  • the overlap wiring 21 and the first metal layer 15 may be provided in the same layer, and the overlap wiring 21 and the first metal layer 15 may be formed through the same process. In order to reduce the process and save production costs.
  • the overlap wiring 21 and the second metal layer 17 may be provided in the same layer, and the overlap wiring 21 and the second metal layer 17 may be formed through the same process.
  • the overlap wiring 21 and the source-drain metal layer 19 may be provided in the same layer, and the overlap wiring 21 and the second metal layer 17 may be formed through the same process.
  • the overlapping wiring 21 includes at least two connecting wires located in different layers, and all the connecting wires in each overlapping wiring 21 are electrically connected .
  • the electrical connection between adjacent active islands 131 is realized by arranging at least two connecting lines located in different layers. Under the premise of ensuring that the active layer 13 can work normally, it can prevent the overlap of the wiring 21 to other metals on the display panel. Wiring causes adverse effects.
  • the two connecting wires are located on different film layers; taking the overlapping wiring 21 including at least three connecting wires as an example, all The connecting lines may be located on different film layers, or one connecting line may be located on one film layer, and the remaining connecting lines may be located on another film layer, or they may be located on multiple film layers.
  • the connecting line is provided in the same layer as one of the first metal layer 15, the second metal layer 17, and the source-drain metal layer 19.
  • the two connecting lines are connected to the first metal layer 15 and the second metal layer 15, respectively.
  • Any two of the metal layer 17 and the source and drain metal layers 19 are arranged in the same layer; taking the overlap wiring 21 including at least three connecting lines as an example, they can be arranged simultaneously with the first metal layer 15, the second metal layer 17 and
  • the connection lines in the same layer of the source-drain metal layer 19 may also be provided only with the connection lines in the same layer as any two of the first metal layer 15, the second metal layer 17, and the source-drain metal layer 19.
  • the overlapping wiring 21 includes a first connecting wire 211 and a second connecting wire 212 located in different layers. .
  • the first connection line 211 may be provided in the same layer as the first metal layer 15, the second connection line 212 may be provided in the same layer as the source and drain metal layer 19, and the second connection line 212 may pass through the via hole. It is electrically connected to the first connecting line 211, thereby electrically connecting two adjacent active islands 131.
  • the first connection line 211 can also be provided in the same layer as the second metal layer 17, the second connection line 212 can be provided in the same layer as the source and drain metal layer 19, and the second connection line 212 is connected to the first through a via hole.
  • the line 211 is electrically connected, thereby electrically connecting two adjacent active islands 131.
  • FIGS. 4 to 7 only illustrate the case where the second connection line 212 and the source-drain metal layer 19 are arranged in the same layer.
  • the first connection line 211 and the second Under the premise that the connecting wires 212 are located in different layers, the second connecting wires 212 may also be arranged in the same layer as the first metal layer 15 or the second metal layer 17.
  • the connecting lines provided in the same layer as the first metal layer 15 may be formed in the same process as the first metal layer 15, and the connecting lines provided in the same layer as the second metal layer 17 may be formed in the same layer as the second metal layer.
  • the metal layer 17 is formed through the same process, and the connection lines provided in the same layer as the source-drain metal layer 19 can be formed through the same process as the source-drain metal layer 19.
  • the first connection line 211 and the second connection line 212 are both electrically connected to at least one active island 131 through a via hole.
  • the interlayer dielectric layer 18 is provided with a lap hole that penetrates the interlayer dielectric layer 18 and extends to the surface of the active island 131, so The lap hole is filled with a conductive material to form a third connection line 213 electrically connected to the first connection line 211 and the active island 131, and the first connection line 211 and the active island are realized by the third connection line 213.
  • the electrical connection of the island 131 is not limited to.
  • the lap hole may penetrate the first connection line 211, so that the electrical connection between the first connection line 211 and the active island 131 can be realized when the lap hole is filled with conductive material.
  • connection line 213 and the second connection line 212 can be formed in the same process to reduce production costs.
  • the interlayer dielectric layer 18 is provided with a trench 181, the trench 181 is filled with an organic layer 22, and the orthographic projection of the trench 181 on the base substrate 11 is compared with the active The orthographic projection of the layer 13 on the base substrate 11 does not overlap.
  • the trenches 181 are formed by trenching in the regions of the interlayer dielectric layer 18 that do not correspond to the active layer 13, so as to reduce the thickness of the regions where the interlayer dielectric layer 18 and the active layer 13 do not correspond to each other.
  • 181 is filled with a flexible organic material to form the organic layer 22, so that the organic layer 22 can relieve the stress during bending and ensure the bending performance of the display panel.
  • the trench 181 includes a first trench 1811 and a second trench 1812, and the first trench 1811 is located on the interlayer dielectric layer 18 and between two adjacent rows of the active islands 131 In the area corresponding to the gap of, the second trench 1812 is located on the interlayer dielectric layer 18 in the area corresponding to the gap between the active islands 131 in two adjacent rows.
  • first trench 1811 and the second trench 1812 intersect and communicate with each other, so as to ensure the bending performance of the area between the active islands 131.
  • the depth of the trench 181 may be less than the thickness of the interlayer dielectric layer 18, and the trench 181 may also penetrate the interlayer dielectric layer 18 and extend to the surface of the base substrate 11.
  • the active island 131 includes a main body 1311 and connection terminals 1312 located on both longitudinal sides of the main body 1311 and electrically connected to the main body 1311.
  • the lap wire 21 is connected to the main body 1311.
  • the connecting terminal 1312 is electrically connected.
  • the connecting terminal 1312 can be integrally formed with the main body 1311, and connected to the overlap wiring 21 through the connecting terminal 1312, so as to realize the electrical connection between the adjacent active islands 131, and the connecting terminal 1312 is located in the main body 1311.
  • the longitudinal side of the cable is convenient for the arrangement of the overlapping wires 21 and the connection with the active island 131.
  • FIGS. 8 and 9 only illustrate the situation in which one active island 131 includes two connection terminals 1312, and the two connection terminals 1312 are respectively located on the longitudinal sides of the main body 1311.
  • one active island 131 may also include three or more connection terminals 1312.
  • the projection of the overlap wiring 21 on the base substrate 11 is parallel to the scan line 152.
  • the overlapping wiring 21 is located between two adjacent bodies 1311 arranged in the longitudinal direction.
  • the overlap wiring 21 is a single-layer film layer
  • the overlap wiring 21 is arranged in the longitudinal direction; when the overlap wiring 21 includes multiple connection lines located in different layers, each connection line is along the horizontal direction. And all the connecting lines are located in the gap area between two adjacent bodies 1311 arranged in the longitudinal direction.
  • FIG. 10 to FIG. 14 are schematic diagrams of preparation steps of a part of the film layer on the base substrate 11 in an embodiment.
  • the active layer 13 is patterned to form a mesh-shaped active island 131.
  • the active islands 131 are separated from each other, and the formed active island 131 includes a body 1311 and two connecting terminals 1312 respectively located on the longitudinal sides of the main body 1311.
  • a first metal layer 15 is formed above the active layer 13, and the first metal layer 15 is patterned to form a first gate 151 and a scan line 152.
  • a second metal layer 17 is formed on the first metal layer 15, and the second metal layer 17 is patterned to form a first connection line 211.
  • the first connection line 211 is connected to each other through a via hole.
  • the connection terminal 1312 is electrically connected.
  • a trench 181 is formed at a predetermined position on the interlayer dielectric layer 18.
  • the trench 181 is formed on the base substrate 11
  • the orthographic projection does not coincide with the orthographic projection of the active layer 13 on the base substrate 11.
  • the trench 181 is filled with organic material to form the organic layer 22.
  • a source/drain metal layer 19 is formed on the interlayer insulating layer, and the source/drain layer is patterned to form source/drain 191, data line 192, high potential source line 193, reset
  • the line 194 and the second connection line 212, and the second connection line 212 is electrically connected to the first connection line 211 and the connection terminal 1312 through a via hole, so as to achieve electrical connection between two adjacent active islands 131.
  • the meshed active layer 13 is cut to form a plurality of independent active islands 131, and at the same time, the adjacent active islands 131 are formed by overlapping wires 21 located in different layers from the active layer 13
  • the electrical connection between the source islands 131 thereby realizing the electrical connection between all the active islands 131, and at the same time trenching and filling the organic layer 22 in the area of the interlayer dielectric layer 18 that does not correspond to the active layer 13
  • the active layer 13 can work normally, the bending stress of the active layer 13 during the bending process is reduced, the display failure caused by the broken line of the active layer 13 during the bending process is prevented, and the bending performance of the display panel is improved .

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
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Abstract

本发明提供一种显示面板，其中，所述显示面板包括衬底基板以及设置于所述衬底基板上且位于不同层别的有源层和搭接金属层；所述有源层包括多个阵列分布且间隔设置的有源岛，所述搭接金属层包括多条搭接走线，相邻两个所述有源岛通过所述搭接走线电连接。

Description

一种显示面板 技术领域
本发明涉及显示技术领域，尤其涉及一种显示面板。
 背景技术
在柔性弯折产品中，应力容易导致TFT器件受损失效，影响产品的正常显示。为了保障小的弯折半径，减小器件在弯折过程中器件受到的应力显得至关重要。
目前，显示面板的阵列基板中，有源层作为半导体器件层，同时掺杂磷或硼元素后作为电路中导线，传统设计的有源层呈网状结构，而这种网状结构在弯折过程中很容易造成有源层断线而引起显示不良。
 技术问题
现有的显示面板中，传统设计的有源层呈网状结构，而这种网状结构在弯折过程中很容易造成有源层断线而引起显示不良的技术问题。
 技术解决方案
第一方面，本申请提供一种显示面板，所述显示面板包括衬底基板以及设置于所述衬底基板上的膜层结构；所述膜层结构包括位于不同层别的有源层和搭接金属层；
其中，所述有源层包括多个阵列分布且间隔设置的有源岛，所述搭接金属层包括多条搭接走线，相邻两个所述有源岛通过所述搭接走线电连接。
在一些实施例中，所述膜层结构还包括：
设置于所述衬底基板上且覆盖所述有源层的第一栅极绝缘层；
设置于所述第一栅极绝缘层上的第一金属层；
设置于所述第一栅极绝缘层和所述第一金属层上的第二栅极绝缘层；
设置于所述第二栅极绝缘层上的第二金属层；
设置于所述第二金属层和所述第二栅极绝缘层上的层间介质层；
设置于所述层间介质层上的源漏金属层。
在一些实施例中，所述搭接走线与所述第一金属层同层设置。
在一些实施例中，所述搭接走线与所述第二金属层同层设置。
在一些实施例中，所述搭接走线与所述源漏金属层同层设置。
在一些实施例中，所述搭接走线包括至少两条位于不同层别的连接线，每一所述搭接走线中所有所述连接线电性连接。
在一些实施例中，所述连接线与所述第一金属层、所述第二金属层以及所述源漏金属层中的一者同层设置。
在一些实施例中，所述有源岛包括本体和位于所述本体的纵向两侧且与所述本体电连接的连接端子，所述搭接走线与所述连接端子电连接。
在一些实施例中，所述第一金属层包括沿横向设置的扫描线，所述搭接走线在所述衬底基板上的投影与所述扫描线平行。
在一些实施例中，所述层间介质层上设置有沟槽，所述沟槽中设置有有机层，所述沟槽在所述衬底基板上的正投影与所述有源层在所述衬底基板上的正投影不重合。
在一些实施例中，所述沟槽包括第一沟槽和第二沟槽，所述第一沟槽位于所述层间介质层上与相邻两列所述有源岛之间的间隙对应的区域处，所述第二沟槽位于所述层间介质层上与相邻两行所述有源岛之间的间隙对应的区域处。
第二方面，本申请还提供一种显示面板，所述显示面板包括衬底基板以及设置于所述衬底基板上的膜层结构；所述衬底基板为单层或多层结构，所述膜层结构包括位于不同层别的有源层和搭接金属层；
其中，所述有源层包括多个阵列分布且间隔设置的有源岛，所述搭接金属层包括多条搭接走线，相邻两个所述有源岛通过所述搭接走线电连接。
在一些实施例中，所述膜层结构还包括：
设置于所述衬底基板上且覆盖所述有源层的第一栅极绝缘层；
设置于所述第一栅极绝缘层上的第一金属层；
设置于所述第一栅极绝缘层和所述第一金属层上的第二栅极绝缘层；
设置于所述第二栅极绝缘层上的第二金属层；
设置于所述第二金属层和所述第二栅极绝缘层上的层间介质层；
设置于所述层间介质层上的源漏金属层。
在一些实施例中，所述搭接走线与所述第一金属层同层设置。
在一些实施例中，所述搭接走线与所述第二金属层同层设置。
在一些实施例中，所述搭接走线与所述源漏金属层同层设置。
在一些实施例中，所述搭接走线包括至少两条位于不同层别的连接线，每一所述搭接走线中所有所述连接线电性连接。
在一些实施例中，所述连接线与所述第一金属层、所述第二金属层以及所述源漏金属层中的一者同层设置。
在一些实施例中，所述有源岛包括本体和位于所述本体的纵向两侧且与所述本体电连接的连接端子，所述搭接走线与所述连接端子电连接。
在一些实施例中，所述第一金属层包括沿横向设置的扫描线，所述搭接走线在所述衬底基板上的投影与所述扫描线平行。
 有益效果
将网状的有源层切断以形成多个相互独立的有源岛，同时通过与有源层位于不同层别的搭接走线实现不同有源走线之间的电连接，从而实现所有有源岛之间的电连接，同时在层间介质层上与有源层未对应的区域处挖槽并填充有机层，从而在保证有源层可以正常工作的前提下，减少弯折过程中有源层受到的弯折应力，防止弯折过程中有源层断线引起的显示不良。
 附图说明
图1为本发明中搭接走线与第一金属层同层设置时显示面板的结构示意图；
图2为本发明中搭接走线与第二金属层同层设置时显示面板的结构示意图；
图3为本发明中搭接走线与源漏金属层同层设置时显示面板的结构示意图；
图4为本发明中搭接走线包括两条位于不同层别的连接线时显示面板的第一种结构示意图；
图5为本发明中搭接走线包括两条位于不同层别的连接线时显示面板的第二种结构示意图；
图6为本发明中搭接走线包括两条位于不同层别的连接线时显示面板的第三种结构示意图；
图7为本发明中搭接走线包括两条位于不同层别的连接线时显示面板的第四种结构示意图；
图8为本发明具体实施方式中显示面板的部分膜层的平面结构示意图；
图9为本发明具体实施方式中显示面板上与一个子像素对应的区域的部分膜层的平面结构示意图；
图10至图14为本发明一实施方式中部分膜层的制备步骤示意图。
附图标记：
11、衬底基板；12、缓冲层；13、有源层；131、有源岛；1311、本体；1312、连接端子；14、第一栅极绝缘层；15、第一金属层；151、栅极；152、扫描线；16、第二栅极绝缘层；17、第二金属层；18、层间介质层；181、沟槽；1811、第一沟槽；1812、第二沟槽；19、源漏金属层；191、源漏极；192、数据线；193、高电位源线；194、复位线；21、搭接走线；211、第一连接线；212、第二连接线；213、第三连接线；22、有机层；23、平坦层；24、像素定义层；25、阳极金属层。
 本发明的实施方式
为使本申请的目的、技术方案及效果更加清楚、明确，以下参照附图并举实施例对本申请进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
本发明针对现有的显示面板中，传统设计的有源层呈网状结构，而这种网状结构在弯折过程中很容易造成有源层断线而引起显示不良的技术问题。本发明可以解决上述问题。
一种显示面板，如图1所示，所述显示面板包括衬底基板11以及设置于所述衬底基板11上的膜层结构；所述膜层结构包括位于不同层别的有源层13和搭接金属层。
需要说明的是，所述显示面板可以为柔性OLED显示面板；所述衬底基板11为柔性玻璃基板或柔性透明塑料基板等，所述衬底基板11可以为单层结构，也可以为多层层叠设置的结构，如通过透明粘结层粘结的至少两层层叠设置的基板。
具体的，所述有源层13包括多个阵列分布且间隔设置的有源岛131，所述搭接金属层包括多条搭接走线21，相邻两个所述有源岛131通过所述搭接走线21电连接。
将网状的有源层13切断，使得有源岛131之间相互独立，同时通过与有源层13位于不同层别的搭接走线21实现相邻的有源岛131之间的电连接，从而实现所有有源岛131之间的电连接，从而保证有源层13在可以正常工作的前提下，减少弯折过程中有源层13受到的弯折应力，防止弯折过程中有源层13断线引起的显示不良。
需要说明的是，所述显示面板还包括多个阵列分布的子像素，所述有源岛131与所述子像素一一对应。
具体的，所述膜层结构还包括：设置于所述衬底基板11上且覆盖所述有源层13的第一栅极绝缘层14、设置于所述第一栅极1绝缘层14上的第一金属层15、设置于所述第一栅极绝缘层14和所述第一金属层15上的第二栅极绝缘层16、设置于所述第二栅极绝缘层16上的第二金属层17、设置于所述第二金属层17和所述第二栅极绝缘层16上的层间介质层18，以及，设置于所述层间介质层18上的源漏金属层19。
具体的，所述显示面板还包括设置于所述层间介质层18上的平坦层23以及设置于所述平坦层23上的像素定义层24和阳极金属层25，所述平坦层23覆盖所述源漏金属层19。
在一实施方式中，所述衬底基板11与所述有源层13之间还可以设置有缓冲层12，所述有源层13设置于所述缓冲层12上，所述缓冲层12可以为单层或多层结构。
在一实施方式中，所述搭接金属层为单层结构，即所有所述搭接走线21位于同一膜层。
其中，如图1所示，所述搭接走线21可以与所述第一金属层15同层设置，所述搭接走线21可以与所述第一金属层15通过同一道工序形成，以减少工序，节约生产成本。
如图2所示，所述搭接走线21可以与所述第二金属层17同层设置，所述搭接走线21可以与所述第二金属层17通过同一道工序形成。
如图3所示，所述搭接走线21可以与所述源漏金属层19同层设置，所述搭接走线21可以与所述第二金属层17通过同一道工序形成。
在另一实施方式中，如图4所示，所述搭接走线21包括至少两条位于不同层别的连接线，每一所述搭接走线21中所有所述连接线电性连接。
通过设置至少两条位于不同层别的连接线实现相邻有源岛131的电连接，在保证有源层13在可以正常工作的前提下，可以防止搭接走线21对显示面板上其他金属走线造成不良影响。
需要说明的是，以搭接走线21包括两条连接线为例，此时两条连接线分别位于不同的膜层上；以搭接走线21包括至少三条连接线为例，此时所有连接线可以均位于不同的膜层上，也可以一条连接线位于一层膜层上，其余的连接线均位于另一层膜层上，或分别位于多层膜层上。
具体的，所述连接线与所述第一金属层15、所述第二金属层17以及所述源漏金属层19中的一者同层设置。
需要说明的是，在至少两条连接线分别位于不同层别的前提下，以搭接走线21包括两条连接线为例，两条连接线分别与第一金属层15、所述第二金属层17以及所述源漏金属层19中的任意两者同层设置；以搭接走线21包括至少三条连接线为例，可以同时设置与第一金属层15、第二金属层17和源漏金属层19同层的连接线，也可以仅设置与第一金属层15、第二金属层17和源漏金属层19中的任意两者同层的连接线。
如图4至图7所示，以搭接走线21包括两条位于不同层别的连接线为例，所述搭接线包括位于不同层别的第一连接线211和第二连接线212。
在一实施方式中，参见图4，第一连接线211可以与第一金属层15同层设置，第二连接线212可以与源漏金属层19同层设置，第二连接线212通过过孔与第一连接线211电连接，从而将相邻两个所述有源岛131电连接。
参见图5，第一连接线211线还可以与第二金属层17同层设置，第二连接线212可以与源漏金属层19同层设置，第二连接线212通过过孔与第一连接线211电连接，从而将相邻两个所述有源岛131电连接。
需要说明的是，图4至图7中仅示意了第二连接线212与所述源漏金属层19同层设置的情况，实际实施中，在所述第一连接线211与所述第二连接线212位于不同层别的前提下，所述第二连接线212还可以与第一金属层15或第二金属层17同层设置。
具体的，与所述第一金属层15同层设置的连接线可以与第一金属层15通过同一道工序形成，与所述第二金属层17同层设置的连接线可以与所述第二金属层17通过同一道工序形成，与所述源漏金属层19同层设置的连接线可以与所述源漏金属层19通过同一道工序形成。
需要说明的是，与所述第一金属层15同层设置的连接线被所述第二栅极绝缘层16覆盖，与所述第二金属层17同层设置的连接线被所述层间介质层18覆盖，与所述源漏金属层19同层设置的连接线被所述平坦层23覆盖。
在一实施方式中，如图4和图5所示，所述第一连接线211和所述第二连接线212均通过过孔与至少一个有源岛131电连接。
在另一实施方式中，如图6和图7所示，所述层间介质层18上设置有贯穿所述层间介质层18且延伸至所述有源岛131表面的搭接孔，所述搭接孔中填充有导电材料以形成与所述第一连接线211和所述有源岛131电连接的第三连接线213，通过第三连接线213实现第一连接线211和有源岛131的电连接。
需要说明的是，所述搭接孔可以贯穿所述第一连接线211，从而在搭接孔中填充导电材料时即可实现第一连接线211与有源岛131的电连接。
需要说明的是，所述第三连接线213可以与所述第二连接线212可以通过同一道工序形成，以降低生产成本。
具体的，如图7和图8所示，所述第一金属层15包括栅极151以及多条沿横向设置的扫描线152，所述源漏金属层19包括源漏极191以及多条沿纵向设置的数据线192、高电位源线193和复位线194，多条扫描线152沿纵向间隔排布，多条数据线192沿横向间隔排布。
具体的，所述层间介质层18上设置有沟槽181，所述沟槽181中填充有有机层22，所述沟槽181在所述衬底基板11上的正投影与所述有源层13在所述衬底基板11上的正投影不重合。
通过在层间介质层18上与有源层13未对应的区域处进行挖槽以形成沟槽181，降低层间介质层18与有源层13未对应的区域处的厚度，并在沟槽181中填充柔韧性强的有机材料以形成有机层22，从而通过有机层22来舒缓弯折时的应力，保障显示面板的弯折性能。
进一步的，所述沟槽181包括第一沟槽1811和第二沟槽1812，所述第一沟槽1811位于所述层间介质层18上与相邻两列所述有源岛131之间的间隙对应的区域处，所述第二沟槽1812位于所述层间介质层18上与相邻两行所述有源岛131之间的间隙对应的区域处。
需要说明的是，第一沟槽1811与第二沟槽1812相互交叉并连通，从而保障有源岛131之间的区域的弯折性能。
需要说明的是，所述沟槽181的深度可以小于所述层间介质层18的厚度，所述沟槽181也可以贯穿层间介质层18并延伸至所述衬底基板11的表面。
参见图8和图9所示，所述有源岛131包括本体1311和位于所述本体1311的纵向两侧且与所述本体1311电连接的连接端子1312，所述搭接走线21与所述连接端子1312电连接。
需要说明的是，所述连接端子1312可以与本体1311一体成型，通过连接端子1312与搭接走线21连接，从而实现相邻有源岛131之间的电连接，同时连接端子1312位于本体1311的纵向侧，便于搭接走线21的排布和与有源岛131的连接。
需要说明的是，图8和图9中仅示意了一个有源岛131包括两个连接端子1312，并且两个连接端子1312分别位于本体1311的纵向两侧的情况，实际实施中，在所述本体1311的纵向两侧均设置有连接端子1312的前提下，一个有源岛131还可以包括三个或更多个连接端子1312。
具体的，所述搭接走线21在所述衬底基板11上的投影与所述扫描线152平行。
其中，所述搭接走线21位于沿纵向排布的两个相邻所述本体1311之间。
需要说明的是，一列有源岛131中，相邻两个本体1311之间存在间隙区域，通过将连接端子1312和搭接走线21均设置在间隙区域处，同时搭接走线21沿横向排布，从而便于搭接走线21的排布，防止搭接走线21对其他信号走线造成不良影响。
需要说明的，搭接走线21为单层膜层时，搭接走线21沿纵向排布；搭接走线21包括多条位于不同层别的连接线时，每条连接线均沿横向排布，并且所有连接线均位于沿纵向排布的两个相邻所述本体1311之间的间隙区域处。
参见图10至图14所示，图10至图14为一实施方式中衬底基板11上的部分膜层的制备步骤示意图。
如图10所示，形成有源层13后，对有源层13进行图案化处理，以形成网状的有源岛131，有源岛131之间相互隔断，形成的有源岛131包括本体1311和与分别位于本体1311纵向两侧的两个连接端子1312。
如图11所示，在所述有源层13的上方形成第一金属层15，并对所述第一金属层15进行图案化处理，以形成第一栅极151和扫描线152。
如图12所示，在第一金属层15的上方形成第二金属层17，并对第二金属层17进行图案化处理，以形成第一连接线211，第一连接线211通过过孔与连接端子1312电连接。
如图13所示，在第二金属层17上方形成层间介质层18后，在层间介质层18上的预设位置处形成沟槽181，沟槽181在所述衬底基板11上的正投影与所述有源层13在所述衬底基板11上的正投影不重合，形成沟槽181后，在沟槽181中填充有机材料以形成有机层22。
如图14所示，在层间绝缘层上形成源漏金属层19，并对所述源漏件层进行图案化处理，以形成源漏极191、数据线192、高电位源线193、复位线194以及第二连接线212，第二连接线212通过过孔与第一连接线211和连接端子1312电连接，以实现相邻两个有源岛131之间的电连接。
本发明的有益效果为：将网状的有源层13进行切断以形成多个相互独立的有源岛131，同时通过与有源层13位于不同层别的搭接走线21实现相邻有源岛131之间的电连接，从而实现所有有源岛131之间的电连接，同时在层间介质层18上与有源层13未对应的区域处挖槽并填充有机层22，从而在保证有源层13可以正常工作的前提下，减少弯折过程中有源层13受到的弯折应力，防止弯折过程中有源层13断线引起的显示不良，提升显示面板的弯折性能。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种显示面板，其中，所述显示面板包括衬底基板以及设置于所述衬底基板上的膜层结构；所述膜层结构包括位于不同层别的有源层和搭接金属层；
    其中，所述有源层包括多个阵列分布且间隔设置的有源岛，所述搭接金属层包括多条搭接走线，相邻两个所述有源岛通过所述搭接走线电连接。
  2. 根据权利要求1所述的显示面板，其中，所述膜层结构还包括：
    设置于所述衬底基板上且覆盖所述有源层的第一栅极绝缘层；
    设置于所述第一栅极绝缘层上的第一金属层；
    设置于所述第一栅极绝缘层和所述第一金属层上的第二栅极绝缘层；
    设置于所述第二栅极绝缘层上的第二金属层；
    设置于所述第二金属层和所述第二栅极绝缘层上的层间介质层；
    设置于所述层间介质层上的源漏金属层。
  3. 根据权利要求2所述的显示面板，其中，所述搭接走线与所述第一金属层同层设置。
  4. 根据权利要求2所述的显示面板，其中，所述搭接走线与所述第二金属层同层设置。
  5. 根据权利要求2所述的显示面板，其中，所述搭接走线与所述源漏金属层同层设置。
  6. 根据权利要求2所述的显示面板，其中，所述搭接走线包括至少两条位于不同层别的连接线，每一所述搭接走线中所有所述连接线电性连接。
  7. 根据权利要求6所述的显示面板，其中，所述连接线与所述第一金属层、所述第二金属层以及所述源漏金属层中的一者同层设置。
  8. 根据权利要求2所述的显示面板，其中，所述有源岛包括本体和位于所述本体的纵向两侧且与所述本体电连接的连接端子，所述搭接走线与所述连接端子电连接。
  9. 根据权利要求8所述的显示面板，其中，所述第一金属层包括沿横向设置的扫描线，所述搭接走线在所述衬底基板上的投影与所述扫描线平行。
  10. 根据权利要求1所述的显示面板，其中，所述层间介质层上设置有沟槽，所述沟槽中设置有有机层，所述沟槽在所述衬底基板上的正投影与所述有源层在所述衬底基板上的正投影不重合。
  11. 根据权利要求10所述的显示面板，其中，所述沟槽包括第一沟槽和第二沟槽，所述第一沟槽位于所述层间介质层上与相邻两列所述有源岛之间的间隙对应的区域处，所述第二沟槽位于所述层间介质层上与相邻两行所述有源岛之间的间隙对应的区域处。
  12. 一种显示面板，其中，所述显示面板包括衬底基板以及设置于所述衬底基板上的膜层结构；所述衬底基板为单层或多层结构，所述膜层结构包括位于不同层别的有源层和搭接金属层；
    其中，所述有源层包括多个阵列分布且间隔设置的有源岛，所述搭接金属层包括多条搭接走线，相邻两个所述有源岛通过所述搭接走线电连接。
  13. 根据权利要求12所述的显示面板，其中，所述膜层结构还包括：
    设置于所述衬底基板上且覆盖所述有源层的第一栅极绝缘层；
    设置于所述第一栅极绝缘层上的第一金属层；
    设置于所述第一栅极绝缘层和所述第一金属层上的第二栅极绝缘层；
    设置于所述第二栅极绝缘层上的第二金属层；
    设置于所述第二金属层和所述第二栅极绝缘层上的层间介质层；
    设置于所述层间介质层上的源漏金属层。
  14. 根据权利要求13所述的显示面板，其中，所述搭接走线与所述第一金属层同层设置。
  15. 根据权利要求13所述的显示面板，其中，所述搭接走线与所述第二金属层同层设置。
  16. 根据权利要求13所述的显示面板，其中，所述搭接走线与所述源漏金属层同层设置。
  17. 根据权利要求13所述的显示面板，其中，所述搭接走线包括至少两条位于不同层别的连接线，每一所述搭接走线中所有所述连接线电性连接。
  18. 根据权利要求17所述的显示面板，其中，所述连接线与所述第一金属层、所述第二金属层以及所述源漏金属层中的一者同层设置。
  19. 根据权利要求13所述的显示面板，其中，所述有源岛包括本体和位于所述本体的纵向两侧且与所述本体电连接的连接端子，所述搭接走线与所述连接端子电连接。
  20. 根据权利要求19所述的显示面板，其中，所述第一金属层包括沿横向设置的扫描线，所述搭接走线在所述衬底基板上的投影与所述扫描线平行。
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