WO2021147032A1 - 显示基板及其驱动方法、显示装置 - Google Patents

显示基板及其驱动方法、显示装置 Download PDF

Info

Publication number
WO2021147032A1
WO2021147032A1 PCT/CN2020/073902 CN2020073902W WO2021147032A1 WO 2021147032 A1 WO2021147032 A1 WO 2021147032A1 CN 2020073902 W CN2020073902 W CN 2020073902W WO 2021147032 A1 WO2021147032 A1 WO 2021147032A1
Authority
WO
WIPO (PCT)
Prior art keywords
display area
power supply
line
supply voltage
display
Prior art date
Application number
PCT/CN2020/073902
Other languages
English (en)
French (fr)
Inventor
吴超
黄炜赟
黄耀
孙开鹏
邱远游
王彬艳
程羽雕
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2020/073902 priority Critical patent/WO2021147032A1/zh
Priority to CN202080000059.4A priority patent/CN113498534B/zh
Publication of WO2021147032A1 publication Critical patent/WO2021147032A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element

Definitions

  • At least one embodiment of the present disclosure relates to a display substrate, a driving method thereof, and a display device.
  • display screens used in electronic devices are developing towards larger screens and full screens, so as to enable users to have a better visual experience.
  • these electronic devices need to incorporate components such as cameras and light sensors, and these components usually occupy the display area of the display screen, which makes it difficult to realize a full-screen design for the display screen.
  • At least one embodiment of the present disclosure provides a display substrate.
  • the display substrate includes a first display area, a second display area, a non-display area, a first power line, a second power line, at least one first data line, and at least one first data line. Two data lines.
  • the first display area includes a plurality of first pixels; the second display area includes a plurality of second pixels, and the pixel density of the second display area is less than the pixel density of the first display area; the non-display area at least partially surrounds the A first display area and the second display area; a first power supply line is connected to the first display area and configured to provide a first power supply voltage to the plurality of first pixels; a second power supply line is connected to the first display area Two display areas and configured to provide a second power supply voltage to the plurality of second pixels, the first power supply voltage and the second power supply voltage have the same polarity; at least one first data line is connected to the first data line A display area configured to provide a first data signal to the plurality of first pixels; at least one second data line is connected to the second display area and configured to provide a second data signal to the plurality of second pixels ; At least part of the second power cord is located in the non-display area and surrounds at least part of the first display area.
  • the first power supply voltage is different from the second power supply voltage.
  • the first power supply voltage is less than the second power supply voltage.
  • the first power supply voltage is the same as the second power supply voltage.
  • it further includes a third power line and a fourth power line;
  • the third power line is connected to the first display area and is configured to provide a third power voltage to the plurality of first pixels;
  • the fourth power line is connected to the second display Area and configured to provide a fourth power supply voltage to a plurality of second pixels;
  • the third power supply voltage and the first power supply voltage have opposite polarities, and the fourth power supply voltage and the second power supply voltage have In the opposite polarity, the fourth power supply voltage is less than or equal to the third power supply voltage.
  • the first data signal is a first data voltage
  • the second data signal is a second data voltage
  • the first display area surrounds at least a part of the second display area;
  • the display substrate further includes a base substrate, and the first power line and the second power line are disposed on the base substrate;
  • the first power cord and the second power cord are arranged in the same layer, and the orthographic projection of the first power cord on the base substrate and the orthographic projection of the second power cord on the base substrate The projections do not overlap;
  • the first power cord includes a first part
  • the second power cord includes a first part and a second part connected to each other, the first part of the first power cord is located in the first display area, the The first part of the second power line is located in the second display area, and the second part of the second power line is connected to the second display area through the non-display area and surrounds at least a part of the first display area.
  • the first display area surrounds at least part of the second display area; the first power line and the second power line are arranged in different layers, and the first power line and the second power line are different An insulating layer is provided therebetween to insulate the first power line and the second power line from each other; the first power line includes a first part, and the second power line includes a first part and a second part connected to each other, The first part of the first power cord is located in the first display area, and the first part of the second power cord is located in the second display area; the second part at least partially passes through the first display area. Connected to the second display area.
  • the first part of the second power line includes a plurality of first sub-wiring lines extending in a first direction and a plurality of second sub-wiring lines extending in a second direction;
  • the second part of the second power line It includes a third sub-line and a fourth sub-line extending along the second direction; the first direction and the second direction intersect; the third sub-line and the fourth sub-line respectively They are located on both sides of the second display area, and are respectively located on both sides of the first display area.
  • the third sub-line and the fourth sub-line are both a single line.
  • the display substrate further includes a gate driving circuit located in the non-display area, wherein at least one of the third sub-wiring and the fourth sub-wiring at least partially overlaps the gate driving circuit .
  • the display substrate further includes: at least one reset signal line connected to the second display area and configured to provide reset signals to the plurality of second pixels, wherein the second display area includes A wiring area between two second pixels, the pixel area includes the plurality of second pixels, at least part of the reset signal line and at least part of the second power line are located in the wiring area, In the second display area, at least a part of the extension direction of the second power line is the same as the extension direction of the reset signal line.
  • the reset signal line of the reset signal the first trace is located between the reset signal line and the second pixel, and the distance between the first trace and the reset signal line is larger than the first The distance between the trace and the second pixel.
  • the display substrate further includes a pad area located in the non-display area, wherein the third power line and the fourth power line are the same common power line, the first power line, the second power line
  • the line and the common power line respectively include a portion located in the pad area, and the portion of the first power line located in the pad area is located in the portion of the first power line located in the pad area and The common power line is located between the portions of the pad area.
  • the display substrate further includes: a first driving circuit configured to provide the first power supply voltage to the first power line; and a second driving circuit configured to provide the second power supply line to the second power line.
  • Power supply voltage, the first driving circuit and the second driving circuit work independently of each other.
  • the display substrate has a first side for display and a second side opposite to the first side, and the second display area includes: a light-transmitting display area and a surrounding display area; The light incident on the first side passes through the display substrate to reach the second side of the display substrate; a peripheral display area surrounds the light-transmitting display area, and the second pixel for driving the light-transmitting display area is provided ⁇ pixel circuit.
  • At least one embodiment of the present disclosure provides a display device, which includes any display substrate provided by the embodiments of the present disclosure.
  • At least one embodiment of the present disclosure provides a method for driving a display substrate, which is applied to the array substrate provided by an embodiment of the present disclosure.
  • the driving method includes: providing a first power source to the plurality of first pixels through the first power line Provide a second power supply voltage to the plurality of second pixels through the second power line; provide a first data signal to the plurality of first pixels through the first data line; through the second data Line to provide a second data signal to the plurality of second pixels; control the first power supply voltage, the second power supply voltage, the first data signal and the second data signal, so that the same display In the case of a picture, the display brightness of the first display area is substantially the same as the display brightness of the second display area.
  • the first power supply voltage is controlled to be different from the second power supply voltage, and the first data signal and the second data signal are not compensated for regional brightness.
  • the first power supply voltage is controlled to be the same as the second power supply voltage, and at least one of the first data signal and the second data signal is subject to regional brightness compensation.
  • the driving method further includes: providing a third power supply voltage to the plurality of first pixels;
  • a fourth power supply voltage is provided to the plurality of second pixels; wherein the third power supply voltage and the first power supply voltage have opposite polarities, and the fourth power supply voltage and the second power supply voltage have opposite polarities The polarity of the fourth power supply voltage is less than or equal to the third power supply voltage.
  • the first data signal is a first data voltage
  • the second data signal is a second data voltage
  • FIG. 1A is a schematic diagram of a display substrate provided by an embodiment of the present disclosure.
  • FIG. 1B is a schematic diagram of pixel distribution in the first display area and the second display area of the display substrate shown in FIG. 1A;
  • FIG. 2 is a partial schematic diagram of the pad area of the display substrate shown in FIG. 1A;
  • FIG. 3 is a schematic diagram of another display substrate provided by an embodiment of the present disclosure.
  • FIG. 4 is a schematic diagram of still another display substrate provided by an embodiment of the present disclosure.
  • Fig. 5A is a schematic cross-sectional view taken along the line B-B' in Fig. 1A;
  • Fig. 5B is another schematic cross-sectional view taken along the line B-B' in Fig. 1A;
  • Fig. 5C is a schematic cross-sectional view taken along the line C-C' in Fig. 4;
  • FIG. 6 is a schematic diagram of a pixel area and a wiring area in a second display area of a display substrate provided by at least one embodiment of the present disclosure
  • FIG. 7A is an equivalent circuit diagram of a pixel circuit of one sub-pixel of a first pixel and one sub-pixel of a second pixel in a display substrate provided by at least one embodiment of the present disclosure
  • FIG. 7B is a schematic structural diagram of the pixel circuit shown in FIG. 7A;
  • FIG. 8 is a partial schematic diagram of another pad area of a display substrate provided by an embodiment of the present disclosure.
  • FIG. 9 is a schematic diagram of still another display substrate provided by an embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram of a display device provided by an embodiment of the present disclosure.
  • the light-transmitting display area of the sensor such as image sensor, infrared sensor
  • the light-transmitting area of the display area is relatively large.
  • the light-transmitting display area can provide convenience for installing sensors and other components while realizing the display function.
  • the light-transmitting display area has a smaller light-emitting area and lower light-emitting brightness, so that the light-emitting brightness of the entire display screen is not uniform.
  • At least one embodiment of the present disclosure provides a display substrate.
  • the display substrate includes a first display area, a second display area, a non-display area, a first power line, a second power line, at least one first data line, and at least one first data line. Two data lines.
  • the first display area includes a plurality of first pixels; the second display area includes a plurality of second pixels, and the pixel density of the second display area is less than the pixel density of the first display area; the non-display area at least partially surrounds the A first display area and the second display area; a first power supply line is connected to the first display area and configured to provide a first power supply voltage to the plurality of first pixels; a second power supply line is connected to the first display area Two display areas and configured to provide a second power supply voltage to the plurality of second pixels, the first power supply voltage and the second power supply voltage have the same polarity; at least one first data line is connected to the first data line A display area configured to provide a first data signal to the plurality of first pixels; at least one second data line is connected to the second display area and configured to provide a second data signal to the plurality of second pixels
  • the first power supply voltage, the second power supply voltage, the first data signal and the second data signal are adjustable, so that the display brightness of the first display area in the case
  • FIG. 1A is a schematic diagram of a display substrate provided by an embodiment of the present disclosure
  • FIG. 1B is a schematic diagram of pixel distribution in the first display area and the second display area of the display substrate shown in FIG. 1A
  • FIG. 7A is At least one embodiment of the present disclosure provides an equivalent circuit diagram of a pixel circuit of one sub-pixel of a first pixel and one sub-pixel of a second pixel in a display substrate.
  • FIG. 7B is a schematic structural diagram of the pixel circuit shown in FIG. 7A.
  • the display substrate 12 includes a first display area 1, a second display area 2, a non-display area 3, a first power line 10, a second power line 20, a plurality of first data lines 600 and multiple second data lines.
  • the pixel circuit for driving one first pixel 11 and the pixel circuit for driving one second pixel 12 may both be as shown in FIG. 7A and FIG. 7B in structure, and this is only used as an example here. Therefore, in the pixel driving circuit of the second pixel, the position and structure of the second data line may refer to the position and structure of the first data line 600 shown in FIG. 7B.
  • the pixel circuit includes a gate layer 700, a first electrode plate 81 and a second electrode plate 82 of the storage capacitor C, and a semiconductor layer 300 stacked in layers.
  • the first electrode plate 81 and the gate layer 700 are arranged in the same layer, that is, the first electrode plate 81 and the gate layer 700 can be formed of the same material through the same patterning process.
  • the first plate 81 is integrally formed with the gate of the driving transistor T1 of the pixel circuit.
  • the first display area 1 surrounds a part of the second display area 2.
  • the first display area 1 includes a plurality of first pixels 11, the second display area 2 includes a plurality of second pixels 21, and the pixel density of the second display area 2 is less than that of the first display area 1. That is, the interval between adjacent second pixels is greater than the interval between adjacent first pixels.
  • the non-display area 3 surrounds the first display area 1 and the second display area 2; the first power supply line 10 is connected to the first display area 1 and is configured to provide the first power supply voltage to the plurality of first pixels 11; the second power supply line 20 It is connected to the second display area 2 and is configured to provide a second power supply voltage to the plurality of second pixels 21.
  • the first power supply voltage and the second power supply voltage have the same polarity, that is, the values of the first power supply voltage and the second power supply voltage are both positive.
  • a plurality of first data lines 600 are connected to the first display area 1 and configured to provide first data signals to the plurality of first pixels 11; a plurality of second data lines are connected to the second display area 2 and configured to provide first data signals to the plurality of first pixels 11;
  • the two pixels 21 provide a second data signal.
  • FIG. 7B takes the structure of a pixel circuit corresponding to one first pixel and one second pixel as an example.
  • a plurality of first pixels 11 are arranged in a first array, and the first array includes multiple rows of first pixels and multiple columns of first pixels.
  • Pixels; a plurality of second pixels 21 are arranged in a second array, the second array includes multiple rows of second pixels and multiple columns of second pixels.
  • a first data line 600 is provided corresponding to each row or column of first pixels; in the second display area 2, a first data line 600 is provided corresponding to each row or column of second pixels.
  • the first power supply voltage and the second power supply voltage are adjustable so that when the same screen is displayed respectively, the display brightness of the first display area 1 and the display brightness of the second display area 2 are basically the same, thereby increasing
  • the full-screen display device adopting the display substrate has the uniformity and consistency of the display brightness at each position of the screen.
  • the second display area 2 is provided with a sensor, such as an image sensor, an infrared sensor, a distance sensor, etc., and the sensor may be implemented in the form of a chip or the like, for example.
  • the display substrate 12 has a first side for display and a second side opposite to the first side, and the sensor is configured to receive light from the first side.
  • the second display area 2 includes a light-transmitting area. Since the pixel density in the second display area 2 is lower than the pixel density of the first display area 1, the area of the light-transmitting area of the second display area 2 is larger.
  • the second display area 1 not only realizes the display, but also provides convenience for the setting of the sensor, which is beneficial to increase the amount of light received by the sensor, thereby improving the working effect of the sensor.
  • the display substrate provided by the embodiment of the present disclosure avoids the low pixel density in the second display area from affecting the display brightness of the second display area.
  • At least part of the second power cord 20 is located in the non-display area and surrounds a portion of the first display area 1, so that when the second display area 2 is located near the edge of the first display area 1, it is convenient to connect the second power cord 20 to the first display area 1. In the second display area 2, at the same time, the signal via the second power line 20 does not interfere with the signal of the first power line 11 connected to the first display area 1.
  • the second display area 2 is located close to the edge of the display substrate 12, for example, located close to the middle of the edge of the display substrate 12.
  • the shape of the second display area 2 is a long strip.
  • the shape of the second display area 2 may also be an ellipse, a rectangle, etc., which is not limited in the embodiment of the present disclosure.
  • the first power supply voltage is different from the second power supply voltage, and the first data signal and the second data signal remain unchanged in the same display state, that is, the first data signal and the second data signal are not compensated for the area brightness.
  • the first data signal is a first data voltage
  • the second data signal is a second data voltage.
  • the pixel circuits of the first pixel 11 and the second pixel 21 are the same 7T1C circuit, and the pixel circuit structure of the two pixels may be the same.
  • the pixel circuit includes first to seventh transistors T1, T2, T3, T4, T5, T6, T7, and includes a storage capacitor C and a light emitting element L1.
  • the positions of the first to seventh transistors T1, T2, T3, T4, T5, T6, and T7 are shown in FIG. 7B.
  • the first transistor T1 is used as a driving transistor
  • the other second to sixth transistors are used as switching transistors.
  • the light-emitting element L1 may be various types of OLEDs, such as top-emission, bottom-emission, double-side emission, etc., which can emit red light, green light, blue light, or white light, which is not limited in the embodiments of the present disclosure.
  • the first transistor T1 works in the saturation region, which satisfies:
  • Id (1/2)* ⁇ *C ox *(W/L)*(V gs -V th ) 2 ⁇ (V data -VDD) 2 *C,
  • Id is the current flowing through the light-emitting element L1
  • VDD is the power supply voltage
  • VDD is the first power supply voltage
  • V data is the first data voltage
  • VDD is the second power supply voltage
  • V data is the second data voltage
  • the first power supply voltage is less than the second supply voltage, this time, in the case of holding a first display region V data 1 to V data and the second display area 2 is constant, i.e., does the first
  • the current flowing through the light-emitting element in the first display area 1 is less than the current flowing through the light-emitting element in the second display area 2, that is, the light-emitting element in the second display area 2 is increased
  • the luminous brightness of the second display area 2 is improved, so that when the pixel density of the second display area 2 is less than the pixel density of the first display area 1, when the same screen is displayed respectively, the first display
  • the display brightness of the area 1 and the display brightness of the second display area 2 are basically the same.
  • the display substrate 12 further includes: a third power line and a fourth power line.
  • the third power line is connected to the first display area 1 and is configured to provide a third power supply voltage to the plurality of first pixels 11;
  • the fourth power line is connected to the second display area and is configured to provide the first plurality of pixels 21 Four power supply voltage.
  • the third power line and the fourth power line are the same common power line 30.
  • the The common power line 30 is electrically connected to the common cathode of the OLED light-emitting element to provide the same power supply voltage for the plurality of first pixels 11 and the plurality of second pixels 21, which is less than the first power voltage and less than the second power voltage.
  • Fig. 5A is a schematic cross-sectional view taken along the line B-B' in Fig. 1A.
  • the display substrate 12 further includes a base substrate, and the first power line 10 and the second power line 20 are disposed on the base substrate. 1A and 5A, the first power line 10 and the second power line 20 are arranged in the same layer, and the orthographic projection of the first power line 10 on the base substrate and the second power line 20 on the base substrate The orthographic projections do not overlap, that is, the first power line and the second power line are spaced apart from each other to simplify the structure and manufacturing process of the array substrate 12.
  • the first power cord 10 includes a first part
  • the second power cord 20 includes a first part and a second part connected to each other.
  • the first part of the first power line 10 is located in the first display area 1, and the first part of the second power line 20 is located in the second display area 2.
  • the second part of the second power cord 20 is located in the non-display area 3 and surrounds a part of the first display area 1.
  • the first part of the second power line 20 includes a plurality of first sub-wiring lines 201 extending in the first direction and a plurality of second sub-wiring lines 202 extending in the second direction; the second part of the second power line 20 It includes a third sub-wiring 203 and a fourth sub-wiring 204 extending in the second direction.
  • the first direction and the second direction intersect, for example, the first direction and the second direction are perpendicular.
  • the first part of the first power line 10 includes a plurality of first sub-wirings 101 extending in a first direction and a plurality of second sub-wirings 102 extending in a second direction.
  • the plurality of first pixels 11 includes a plurality of rows of first pixels extending in a first direction and a plurality of columns of first pixels extending in a second direction;
  • the plurality of second pixels 21 includes a plurality of rows of second pixels extending in the first direction. Pixels and a plurality of columns of second pixels extending in the second direction.
  • reference numeral 7 represents a part of the pixel driving circuit in the first display area.
  • the first power line 10 and the second power line 20 can be arranged in the same layer as the data line 600 (the first data line and the second data line are located in the SD layer), and the first power line 10 and the second power line
  • the line 20 is made of the same material as the first data line and the second data line, and is formed by performing the same patterning on the same film layer.
  • the third sub-wiring 203 and the fourth sub-wiring 204 are located on both sides of the second display area 2, and the third sub-wiring 203 and the fourth sub-wiring 204 are respectively located in the first display area. Both sides of area 1.
  • the second part of the second power line 20 further includes a fifth sub-line 205 and a sixth sub-line 206 extending along the first direction and respectively connected to the third sub-line 203 and the fourth sub-line 204 , The fifth sub-line 205 and the sixth sub-line 206 further extend into the second display area 2 and are connected to the first part of the second power line 20.
  • FIG. 1A the third sub-wiring 203 and the fourth sub-wiring 204 are located on both sides of the second display area 2, and the third sub-wiring 203 and the fourth sub-wiring 204 are respectively located in the first display area.
  • the second part of the second power line 20 further includes a fifth sub-line 205 and a sixth sub-line 206 extending along the first direction and respectively connected
  • the fifth sub-wiring 205 and the sixth sub-wiring 206 are both located on the side of the second display area 2 away from the first display area 1.
  • the fifth sub-wiring 205 and the sixth sub-wiring 206 all extend into the second display area 2 from the non-display area 3 on the side of the second display area 2 away from the first display area.
  • the third sub-wiring 203 and the fourth sub-wiring 204 are both a single wiring, so as to facilitate the realization of a narrower frame and simplify the manufacturing process of the display substrate.
  • the third sub-wiring 203 and the fourth sub-wiring 204 may also include multiple parallel wirings, which is not limited in the present disclosure.
  • the third sub-line 203 and the fourth sub-line 204 are both straight lines.
  • the third sub-line 203 and the fourth sub-line 204 may also include curves.
  • first power line 10 and the second power line 20 in the same layer means that the first power line 10 and the second power line 20 are formed of the same material through the same patterning process at the same time, and are perpendicular to the substrate. In the direction of the base substrate, there is no other layer between the first power line 10 and the second power line 20.
  • the first power line 10 (FIG. 5B uses the first trace 101 of the first power line 10 as an example) and the second power line 20 (FIG. 5B uses the second power line
  • the third trace 203 of 20 as an example) can also be arranged in different layers.
  • the second power line 20 is located on the side of the first power line 10 away from the base substrate 100; in other implementations, the second power line 20 may also be located on the side of the first power line 10 close to the base substrate 100 .
  • the arrangement of the first power cord 10 and the second power cord 20 in different layers can also meet the different location requirements of the first power cord 10 and the second power cord 20, which will be introduced in the following embodiments.
  • the display substrate 12 further includes a gate driving circuit 6 (such as a GOA circuit) located in the non-display area 3.
  • a gate driving circuit 6 such as a GOA circuit located in the non-display area 3.
  • the gate driving circuit 6 is only located in the non-display area on the left side of FIG. 5A, and the third sub-wiring 203 at least partially overlaps the gate driving circuit 6; for example, the gate driving circuit 6 is only located in the right side of FIG. 5A.
  • the fourth sub-wiring 204 at least partially overlaps the gate drive circuit 6; for example, the non-display area on the right side and the non-display area on the left side in FIG. Both the wiring 203 and the fourth sub-wiring 204 at least partially overlap the gate driving circuit 6. It should be noted that at least one of the third sub-wiring 203 and the fourth sub-wiring 204 at least partially overlaps the gate driving circuit 6 means: at least one of the third sub-wiring 203 and the fourth sub-wiring 204 One of the orthographic projections on the base substrate at least partially overlaps with the orthographic projection of the gate drive circuit 6 on the base substrate.
  • At least one of the third sub-wiring 203 and the fourth sub-wiring 204 is on the substrate.
  • the orthographic projection on the substrate is located within the orthographic projection of the gate drive circuit 6 on the base substrate.
  • the orthographic projection of at least one of the third sub-wiring 203 and the fourth sub-wiring 204 on the base substrate is located inside the orthographic projection of the gate driving circuit 6 on the base substrate ( Near the side of the display area).
  • the structure of the gate driving circuit 6 is more complicated than the structure of the third sub-wiring 203 and the fourth sub-wiring 204, especially when the third sub-wiring 203 and the fourth sub-wiring are a single wiring, the third sub-wiring
  • the wiring 203 and the fourth sub-wiring 204 are arranged inside the gate driving circuit 6 to prevent the second power line from crossing the gate driving circuit 6 so as to ensure the manufacturing accuracy of the second power line and reduce manufacturing defects.
  • the third sub-wiring 203 and the fourth sub-wiring 204 start from the pad area and extend along the edge of the first display area 1.
  • the planar shape of the display substrate 12 is a rectangle
  • the second part of the second power line 20 has a first corner at the junction of the third sub-wiring 203 and the fifth sub-wiring 205
  • the second part of the second power line 20 has a second corner at the junction of the fourth sub-line 204 and the sixth sub-line 206, and the first corner and the second corner are located at two adjacent corners of the rectangle. At the top corner.
  • FIG. 6 is a schematic diagram of a pixel area and a wiring area in a second display area of a display substrate provided by at least one embodiment of the present disclosure.
  • the display substrate 12 further includes a plurality of reset signal lines 9.
  • the plurality of reset signal lines 9 are connected to the second display area 2 and are configured to provide reset signals to the plurality of second pixels 21.
  • the second display area 2 includes a wiring area 22 located between the plurality of second pixels 21, and a part of each reset signal line 9 and a part of the second power line 20 (for example, the first wiring 201) are located in the wiring area 22.
  • the extension direction of the first wiring 201 is the same as the extension direction of the reset signal line 9, for example, both extend along the first direction.
  • the first wiring 201 is located between the reset signal line 9 and the second pixel in the row. Between two pixels 21, and the distance L between the first wiring 201 and the reset signal line 9 is greater than the distance l between the first wiring 201 and the row of second pixels 21.
  • the reset signal is, for example, a reset voltage, and the polarity of the reset voltage is opposite to the second power supply voltage.
  • the line width of the first portion of the second power supply line 20 is 25 ⁇ m to 35 ⁇ m.
  • the first part of the second power line 20, for example, the distance between the first trace 201 and the reset signal line 9 is 45 ⁇ m to 55 ⁇ m ⁇ m
  • the first part of the second power line, for example, the distance between the first trace 201 and the second pixel 21 It is 10 ⁇ m ⁇ 20 ⁇ m.
  • the display substrate 12 further includes a pad area 4 located in the non-display area 3.
  • the first power supply line 10, the second power supply line 20, and the common power supply line 30 respectively include portions located in the pad area 4.
  • FIG. 2 is a partial schematic diagram of the pad area of the display substrate shown in FIG. 1A. As shown in FIG. 2, the portion of the second power line 20 located in the pad area 4 (for example, the portion of the third trace 203 of the second power line 20 located in the pad area 4) is located in the soldering area of the first power line 10.
  • the second wiring 102 is connected to the first display area 1 with a larger area and the third wiring 203 of the second power line 20 is wired in the non-display area 3.
  • the line width of the portion of the second power line 20 located in the pad area 4 has a line width of 150 ⁇ m to 250 ⁇ m ;
  • the portion of the second power line 20 located in the pad area 4 (for example, the portion of the third trace 203 of the second power line 20 located in the pad area 4) and the portion of the first power line 10 located in the pad area (
  • the distance between the portion of the second trace 102 of the first power line 10 located in the pad area 4) is 140 ⁇ m to 160 ⁇ m
  • the distance between the portion of the second trace 102 of the first power line 10 and the portion located in the pad area 4 is 140 ⁇ m. ⁇ 160 ⁇ m.
  • the structural features of the part located in the pad area 4 corresponding to the fourth wiring 204 are the same as those of the third wiring 203.
  • the overall planar pattern formed by the common power line 30, the second power line 20, and the first power line 10 located in the pad area 4 of FIG. 1A is symmetrical.
  • the overall planar pattern formed by the common power line 30, the second power line 20, and the first power line 10 located in the pad area 4 of FIG. 1A may not be bilaterally symmetrical.
  • the display substrate 12 also includes a circuit board, such as COF 5.
  • the COF5 is provided with a first driving circuit 51 and a second driving circuit 52; the first driving circuit 51 is configured to provide a first power supply voltage to the first power line 10; the second driving circuit 52 is configured to provide a second power line 20 The second power supply voltage.
  • the first driving circuit 51 and the second driving circuit 52 work independently of each other and do not interfere with each other to provide a first power voltage and a second power voltage that are different from each other.
  • the embodiment of the present disclosure does not limit the specific location of the circuit board, for example, it may be located in the pad area shown in FIG. 1A. It can be located on the first surface of the base substrate on which the first power line and the second power line are provided, or on the second surface of the base substrate opposite to the first surface. Those skilled in the art can refer to conventional techniques.
  • FIG. 3 is a schematic diagram of another display substrate provided by an embodiment of the present disclosure.
  • the display substrate shown in FIG. 3 has the following differences from the display substrate shown in FIG. 1A.
  • the second display area 2 is located at a corner of the planar shape of the display substrate 12 close to the edge position thereof.
  • the third sub-wiring 203 and the fourth sub-wiring 204 respectively extend from the non-display area 3 on the left side of the second display area 2 and the non-display area 3 on the upper side into the second display area 2.
  • the other features and corresponding technical effects of the display substrate shown in FIG. 3 are the same as those in FIG. 1A, please refer to the previous description, and will not be repeated here.
  • FIG. 4 is a schematic diagram of still another display substrate provided by an embodiment of the present disclosure.
  • the display substrate shown in FIG. 4 has the following differences from the display substrate shown in FIG. 1A.
  • the second display area 2 is located in the middle area of the planar shape of the display substrate 12, and the entire second display area 2 is surrounded by the first display area 1.
  • the third sub-wiring 203 and the fourth sub-wiring 204 respectively extend into the second display area 2 from opposite sides of the second display area 2 in the first direction, and the third sub-wiring 203 and the fourth sub-wiring
  • the line 204 passes through the first display area 1.
  • the first power line 10 and the second power line 20 may also be arranged in different layers.
  • Fig. 5C is a schematic cross-sectional view taken along the line C-C' in Fig. 4.
  • the first display area 1 is located in the middle area of the second display area 2, and the entire second display area 2 is surrounded by the first display area 1. Therefore, it extends from the surrounding non-display area 3 into the second display area 2.
  • the second power line such as the fifth wiring 205 and the sixth wiring 206 in FIG. 4, passes through the first display area 1, so that the fifth wiring 205 and the sixth wiring 206 intersect with the first power line 10. As shown in FIG.
  • the orthographic projection of the fifth trace 205 on the base substrate and the orthographic projection of the sixth trace 206 on the base substrate and the orthographic projection of the first power line 10 on the base substrate At least partially overlap.
  • the second power cord 20 may pass through the first display area 1 to be connected to the second display area 2.
  • the second display area 2 of the array substrate 12 can be used to realize functions such as an under-screen camera and under-screen fingerprint recognition.
  • the third sub-wiring 203 and the fourth sub-wiring 204 are respectively located on both sides of the second display area 2, that is, the third sub-wiring 203 and the fourth sub-wiring 204 are separated from the second display area.
  • the non-display areas 3 on both sides of the area 2 extend into the second display area 2.
  • the third sub-wiring 203 and the fourth sub-wiring 204 respectively extend into the second display area 2 from two sides of the second display area 2 opposite to each other in the first direction.
  • the third sub-wiring 203 and the fourth sub-wiring 204 are respectively located on both sides of the first display area 1.
  • the other features and corresponding technical effects of the display substrate shown in FIG. 4 are the same as those in FIG. 1A. Please refer to the previous description, which will not be repeated here.
  • the shape of the second display area 2 is a circle, an ellipse, a rectangle, an irregular pattern, etc., which is not limited in the embodiment of the present disclosure.
  • the specific position of the second display area 2 in the display substrate is also not limited.
  • the above-mentioned embodiments are all exemplary embodiments.
  • the first power supply voltage is the same as the second power supply voltage, and at least one of the first data signal and the second data signal is compensated for regional brightness.
  • the first data signal and the second data signal are the first data voltage and the second data voltage, respectively.
  • the value of the second data voltage is greater than the value of the first data voltage in the same display state.
  • the first data voltage is kept unchanged, and the value of the second data voltage is increased, so that the value of the second data voltage in the same display state is greater than the value of the first data voltage, so that the first display area 1
  • the display brightness of is the same as the display brightness of the second display area 2, that is, the second data signal is compensated by the area brightness.
  • the second data voltage may also be kept unchanged, and the first data voltage may be appropriately reduced, so that the value of the second data voltage in the same display state is greater than the value of the first data voltage, so that the value of the first display area 1
  • the display brightness is the same as the display brightness of the second display area 2, that is, the first data signal is compensated by the area brightness; or, the value of the second data voltage is increased while the value of the first data voltage is reduced, so that the second data voltage is increased in the same display state.
  • the value of the data voltage is greater than the value of the first data voltage, so that the display brightness of the first display area 1 is the same as the display brightness of the second display area 2, that is, both the first data signal and the second data signal are compensated by the area brightness. Therefore, this embodiment makes the display brightness of the first display area 1 the same as the display brightness of the second display area 2 under other conditions such as the aspect ratio of the driving transistor T1 and the reset signal unchanged.
  • the principle of this area brightness compensation is as follows.
  • the first transistor T1 in FIG. 7A works in the saturation region, which satisfies:
  • Id (1/2)* ⁇ *C ox *(W/L)*(V gs -V th ) 2 ⁇ (V data -VDD) 2 *C,
  • Id is the current flowing through the light-emitting element L1
  • VDD is the power supply voltage
  • VDD is the first power supply voltage
  • V data is the first data voltage
  • VDD is the second power supply voltage
  • V data is the second data voltage
  • the second data voltage when the same screen is displayed, under the condition that the first power supply voltage is equal to the second power supply voltage, the second data voltage can be increased to make the second data voltage greater than the first data voltage, so that the second light emitting The current flowing through the light emitting element in the area 2 is greater than the current flowing through the light emitting element in the first light emitting area 1, so that the display brightness of the first display area 1 and the display brightness of the second display area 2 are basically the same.
  • the fourth power supply voltage is equal to the third power supply voltage and is the common power supply voltage VSS.
  • the common power supply voltage has an opposite polarity to the first power supply voltage, and has an opposite polarity to the second power supply voltage.
  • the common power supply voltage VSS of this embodiment is smaller. Because when the TFT works in the linear region, it satisfies: Vds ⁇ Vgs-Vth, and when the TFT works in the saturation region, it satisfies: Vds>Vgs-Vth.
  • VDD-VSS Vds(DTFT)+V EL ,
  • Vds is the source and drain voltage of the driving transistor T1
  • V EL is the voltage on the light-emitting element. Therefore, in this embodiment, VSS is reduced to increase Vds (DTFT), so that the driving transistor T1 can quickly enter the saturation region.
  • the adjustment of the second data voltage in this embodiment can be achieved by changing the data voltage control circuit connected to the data line 600 shown in FIGS. 7A and 7B to achieve the above effect.
  • the specific adjustment value and amplitude of the second data voltage can be obtained by those skilled in the art through testing and modulation according to actual requirements.
  • FIG. 8 is a partial schematic diagram of the pad area of the display substrate provided by this embodiment.
  • a driving circuit 50 is provided on the COF 5, and the same driving circuit 50 is configured to provide a first power supply voltage to the first power supply line 10 and a second power supply voltage to the second power supply line 20 .
  • FIG. 9 is a schematic diagram of still another display substrate provided by an embodiment of the present disclosure.
  • the second display area 2 includes: a light-transmitting display area 200 and a peripheral display area 2000.
  • the light-transmitting display area 200 allows light incident from the first side of the display substrate, that is, the display side, to pass through the display substrate and reach the back side of the display substrate.
  • the above-mentioned sensor can be arranged in the light-transmitting display area, which is beneficial to increase the amount of light incident to the sensor, so as to improve the working effect of the sensor.
  • the peripheral display area 2000 surrounds the light-transmitting display area 200 and is provided with a pixel circuit for driving the second pixels 21 of the light-transmitting display area 200. That is, the pixel circuit used to drive the second pixel in the light-transmitting display area 200, such as the pixel circuit shown in FIGS. 7A and 7B, is arranged in the peripheral display area 2000 but not in the light-transmitting display area 200.
  • the display area 200 is provided with the light-emitting element of the second pixel, and the second power supply line of the pixel circuit for driving the second pixel in the light-transmitting display area 200 arranged in the peripheral display area 2000 extends from the peripheral display area 2000 into The light-transmitting display area 200 is thereby connected to the light-emitting elements in the light-transmitting display area 200.
  • the transparent display area 200 may have various shapes such as a circle (as shown in FIG. 9), a rectangle, a triangle, etc.
  • the embodiment of the present disclosure does not make any difference to the shape of the transparent display area 200. limited.
  • each of the plurality of first pixels 11 has a first center
  • each of the plurality of second pixels 21 has a second center
  • in the first direction a plurality of The distance between the first centers of two adjacent first pixels 11 in the first pixel 11 is smaller than the distance between the second centers of two adjacent second pixels 21 in the plurality of second pixels 21
  • in the second direction The pitch between the first centers of two adjacent first pixels 11 among the plurality of first pixels 11 is smaller than the pitch between the second centers of two adjacent second pixels 21 among the plurality of second pixels 21.
  • the distance between the first centers of two adjacent second pixels 21 in the plurality of second pixels 21 is the first center of the adjacent two first pixels 11 in the plurality of first pixels 11
  • the distance between the second centers of adjacent two second pixels 21 among the plurality of second pixels 21 is an integer multiple of the distance between the centers, such as 2 times;
  • the distance between the first centers of the two first pixels 11 is an integer multiple of, for example, 2 times.
  • it is not limited to 2 times, but can also be 3 times, 4 times, etc., and the company does not limit this.
  • FIG. 10 is a schematic diagram of a display device provided by an embodiment of the present disclosure.
  • the display device 120 provided by the embodiment of the present disclosure includes any display substrate 12 provided by the embodiment of the present disclosure.
  • the display device may be an electroluminescent display device, such as an OLED display device.
  • the display device is a mobile phone, a tablet computer, a display, and so on.
  • a sensor is provided in the second display area, which can be used to realize functions such as an off-screen camera, an under-screen camera, and under-screen fingerprint recognition.
  • At least one embodiment of the present disclosure further provides a method for driving a display substrate, which is applied to the array substrate provided by an embodiment of the present disclosure.
  • the driving method includes: providing first pixels to the plurality of first pixels through the first power line. Power supply voltage; provide a second power supply voltage to the plurality of second pixels through the second power line; provide a first data signal to the plurality of first pixels through the first data line; The data line provides a second data signal to the plurality of second pixels; controls the first power supply voltage, the second power supply voltage, the first data signal, and the second data signal so that the In the case of the same screen, the display brightness of the first display area is substantially the same as the display brightness of the second display area.
  • the first power supply voltage is controlled to be different from the second power supply voltage, and the first data signal and the second data signal are not compensated for regional brightness, that is, the first data signal and the second data signal are maintained in the same display state.
  • the first data signal is a first data voltage
  • the second data signal is a second data voltage.
  • the first power supply voltage is controlled to be less than the second power supply voltage, so that the display brightness of the first display area 1 and the display brightness of the second display area 2 are substantially the same.
  • the driving method can be applied to the embodiments shown in FIGS. 1A-4.
  • the first transistor T1 works in the saturation region, which satisfies:
  • Id (1/2)* ⁇ *C ox *(W/L)*(V gs -V th ) 2 ⁇ (V data -VDD) 2 *C,
  • Id is the current flowing through the light-emitting element L1
  • VDD is the power supply voltage
  • VDD is the first power supply voltage
  • V data is the first data voltage
  • VDD is the second power supply voltage
  • V data is the second data voltage
  • the first power supply voltage is less than the second supply voltage, this time, in the case of holding a first display region V data 1 to V data and the second display area 2 is constant, i.e., does the first
  • the current flowing through the light-emitting element in the first display area 1 is less than the current flowing through the light-emitting element in the second display area 2, that is, the light-emitting element in the second display area 2 is increased
  • the luminous brightness of the second display area 2 is improved, so that when the pixel density of the second display area 2 is less than the pixel density of the first display area 1, when the same screen is displayed respectively, the first display
  • the display brightness of the area 1 and the display brightness of the second display area 2 are basically the same.
  • the first power supply voltage is controlled to be the same as the second power supply voltage, and at least one of the first data signal and the second data signal is not compensated for regional brightness.
  • the first data signal and the second data signal are the first data voltage and the second data voltage, respectively.
  • the value of the second data voltage is greater than the value of the first data voltage in the same display state.
  • the first data voltage is kept unchanged, and the value of the second data voltage is increased, so that the value of the second data voltage in the same display state is greater than the value of the first data voltage, so that the first display area 1
  • the display brightness of is the same as the display brightness of the second display area 2, that is, the second data signal is compensated by the area brightness.
  • the second data voltage can also be kept unchanged, and the first data voltage can be appropriately reduced, so that the value of the second data voltage in the same display state is greater than the value of the first data voltage, so that the value of the first display area 1
  • the display brightness is the same as the display brightness of the second display area 2, that is, the first data signal is compensated by the area brightness;
  • the value of the data voltage is greater than the value of the first data voltage, so that the display brightness of the first display area 1 is the same as the display brightness of the second display area 2, that is, the first data signal and the second data signal are both subject to area brightness compensation.
  • the principle of this area brightness compensation is as follows.
  • the first transistor T1 in FIG. 7A works in the saturation region, which satisfies:
  • Id (1/2)* ⁇ *C ox *(W/L)*(V gs -V th ) 2 ⁇ (V data -VDD) 2 *C,
  • Id is the current flowing through the light-emitting element L1
  • VDD is the power supply voltage
  • VDD is the first power supply voltage
  • V data is the first data voltage
  • VDD is the second power supply voltage
  • V data is the second data voltage
  • the second data voltage when the same screen is displayed, under the condition that the first power supply voltage is equal to the second power supply voltage, the second data voltage can be increased to make the second data voltage greater than the first data voltage, so that the second light emitting The current flowing through the light emitting element in the area 2 is greater than the current flowing through the light emitting element in the first light emitting area 1, so that the display brightness of the first display area 1 and the display brightness of the second display area 2 are basically the same.
  • the driving method can be applied to the embodiment corresponding to FIG. 8.
  • the driving method provided in this embodiment further includes: providing a third power voltage to the plurality of first pixels; providing a fourth power voltage to the plurality of second pixels; the third power voltage and the first power voltage have opposite polarities, and the first The fourth power supply voltage and the second power supply voltage have opposite polarities, and the fourth power supply voltage is less than or equal to the third power supply voltage.
  • the third power supply voltage is provided to the plurality of first pixels through the third power supply line
  • the fourth power supply voltage is provided to the plurality of second pixels through the fourth power supply line.
  • the third power line and the fourth power line are the same common power line 30, and the fourth power voltage is equal to the third power voltage and is the common power voltage VSS.
  • the common power supply voltage VSS is smaller. Because when the TFT works in the linear region, it satisfies: Vds ⁇ Vgs-Vth, and when it works in the saturation region, it satisfies: Vds>Vgs-Vth. 7A, for the driving transistor T1 in the second display area 2, because Vdata is increased in this method, Vgs is increased, and Vds needs to be increased to make the driving transistor T1 quickly enter the saturation region; and because according to the figure
  • the 7A pixel circuit shows that:
  • VDD-VSS Vds(DTFT)+V EL ,
  • Vds is the source and drain voltage of the driving transistor T1
  • V EL is the voltage on the light-emitting element. Therefore, in this embodiment, VSS is reduced to increase Vds (DTFT), so that the driving transistor T1 can quickly enter the saturation region.
  • the adjustment of the second data voltage in this embodiment can be achieved by changing the data voltage control circuit connected to the data line 600 shown in FIGS. 7A and 7B to achieve the above effect.
  • the specific adjusted value can be obtained by those skilled in the art through testing and modulation according to actual needs.

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种显示基板及其驱动方法、显示装置，该显示基板包括第一显示区域、第二显示区域、非显示区域、第一电源线、第二电源线、第一数据线和第二数据线。第一显示区域包括多个第一像素；第二显示区域包括多个第二像素，第一像素的密度小于第二像素的密度；第一电源线配置为向第一像素提供第一电源电压；第二电源线配置为向第二像素提供第二电源电压，第一电源电压与第二电源电压极性相同；第一数据线配置为向多个第一像素提供第一数据信号；第二数据线配置为向多个第二像素提供第二数据信号；第一电源电压、第二电源电压、第一数据信号和第二数据信号可调，以使得在分别显示相同画面的情形下第一显示区域的显示亮度与第二显示区域的显示亮度基本相同。

Description

显示基板及其驱动方法、显示装置 技术领域
本公开至少一实施例涉及一种显示基板及其驱动方法、显示装置。
背景技术
目前，用于电子装置的显示屏正往大屏化、全屏化方向发展，以使用户具有更好的视觉体验。以手机、平板电脑等电子产品为例，由于这些电子装置需要结合摄像头、光线传感器等部件，而这些部件通常占据显示屏的显示区，由此导致显示屏难以实现全屏化设计。
发明内容
本公开至少一实施例提供一种显示基板，该显示基板包括第一显示区域、第二显示区域、非显示区域、第一电源线、第二电源线、至少一条第一数据线和至少一条第二数据线。第一显示区域包括多个第一像素；第二显示区域包括多个第二像素，所述第二显示区域的像素密度小于所述第一显示区域的像素密度；非显示区域至少部分围绕所述第一显示区域和所述第二显示区域；第一电源线连接到所述第一显示区域且配置为向所述多个第一像素提供第一电源电压；第二电源线连接到所述第二显示区域且配置为向所述多个第二像素提供第二电源电压，所述第一电源电压与所述第二电源电压具有相同的极性；至少一条第一数据线连接到所述第一显示区域且配置为向所述多个第一像素提供第一数据信号；至少一条第二数据线连接到所述第二显示区域且配置为向所述多个第二像素提供第二数据信号；所述第二电源线的至少部分位于所述非显示区域且围绕至少部分所述第一显示区域。
例如，所述第一电源电压不同于所述第二电源电压。
例如，所述第一电源电压小于所述第二电源电压。
例如，所述第一电源电压与所述第二电源电压相同。
例如，还包括第三电源线和第四电源线；第三电源线连接到第一显示区 域且配置为向所述多个第一像素提供第三电源电压；第四电源线连接到第二显示区域，且配置为向多个第二像素提供第四电源电压；所述第三电源电压与所述第一电源电压具有相反的极性，所述第四电源电压与所述第二电源电压具有相反的极性，所述第四电源电压小于等于所述第三电源电压。
例如，述第一数据信号为第一数据电压，所述第二数据信号为第二数据电压。
例如，所述第一显示区域围绕至少部分所述第二显示区域；所述显示基板还包括衬底基板，所述第一电源线和所述第二电源线设置于所述衬底基板上；所述第一电源线和所述第二电源线同层设置，且所述第一电源线在所述衬底基板上的正投影和所述第二电源线在所述衬底基板上的正投影不重叠；所述第一电源线包括第一部分，所述第二电源线包括彼此连接的第一部分和第二部分，所述第一电源线的第一部分位于所述第一显示区，所述第二电源线的第一部分位于所述第二显示区域，所述第二电源线的第二部分经所述非显示区域连接到所述第二显示区域且围绕至少部分所述第一显示区域。
例如，所述第一显示区域围绕至少部分所述第二显示区域；所述第一电源线和所述第二电源线异层设置，且所述第一电源线和所述第二电源线之间设置有绝缘层以使所述第一电源线和所述第二电源线彼此绝缘；所述第一电源线包括第一部分，所述第二电源线包括彼此连接的第一部分和第二部分，所述第一电源线的第一部分位于所述第一显示区，所述第二电源线的第一部分位于所述第二显示区域；所述第二部分至少部分穿过所示第一显示区域而连接到所述第二显示区域。
例如，所述第二电源线的第一部分包括沿第一方向延伸的多条第一子走线和沿第二方向延伸的多条第二子走线；所述第二电源线的第二部分包括沿所述第二方向延伸的第三子走线和第四子走线；所述第一方向和所述第二方向相交；所述第三子走线和所述第四子走线分别位于所述第二显示区域的两侧，且分别位于所述第一显示区域的两侧。
例如，所述第三子走线和所述第四子走线均为单条走线。
例如，显示基板还包括位于所述非显示区域的栅极驱动电路，其中，所述第三子走线和所述第四子走线中的至少之一与所述栅极驱动电路至少部分 重叠。
例如，显示基板还包括：至少一条复位信号线，连接到所述第二显示区域，且配置为向所述多个第二像素提供复位信号，其中，所述第二显示区包括位于所述多个第二像素之间的走线区，所述像素区包括所述多个第二像素，所述复位信号线的至少部分和所述第二电源线的至少部分位于所述走线区，在所述第二显示区域中，所述第二电源线的至少部分的延伸方向与所述复位信号线的延伸方向相同，对于给同第二像素分别提供第二电源电压的所述第二电源线的至少部分和复位信号的所述复位信号线，该第一走线位于该复位信号线与该第二像素之间，且该第一走线与该复位信号线之间的间距大于该第一走线与该第二像素之间的间距。
例如，显示基板还包括位于所述非显示区的焊盘区，其中，所述第三电源线和所述第四电源线为同一公共电源线，所述第一电源线、所述第二电源线和所述公共电源线分别包括位于所述焊盘区的部分，所述第一电源线的位于所述焊盘区的部分位于所述第一电源线的位于所述焊盘区的部分和所述公共电源线的位于所述焊盘区的部分之间。
例如，显示基板，还包括：第一驱动电路，配置为向所述第一电源线提供所述第一电源电压；以及第二驱动电路，配置为向所述第二电源线提供所述第二电源电压，所述第一驱动电路与所述第二驱动电路彼此独立工作。
例如，所述显示基板具有用于显示的第一侧和与第一侧相对的第二侧，所述第二显示区域包括：透光显示区和周围显示区；透光显示区允许从显示基板第一侧射入的光透过显示基板而到达所述显示基板的第二侧；周边显示区围绕所述透光显示区，且设置有用于驱动所述透光显示区的所述第二像素的像素电路。
本公开至少一实施例提供一种显示装置，该显示装置包括本公开实施例提供的任意一种显示基板。
本公开至少一实施例提供一种显示基板的驱动方法，应用于本公开实施例提供的阵列基板，该驱动方法包括：通过所述第一电源线向所述多个第一像素提供第一电源电压；通过所述第二电源线向所述多个第二像素提供第二电源电压；通过所述第一数据线向所述多个第一像素提供第一数据信号；通 过所述第二数据线向所述多个第二像素提供第二数据信号；控制所述第一电源电压、所述第二电源电压、所述第一数据信号和所述第二数据信号，以使得在分别显示相同画面的情形下所述第一显示区域的显示亮度与所述第二显示区域的显示亮度基本相同。
例如，控制所述第一电源电压不同于所述第二电源电压，且所述第一数据信号和所述第二数据信号未经区域亮度补偿。
例如，控制所述第一电源电压小于所述第二电源电压。
例如，控制所述第一电源电压与所述第二电源电压相同，且所述第一数据信号和所述第二数据信号至少之一经区域亮度补偿。
例如，驱动方法还包括：向所述多个第一像素提供第三电源电压；
向所述多个第二像素提供第四电源电压；其中，所述第三电源电压与所述第一电源电压具有相反的极性，所述第四电源电压与所述第二电源电压具有相反的极性，所述第四电源电压小于等于所述第三电源电压。
例如，所述第一数据信号为第一数据电压，所述第二数据信号为第二数据电压。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1A为本公开一实施例提供的一种显示基板的示意图；
图1B为图1A所示的显示基板的第一显示区域和第二显示区域中的像素分布示意图；
图2为图1A所示的显示基板的焊盘区的局部示意图；
图3为本公开一实施例提供的另一种显示基板的示意图；
图4为本公开一实施例提供的又一种显示基板的示意图；
图5A为沿图1A中的B-B’线的一种剖面示意图；
图5B为沿图1A中的B-B’线的另一种剖面示意图；
图5C为沿图4中的C-C’线的剖面示意图；
图6为本公开至少一实施例提供的一种显示基板中第二显示区域的像素区和走线区示意图；
图7A为本公开至少一实施例提供的一种显示基板中的第一像素一个子像素和第二像素的一个子像素的像素电路的等效电路图；
图7B为图7A所示的像素电路的结构示意图；
图8为本公开一实施例提供的又一种显示基板的焊盘区的局部示意图；
图9为本公开一实施例提供的再一种显示基板的示意图；
图10为本公开一实施例提供的一种显示装置的示意图。
具体实施方式
为了使得本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
为了保持本公开实施例的以下说明清楚且简明，本公开省略了部分已知功能和已知部件的详细说明。
为了实现显示屏的全屏化设计，在一些实施方式中，可以单独用于安装传感器(例如图像传感器、红外传感器)等部件的透光显示区域，该显示区域的透光面积较大，由此该透光显示区域可以在实现显示功能的同时，为安 装传感器等部件提供便利。但是，相比于不设置上述传感器的显示区域，该透光显示区域的发光面积较小，发光亮度较小，从而使得整个显示屏的发光亮度不均匀。
本公开至少一实施例提供一种显示基板，该显示基板包括第一显示区域、第二显示区域、非显示区域、第一电源线、第二电源线、至少一条第一数据线和至少一条第二数据线。第一显示区域包括多个第一像素；第二显示区域包括多个第二像素，所述第二显示区域的像素密度小于所述第一显示区域的像素密度；非显示区域至少部分围绕所述第一显示区域和所述第二显示区域；第一电源线连接到所述第一显示区域且配置为向所述多个第一像素提供第一电源电压；第二电源线连接到所述第二显示区域且配置为向所述多个第二像素提供第二电源电压，所述第一电源电压与所述第二电源电压具有相同的极性；至少一条第一数据线连接到所述第一显示区域且配置为向所述多个第一像素提供第一数据信号；至少一条第二数据线连接到所述第二显示区域且配置为向所述多个第二像素提供第二数据信号；所述第一电源电压、所述第二电源电压、所述第一数据信号和所述第二数据信号可调，以使得在分别显示相同画面的情形下所述第一显示区域的显示亮度与所述第二显示区域的显示亮度基本相同；所述第二电源线的至少部分位于所述非显示区域且围绕至少部分所述第一显示区域。
示例性地，图1A为本公开一实施例提供的一种显示基板的示意图，图1B为图1A所示的显示基板的第一显示区域和第二显示区域中的像素分布示意图，图7A为本公开至少一实施例提供的一种显示基板中的第一像素一个子像素和第二像素的一个子像素的像素电路的等效电路图，图7B为图7A所示的像素电路的结构示意图。
结合图1A-1B和图7A-7B，显示基板12包括第一显示区域1、第二显示区域2、非显示区域3、第一电源线10、第二电源线20、多条第一数据线600和多条第二数据线。例如，用于驱动一个第一像素11的像素电路和用于驱动一个第二像素12的像素电路在结构上可以均如图7A和图7B所示，在此仅以此作为示例。因此，在第二像素的像素驱动电路中，第二数据线的位置和结构可参考图7B所示的第一数据线600的位置和结构。该像素电路包括层 叠设置的栅极层700、存储电容C的第一极板81和第二极板82、半导体层300。例如第一极板81与栅极层700同层设置，即第一极板81与栅极层700可由同一材料经同一次构图工艺形成。例如，在本实施例中，第一极板81与像素电路的驱动晶体管T1的栅极一体成型。
例如，第一显示区域1围绕第二显示区域2的一部分。如图1B所示，在第一显示区域1包括多个第一像素11，第二显示区域2包括多个第二像素21，第二显示区域2的像素密度小于第一显示区域1的像素密度，即相邻的第二像素之间的间隔大于相邻的第一像素之间的间隔。非显示区域3围绕第一显示区域1和第二显示区域2；第一电源线10连接到第一显示区域1且配置为向多个第一像素11提供第一电源电压；第二电源线20连接到第二显示区2域且配置为向多个第二像素21提供第二电源电压。第一电源电压与第二电源电压具有相同的极性，即第一电源电压的数值与第二电源电压的数值均为正值。多条第一数据线600连接到第一显示区域1且配置为向多个第一像素11提供第一数据信号；多条第二数据线连接到第二显示区域2且配置为向多个第二像素21提供第二数据信号。图7B以对应于一个第一像素和一个第二像素的像素电路的结构为例，例如多个第一像素11呈第一阵列排布，第一阵列包括多行第一像素和多列第一像素；多个第二像素21呈第二阵列排布，第二阵列包括多行第二像素和多列第二像素。相应地，在第一显示区域1中，对应于每一行或每一列第一像素设置有一条第一数据线600；在第二显示区域2中，对应于每一行或每一列第二像素设置有一条第二数据线。在本实施例中，第一电源电压和第二电源电压可调以使得在分别显示相同画面的情形下，第一显示区域1的显示亮度与第二显示区域2的显示亮度基本相同，从而提高采用该显示基板的全面屏显示装置在屏幕的各个位置的显示亮度的均匀一致性。
例如，第二显示区域2中设置有传感器，传感器例如为图像传感器、红外传感器、距离传感器等，传感器例如可以实现为芯片等形式。显示基板12具有用于显示的第一侧和与第一侧相对的第二侧，传感器配置为接收来自第一侧的光。第二显示区域2包括透光区，由于第二显示区域2中的像素密度小于第一显示区域1的像素密度，因此，第二显示区域2的透光区的面积较 大。由此，第二显示区域1在实现显示的同时，还为传感器的设置提供了便利，利于提高传感器接收到的光的量，从而提升传感器的工作效果。在这种情况下，本公开实施例提供的显示基板避免了由于第二显示区域中的像素密度较低而影响第二显示区域的显示亮度。
第二电源线20的至少部分位于非显示区域且围绕部分第一显示区域1，从而，当第二显示区域2位于第一显示区域1的边缘附近时，便于将第二电源线20连接到第二显示区域2，同时，经第二电源线20的信号不干扰连接到第一显示区域1的第一电源线11的信号。
例如，在图1A中，第二显示区域2位于靠近显示基板12的边缘的位置，例如位于靠近显示基板12的边缘的中部。例如，第二显示区域2的形状为长条形。当然，在其他实施例中，第二显示区域2的形状也可以为椭圆形、矩形等，本公开实施例对此不作限定。
例如，第一电源电压不同于第二电源电压，在同一显示状态下第一数据信号和第二数据信号保持不变，即第一数据信号和第二数据信号未经区域亮度补偿。例如，第一数据信号为第一数据电压，第二数据信号为第二数据电压。
参考图7A，例如，第一像素11和第二像素21的像素电路均为该同一7T1C电路，两者的像素电路结构可以相同。该像素电路包括：第一至第七晶体管T1、T2、T3、T4、T5、T6、T7以及包括存储电容C和发光元件L1。第一至第七晶体管T1、T2、T3、T4、T5、T6、T7的位置如图7B所示。例如，第一晶体管T1被用作驱动晶体管，其他的第二至第六晶体管被用作开关晶体管。例如，发光元件L1可以为各种类型的OLED，例如顶发射、底发射、双侧发射等，可以发红光、绿光、蓝光或白光等，本公开的实施例对此不作限制。
在发光阶段，第一晶体管T1工作在饱和区，满足：
Id＝(1/2)*μ*C ox*(W/L)*(V gs-V th) 2≈(V data-VDD) 2*C，
其中，Id为流经发光元件L1的电流，VDD为电源电压，例如，在本实施例的第一显示区域，VDD为第一电源电压，V data为第一数据电压；在本实 施例的第二显示区域，VDD为第二电源电压，V data为第二数据电压。例如，在本实施例中，第一电源电压小于第二电源电压，此时，在保持第一显示区域1的V data和第二显示区域2的V data不变的情况下，即不对第一数据电压和第二数据电压进行区域亮度补偿时，流经第一显示区域1的发光元件的电流小于流经第二显示区域2的发光元件的电流，即提高了第二显示区域2的发光元件的发光亮度，从而提高了第二显示区域2的发光亮度，以达到在第二显示区域2的像素密度小于第一显示区域1的像素密度的情况下，在分别显示相同画面时，第一显示区域1的显示亮度与第二显示区域2的显示亮度基本相同。
例如，显示基板12还包括：第三电源线和第四电源线。第三电源线连接到第一显示区域1且配置为向多个第一像素11提供第三电源电压；第四电源线连接到第二显示区域，且配置为向多个第二像素21提供第四电源电压。例如，第三电源线和第四电源线为同一公共电源线30，结合图1A和图7A，例如，当第一显示区域1和第二显示区域2的发光元件L1为OLED发光元件时，该公共电源线30与OLED发光元件的公共阴极电连接，以为多个第一像素11和多个第二像素21提供相同的电源电压，该电源电压小于第一电源电压且小于第二电源电压。
图5A为沿图1A中的B-B’线的一种剖面示意图。例如，显示基板12还包括衬底基板，第一电源线10和第二电源线20设置于衬底基板上。如图1A和图5A所示，第一电源线10和第二电源线20同层设置，且第一电源线10在衬底基板上的正投影和第二电源线20在衬底基板上的正投影不重叠，即第一电源线和第二电源线彼此间隔开，以简化阵列基板12的结构及制作工艺。第一电源线10包括第一部分，第二电源线20包括彼此连接的第一部分和第二部分。第一电源线10的第一部分位于第一显示区1，第二电源线20的第一部分位于第二显示区域2。第二电源线20的第二部分位于非显示区域3且围绕部分第一显示区域1。例如，第二电源线20的第一部分包括沿第一方向延伸的多条第一子走线201和沿第二方向延伸的多条第二子走线202；第二电源线20的第二部分包括沿第二方向延伸的第三子走线203和第四子走线204。第一方向和第二方向相交，例如第一方向和第二方向垂直。例如，第一电源线10的第一部分包括沿第一方向延伸的多条第一子走线101和沿第二方 向延伸的多条第二子走线102。例如，多个第一像素11包括沿第一方向延伸的多行第一像素和沿第二方向延伸的多列第一像素；多个第二像素21包括沿第一方向延伸的多行第二像素和沿第二方向延伸的多列第二像素。例如，在图5A中，以标号7代表第一显示区域中的像素驱动电路的一部分。
例如，参考图7B，第一电源线10和第二电源线20可以与数据线600(第一数据线和第二数据线，位于SD层)同层设置，第一电源线10和第二电源线20与第一数据线和第二数据线材料相同，且经过对同一膜层进行同一次构图形成。
例如，在图1A中，第三子走线203和第四子走线204位于第二显示区域2的两侧，并且，第三子走线203和第四子走线204分别位于第一显示区域1的两侧。例如，第二电源线20的第二部分还包括沿第一方向延伸且分别与第三子走线203和第四子走线204相接的第五子走线205和第六子走线206，第五子走线205和第六子走线206进而延伸进入第二显示区域2，与第二电源线20的第一部分连接。例如，在图1A中，第五子走线205和第六子走线206均位于第二显示区域2的远离第一显示区域1的一侧，第五子走线205和第六子走线206均从第二显示区域2的远离第一显示区域的一侧的非显示区域3延伸进入第二显示区域2。
例如，第三子走线203和第四子走线204均为单条走线，以利于实现更窄的边框以及简化显示基板的制作工艺。当然，在其他实施例中，第三子走线203和第四子走线204也可以分别包括多条并列的走线，本公开对此不作限定。
例如，第三子走线203和第四子走线204均为直线。当然，在其他实施例中，第三子走线203和第四子走线204也可以包括曲线。
需要说明的是，第一电源线10和第二电源线20同层设置是指：第一电源线10和第二电源线20由同一材料通过同一次构图工艺同时形成，并且，在垂直于衬底基板的方向上，第一电源线10和第二电源线20之间不存在任何其他的层。
当然，在如图5B所示的实施例中，第一电源线10(图5B以第一电源线10的第一走线101为例)和第二电源线20(图5B以第二电源线20的第 三走线203为例)也可以异层设置，例如，第一电源线10和第二电源线20之间具有层间绝缘层8以使第一电源线10和第二电源线20彼此绝缘。例如，第二电源线20位于第一电源线10的远离衬底基板100的一侧；在其他实施中，第二电源线20也可以位于第一电源线10的靠近衬底基板100的一侧。第一电源线10和第二电源线20异层设置还能够适应第一电源线10和第二电源线20不同的位置需求，对此，在后面的实施例中进行介绍。
如图5A所示，显示基板12还包括位于非显示区域3的栅极驱动电路6(例如GOA电路)，第三子走线203和第四子走线204中的至少之一与栅极驱动电路6至少部分重叠，以利于实现窄边框。例如，栅极驱动电路6仅位于图5A中左侧的非显示区，第三子走线203与栅极驱动电路6至少部分重叠；例如，栅极驱动电路6仅位于图5A中右侧的非显示区，第四子走线204与栅极驱动电路6至少部分重叠；例如，图5A中右侧的非显示区和左侧的非显示区均设置有栅极驱动电路6，第三子走线203和第四子走线204均与栅极驱动电路6至少部分重叠。需要说明的是，第三子走线203和第四子走线204中的至少之一与栅极驱动电路6至少部分重叠指：第三子走线203和第四子走线204中的至少之一在衬底基板上的正投影与栅极驱动电路6在衬底基板上的正投影至少部分重叠，例如第三子走线203和第四子走线204中的至少之一在衬底基板上的正投影位于栅极驱动电路6在衬底基板上的正投影内。在另一个实施例中，第三子走线203和第四子走线204中的至少之一在衬底基板上的正投影位于栅极驱动电路6在衬底基板上的正投影的内侧(靠近显示区域的一侧)。栅极驱动电路6的结构比第三子走线203和第四子走线204的结构更加复杂，尤其在第三子走线203和第四子走线为单条走线时，将第三子走线203和第四子走线204设置于栅极驱动电路6的内侧可以避免第二电源线跨过栅极驱动电路6，从而利于保证第二电源线的制作精度以及减少制作不良。
例如，在图1A中，第三子走线203和第四子走线204从焊盘区出发，沿第一显示区域1的边缘延伸。
例如，如图1A所示，显示基板12的平面形状为矩形，所述第二电源线20的第二部分在第三子走线203与第五子走线205相接处具有第一拐角，所 述第二电源线20的第二部分在第四子走线204与第六子走线206相接处具有第二拐角，第一拐角和第二拐角分别位于所述矩形的两个相邻的顶角处。
图6为本公开至少一实施例提供的一种显示基板中第二显示区域的像素区和走线区示意图。参考图6和图7A-7B，例如，显示基板12还包括多条复位信号线9。多条复位信号线9连接到第二显示区域2，且配置为向多个第二像素21提供复位信号。第二显示区2包括位于多个第二像素21之间的走线区22，每条复位信号线9一部分和第二电源线20的一部分(例如第一走线201)位于走线区22。在第二显示区域2中，第一走线201的延伸方向与复位信号线9的延伸方向相同，例如均沿第一方向延伸。对于给沿第一方向排列的同一行第二像素分别提供第二电源电压的第一走线201和复位信号的复位信号线9，该第一走线201位于该复位信号线9与该行第二像素21之间，且该第一走线201与该复位信号线9之间的间距L大于该第一走线201与该行第二像素21之间的间距l。从而使得该第一走线201与该复位信号线9之间的距离较大，以防止复位信号线9上的复位信号与该第一走线201上的第二电源电压之间的干扰。复位信号例如为复位电压，复位电压与第二电源电压的极性相反。
例如，在第二显示区域2中，第二电源线20的第一部分的线宽为25μm～35μm。第二电源线20的第一部分例如第一走线201与复位信号线9之间的间距为45μm～55μmμm，第二电源线的第一部分例如第一走线201与第二像素21之间的间距为10μm～20μm。
例如，如图1A所示，显示基板12还包括位于非显示区3的焊盘区4。第一电源线10、第二电源线20和公共电源线30分别包括位于焊盘区4的部分。图2为图1A所示的显示基板的焊盘区的局部示意图。如图2所示，第二电源线20的位于焊盘区4的部分(例如第二电源线20的第三走线203的位于焊盘区4的部分)位于第一电源线10的位于焊盘区4的部分(例如第一电源线10的第二走线102的位于焊盘区4的部分)和公共电源线30的位于焊盘区4的部分之间，以便于第一电源线10的第二走线102连接至面积较大的第一显示区域1以及第二电源线20的第三走线203在非显示区域3布线。
如图2所示，例如，第二电源线20的位于焊盘区4的部分(例如第二电 源线20的第三走线203的位于焊盘区4的部分)的线宽为150μm～250μm；第二电源线20的位于焊盘区4的部分(例如第二电源线20的第三走线203的位于焊盘区4的部分)与第一电源线10的位于焊盘区的部分(例如第一电源线10的第二走线102的位于焊盘区4的部分)之间的间距为140μm～160μm，且与公共电源线30的位于焊盘区4的部分之间的间距为140μm～160μm。
需要说明的是，对应第四走线204的位于焊盘区4的部分的结构特征与第三走线203的相同。例如，位于图1A焊盘区4的公共电源线30、第二电源线20和第一电源线10所构成的整体的平面图形是左右对称的。当然，在一些实施例中，位于图1A焊盘区4的公共电源线30、第二电源线20和第一电源线10所构成的整体的平面图形也可以不是左右对称的。
例如，如图2所示，显示基板12还包括电路板，例如COF 5。例如COF5上设置有第一驱动电路51和第二驱动电路52；第一驱动电路51配置为向第一电源线10提供第一电源电压；第二驱动电路52配置为向第二电源线20提供第二电源电压。第一驱动电路51与第二驱动电路52彼此独立工作，互不干扰，以提供彼此不同的第一电源电压与第二电源电压。本公开实施例对电路板的具体位置不作限定，例如可以位于图1A所示的焊盘区。可以位于衬底基板的设置有第一电源线和第二电源线的第一面，也可以设置于衬底基板与该第一面相对的第二面，本领域技术人员可参考常规技术。
例如，图3为本公开一实施例提供的另一种显示基板的示意图。图3所示的显示基板与图1A所示的显示基板具有以下区别。如图3所示，第二显示区域2位于显示基板12的平面形状的靠近其边缘位置的拐角处。第三子走线203和第四子走线204分别从位于第二显示区域2的左侧的非显示区3和上侧的非显示区3延伸进入第二显示区域2。图3所示的显示基板的其他特征和相应技术效果均与图1A中的相同，请参考之前的描述，在此不再重复。
例如，图4为本公开一实施例提供的又一种显示基板的示意图。图4所示的显示基板与图1A所示的显示基板具有以下区别。如图4所示，第二显示区域2位于显示基板12的平面形状的中间区域，整个第二显示区域2被第一显示区域1围绕。第三子走线203和第四子走线204分别从第二显示区域 2的在第一方向彼此相对的两侧延伸进入第二显示区域2，且第三子走线203和第四子走线204经过第一显示区域1。
例如，在图4所示的实施例中，第一电源线10和第二电源线20也可以异层设置。图5C为沿图4中的C-C’线的一种剖面示意图。本实施例中，第一显示区域1位于第二显示区域2的中间区域，整个第二显示区域2被第一显示区域1围绕，因此，从周围的非显示区域3延伸进第二显示区域2的第二电源线例如图4中的第五走线205和第六走线206穿过第一显示区域1，从而，第五走线205和第六走线206与第一电源线10存在交叠，如图5C所示，即第五走线205在衬底基板上的正投影和第六走线206在衬底基板上的正投影与第一电源线10在衬底基板上的正投影至少部分重叠。此时，第一电源线10和第二电源线20之间具有层间绝缘层8，以使第一电源线10与第二电源线20彼此绝缘，以满足第二显示区域的不同位置需求，第二电源线20可以穿过第一显示区域1而连接到第二显示区域2。该阵列基板12的第二显示区域2可用于实现屏下摄像头、屏下指纹识别等功能。
例如，在图4中，第三子走线203和第四子走线204分别位于第二显示区域2的两侧，即第三子走线203和第四子走线204分别从第二显示区域2的两侧的非显示区域3延伸进入第二显示区域2。例如，在图1A所示的情况下，第三子走线203和第四子走线204分别从第二显示区域2的在第一方向上彼此相对的两侧延伸进入第二显示区域2。并且，第三子走线203和第四子走线204分别位于第一显示区域1的两侧。图4所示的显示基板的其他特征和相应技术效果均与图1A中的相同，请参考之前的描述，在此不再重复。
例如，在本公开实施例提供的显示基板中，第二显示区域2的形状为圆形、椭圆、矩形以及不规则图形等，本公开实施例对此不作限定。对第二显示区域2在显示基板中的具体位置也不作限定。上述实施例均为示例性实施例。
本公开另一实施例提供的阵列基板中，第一电源电压与第二电源电压相同，第一数据信号和第二数据信号至少之一经区域亮度补偿。例如第一数据信号和第二数据信号分别为第一数据电压和第二数据电压。例如，在同一显示状态下第二数据电压的值大于第一数据电压的值。例如，在本实施例中， 保持第一数据电压不变，提高第二数据电压的值，以使得同一显示状态下第二数据电压的值大于第一数据电压的值，从而第一显示区域1的显示亮度与第二显示区域2的显示亮度相同，即第二数据信号经区域亮度补偿。在其他实施例中，也可以保持第二数据电压不变，适当降低第一数据电压，以使得同一显示状态下第二数据电压的值大于第一数据电压的值，从而第一显示区域1的显示亮度与第二显示区域2的显示亮度相同，即第一数据信号经区域亮度补偿；或者，在降低第一数据电压的值得同时提高第二数据电压的值，以使得同一显示状态下第二数据电压的值大于第一数据电压的值，从而第一显示区域1的显示亮度与第二显示区域2的显示亮度相同，即第一数据信号和第二数据信号均经区域亮度补偿。从而，本实施例使得在其他条件例如驱动晶体管T1的宽长比以及复位信号不变的情况下，第一显示区域1的显示亮度与第二显示区域2的显示亮度相同。这种区域亮度补偿的原理如下。
发光阶段，图7A中的第一晶体管T1工作在饱和区，满足：
Id＝(1/2)*μ*C ox*(W/L)*(V gs-V th) 2≈(V data-VDD) 2*C，
其中，Id为流经发光元件L1的电流，VDD为电源电压，例如，在本实施例的第一显示区域，VDD为第一电源电压，V data为第一数据电压；在本实施例的第二显示区域，VDD为第二电源电压，V data为第二数据电压。在本实施例中，在显示同一画面时，可以在第一电源电压等于第二电源电压的条件下，通过提高第二数据电压，使第二数据电压大于第一数据电压，以使得第二发光区域2中流经发光元件的电流大于第一发光区域1中流经发光元件的电流，从而使得第一显示区域1的显示亮度与第二显示区域2的显示亮度基本相同。
在本实施例中，第四电源电压等于第三电源电压，为公共电源电压VSS。公共电源电压与第一电源电压具有相反的极性，且与第二电源电压具有相反的极性。与不经过调制的显示状态相比，例如与图1A-图4所示的实施例相比，本实施例的公共电源电压VSS较小。因为当TFT工作在线性区满足：Vds<Vgs-Vth，工作在饱和区满足：Vds>Vgs-Vth。结合图7A，对于第二显示区域2中的驱动晶体管T1，由于Vdata增大，所以Vgs增大，需要使Vds增大以使驱动晶体管T1快速进入饱和区；又因为根据图7A的像素电路可知：
VDD-VSS＝Vds(DTFT)+V EL，
其中，Vds(DTFT)为驱动晶体管T1的源漏电压，V EL为发光元件上的电压。因此，在本实施例中，减小VSS以使Vds(DTFT)增大，从而能够使得使驱动晶体管T1快速进入饱和区。
例如，可通过改变与图7A和7B所示的数据线600连接的数据电压控制电路来实现本实施例对第二数据电压的调整，以达到上述效果。具体的对第二数据电压的调整数值和幅度，本领域技术人员可根据实际需求进行测试和调制而获得。
图8为本实施例提供的显示基板的焊盘区的局部示意图。如图8所示，本实施例中，例如COF 5上设置有驱动电路50，同一驱动电路50配置为向第一电源线10提供第一电源电压以及向第二电源线20提供第二电源电压。
本实施例提供的显示基板的未提及的其他特征及相应技术效果均与之前的实施例中的相同，请参考之前实施例中的描述。
图9为本公开一实施例提供的再一种显示基板的示意图。如图9所示，例如，第二显示区域2包括：透光显示区200和周边显示区2000。透光显示区200允许从显示基板的第一侧即显示侧射入的光透过显示基板而到达显示基板的背侧。此时，上述传感器可设置于透光显示区，利于提高入射至传感器的光的量，以提高传感器的工作效果。周边显示区2000围绕透光显示区200，且设置有用于驱动透光显示区200的第二像素21的像素电路。即，用于驱动透光显示区200中的第二像素工作的像素电路，例如图7A和7B所示的像素电路，设置于周边显示区2000而不设置于透光显示区200中，透光显示区200中设置有第二像素的发光元件，设置于周边显示区2000中的用于驱动透光显示区200中的第二像素工作的像素电路的第二电源线从周边显示区2000延伸进入透光显示区200从而与透光显示区200中的发光元件连接。
例如，在本公开的实施例中，透明显示区200可以为圆形(图9中示出的情形)、矩形、三角形等各种形状，本公开的实施例对透明显示区200的形状不做限定。
图9所示实施例的未提及的其他特征及相应技术效果均与之前的实施例中的相同，请参考之前实施例中的描述。
在本公开的实施例提供的阵列基板中，例如，多个第一像素11的每个具有第一中心，多个第二像素21的每个具有第二中心；在第一方向上，多个第一像素11中的相邻两个第一像素11的第一中心的间距小于多个第二像素21中的相邻两个第二像素21的第二中心的间距；在第二方向上，多个第一像素11中的相邻两个第一像素11的第一中心的间距小于多个第二像素21中的相邻两个第二像素21的第二中心的间距。例如，在第一方向上，多个第二像素21中的相邻两个第二像素21的第一中心的间距是多个第一像素11中的相邻两个第一像素11的第一中心的间距的整数倍，例如2倍；在第二方向上，多个第二像素21中的相邻两个第二像素21的第二中心的间距是多个第一像素11中的相邻两个第一像素11的第一中心的间距的整数倍，例如2倍。当然，不限于是2倍，也可以是3倍、4倍等，本公对此不作限定。
本公开至少一实施例还提供一种显示装置，该显示装置包括本公开实施例提供的任意一种显示基板。图10为本公开一实施例提供的一种显示装置的示意图。如图所示，本公开实施例提供的显示装置120包括本公开实施例提供的任意一种显示基板12。例如该显示装置可以为电致发光显示装置，例如OLED显示装置。例如，该显示装置为手机、平板电脑、显示器等等。例如第二显示区域中设置有传感器，可用于实现屏外摄像头、屏下摄像头、屏下指纹识别等功能。
本公开至少一实施例还提供一种显示基板的驱动方法，应用于本公开实施例提供的阵列基板，该驱动方法包括：通过所述第一电源线向所述多个第一像素提供第一电源电压；通过所述第二电源线向所述多个第二像素提供第二电源电压；通过所述第一数据线向所述多个第一像素提供第一数据信号；通过所述第二数据线向所述多个第二像素提供第二数据信号；控制所述第一电源电压、所述第二电源电压、所述第一数据信号和所述第二数据信号，以使得在分别显示相同画面的情形下所述第一显示区域的显示亮度与所述第二显示区域的显示亮度基本相同。
在一个实施例中，控制第一电源电压不同于第二电源电压，且第一数据信号和第二数据信号未经区域亮度补偿，即在同一显示状态下第一数据信号和第二数据信号保持不变。例如，第一数据信号为第一数据电压，第二数据 信号为第二数据电压。例如控制第一电源电压小于第二电源电压，以使第一显示区域1的显示亮度与所述第二显示区域2的显示亮度基本相同。例如该驱动方法可应用于图1A-图4所示的实施例。
在发光阶段，第一晶体管T1工作在饱和区，满足：
Id＝(1/2)*μ*C ox*(W/L)*(V gs-V th) 2≈(V data-VDD) 2*C，
其中，Id为流经发光元件L1的电流，VDD为电源电压，例如，在本实施例的第一显示区域，VDD为第一电源电压，V data为第一数据电压；在本实施例的第二显示区域，VDD为第二电源电压，V data为第二数据电压。例如，在本实施例中，第一电源电压小于第二电源电压，此时，在保持第一显示区域1的V data和第二显示区域2的V data不变的情况下，即不对第一数据电压和第二数据电压进行区域亮度补偿时，流经第一显示区域1的发光元件的电流小于流经第二显示区域2的发光元件的电流，即提高了第二显示区域2的发光元件的发光亮度，从而提高了第二显示区域2的发光亮度，以达到在第二显示区域2的像素密度小于第一显示区域1的像素密度的情况下，在分别显示相同画面时，第一显示区域1的显示亮度与第二显示区域2的显示亮度基本相同。
在另一个实施例中，控制第一电源电压与第二电源电压相同，且第一数据信号和第二数据信号至少之一经未经区域亮度补偿。例如第一数据信号和第二数据信号分别为第一数据电压和第二数据电压。例如，在同一显示状态下第二数据电压的值大于第一数据电压的值。例如，在本实施例中，保持第一数据电压不变，提高第二数据电压的值，以使得同一显示状态下第二数据电压的值大于第一数据电压的值，从而第一显示区域1的显示亮度与第二显示区域2的显示亮度相同，即第二数据信号经区域亮度补偿。在其他实施例中，也可以保持第二数据电压不变，适当降低第一数据电压，以使得同一显示状态下第二数据电压的值大于第一数据电压的值，从而第一显示区域1的显示亮度与第二显示区域2的显示亮度相同，即第一数据信号经区域亮度补偿；或者，在降低第一数据电压的值得同时提高第二数据电压的值，以使得同一显示状态下第二数据电压的值大于第一数据电压的值，从而第一显示区域1的显示亮度与第二显示区域2的显示亮度相同，即第一数据信号和第二数据信号均经区域亮度补偿。这种区域亮度补偿的原理如下。
发光阶段，图7A中的第一晶体管T1工作在饱和区，满足：
Id＝(1/2)*μ*C ox*(W/L)*(V gs-V th) 2≈(V data-VDD) 2*C，
其中，Id为流经发光元件L1的电流，VDD为电源电压，例如，在本实施例的第一显示区域，VDD为第一电源电压，V data为第一数据电压；在本实施例的第二显示区域，VDD为第二电源电压，V data为第二数据电压。在本实施例中，在显示同一画面时，可以在第一电源电压等于第二电源电压的条件下，通过提高第二数据电压，使第二数据电压大于第一数据电压，以使得第二发光区域2中流经发光元件的电流大于第一发光区域1中流经发光元件的电流，从而使得第一显示区域1的显示亮度与第二显示区域2的显示亮度基本相同。例如该驱动方法可应用于图8所对应的实施例。
本实施例提供的驱动方法还包括：向多个第一像素提供第三电源电压；向多个第二像素提供第四电源电压；第三电源电压与第一电源电压具有相反的极性，第四电源电压与第二电源电压具有相反的极性，第四电源电压小于等于第三电源电压。例如，通过第三电源线向多个第一像素提供第三电源电压，通过第四电源线向多个第二像素提供第四电源电压。例如，第三电源线和第四电源线为同一公共电源线30，第四电源电压等于第三电源电压，为公共电源电压VSS。
与不经过调制的显示状态相比，例如与图1A-图4所示的实施例对应的驱动方法相比，本实施例提供的驱动方法中，公共电源电压VSS较小。因为当TFT工作在线性区满足：Vds<Vgs-Vth，工作在饱和区满足：Vds>Vgs-Vth。结合图7A，对于第二显示区域2中的驱动晶体管T1，由于在该方法中增大了Vdata，所以Vgs增大，需要使Vds增大以使驱动晶体管T1快速进入饱和区；又因为根据图7A的像素电路可知：
VDD-VSS＝Vds(DTFT)+V EL，
其中，Vds(DTFT)为驱动晶体管T1的源漏电压，V EL为发光元件上的电压。因此，在本实施例中，减小VSS以使Vds(DTFT)增大，从而能够使得使驱动晶体管T1快速进入饱和区。
例如，可通过改变与图7A和7B所示的数据线600连接的数据电压控制电路来实现本实施例对第二数据电压的调整，以达到上述效果。具体的调整 的数值，本领域技术人员可根据实际需求进行测试和调制而获得。
以上所述仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (22)

  1. 一种显示基板，包括：
    第一显示区域，包括多个第一像素；
    第二显示区域，包括多个第二像素，其中，所述第二显示区域的像素密度小于所述第一显示区域的像素密度；
    非显示区域，至少部分围绕所述第一显示区域和所述第二显示区域；
    第一电源线，连接到所述第一显示区域且配置为向所述多个第一像素提供第一电源电压；
    第二电源线，连接到所述第二显示区域且配置为向所述多个第二像素提供第二电源电压，其中，所述第一电源电压与所述第二电源电压具有相同的极性；
    至少一条第一数据线，连接到所述第一显示区域且配置为向所述多个第一像素提供第一数据信号；以及
    至少一条第二数据线，连接到所述第二显示区域且配置为向所述多个第二像素提供第二数据信号；
    其中，所述第二电源线的至少部分位于所述非显示区域且围绕至少部分所述第一显示区域。
  2. 根据权利要求1所述的显示基板，其中，所述第一电源电压不同于所述第二电源电压。
  3. 根据权利要求2所述的显示基板，其中，所述第一电源电压小于所述第二电源电压。
  4. 根据权利要求1所述的显示基板，其中，所述第一电源电压与所述第二电源电压相同，所述第一数据信号和所述第二数据信号至少之一经区域亮度补偿。
  5. 根据权利要求4所述的显示基板，还包括：
    第三电源线，连接到所述第一显示区域且配置为向所述多个第一像素提供第三电源电压；
    第四电源线，连接到所述第二显示区域，且配置为向所述多个第二像素 提供第四电源电压，其中，
    所述第三电源电压与所述第一电源电压具有相反的极性，所述第四电源电压与所述第二电源电压具有相反的极性，所述第四电源电压小于等于所述第三电源电压。
  6. 根据权利要求1-5任一所述的显示基板，其中，所述第一数据信号为第一数据电压，所述第二数据信号为第二数据电压。
  7. 根据权利要求2-5任一所述的显示基板，其中，所述第一显示区域围绕至少部分所述第二显示区域；所述显示基板还包括衬底基板，所述第一电源线和所述第二电源线设置于所述衬底基板上；
    所述第一电源线和所述第二电源线同层设置，且所述第一电源线在所述衬底基板上的正投影和所述第二电源线在所述衬底基板上的正投影不重叠；
    所述第一电源线包括第一部分，所述第二电源线包括彼此连接的第一部分和第二部分，所述第一电源线的第一部分位于所述第一显示区，所述第二电源线的第一部分位于所述第二显示区域，所述第二电源线的第二部分经所述非显示区域连接到所述第二显示区域且围绕至少部分所述第一显示区域。
  8. 根据权利要求2-5任一所述的显示基板，其中，所述第一显示区域围绕至少部分所述第二显示区域；所述第一电源线和所述第二电源线异层设置，且所述第一电源线和所述第二电源线之间设置有绝缘层以使所述第一电源线和所述第二电源线彼此绝缘；
    所述第一电源线包括第一部分，所述第二电源线包括彼此连接的第一部分和第二部分，所述第一电源线的第一部分位于所述第一显示区，所述第二电源线的第一部分位于所述第二显示区域；所述第二部分至少部分穿过所示第一显示区域而连接到所述第二显示区域。
  9. 根据权利要求7或8所述的显示基板，其中，所述第二电源线的第一部分包括沿第一方向延伸的多条第一子走线和沿第二方向延伸的多条第二子走线；所述第二电源线的第二部分包括沿所述第二方向延伸的第三子走线和第四子走线；所述第一方向和所述第二方向相交；
    所述第三子走线和所述第四子走线分别位于所述第二显示区域的两侧，且分别位于所述第一显示区域的两侧。
  10. 根据权利要求9所述的显示基板，其中，所述第三子走线和所述第四子走线均为单条走线。
  11. 根据权利要求9或10所述的显示基板，还包括位于所述非显示区域的栅极驱动电路，其中，所述第三子走线和所述第四子走线中的至少之一与所述栅极驱动电路至少部分重叠。
  12. 根据权利要求1-11任一所述的显示基板，还包括：
    至少一条复位信号线，连接到所述第二显示区域，且配置为向所述多个第二像素提供复位信号，其中，所述第二显示区包括位于所述多个第二像素之间的走线区，所述像素区包括所述多个第二像素，所述复位信号线的至少部分和所述第二电源线的至少部分位于所述走线区，
    在所述第二显示区域中，所述第二电源线的至少部分的延伸方向与所述复位信号线的延伸方向相同，对于给同第二像素分别提供第二电源电压的所述第二电源线的至少部分和复位信号的所述复位信号线，该第一走线位于该复位信号线与该第二像素之间，且该第一走线与该复位信号线之间的间距大于该第一走线与该第二像素之间的间距。
  13. 根据权利要求5所述的显示基板，还包括位于所述非显示区的焊盘区，其中，所述第三电源线和所述第四电源线为同一公共电源线，所述第一电源线、所述第二电源线和所述公共电源线分别包括位于所述焊盘区的部分，所述第一电源线的位于所述焊盘区的部分位于所述第一电源线的位于所述焊盘区的部分和所述公共电源线的位于所述焊盘区的部分之间。
  14. 根据权利要求1-13任一所述的显示基板，还包括：
    第一驱动电路，配置为向所述第一电源线提供所述第一电源电压；以及
    第二驱动电路，配置为向所述第二电源线提供所述第二电源电压，其中，所述第一驱动电路与所述第二驱动电路彼此独立工作。
  15. 根据权利要求1-14任一所述的显示基板，其中，所述显示基板具有用于显示的第一侧和与第一侧相对的第二侧，所述第二显示区域包括：
    透光显示区，允许从显示基板第一侧射入的光透过显示基板而到达所述显示基板的第二侧；以及
    周边显示区，围绕所述透光显示区，且设置有用于驱动所述透光显示区 的所述第二像素的像素电路。
  16. 一种显示装置，包括权利要求1-15任一所述的显示基板。
  17. 一种权利要求1-16任一所述的显示基板的驱动方法，包括：
    通过所述第一电源线向所述多个第一像素提供第一电源电压；
    通过所述第二电源线向所述多个第二像素提供第二电源电压；
    通过所述第一数据线向所述多个第一像素提供第一数据信号；
    通过所述第二数据线向所述多个第二像素提供第二数据信号；
    控制所述第一电源电压、所述第二电源电压、所述第一数据信号和所述第二数据信号，以使得在分别显示相同画面的情形下所述第一显示区域的显示亮度与所述第二显示区域的显示亮度基本相同。
  18. 根据权利要求17所述的驱动方法，其中，
    控制所述第一电源电压不同于所述第二电源电压，且所述第一数据信号和所述第二数据信号未经区域亮度补偿。
  19. 根据权利要求18所述的驱动方法，其中，控制所述第一电源电压小于所述第二电源电压。
  20. 根据权利要求19所述的驱动方法，其中，控制所述第一电源电压与所述第二电源电压相同，且所述第一数据信号和所述第二数据信号至少之一经区域亮度补偿。
  21. 根据权利要求20所述的驱动方法，还包括：
    向所述多个第一像素提供第三电源电压；
    向所述多个第二像素提供第四电源电压；其中，
    所述第三电源电压与所述第一电源电压具有相反的极性，所述第四电源电压与所述第二电源电压具有相反的极性，所述第四电源电压小于等于所述第三电源电压。
  22. 根据权利要求17-21任一所述的驱动方法，所述第一数据信号为第一数据电压，所述第二数据信号为第二数据电压。
PCT/CN2020/073902 2020-01-22 2020-01-22 显示基板及其驱动方法、显示装置 WO2021147032A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/CN2020/073902 WO2021147032A1 (zh) 2020-01-22 2020-01-22 显示基板及其驱动方法、显示装置
CN202080000059.4A CN113498534B (zh) 2020-01-22 2020-01-22 显示基板及其驱动方法、显示装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2020/073902 WO2021147032A1 (zh) 2020-01-22 2020-01-22 显示基板及其驱动方法、显示装置

Publications (1)

Publication Number Publication Date
WO2021147032A1 true WO2021147032A1 (zh) 2021-07-29

Family

ID=76991956

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/073902 WO2021147032A1 (zh) 2020-01-22 2020-01-22 显示基板及其驱动方法、显示装置

Country Status (2)

Country Link
CN (1) CN113498534B (zh)
WO (1) WO2021147032A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114143965A (zh) * 2021-11-30 2022-03-04 武汉天马微电子有限公司 线路板

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023092317A1 (zh) * 2021-11-24 2023-06-01 京东方科技集团股份有限公司 电子基板及电子设备

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108597436A (zh) * 2018-05-09 2018-09-28 昆山国显光电有限公司 显示面板及显示装置
CN109272873A (zh) * 2018-11-20 2019-01-25 武汉天马微电子有限公司 显示面板及显示装置
CN109637457A (zh) * 2019-02-14 2019-04-16 成都京东方光电科技有限公司 像素电路、显示面板及显示装置
CN110070801A (zh) * 2019-04-30 2019-07-30 武汉天马微电子有限公司 一种显示面板及显示装置
CN110288915A (zh) * 2019-06-28 2019-09-27 武汉天马微电子有限公司 一种显示面板和显示装置
US20190373166A1 (en) * 2018-06-04 2019-12-05 Guangdong Oppo Mobile Telecommunications Corp., Ltd. Electronic Device and Method for Taking Picture Using the Same

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102484383B1 (ko) * 2014-09-30 2023-01-03 엘지디스플레이 주식회사 유기발광다이오드 표시패널 및 이의 표시장치
KR102645333B1 (ko) * 2016-08-23 2024-03-12 삼성디스플레이 주식회사 표시장치
CN209418111U (zh) * 2019-02-22 2019-09-20 上海和辉光电有限公司 一种显示面板和显示装置
CN110264966A (zh) * 2019-05-09 2019-09-20 京东方科技集团股份有限公司 显示基板及其驱动方法、显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108597436A (zh) * 2018-05-09 2018-09-28 昆山国显光电有限公司 显示面板及显示装置
US20190373166A1 (en) * 2018-06-04 2019-12-05 Guangdong Oppo Mobile Telecommunications Corp., Ltd. Electronic Device and Method for Taking Picture Using the Same
CN109272873A (zh) * 2018-11-20 2019-01-25 武汉天马微电子有限公司 显示面板及显示装置
CN109637457A (zh) * 2019-02-14 2019-04-16 成都京东方光电科技有限公司 像素电路、显示面板及显示装置
CN110070801A (zh) * 2019-04-30 2019-07-30 武汉天马微电子有限公司 一种显示面板及显示装置
CN110288915A (zh) * 2019-06-28 2019-09-27 武汉天马微电子有限公司 一种显示面板和显示装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114143965A (zh) * 2021-11-30 2022-03-04 武汉天马微电子有限公司 线路板
CN114143965B (zh) * 2021-11-30 2024-04-05 武汉天马微电子有限公司 线路板

Also Published As

Publication number Publication date
CN113498534B (zh) 2024-04-09
CN113498534A (zh) 2021-10-12

Similar Documents

Publication Publication Date Title
JP7359701B2 (ja) 表示パネルおよび表示装置
CN106653817B (zh) 透明oled显示面板
WO2020228205A1 (zh) 显示面板及显示装置
CN104464533B (zh) 一种显示面板、显示装置
WO2020134914A1 (zh) 一种显示屏、移动终端及其控制方法
US10355063B2 (en) Organic light emitting display panel and organic light emitting diode display device including the same
WO2022056907A1 (zh) 显示基板及显示装置
WO2021190163A1 (zh) 显示面板及显示装置
US20150364712A1 (en) Organic Light-Emitting Diode Display With Split Anodes
KR20210109709A (ko) 표시 장치
WO2021147032A1 (zh) 显示基板及其驱动方法、显示装置
CN114582949A (zh) 显示基板和显示装置
WO2019024565A1 (zh) 布线结构及其制备方法、oled阵列基板以及显示装置
KR102481789B1 (ko) 유기 발광 표시 장치
WO2020248837A1 (zh) 阵列基板、显示面板和显示装置
JP2019003040A (ja) 表示装置
US20230189596A1 (en) Display panel and display device
KR100614474B1 (ko) 전기 광학 장치, 액티브 매트릭스 기판 및 전자 기기
US20240074257A1 (en) Display panel and electronic device
US11849618B2 (en) Electronic device
WO2022110015A1 (zh) 显示基板、显示面板、显示装置
KR20190079487A (ko) 패널 내장형 게이트 드라이버를 포함한 표시장치
US20220005405A1 (en) Display device
TWI692665B (zh) 顯示裝置
KR20170080266A (ko) 디스플레이 장치

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20915081

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20915081

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 20915081

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 20.03.2023)

122 Ep: pct application non-entry in european phase

Ref document number: 20915081

Country of ref document: EP

Kind code of ref document: A1