WO2021143648A1 - 时序控制器、显示装置、信号调整方法 - Google Patents

时序控制器、显示装置、信号调整方法 Download PDF

Info

Publication number
WO2021143648A1
WO2021143648A1 PCT/CN2021/071103 CN2021071103W WO2021143648A1 WO 2021143648 A1 WO2021143648 A1 WO 2021143648A1 CN 2021071103 W CN2021071103 W CN 2021071103W WO 2021143648 A1 WO2021143648 A1 WO 2021143648A1
Authority
WO
WIPO (PCT)
Prior art keywords
swing amplitude
frame signal
error rate
bit error
insertion loss
Prior art date
Application number
PCT/CN2021/071103
Other languages
English (en)
French (fr)
Inventor
刘媛媛
乔玄玄
刘帅
袁先锋
陈泽君
王建军
邢振周
Original Assignee
京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 合肥鑫晟光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/424,132 priority Critical patent/US11769467B2/en
Publication of WO2021143648A1 publication Critical patent/WO2021143648A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/18—Timing circuits for raster scan displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2018—Display of intermediate tones by time modulation using two or more time intervals
    • G09G3/2022—Display of intermediate tones by time modulation using two or more time intervals using sub-frames
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G5/006—Details of the interface to the display terminal
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a timing controller, a display device, and a signal adjustment method.
  • the display panel needs to provide input signals from the front-end system, such as RGB (red, green and blue) signals, Low-Voltage Differential Signaling (LVDS) signals, Embedded Display Port (EDP) signals, etc.
  • RGB red, green and blue
  • LVDS Low-Voltage Differential Signaling
  • EDP Embedded Display Port
  • the input signal provided by the front-end system is affected by the following three factors: the first is affected by the quality of the signal when it is generated; the second is affected by the resistance and capacitance in the input signal transmission line; the third is affected by the external electromagnetic field.
  • the quality of the input signal There are many factors that affect the quality of the input signal, and once the quality of the input signal deteriorates, it will directly cause problems such as color cast and flickering of the screen. Therefore, it is very important to improve the quality of the input signal of the display panel.
  • a timing controller including: a receiving circuit, a timing control circuit, and a plurality of insertion loss circuits; the receiving circuit and the insertion loss circuit are respectively connected to the timing control circuit;
  • the receiving circuit is configured to: receive N frame signals;
  • the timing control circuit is configured as:
  • M and N are both positive integers, and 1 ⁇ M ⁇ N.
  • adjusting the swing amplitude of the M-1 frame signal according to the target swing amplitude value corresponding to the bit error rate of the M-1 frame signal includes:
  • the multiple insertion loss circuits are divided into multiple groups of insertion loss units, and each group of the insertion loss units includes a first insertion loss circuit and a second insertion loss circuit, and the first insertion loss circuit is used for the loss of the first insertion loss circuit.
  • the second insertion loss circuit is used to lose a signal of a second frequency, and the first frequency is smaller than the second frequency.
  • the target swing amplitude value corresponds to the insertion loss unit one-to-one.
  • the first insertion loss circuit includes: a capacitor, a first switch, a first ground terminal, and a second ground terminal; both ends of the capacitor are respectively connected to the first ground terminal And the first terminal of the first switch, and the second terminal of the first switch is connected to the second ground terminal;
  • the second insertion loss circuit includes: a magnetic bead, a second switch, a third ground terminal, and a fourth ground terminal; the two ends of the magnetic bead are respectively connected to the third ground terminal and the first terminal of the second switch, the The second terminal of the second switch is connected to the fourth ground terminal.
  • the first ground terminals of the multiple first insertion loss circuits and the third ground terminals of the multiple second insertion loss circuits are the same ground terminal, and the multiple first insertion loss circuits
  • the second ground terminal of the circuit and the fourth ground terminal of the plurality of second insertion loss circuits are the same ground terminal.
  • the timing control circuit adjusting the swing amplitude of the M-1th frame signal according to the corresponding relationship between the bit error rate interval in the swing amplitude adjustment table and the target swing amplitude value includes:
  • the timing control circuit determines the target swing amplitude value corresponding to the error rate of the M-1th frame signal according to the corresponding relationship between the bit error rate interval and the target swing amplitude value in the swing amplitude adjustment table;
  • the relationship between the bit error rate interval and the target swing amplitude value is stored in a swing amplitude adjustment table.
  • timing control circuit is further configured to:
  • the swing amplitude adjustment table Before the blanking phase of the first frame signal, the swing amplitude adjustment table is stored, wherein the swing amplitude adjustment table includes a plurality of the error rate intervals, a plurality of the target swing amplitude values, and the error code The corresponding relationship between the rate interval and the target swing amplitude.
  • a display device including the above-mentioned timing controller.
  • a signal adjustment method is provided, which is applied to the above-mentioned timing controller, the timing controller includes a receiving circuit and a plurality of insertion loss circuits, the receiving circuit is configured to receive N frames of signals, the method include:
  • M and N are both positive integers, and 1 ⁇ M ⁇ N.
  • the adjusting the swing amplitude of the M-1 frame signal according to the target swing amplitude value corresponding to the bit error rate of the M-1 frame signal includes:
  • the adjusting the swing amplitude of the M-1th frame signal according to the corresponding relationship between the bit error rate interval in the swing amplitude adjustment table and the target swing amplitude value includes:
  • the method before the blanking phase of the first frame signal, the method further includes:
  • the swing amplitude adjustment table is stored, wherein the swing amplitude adjustment table includes a plurality of the error rate intervals, a plurality of the target swing amplitude values, and the correspondence relationship between the error rate interval and the swing amplitude value .
  • the blanking phase of the M-th frame signal includes an initial phase, an intermediate phase, and an end phase;
  • detecting the bit error rate of the M-1th frame signal includes:
  • the bit error rate of the M-1th frame signal is detected.
  • a non-volatile computer-readable storage medium which contains a calculation program, and when the computer program is executed by an electronic device, the electronic device executes the aforementioned signal adjustment method.
  • a computer program product including a computer program, and when the computer program is executed by an electronic device, the electronic device executes the aforementioned signal adjustment method.
  • Figure 1 is an eye diagram of an input signal provided by related technologies
  • Figure 2 is an eye diagram of another input signal provided by related technologies
  • FIG. 3 is a schematic structural diagram of a timing controller provided by an embodiment of the disclosure.
  • FIG. 4 is a schematic diagram of a signal provided by an embodiment of the disclosure.
  • FIG. 5 is a schematic diagram of another signal provided by an embodiment of the disclosure.
  • FIG. 6 is a schematic diagram of a first insertion loss circuit provided by an embodiment of the disclosure.
  • FIG. 7 is a schematic diagram of a second insertion loss circuit provided by an embodiment of the disclosure.
  • FIG. 8 is a design layout of an insertion loss circuit provided by an embodiment of the disclosure.
  • FIG. 9 is a schematic flowchart of a signal adjustment method provided by an embodiment of the disclosure.
  • FIG. 10 is a schematic flowchart of another signal adjustment method provided by an embodiment of the present disclosure.
  • Fig. 11 schematically shows a block diagram of an electronic device for executing the method according to the present disclosure
  • Fig. 12 schematically shows a storage unit for holding or carrying computer program codes for implementing the method according to the present disclosure.
  • the method of improving the quality of the input signal in the related technology is: after the control chip TCON chip of the display panel receives the input signal transmitted by the front-end system, it adjusts the signal swing (ie the signal swing), which can make the signal fluctuation obvious , Which makes it easier to obtain effective signal output.
  • the eye diagram of the original input signal the eye height is about 182mV.
  • the eye diagram of the signal is shown in Figure 2.
  • the eye height is about 426mV, the increase is about 240mV, the signal quality has been improved, and the display panel is easier to see from Figure 2. Obtain a valid signal from the displayed signal.
  • EMC electromagnetic compatibility
  • the embodiments of the present disclosure provide a timing controller, a display device, and a signal adjustment method.
  • the timing controller can improve the quality of the input signal while reducing EMC interference caused by the enhanced signal.
  • the embodiment of the present disclosure provides a timing controller.
  • the timing controller includes: a receiving circuit 1, a timing control circuit 2, a plurality of insertion loss circuits 3; the receiving circuit 1, the insertion loss circuit 3 and The timing control circuit 2 is connected.
  • the receiving circuit is configured to receive N frame signals.
  • the timing control circuit is configured as:
  • the target swing amplitude value corresponding to the bit error rate of the M-1 frame signal select the corresponding insertion loss circuit to adjust the energy generated by the swing amplitude of the M-1 frame signal with loss; where M and N are both positive Integer, and 1 ⁇ M ⁇ N.
  • adjusting the swing amplitude of the M-1 frame signal according to the target swing amplitude value corresponding to the bit error rate of the M-1 frame signal may include:
  • the foregoing receiving circuit may include an interface, and the interface type is not limited, and may be determined according to the signal type output by the front-end system.
  • the timing control circuit can be a circuit printed on the circuit board by printing or other methods, or a timing control chip, etc.
  • the type of the timing control chip mentioned above is not limited, and it can be a single-chip microcomputer, ARM (Advanced RISC Machines, advanced Chips such as simplified instruction set computing machine) or FPGA (Field Programmable Gate Array) can be determined according to actual design requirements.
  • the timing controller includes three insertion loss circuits as an example for drawing.
  • a frame of signal includes an active area 10 and a blanking area 11; among them, the active zone corresponds to the effective time of the signal, and the blanking area ( blanking zone) corresponds to the preparation time of the signal.
  • the effective area corresponds to the stage of displaying the picture
  • the blanking area corresponds to the stage of not displaying the picture (the corresponding time of the blanking area is very short and it is difficult for the human eye to feel).
  • the aforementioned blanking stage of the M-th frame signal corresponds to the blanking area of the M-th frame signal.
  • a bit error rate (BER) detection area 112 is added to the blanking area 11, that is, the error of the M-1 frame signal is performed during the blanking phase of the M-th frame signal. Bit rate detection.
  • the above swing amplitude adjustment table can be pre-stored in the timing control circuit, and the specific content of the bit error rate interval and the target swing amplitude value in the table can be determined according to the actual situation.
  • the embodiment of the present disclosure provides a timing controller. While adjusting the signal swing, the timing controller (TCON) uses insertion loss circuit loss to adjust the energy generated by the signal swing, so as to improve the input At the same time of signal quality, EMC interference caused by enhanced signal is reduced.
  • TCON timing controller
  • all the insertion loss circuits are divided into multiple groups of insertion loss units, each group of insertion loss units includes a first insertion loss circuit and a second insertion loss circuit, the first insertion loss circuit is used to loss the signal of the first frequency, and the second The insertion loss circuit is used to loss the signal of the second frequency, and the first frequency is less than the second frequency.
  • Signals are divided into high-frequency signals and low-frequency signals.
  • the first insertion loss circuit can lose low-frequency signal energy, and the second insertion loss circuit can lose high-frequency signal energy, which can maximize signal loss and further reduce EMC energy interference.
  • the target swing amplitude value in the swing amplitude adjustment table corresponds to the insertion loss unit one-to-one, that is, the target swing amplitude value in the swing amplitude adjustment table, the first insertion loss circuit and the second insertion loss in the same insertion loss unit
  • the three circuits have a one-to-one correspondence relationship, which can reduce the design difficulty.
  • the target swing amplitude value in the swing amplitude adjustment table and the insertion loss unit may not have a one-to-one correspondence.
  • the first insertion loss circuit includes: a capacitor C1, a first switch S5, a first ground terminal GND, and a second ground terminal Ground; both ends of the capacitor C1 are respectively
  • the first ground terminal GND is connected to the first terminal (not marked in FIG. 6) of the first switch S5, and the second terminal (not marked in FIG. 6) of the first switch S5 is connected to the second ground terminal Ground.
  • the second insertion loss circuit includes: a magnetic bead B1, a second switch S1, a third ground terminal GND, and a fourth ground terminal Ground; both ends of the magnetic bead B1 are connected to the third ground terminal GND and the second ground terminal respectively.
  • the first terminal (not marked in FIG. 7) of the switch S1 and the second terminal (not marked in FIG. 7) of the second switch 7 are connected to the fourth ground terminal Ground.
  • FIGS. 6 and 7 respectively take four first insertion loss circuits and four second insertion loss circuits as examples for drawing. At this time, the corresponding swing adjustment table can be as shown in Table 1.
  • the capacitors in the four first insertion loss circuits in Figure 6 are marked as C1, C2, C3, C4, and the first switches corresponding to C1, C2, C3, and C4 are marked as S5, S6, S7, respectively. , S8; the magnetic beads in the four second insertion loss circuits in Figure 7 are respectively marked as B1, B2, B3, B4, and the second switches corresponding to B1, B2, B3, and B4 are respectively marked as S1, S2, S3 , S4.
  • the switches S1-S8 are controlled by the timing control circuit.
  • the first ground terminals of all the first insertion loss circuits and the third ground terminals of all the second insertion loss circuits are the same ground terminal (GND), and the second ground terminals of all the first insertion loss circuits
  • the ground terminal and the fourth ground terminal of all the second insertion loss circuits are the same ground terminal (Ground).
  • the ground terminal GND Pad area is marked as 21, GND is the logic ground of the drive circuit in the timing controller; the ground terminal Ground Pad area is marked as 20, and the ground pad area is marked as 20.
  • Plane shape (Plane Shape) layout the above timing controller is applied to the liquid crystal display, Ground can be the ground area in the back panel of the liquid crystal display; B1-B4, C1-C4 end pins (Pin) use Plane Shape ) Is connected to Ground Pad 20, and one end of the pin is connected to GND Pad 21 through an analog control switch (not shown in Figure 8).
  • the Ground Pad area 20 can be uniformly punched (not shown in FIG. 8).
  • the Ground Pad area 20 can be made of copper and can be fixed by screw holes 22. In this way, when there is EMC energy, the energy can be lost through this circuit.
  • the above timing control circuit is configured to adjust the swing of the M-1th frame signal according to the corresponding relationship between the bit error rate interval in the swing adjustment table and the target swing amplitude.
  • the timing control circuit is configured as:
  • the target swing amplitude corresponding to the bit error rate of the M-1 frame signal is determined.
  • timing control circuit is further configured as:
  • the swing amplitude adjustment table Before the blanking stage of the first frame signal, the swing amplitude adjustment table is stored, where the swing amplitude adjustment table includes multiple error rate intervals, multiple target swing amplitude values, and the corresponding relationship between the error rate interval and the target swing amplitude value .
  • the swing amplitude adjustment table can be referred to as shown in Table 1.
  • the swing amplitude adjustment table includes 4 bit error rate intervals and 4 target swing amplitude values for example.
  • An embodiment of the present disclosure provides a display device including: the aforementioned timing controller.
  • the display device can be a rigid display device or a flexible display device (that is, bendable, foldable); its type can be twisted nematic (TN) type, vertical alignment (VA) type , In-Plane Switching (IPS) type or Advanced Super Dimension Switch (ADS) type liquid crystal display devices, and can also be organic light-emitting diode (Organic Light-Emitting Diode, OLED) display devices, and Including these display devices, televisions, digital cameras, mobile phones, tablet computers, and any other products or components with display functions.
  • TN twisted nematic
  • VA vertical alignment
  • IPS In-Plane Switching
  • ADS Advanced Super Dimension Switch
  • the embodiment of the present disclosure provides a display device, which has a good display screen, strong resistance to electromagnetic interference, weak interference, and good user experience.
  • the embodiment of the present disclosure provides a signal adjustment method, which is applied to the aforementioned timing controller.
  • the timing controller includes a receiving circuit and a plurality of insertion loss circuits.
  • the receiving circuit is configured to receive N frame signals. Methods include:
  • S02. Adjusting the swing amplitude of the M-1th frame signal according to the target swing amplitude value corresponding to the bit error rate of the M-1th frame signal may include:
  • S02a Determine the bit error rate of the M-1th frame signal and the bit error rate interval to which it belongs in the pre-stored swing adjustment table;
  • the embodiment of the present disclosure provides a signal adjustment method.
  • this signal adjustment method it is possible to adjust the signal swing while adopting the insertion loss circuit loss to adjust the energy generated by the signal swing, thereby improving the quality of the input signal. At the same time, reduce the EMC interference caused by the enhanced signal.
  • S02b. Adjusting the swing amplitude of the M-1th frame signal according to the corresponding relationship between the bit error rate interval in the swing amplitude adjustment table and the target swing amplitude value includes:
  • the target swing amplitude corresponding to the bit error rate of the M-1 frame signal is determined.
  • the method before the blanking stage of the first frame signal, the method further includes: storing a swing adjustment table, where the swing adjustment table includes multiple bit error rate intervals, multiple target swing values, and bit error rate. Correspondence between interval and swing amplitude.
  • the blanking phase of the M-th frame signal includes an initial phase, an intermediate phase, and an end phase.
  • detecting the bit error rate of the M-1th frame signal includes:
  • the bit error rate of the M-1th frame signal is detected.
  • the method includes:
  • S104 Determine whether the bit error rate of the first frame signal is the same as the initial bit error rate interval in the swing adjustment table.
  • S201 In the blanking stage of the third frame signal, detect the bit error rate of the second frame signal.
  • S202 Determine the bit error rate of the second frame signal, and the bit error rate interval to which it belongs in the prestored swing adjustment table.
  • the adjustment method of the signal from the third frame to the last frame is similar to the adjustment method of the signal of the second frame, and will not be described in detail here.
  • the signal adjustment method belongs to the adaptive signal adjustment method, which can adjust the signal quality in real time and improve the picture quality; at the same time, according to the target swing amplitude of the signal, the insertion loss circuit is used to lose energy, which reduces the EMC risk, reduces the panel interference ability and increases Great its anti-interference ability.
  • the device embodiments described above are merely illustrative, where the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in One place, or it can be distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the objectives of the solutions of the embodiments. Those of ordinary skill in the art can understand and implement it without creative work.
  • the various component embodiments of the present disclosure may be implemented by hardware, or by software modules running on one or more processors, or by a combination of them.
  • a microprocessor or a digital signal processor (DSP) may be used in practice to implement some or all of the functions of some or all of the components in the electronic device according to the embodiments of the present disclosure.
  • DSP digital signal processor
  • the present disclosure can also be implemented as a device or device program (for example, a computer program and a computer program product) for executing part or all of the methods described herein.
  • Such a program for realizing the present disclosure may be stored on a computer-readable medium, or may have the form of one or more signals.
  • Such a signal can be downloaded from an Internet website, or provided on a carrier signal, or provided in any other form.
  • FIG. 11 shows a computing processing device that can implement the method according to the present disclosure.
  • the electronic device traditionally includes a processor 1010 and a computer program product in the form of a memory 1020 or a computer-readable medium.
  • the memory 1020 may be an electronic memory such as flash memory, EEPROM (Electrically Erasable Programmable Read Only Memory), EPROM, hard disk, or ROM.
  • the memory 1020 has a storage space 1030 for executing program codes 1031 of any method steps in the above methods.
  • the storage space 1030 for program codes may include various program codes 1031 respectively used to implement various steps in the above method. These program codes can be read from or written into one or more computer program products.
  • These computer program products include program code carriers such as hard disks, compact disks (CDs), memory cards, or floppy disks.
  • Such a computer program product is usually a portable or fixed storage unit as described with reference to FIG. 12.
  • the storage unit may have storage segments, storage spaces, etc. arranged similarly to the storage 1020 in the electronic device of FIG. 11.
  • the program code can be compressed in an appropriate form, for example.
  • the storage unit includes computer readable codes 1031', that is, codes that can be read by, for example, a processor such as 1010. When run by an electronic device, these codes cause the electronic device to execute each of the methods described above. step.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Multimedia (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种时序控制器包括：接收电路、时序控制电路、多个插损电路；接收电路被配置为接收N帧信号；时序控制电路时序控制电路被配置为在第M帧信号的消隐阶段，检测第M-1帧信号的误码率；根据所述第M-1帧信号的误码率对应的目标摆幅值，调整所述第M-1帧信号的摆幅；根据第M-1帧信号的误码率对应的目标摆幅值，选择对应的插损电路；M、N均为正整数且1＜M≤N。本公开应用于时序控制器的信号调整。

Description

时序控制器、显示装置、信号调整方法
本公开要求在2020年01月13日提交中国专利局、申请号为202010032632.1、名称为“一种时序控制器、显示装置、信号调整方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，尤其涉及一种时序控制器、显示装置、信号调整方法。
背景技术
显示面板显示画面需要前端系统提供输入信号，如RGB(红绿蓝)信号、低电压差分信号(Low-Voltage Differential Signaling，LVDS)信号、嵌入式显示端口(Embedded Display Port，EDP)信号等。这些输入信号包含RGB灰阶数据信号、控制信号、时钟信号等，因此输入信号的质量决定了显示面板画质的好坏。
前端系统提供的输入信号受以下三个因素影响：第一个是受信号生成时本身质量的影响；第二个是受输入信号传输线中电阻电容的影响；第三个是受外界电磁场的影响。影响输入信号质量的因素较多，而一旦输入信号的质量变差，会直接造成画面偏色、闪屏等问题，因此提升显示面板输入信号的质量是非常重要的。
概述
为达到上述目的，本公开的实施例采用如下技术方案：
一方面，提供了一种时序控制器，包括：接收电路、时序控制电路、多个插损电路；所述接收电路、所述插损电路分别与所述时序控制电路相连；
所述接收电路被配置为：接收N帧信号；
所述时序控制电路被配置为：
在第M帧信号的消隐阶段，检测第M-1帧信号的误码率；
根据所述第M-1帧信号的误码率对应的目标摆幅值，调整所述第M-1帧信号的摆幅；
根据所述第M-1帧信号的误码率对应的所述目标摆幅值，选择对应的所述插损电路，以损耗调整所述第M-1帧信号的摆幅所产生的能量；
其中，M、N均为正整数，且1＜M≤N。
可选的，根据所述第M-1帧信号的误码率对应的目标摆幅值，调整所述第M-1帧信号的摆幅，包括：
确定所述第M-1帧信号的误码率所属的误码率区间；
根据所述误码率区间与目标摆幅值的对应关系，调整所述第M-1帧信号的摆幅。
可选的，多个所述插损电路分为多组插损单元，每组所述插损单元包括第一插损电路和第二插损电路，所述第一插损电路用于损耗第一频率的信号，所述第二插损电路用于损耗第二频率的信号，所述第一频率小于所述第二频率。
可选的，所述目标摆幅值与所述插损单元一一对应。
可选的，每组所述插损单元中，所述第一插损电路包括：电容、第一开关、第一接地端和第二接地端；所述电容的两端分别连接第一接地端和第一开关的第一端，所述第一开关的第二端连接所述第二接地端；
所述第二插损电路包括：磁珠、第二开关、第三接地端和第四接地端；所述磁珠的两端分别连接第三接地端和第二开关的第一端，所述第二开关的第二端连接所述第四接地端。
可选的，多个所述第一插损电路的所述第一接地端和多个所述第二插损电路的所述第三接地端为同一接地端，多个所述第一插损电路的所述第二接地端和多个所述第二插损电路的所述第四接地端为同一接地端。
可选的，所述时序控制电路根据所述摆幅调节表中误码率区间与目标摆幅值的对应关系，调整所述第M-1帧信号的摆幅包括：
时序控制电路根据所述摆幅调节表中误码率区间与目标摆幅值的对应关系，确定所述第M-1帧信号的误码率对应的所述目标摆幅值；
调整所述第M-1帧信号的摆幅值为所述第M-1帧信号的误码率对应的所述目标摆幅值。
可选的，所述误码率区间和所述目标摆幅值的关系存储在摆幅调节表中。
可选的，所述时序控制电路还被配置为：
在第1帧信号的消隐阶段之前，存储所述摆幅调节表，其中，所述摆幅 调节表包括多个所述误码率区间、多个所述目标摆幅值、所述误码率区间与所述目标摆幅值的对应关系。
另一方面，提供了一种显示装置，包括上述的时序控制器。
再一方面，提供了一种信号调整方法，应用于上述的时序控制器，所述时序控制器包括接收电路和多个插损电路，所述接收电路被配置为接收N帧信号，所述方法包括：
在第M帧信号的消隐阶段，检测第M-1帧信号的误码率；
根据所述第M-1帧信号的误码率对应的目标摆幅值，调整所述第M-1帧信号的摆幅；
根据所述第M-1帧信号的误码率对应的所述目标摆幅值，选择对应的所述插损电路，以损耗调整所述第M-1帧信号的摆幅所产生的能量；
其中，M、N均为正整数，且1＜M＜N。
可选的，所述根据所述第M-1帧信号的误码率对应的目标摆幅值，调整所述第M-1帧信号的摆幅，包括：
确定所述第M-1帧信号的误码率所属的误码率区间；
根据所述误码率区间与目标摆幅值的对应关系，调整所述第M-1帧信号的摆幅。
可选的，所述根据所述摆幅调节表中误码率区间与目标摆幅值的对应关系，调整所述第M-1帧信号的摆幅包括：
根据所述摆幅调节表中误码率区间与目标摆幅值的对应关系，确定所述第M-1帧信号的误码率对应的所述目标摆幅值；
调整所述第M-1帧信号的摆幅值为所述第M-1帧信号的误码率对应的所述目标摆幅值。
可选的，在第1帧信号的消隐阶段之前，所述方法还包括：
存储所述摆幅调节表，其中，所述摆幅调节表包括多个所述误码率区间、多个所述目标摆幅值、所述误码率区间与所述摆幅值的对应关系。
可选的，所述第M帧信号的消隐阶段包括起始阶段、中间阶段和结束阶段；
所述在第M帧信号的消隐阶段，检测第M-1帧信号的误码率包括：
在第M帧信号的消隐阶段的中间阶段，检测第M-1帧信号的误码率。
再一方面，公开一种非易失性计算机可读存储介质，包含计算程序， 所述计算机程序在被电子设备执行时，所述电子设备执行前述的信号调整方法。
再一方面，公开一种计算机程序产品，包含计算机程序，所述计算机程序在被电子设备执行时，所述电子设备执行前述的信号调整方法。
上述说明仅是本公开技术方案的概述，为了能够更清楚了解本公开的技术手段，而可依照说明书的内容予以实施，并且为了让本公开的上述和其它目的、特征和优点能够更明显易懂，以下特举本公开的具体实施方式。
附图简述
为了更清楚地说明本公开实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为相关技术提供的一种输入信号的眼图；
图2为相关技术提供的另一种输入信号的眼图；
图3为本公开实施例提供的一种时序控制器的结构示意图；
图4为本公开实施例提供的一种信号示意图；
图5为本公开实施例提供的另一种信号示意图；
图6为本公开实施例提供的一种第一插损电路的示意图；
图7为本公开实施例提供的一种第二插损电路的示意图；
图8为本公开实施例提供的一种插损电路的设计版图；
图9为本公开实施例提供的一种信号调整方法的流程示意图；
图10为本公开实施例提供的另一种信号调整方法的流程示意图；
图11示意性地示出了用于执行根据本公开的方法的电子设备的框图；
图12示意性地示出了用于保持或者携带实现根据本公开的方法的计算机程序代码的存储单元。
详细描述
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做 出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
在本公开的实施例中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
相关技术中的提升输入信号质量的方法是：显示面板的控制芯片TCON芯片在接收到前端系统传送的输入信号后，对信号的摆幅(即信号Swing)进行调整，这样可以使信号的波动明显，从而更易获得有效的信号输出。参考图1所示，原输入信号的眼图中，眼高约为182mV。将图1所示的输入信号的摆幅增大后，其信号的眼图如图2所示，眼高约为426mV，增幅约为240mV，信号质量得到了提升，显示面板更易从图2所示的信号中获得有效信号。
但是信号的摆幅提升后，由于信号得到了增强，显示面板的电磁兼容性(Electromagnetic Compatibility，EMC)也会随之增大，这样不仅会对周边电子产品产生电磁干扰，而且更易受其它电子产品的干扰。
本公开的实施例提供一种时序控制器、显示装置、信号调整方法，该时序控制器可以在提升输入信号质量的同时，降低因增强信号带来的EMC干扰。
本公开实施例提供了一种时序控制器，参考图3所示，该时序控制器包括：接收电路1、时序控制电路2、多个插损电路3；接收电路1、插损电路3分别与时序控制电路2相连。
接收电路被配置为接收N帧信号。
一实施例中，时序控制电路被配置为：
在第M帧信号的消隐阶段，检测第M-1帧信号的误码率；
根据所述第M-1帧信号的误码率对应的目标摆幅值，调整所述第M-1帧信号的摆幅；
根据第M-1帧信号的误码率对应的目标摆幅值，选择对应的插损电路，以损耗调整第M-1帧信号的摆幅所产生的能量；其中，M、N均为正整数，且1＜M≤N。
可选地，根据所述第M-1帧信号的误码率对应的目标摆幅值，调整所述第M-1帧信号的摆幅，这一操作可以包括：
确定第M-1帧信号的误码率，在预存的摆幅调节表中所属的误码率区间；以及
根据摆幅调节表中误码率区间与目标摆幅值的对应关系，调整第M-1帧信号的摆幅。
上述接收电路可以包括接口，该接口类型不做限定，可以根据前端系统输出的信号类型确定。
时序控制电路可以为利用印刷或其他的方式印制在电路板上的电路，或是时序控制芯片等，上述时序控制芯片的类型也不做限定，其可以是单片机、ARM(Advanced RISC Machines，高级精简指令集运算机器)或者FPGA(Field Programmable Gate Array，现场可编程门阵列)等芯片，具体可以根据实际设计要求确定。
上述插损电路的具体结构和数量均不做限定，只要可以满足损耗信号能量的作用即可。图3中以时序控制器包括3个插损电路为例进行绘示。
需要说明的是，参考图4所示，以帧频为分时点，一帧信号包括有效区10和消隐区11；其中，有效区(active zone)对应信号的有效时间，消隐区(blanking zone)对应信号的准备时间。将上述时序控制器应用到显示装置中，有效区对应显示画面阶段，消隐区对应不显示画面阶段(消隐区对应时间非常短暂，人眼难以感受)。上述第M帧信号的消隐阶段即对应第M帧信号的消隐区。参考图5所示，本公开中，在消隐区11增加了误码率(Bit Error Rate,BER)检测区112，即在第M帧信号的消隐阶段进行第M-1帧信号的误码率的侦测。
上述摆幅调节表可以预存在时序控制电路，表中的误码率区间与目标摆幅值的具体内容可以根据实际情况而定。
本公开的实施例提供了一种时序控制器，该时序控制器(Timing Controller,TCON)在调整信号摆幅的同时，采用插损电路损耗调整信号摆幅所产生的能量，从而可以在提升输入信号质量的同时，降低因增强信号带来的EMC干扰。
可选的，所有插损电路分为多组插损单元，每组插损单元包括第一插损电路和第二插损电路，第一插损电路用于损耗第一频率的信号，第二插损电路用于损耗第二频率的信号，第一频率小于第二频率。
信号有高频信号和低频信号之分，采用第一插损电路可以损耗低频信号能量，采用第二插损电路损耗高频信号能量，这样可以最大程度地损耗信号，进一步降低EMC能量干扰。
可选的，摆幅调节表中的目标摆幅值与插损单元一一对应，即摆幅调节 表中的目标摆幅值、同一插损单元中的第一插损电路、第二插损电路三者是一一相互对应关系，可以降低设计难度。在其他可选的实施例中，摆幅调节表中的目标摆幅值与插损单元也可以不是一一对应的关系。
可选的，每组插损单元中，参考图6所示，第一插损电路包括：电容C1、第一开关S5、第一接地端GND和第二接地端Ground；电容C1的两端分别连接第一接地端GND和第一开关S5的第一端(图6未标记)，第一开关S5的第二端(图6未标记)连接第二接地端Ground。
参考图7所示，第二插损电路包括：磁珠B1、第二开关S1、第三接地端GND和第四接地端Ground；磁珠B1的两端分别连接第三接地端GND和第二开关S1的第一端(图7未标记)，第二开关7的第二端(图7未标记)连接第四接地端Ground。
需要说明的是，图6和图7分别以四个第一插损电路和四个第二插损电路为例进行绘示，此时对应的摆幅调节表可以如表一所示。
表一
误码率区间 目标摆幅值
≤BER1 Swing1
BER1-BER2 Swing2
BER2-BER3 Swing3
≥BER3 Swing4
为了便于描述，图6中四个第一插损电路中的电容分别标记为C1、C2、C3、C4，与C1、C2、C3、C4分别对应的第一开关分别标记为S5、S6、S7、S8；图7中四个第二插损电路中的磁珠分别标记为B1、B2、B3、B4，与B1、B2、B3、B4分别对应的第二开关分别标记为S1、S2、S3、S4。这里开关S1-S8由时序控制电路控制，当目标摆幅值位于档位1(Swing1)时，S1及S5闭合，组成档位1插损单元；当目标摆幅值位于档位2(Swing2)时，S2及S6闭合，组成档位2插损单元，依此类推。每个档位的插损单元中的磁珠(Bead)及电容的值通过提前模拟调试确定。
结合图6和图7所示，所有第一插损电路的第一接地端和所有第二插损电路的第三接地端为同一接地端(GND)，所有第一插损电路的第二接地端和所有第二插损电路的第四接地端为同一接地端(Ground)。
上述图6和图7的版图(Layout)可以参考图8所示，接地端GND Pad区域标记为21，GND为时序控制器中驱动电路的逻辑地；接地端Ground Pad区域标记为20，采用面状(Plane Shape)布置，将上述时序控制器应用到液 晶显示器中，Ground可以是液晶显示器的背板中的接地区；B1-B4、C1-C4一端引脚(Pin)用面状(Plane Shape)方式与Ground Pad20连接，一端引脚通过模拟控制开关(图8未示出)后与GND Pad21连接。为了提高散热性，Ground Pad区域20可均匀打孔(图8未示出)。图8中，Ground Pad区域20可以采用铜皮制作，并可以通过螺丝孔22固定。这样，当有EMC能量时，能量可通过此电路损耗掉。
可选的，为了降低调整信号摆幅的难度，上述时序控制电路被配置为：根据摆幅调节表中误码率区间与目标摆幅值的对应关系，调整第M-1帧信号的摆幅包括：
时序控制电路被配置为：
根据摆幅调节表中误码率区间与目标摆幅值的对应关系，确定第M-1帧信号的误码率对应的目标摆幅值。
调整第M-1帧信号的摆幅值为第M-1帧信号的误码率对应的目标摆幅值。
可选的，时序控制电路还被配置为：
在第1帧信号的消隐阶段之前，存储摆幅调节表，其中，摆幅调节表包括多个误码率区间、多个目标摆幅值、误码率区间与目标摆幅值的对应关系。该摆幅调节表可以参考表1所示，表1以摆幅调节表包括4个误码率区间和4个目标摆幅值为例进行绘示。
本公开实施例提供了一种显示装置，包括：前述的时序控制器。
该显示装置可以是刚性的显示装置，也可以是柔性的显示装置(即可弯曲、可折叠)；其类型可以是扭曲向列(Twisted Nematic，TN)型、垂直取向(Vertical Alignment，VA)型、平面转换(In-Plane Switching，IPS)型或高级超维场转换(Advanced Super Dimension Switch，ADS)型等液晶显示装置，还可以是有机发光二极管(Organic Light-Emitting Diode，OLED)显示装置以及包括这些显示装置的电视、数码相机、手机、平板电脑等任何具有显示功能的产品或者部件。
本公开的实施例提供了一种显示装置，该显示装置的显示画面好，抗电磁干扰性强，干扰性弱，用户体验佳。
本公开实施例提供了一种信号调整方法，应用于前述的时序控制器，时 序控制器包括接收电路和多个插损电路，接收电路被配置为接收N帧信号，参考图9所示，该方法包括：
S01、在第M帧信号的消隐阶段，检测第M-1帧信号的误码率。
S02、根据所述第M-1帧信号的误码率对应的目标摆幅值，调整所述第M-1帧信号的摆幅；
S03、根据第M-1帧信号的误码率对应的目标摆幅值，选择对应的插损电路，以损耗调整第M-1帧信号的摆幅所产生的能量；其中，M、N均为正整数，且1＜M＜N。
需要说明的是，上述S01-S03均在第M帧信号的消隐阶段完成，这样不影响正常显示。
可选的，S02、根据所述第M-1帧信号的误码率对应的目标摆幅值，调整所述第M-1帧信号的摆幅，可以包括：
S02a、确定第M-1帧信号的误码率，在预存的摆幅调节表中所属的误码率区间；以及
S02b、根据摆幅调节表中误码率区间与目标摆幅值的对应关系，调整第M-1帧信号的摆幅。
本公开的实施例提供了一种信号调整方法，采用该信号调整方法，可以在调整信号摆幅的同时，采用插损电路损耗调整信号摆幅所产生的能量，从而可以在提升输入信号质量的同时，降低因增强信号带来的EMC干扰。
可选的，S02b、根据摆幅调节表中误码率区间与目标摆幅值的对应关系，调整第M-1帧信号的摆幅包括：
根据摆幅调节表中误码率区间与目标摆幅值的对应关系，确定第M-1帧信号的误码率对应的目标摆幅值。
调整第M-1帧信号的摆幅值为第M-1帧信号的误码率对应的目标摆幅值。
可选的，在第1帧信号的消隐阶段之前，该方法还包括：存储摆幅调节表，其中，摆幅调节表包括多个误码率区间、多个目标摆幅值、误码率区间与摆幅值的对应关系。
可选的，第M帧信号的消隐阶段包括起始阶段、中间阶段和结束阶段。
在第M帧信号的消隐阶段，检测第M-1帧信号的误码率包括：
在第M帧信号的消隐阶段的中间阶段，检测第M-1帧信号的误码率。
由于在消隐阶段的起始阶段和结束阶段，一般还会进行其它信号处理。 在第M帧信号的消隐阶段的中间阶段进行检测，可以避免互相影响，提高检测的准确率。
下面具体说明如何调整第1帧信号的摆幅。参考图10所示，该方法包括：
S101、在第1帧信号的消隐阶段，设置第1帧信号对应的初始误码率区间和初始摆幅值。
S102、在第2帧信号的消隐阶段，检测第1帧信号的误码率。
S103、确定第1帧信号的误码率，在预存的摆幅调节表中所属的误码率区间。
S104、判断第1帧信号的误码率，在摆幅调节表中所属的误码率区间与初始误码率区间是否相同。
S105、若是，则将第1帧信号的摆幅调整至初始摆幅值，并选择初始摆幅值对应的插损电路，以损耗调整第1帧信号的摆幅所产生的能量。
S106、若否，则确定第1帧信号的误码率对应的目标摆幅值，将第1帧信号的摆幅调整至目标摆幅值，并选择与目标摆幅值对应的插损电路，以损耗调整第1帧信号的摆幅所产生的能量。
在S105或者S106之后，进行下一帧信号(即第2帧信号)的调整，具体方法包括：
S201、在第3帧信号的消隐阶段，检测第2帧信号的误码率。
S202、确定第2帧信号的误码率，在预存的摆幅调节表中所属的误码率区间。
S203、根据摆幅调节表中误码率区间与目标摆幅值的对应关系，确定第2帧信号的误码率对应的目标摆幅值；调整第2帧信号的摆幅值为第2帧信号的误码率对应的目标摆幅值。
S204、根据第2帧信号的误码率对应的目标摆幅值，选择对应的插损电路，以损耗调整第2帧信号的摆幅所产生的能量。
依此类推，直到将所有帧信号都调整完毕。第3帧到最后一帧信号的调整方法与第2帧信号的调整方法类似，这里不再详细说明。该信号调整方法属于自适应信号调整方法，可以实时调整信号质量，提升画面品质；同时，根据信号的目标摆幅值，同步采用插损电路损耗能量，降低EMC风险，减小面板干扰能力及增大其抗干扰能力。
以上所描述的装置实施例仅仅是示意性的，其中所述作为分离部件说 明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部模块来实现本实施例方案的目的。本领域普通技术人员在不付出创造性的劳动的情况下，即可以理解并实施。
本公开的各个部件实施例可以以硬件实现，或者以在一个或者多个处理器上运行的软件模块实现，或者以它们的组合实现。本领域的技术人员应当理解，可以在实践中使用微处理器或者数字信号处理器(DSP)来实现根据本公开实施例的电子设备中的一些或者全部部件的一些或者全部功能。本公开还可以实现为用于执行这里所描述的方法的一部分或者全部的设备或者装置程序(例如，计算机程序和计算机程序产品)。这样的实现本公开的程序可以存储在计算机可读介质上，或者可以具有一个或者多个信号的形式。这样的信号可以从因特网网站上下载得到，或者在载体信号上提供，或者以任何其他形式提供。
例如，图11示出了可以实现根据本公开的方法的计算处理设备。该电子设备传统上包括处理器1010和以存储器1020形式的计算机程序产品或者计算机可读介质。存储器1020可以是诸如闪存、EEPROM(电可擦除可编程只读存储器)、EPROM、硬盘或者ROM之类的电子存储器。存储器1020具有用于执行上述方法中的任何方法步骤的程序代码1031的存储空间1030。例如，用于程序代码的存储空间1030可以包括分别用于实现上面的方法中的各种步骤的各个程序代码1031。这些程序代码可以从一个或者多个计算机程序产品中读出或者写入到这一个或者多个计算机程序产品中。这些计算机程序产品包括诸如硬盘，紧致盘(CD)、存储卡或者软盘之类的程序代码载体。这样的计算机程序产品通常为如参考图12所述的便携式或者固定存储单元。该存储单元可以具有与图11的电子设备中的存储器1020类似布置的存储段、存储空间等。程序代码可以例如以适当形式进行压缩。通常，存储单元包括计算机可读代码1031’，即可以由例如诸如1010之类的处理器读取的代码，这些代码当由电子设备运行时，导致该电子设备执行上面所描述的方法中的各个步骤。
需要说明的是，本实施例中关于时序控制器的相关内容可以参考前述实施例，这里不再赘述。
本文中所称的“一个实施例”、“实施例”或者“一个或者多个实施例”意味着，结合实施例描述的特定特征、结构或者特性包括在本公开的至少一个实施例中。此外，请注意，这里“在一个实施例中”的词语例子不一定全指同一个实施例。
在此处所提供的说明书中，说明了大量具体细节。然而，能够理解，本公开的实施例可以在没有这些具体细节的情况下被实践。在一些实例中，并未详细示出公知的方法、结构和技术，以便不模糊对本说明书的理解。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (17)

  1. 一种时序控制器，包括：接收电路、时序控制电路、多个插损电路；
    所述接收电路、所述插损电路分别与所述时序控制电路相连；
    所述接收电路被配置为接收N帧信号；
    所述时序控制电路被配置为：
    在第M帧信号的消隐阶段，检测第M-1帧信号的误码率；
    根据所述第M-1帧信号的误码率对应的目标摆幅值，调整所述第M-1帧信号的摆幅；
    根据所述第M-1帧信号的误码率对应的所述目标摆幅值，选择对应的所述插损电路，以损耗调整所述第M-1帧信号的摆幅所产生的能量；
    其中，M、N均为正整数，且1＜M≤N。
  2. 根据权利要求1所述的时序控制器，其中，所述根据所述第M-1帧信号的误码率对应的目标摆幅值，调整所述第M-1帧信号的摆幅，包括：
    确定所述第M-1帧信号的误码率所属的误码率区间；
    根据所述误码率区间与目标摆幅值的对应关系，调整所述第M-1帧信号的摆幅。
  3. 根据权利要求1或2所述的时序控制器，其中，多个所述插损电路被分为多组插损单元，每组所述插损单元包括第一插损电路和第二插损电路，所述第一插损电路用于损耗第一频率的信号，所述第二插损电路用于损耗第二频率的信号，所述第一频率小于所述第二频率。
  4. 根据权利要求3所述的时序控制器，其中，所述目标摆幅值与所述插损单元一一对应。
  5. 根据权利要求3或4所述的时序控制器，其中，每组所述插损单元中，所述第一插损电路包括：电容、第一开关、第一接地端和第二接地端；所述电容的两端分别连接第一接地端和第一开关的第一端，所述第一开关的第二端连接所述第二接地端；
    所述第二插损电路包括：磁珠、第二开关、第三接地端和第四接地端；所述磁珠的两端分别连接第三接地端和第二开关的第一端，所述第二开关的第二端连接所述第四接地端。
  6. 根据权利要求5所述的时序控制器，其中，多个所述第一插损电路的所述第一接地端和多个所述第二插损电路的所述第三接地端为同一接地端，多个所述第一插损电路的所述第二接地端和多个所述第二插损电路的所述第四接地端为同一接地端。
  7. 根据权利要求2-6任一项所述的时序控制器，其中，所述时序控制电路根据所述摆幅调节表中误码率区间与目标摆幅值的对应关系，调整所述第M-1帧信号的摆幅包括：
    时序控制电路根据所述摆幅调节表中误码率区间与目标摆幅值的对应关系，确定所述第M-1帧信号的误码率对应的所述目标摆幅值；
    调整所述第M-1帧信号的摆幅值为所述第M-1帧信号的误码率对应的所述目标摆幅值。
  8. 根据权利要求2所述的时序控制器，其中，所述误码率区间和所述目标摆幅值的关系存储在摆幅调节表中。
  9. 根据权利要求7所述的时序控制器，其中，所述时序控制电路还被配置为：
    在第1帧信号的消隐阶段之前，存储摆幅调节表，其中，所述摆幅调节表包括多个所述误码率区间、多个所述目标摆幅值、所述误码率区间与所述目标摆幅值的对应关系。
  10. 一种显示装置，包括：权利要求1-9任一项所述的时序控制器。
  11. 一种信号调整方法，应用于权利要求1-9任一项所述的时序控制器，所述时序控制器包括接收电路和多个插损电路，所述接收电路被配置为接收N帧信号，其特征在于，所述方法包括：
    在第M帧信号的消隐阶段，检测第M-1帧信号的误码率；
    根据所述第M-1帧信号的误码率对应的目标摆幅值，调整所述第M-1帧信号的摆幅；
    根据所述第M-1帧信号的误码率对应的所述目标摆幅值，选择对应的所述插损电路，以损耗调整所述第M-1帧信号的摆幅所产生的能量；
    其中，M、N均为正整数，且1＜M＜N。
  12. 根据权利要求11所述的信号调整方法，其中，所述根据所述第M-1帧信号的误码率对应的目标摆幅值，调整所述第M-1帧信号的摆幅，包括：
    确定所述第M-1帧信号的误码率所属的误码率区间；
    根据所述误码率区间与目标摆幅值的对应关系，调整所述第M-1帧信号的摆幅。
  13. 根据权利要求12所述的信号调整方法，其中，所述根据所述摆幅调节表中误码率区间与目标摆幅值的对应关系，调整所述第M-1帧信号的摆幅包括：
    根据所述摆幅调节表中误码率区间与目标摆幅值的对应关系，确定所述第M-1帧信号的误码率对应的所述目标摆幅值；
    调整所述第M-1帧信号的摆幅值为所述第M-1帧信号的误码率对应的所述目标摆幅值。
  14. 根据权利要求12所述的信号调整方法，其中，在第1帧信号的消隐阶段之前，所述方法还包括：
    存储所述摆幅调节表，其中，所述摆幅调节表包括多个所述误码率区间、多个所述目标摆幅值、所述误码率区间与所述摆幅值的对应关系。
  15. 根据权利要求11-14任一项所述的信号调整方法，其中，所述第M帧信号的消隐阶段包括起始阶段、中间阶段和结束阶段；
    所述在第M帧信号的消隐阶段，检测第M-1帧信号的误码率包括：
    在第M帧信号的消隐阶段的中间阶段，检测第M-1帧信号的误码率。
  16. 一种非易失性计算机可读存储介质，包含计算程序，所述计算机程序在被电子设备执行时，所述电子设备执行如权利要求11-15任一项所述的信号调整方法。
  17. 一种计算机程序产品，包含计算机程序，所述计算机程序在被电子设备执行时，所述电子设备执行如权利要求11-15任一项所述的信号调整方法。
PCT/CN2021/071103 2020-01-13 2021-01-11 时序控制器、显示装置、信号调整方法 WO2021143648A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/424,132 US11769467B2 (en) 2020-01-13 2021-01-11 Timing controller, display device, and signal adjustment method

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202010032632.1 2020-01-13
CN202010032632.1A CN111179804B (zh) 2020-01-13 2020-01-13 一种时序控制器、显示装置、信号调整方法

Publications (1)

Publication Number Publication Date
WO2021143648A1 true WO2021143648A1 (zh) 2021-07-22

Family

ID=70658076

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/071103 WO2021143648A1 (zh) 2020-01-13 2021-01-11 时序控制器、显示装置、信号调整方法

Country Status (3)

Country Link
US (1) US11769467B2 (zh)
CN (1) CN111179804B (zh)
WO (1) WO2021143648A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111179804B (zh) * 2020-01-13 2023-04-18 合肥鑫晟光电科技有限公司 一种时序控制器、显示装置、信号调整方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1838095A (zh) * 2005-03-26 2006-09-27 鸿富锦精密工业（深圳）有限公司 高速信号传输电路
US20070273631A1 (en) * 2006-05-23 2007-11-29 Hsiao-Lan Su Interface circuit for data transmission and method thereof
CN109192127A (zh) * 2018-10-29 2019-01-11 合肥鑫晟光电科技有限公司 时序控制器及其驱动方法、显示装置
CN110299162A (zh) * 2018-03-23 2019-10-01 美光科技公司 信令输出阻抗校准
CN111179804A (zh) * 2020-01-13 2020-05-19 合肥鑫晟光电科技有限公司 一种时序控制器、显示装置、信号调整方法

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4491808A (en) * 1981-11-05 1985-01-01 Mitsubishi Denki Kabushiki Kaisha Equalizer circuit for use in communication unit
JP2006250586A (ja) * 2005-03-08 2006-09-21 Fujitsu Ltd 半導体集積回路、およびその試験方法
JP2007068143A (ja) * 2005-08-05 2007-03-15 Matsushita Electric Ind Co Ltd アンテナ整合器とこれを用いた高周波受信装置
JP2010245749A (ja) * 2009-04-03 2010-10-28 Panasonic Corp ノイズキャンセル部とこれを用いた高周波受信部
KR101187571B1 (ko) * 2010-12-28 2012-10-05 주식회사 실리콘웍스 Ｂｅｒｔ 기능이 추가된 타이밍 컨트롤러와 소스 드라이버 사이의 데이터 전송 방법 및 장치
DE202011110299U1 (de) * 2011-12-02 2013-08-27 Technisat Digital Gmbh TV-Empfangsteil mit Eingangsfiltermitteln zum Unterdrücken von Störleistung in einem Eingangskreis
US9207404B2 (en) * 2013-10-04 2015-12-08 Calient Technologies, Inc. Compound optical circuit switch
KR102229371B1 (ko) * 2014-10-30 2021-03-19 삼성디스플레이 주식회사 로딩 이펙트 제어 장치 및 이를 포함하는 유기 발광 표시 장치
CN104505017A (zh) * 2015-01-26 2015-04-08 京东方科技集团股份有限公司 一种驱动电路及其驱动方法、显示装置
JP6540043B2 (ja) * 2015-01-27 2019-07-10 セイコーエプソン株式会社 ドライバー、電気光学装置及び電子機器
KR102582286B1 (ko) * 2015-12-30 2023-09-22 엘지디스플레이 주식회사 유기발광 표시장치 및 유기발광 표시장치의 화질 보상 방법
CN106098017B (zh) 2016-08-25 2019-02-22 深圳市华星光电技术有限公司 一种降低电磁干扰的驱动方法及驱动装置
US10615757B2 (en) * 2017-06-21 2020-04-07 Skyworks Solutions, Inc. Wide bandwidth envelope trackers
US11024209B2 (en) * 2018-05-03 2021-06-01 Novatek Microelectronics Corp. Integrated circuit and anti-interference method thereof
CN108898986B (zh) * 2018-07-27 2021-08-20 京东方科技集团股份有限公司 显示方法及显示装置
US11165393B2 (en) * 2019-03-25 2021-11-02 Skyworks Solutions, Inc. Envelope tracking for Doherty power amplifiers
US11595005B2 (en) * 2020-01-10 2023-02-28 Skyworks Solutions, Inc. Apparatus and methods for envelope tracking

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1838095A (zh) * 2005-03-26 2006-09-27 鸿富锦精密工业（深圳）有限公司 高速信号传输电路
US20070273631A1 (en) * 2006-05-23 2007-11-29 Hsiao-Lan Su Interface circuit for data transmission and method thereof
CN110299162A (zh) * 2018-03-23 2019-10-01 美光科技公司 信令输出阻抗校准
CN109192127A (zh) * 2018-10-29 2019-01-11 合肥鑫晟光电科技有限公司 时序控制器及其驱动方法、显示装置
CN111179804A (zh) * 2020-01-13 2020-05-19 合肥鑫晟光电科技有限公司 一种时序控制器、显示装置、信号调整方法

Also Published As

Publication number Publication date
US11769467B2 (en) 2023-09-26
CN111179804A (zh) 2020-05-19
CN111179804B (zh) 2023-04-18
US20230162705A1 (en) 2023-05-25

Similar Documents

Publication Publication Date Title
US9773771B2 (en) Display panel
KR102196101B1 (ko) 표시 장치
EP2761613B1 (en) Systems and methods for display temperature detection
US9099028B2 (en) RGBW dynamic color fidelity control
US9437130B2 (en) Display panel and method for manufacturing the same
WO2021143648A1 (zh) 时序控制器、显示装置、信号调整方法
US9990248B2 (en) Display driver integrated circuit and display device having the same
US10303283B2 (en) Touch display panel and control circuit thereof
WO2016008403A1 (zh) 移动终端的控制装置、控制方法及其移动终端
US20160291779A1 (en) Array substrate, touch display panel, and detection method
KR20080009984A (ko) 신호 생성 회로 및 이를 포함하는 액정 표시 장치
CN109036317A (zh) 显示装置和驱动方法
US9972261B2 (en) Liquid crystal display device and GOA circuit
WO2011119295A1 (en) Clock feedthrough and crosstalk reduction method
US10108049B2 (en) Gray scale inversion reduction or prevention in liquid crystal displays
WO2023221627A1 (zh) 写数据信号延迟控制方法、装置、设备和介质
US10862506B2 (en) Encoder, encoding method, decoder, decoding method, and codec system
CN107621982A (zh) 一种调整处理器的性能参数的方法及移动终端
KR100805836B1 (ko) 버스 폭 설정 장치, 디스플레이 장치 그리고 버스 폭 설정방법
TWI441152B (zh) 液晶顯示面板之顯示畫素之驅動電路及其驅動方法
US11107435B2 (en) Display apparatus and method of driving the same
US11393420B2 (en) Display device, pixel circuit and its driving method and driving device
CN103440838B (zh) 一种显示控制方法及显示设备
TW202238558A (zh) 電子紙顯示裝置及其操作方法
US20230206972A1 (en) Circuit and method for setting synchronous dynamic random access memory

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21741486

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21741486

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 21741486

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 28.02.2023)

122 Ep: pct application non-entry in european phase

Ref document number: 21741486

Country of ref document: EP

Kind code of ref document: A1