WO2021143122A1 - 信号处理电路 - Google Patents

信号处理电路 Download PDF

Info

Publication number
WO2021143122A1
WO2021143122A1 PCT/CN2020/108664 CN2020108664W WO2021143122A1 WO 2021143122 A1 WO2021143122 A1 WO 2021143122A1 CN 2020108664 W CN2020108664 W CN 2020108664W WO 2021143122 A1 WO2021143122 A1 WO 2021143122A1
Authority
WO
WIPO (PCT)
Prior art keywords
switch
capacitor
coupled
signal
signal processing
Prior art date
Application number
PCT/CN2020/108664
Other languages
English (en)
French (fr)
Inventor
王仲益
林郁轩
洪自立
Original Assignee
神盾股份有限公司
神亚科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 神盾股份有限公司, 神亚科技股份有限公司 filed Critical 神盾股份有限公司
Priority to US17/792,395 priority Critical patent/US20230041756A1/en
Publication of WO2021143122A1 publication Critical patent/WO2021143122A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/017509—Interface arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C27/00—Electric analogue stores, e.g. for storing instantaneous values
    • G11C27/02—Sample-and-hold arrangements
    • G11C27/024—Sample-and-hold arrangements using a capacitive memory element
    • G11C27/026—Sample-and-hold arrangements using a capacitive memory element associated with an amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices

Definitions

  • the present disclosure relates to signal processing circuits, and more particularly to signal processing circuits that can sample signals through multiple path units.
  • the signal obtained from the panel side can be sampled and transmitted to the integrated circuit side for processing.
  • the panel side has a buffer to transmit the acquired signal to the sampling switch located on the integrated circuit side.
  • the sampling switch When the sampling switch is turned on, the signal is transmitted to the sampling capacitor. Then, when the sampling switch is turned off, the sampled signal is transmitted to the back-end circuit for analysis and processing.
  • the above architecture can be used, because the panel side often has serious parasitic effects, and the thrust of the buffer on the panel side is weak, it takes a long time for the signal to be transmitted to the integrated circuit side, and it takes a long time to store Because of the sampling capacitance, it is not conducive to the performance of signal processing, and it is not easy to improve the signal resolution. Solutions are still needed in this field to improve the performance of signal processing.
  • the embodiment provides a signal processing circuit including a buffer, a first capacitor, a second capacitor, a first switch, and a second switch.
  • the buffer receives an external signal and generates an input signal accordingly.
  • the buffer includes an input terminal to receive the external signal, and an output terminal to output the input signal.
  • the first switch is coupled between the output terminal of the buffer and the first capacitor.
  • the second switch is coupled between the output terminal of the buffer and the second capacitor. The first switch and the second switch are turned on alternately.
  • the signal processing circuit further includes: a third switch coupled between the first switch and a reference voltage terminal; a fourth switch coupled between the second switch and the reference voltage terminal; A fifth switch, coupled between the first capacitor and an operating voltage terminal;
  • a sixth switch coupled between the second capacitor and the operating voltage terminal; a seventh switch, coupled to the first capacitor and the fifth switch; and an eighth switch, including coupled to the first capacitor Between the second capacitor and the seventh switch.
  • the fourth switch, the fifth switch and the eighth switch are turned on, and the third switch, the sixth switch and the seventh switch are turned off.
  • the fourth switch, the fifth switch and the eighth switch are turned off, and the third switch, the sixth switch and the seventh switch are turned on.
  • the signal processing circuit further includes: an amplifier, including a first input terminal, coupled to the seventh switch and the eighth switch, a second input terminal, coupled to the operating voltage terminal, and an output Terminal, outputting an output signal; and a feedback capacitor, coupled between the first input terminal of the amplifier and the output terminal of the amplifier; wherein the output signal corresponds to the input signal.
  • an amplifier including a first input terminal, coupled to the seventh switch and the eighth switch, a second input terminal, coupled to the operating voltage terminal, and an output Terminal, outputting an output signal
  • a feedback capacitor coupled between the first input terminal of the amplifier and the output terminal of the amplifier; wherein the output signal corresponds to the input signal.
  • the signal processing circuit further includes: an integration circuit coupled to the amplifier, and performs an integration operation according to the output signal to generate a result signal.
  • the buffer is arranged on a panel, the first switch, the second switch, the first capacitor and the second capacitor are arranged on an integrated circuit, and the integrated circuit is located outside the panel.
  • the output end of the buffer is coupled to a panel, the buffer, the first switch, the second switch, the first capacitor and the second capacitor are arranged in an integrated circuit, and the integrated circuit is located in Outside of this panel.
  • the signal processing circuit further includes: an integrating circuit coupled to the amplifier, and performing N integration operations according to the output signal corresponding to N time periods; wherein the buffer is arranged on a panel, the first switch, The second switch, the third switch, the fourth switch, the fifth switch, the sixth switch, the seventh switch, the eighth switch, the first capacitor, the second capacitor, the amplifier, and the integral
  • the circuit is arranged in an integrated circuit, the integrated circuit is located outside the panel, the integrated circuit must use a first operating time to transmit a piece of data, the buffer must use a second operating time to transmit the piece of data, the second operation
  • the time is n times the first operation time, n is a positive number greater than zero, and N is the largest positive integer not greater than n.
  • FIG. 1 and FIG. 2 are schematic diagrams of the signal processing circuit in the embodiment.
  • FIG. 3 is an operation clock diagram of the signal processing circuit of FIG. 1 and FIG. 2.
  • Fig. 4 is a schematic diagram of a signal processing circuit in another embodiment.
  • Fig. 5 is a flowchart of a signal processing method of the signal processing circuit of Figs. 1, 2 and 4;
  • Fig. 6 is a schematic diagram of a signal processing circuit in another embodiment.
  • T1 The first period
  • FIG. 1 and 2 are schematic diagrams of the signal processing circuit 100 in the embodiment.
  • the input signal Vin is sampled through the path unit PT1; and in FIG. 2, the input signal Vin is sampled through the path unit PT2.
  • the related details are as follows.
  • Each switch and each capacitor described herein may include a first terminal and a second terminal, and the related coupling methods are as follows.
  • the signal processing circuit 100 may include a buffer 105 and path units PT1 and PT2.
  • the path unit PT1 may include a first switch 110 and a first capacitor C1
  • the path unit PT2 may include a second switch 120 and a second capacitor C2.
  • the buffer 105 may include an input terminal and an output terminal.
  • the input terminal receives the external signal Vx, and the output terminal outputs the input signal Vin.
  • the first terminals of the first switch 110 and the second switch may be coupled to the output terminal of the buffer 105.
  • the first terminal of the first capacitor C1 can be coupled to the second terminal of the first switch 110.
  • the first terminal of the second capacitor C2 can be coupled to the second terminal of the second switch 120.
  • the first switch 110 and the second switch 120 can be turned on alternately, but are not turned on at the same time.
  • the path unit PT1 may further include a third switch 130, a fifth switch 150 and a seventh switch 170.
  • the path unit PT2 may further include a fourth switch 140, a sixth switch 160, and an eighth switch 180.
  • the first terminal of the third switch 130 may be coupled to the second terminal of the first switch 110, and the second terminal may be coupled to the reference voltage terminal VR.
  • the first terminal of the fourth switch 140 may be coupled to the second terminal of the second switch 120, and the second terminal may be coupled to the reference voltage terminal VR.
  • the first terminal of the fifth switch 150 can be coupled to the operating voltage terminal VCM, and the second terminal can be coupled to the second terminal of the first capacitor C1.
  • the first terminal of the sixth switch 160 can be coupled to the second terminal of the second capacitor C2, and the second terminal can be coupled to the operating voltage terminal VCM.
  • the first terminal of the seventh switch 170 can be coupled to the second terminal of the first capacitor C1.
  • the first terminal of the eighth switch 180 can be coupled to the second terminal of the second capacitor C2, and the second terminal can be coupled to the second terminal of the seventh switch 170.
  • the fourth switch 140, the fifth switch 150, and the eighth switch 180 are turned on, and the second switch 120, the third switch 130, the sixth switch 160, and the seventh switch are turned on.
  • the switch 170 is turned off.
  • the signal processing circuit 100 may further include an amplifier 195, a feedback capacitor Cf, and an integrating circuit 198.
  • the first input terminal of the amplifier 195 can be coupled to the second terminal of the seventh switch 170, the second input terminal can be coupled to the operating voltage terminal VCM, and the output terminal can output an output signal Vout, wherein the output signal Vout corresponds to the input signal Vin.
  • the first terminal of the feedback capacitor Cf can be coupled to the first input terminal of the amplifier 195, and the second terminal can be coupled to the output terminal of the amplifier 195.
  • the integration circuit 198 may perform an integration operation according to the output signal Vout to generate the result signal VRR.
  • FIG. 3 is an operation clock diagram of the signal processing circuit 100 of FIG. 1 and FIG. 2.
  • the output signals Vout corresponding to the first time period T1, the second time period T2, and the third time period T3 are respectively denoted as Vout(1), Vout(2), and Vout(3).
  • the output signal Vout corresponding to the period before the first period T1 (hereinafter referred to as the zeroth period) may be expressed as Vout(0).
  • the operation of the signal processing circuit 100 can be as follows.
  • the state of the switch of the signal processing circuit 100 can be as shown in FIG. 1, the first switch 110 is turned on, the second switch 120 is turned off, and the input signal Vin can be transmitted to the first capacitor C1 through the first switch 110 , Thereby gradually storing in the first capacitor C1.
  • the first capacitor c1 samples the input signal Vin, and the amplifier 195 can generate the output signal vout(0) corresponding to the period before the first period T1 (ie, the zeroth period).
  • the signal sampled and stored in the second capacitor C2 in the zeroth period can be transmitted to the amplifier 195 through the eighth switch 180.
  • the level of the input signal Vout(0) can rise accordingly.
  • the integration circuit 198 may perform an integration operation using the output signal V(0).
  • the state of the switch of the signal processing circuit 100 may be as shown in FIG. 2.
  • the first switch 110 is turned off, the second switch 120 is turned on, and the input signal Vin can be passed through the second switch 120. It is transferred to the second capacitor C2 and then stored in the second capacitor C2.
  • the second capacitor c2 can sample the input signal Vin corresponding to the second period T2.
  • the signal sampled in the first period T1 can be transmitted to the amplifier 195 through the seventh switch 170, the amplifier 195 can generate the output signal Vout(1) corresponding to the first period T1, and the integrating circuit 198 can be used
  • the output signal Vout(1) performs an integral operation.
  • the first switch 110 can be turned on, the second switch 120 can be turned off, and the input signal Vin can pass through the first time period T1.
  • the switch 110 and the first capacitor C1 are sampled.
  • the amplifier 195 can generate the output signal Vout(2) corresponding to the second period, and the integration circuit 198 can use the output signal vout(2) to perform an integration operation.
  • the first switch 110 can be turned off, the second switch 120 can be turned on, and the input signal Vin can pass through the second time period T2.
  • the switch 120 and the second capacitor C2 are sampled.
  • the amplifier 195 can generate the output signal Vout(3) corresponding to the third period, and the integration circuit 198 can use the output signal vout(3) to perform an integration operation.
  • the signal processing circuit 100 may allow multiple path units to be used to perform signal sampling and integration simultaneously, thereby achieving pipelined synchronization processing.
  • the amplifier 195 when the signal is sampled through the path unit PT1, the amplifier 195 can generate the output signal Vout according to the signal sampled through the path PT2 in the previous period, so that the integration circuit 198 can perform the integration operation synchronously.
  • the amplifier 195 can generate the output signal Vout according to the signal sampled through the path PT1 in the previous period, so that the integration circuit 198 can perform the integration operation synchronously.
  • the integration circuit 198 can wait for a signal to be gradually transmitted from the buffer 105 to achieve synchronous operation.
  • the buffer 105 may be disposed on the panel P, and the first switch 110 to the eighth switch 180, the first capacitor C1, the second capacitor C2, the feedback capacitor Cf, the amplifier 195, and the integrating circuit 198 It can be provided on the integrated circuit ic, where the integrated circuit ic can be located outside the panel p.
  • the transmission speed of the signal to the panel p is much lower than the transmission speed of the signal to the integrated circuit ic, which is not conducive to signal processing.
  • the speed of signal processing can be increased, and the resolution can be improved.
  • the integration circuit 198 can perform N integration operations according to the output signal Vout corresponding to the N periods.
  • n is a positive number greater than zero
  • the data collected by a single sampling in the prior art can be divided into N samplings in this embodiment, and the noise obtained by multiple samplings can be subtracted from each other during the integration process, which can improve the signal-to-noise ratio, and The resolution of the output signal Vout can be equivalently increased to n1/2 times.
  • FIG. 4 is a schematic diagram of a signal processing circuit 400 in another embodiment.
  • the signal processing circuit 400 may be similar to the signal processing circuit 100 of FIGS. 1 and 2.
  • the output terminal of the buffer 105 can be coupled to the panel P, and the buffer 105, the first switch 110 to the eighth switch 180, the first capacitor C1, the second capacitor C2, the feedback capacitor Cf,
  • the amplifier 195 and the integrating circuit 198 can be disposed on the integrated circuit ic, where the integrated circuit ic can be located outside the panel p.
  • the signal processing circuit 400 can be used in touch applications.
  • Fig. 4 is similar to Fig. 1 in that the first switch 110 is turned on. In another scenario, the state of the switch in FIG. 4 can also be as shown in FIG. 2, and the related operations will not be repeated here.
  • the capacitance cp can represent the load of the panel p.
  • the signal transmission of the buffer 105 will be dragged down.
  • the signal processing circuit 400 it is possible to simultaneously wait for the panel P to enter a steady state while sampling the signal, and use the output signal Vout corresponding to the previous period to perform integration, which can also improve the speed and resolution of signal processing.
  • Each switch described in FIG. 1, FIG. 2 and FIG. 4 may be a transistor switch. If an N-type transistor switch is used, a high voltage can be applied to the control terminal of the switch to turn on the switch. If a P-type transistor switch is used, a low voltage can be applied to the control terminal of the switch to turn on the switch.
  • FIG. 5 is a flowchart of a signal processing method 500 of the signal processing circuit 100 of FIG. 1 and the signal processing circuit 400 of FIG. 4.
  • the signal processing method 500 may include the following steps:
  • S510 Turn on the first switch 110, the fourth switch 140, the fifth switch 150, and the eighth switch 180, and turn off the second switch 120, the third switch 130, the sixth switch 160, and the seventh switch 170;
  • step S510 may be an initial step, and corresponds to FIG. 1.
  • Step S520 may correspond to the second period T2 and the fourth period T4 of FIG. 2 and FIG. 3.
  • Step S530 may correspond to the first time period T1 and the third time period T3 of FIGS. 1 and 3.
  • Steps S520 and S530 can be executed cyclically, so as to control the switches corresponding to the path units PT1 and PT2 in a ping-pong manner.
  • the relevant principles and technical effects can be as above and will not be repeated.
  • FIG. 6 is a schematic diagram of a signal processing circuit 600 in another embodiment.
  • the signal processing circuit 600 may be similar to the signal processing circuit 100, but further includes a path unit PT3.
  • the integration circuit 198 can synchronously perform an integration operation based on the previously sampled signal, thereby improving the processing speed and resolution. Relevant details will not be restated.
  • the input signal can be sampled synchronously, and the integration can be performed based on the previously obtained output signal, thereby reducing the signal of the panel P and the integrated circuit ic
  • the problem caused by the inconsistent transmission speed, and can improve the resolution of the signal, is really helpful for reducing the problems in the field.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Amplifiers (AREA)
  • Analogue/Digital Conversion (AREA)
  • Electrophonic Musical Instruments (AREA)

Abstract

信号处理电路包含缓冲器、第一电容、第二电容、第一开关及第二开关。该缓冲器接收外部信号及据以产生输入信号。该缓冲器包含输入端，接收该外部信号，及输出端，输出该输入信号。该第一开关耦接于该缓冲器的该输出端及该第一电容之间。该第二开关耦接于该缓冲器的该输出端及该第二电容之间。该第一开关及该第二开关交互导通。

Description

信号处理电路 技术领域
本公开涉及信号处理电路，特别涉及可通过多个路径单元采样信号的信号处理电路。
背景技术
于面板相关的信号处理应用，可将从面板端上得到的信号，采样且传至集成电路端，以进行处理。举例来说，面板端具有缓冲器，将获取到的信号传至位于集成电路端的采样开关。当采样开关导通，信号被传至采样电容。而后，当采样开关截止，被采样的信号，传送到后端电路进行分析处理。
上述架构虽可堪用，但因面板端常有严重的寄生效应，且面板端的缓冲器的推力较弱，信号须耗费较长时间方可传至集成电路端，且须较长时间才可存储于采样电容，因此，不利于信号处理的效能，也不易改善信号分辨率。本领域仍须解决方案，以改善信号处理的效能。
发明内容
实施例提供一种信号处理电路，包含一缓冲器、一第一电容、一第二电容、一第一开关及一第二开关。该缓冲器接收一外部信号及据以产生一输入信号。该缓冲器包含一输入端，接收该外部信号，及一输出端，输出该输入信号。该第一开关耦接于该缓冲器的该输出端及该第一电容之间。该第二开关耦接于该缓冲器的该输出端及该第二电容之间。该第一开关及该第二开关交互导通。
优选地，信号处理电路，另包含：一第三开关，耦接于该第一开关及一参考电压端之间；一第四开关，耦接于该第二开关及该参考电压端之间；一第五开关，耦接于该第一电容及一操作电压端之间；
一第六开关，耦接于该第二电容及该操作电压端之间；一第七开关，耦接于该第一电容及该第五开关；及一第八开关，包含耦接于该第二电容及该第七开关之间。
优选地，当该第一开关导通时，该第四开关、该第五开关及该第八开关导通，且该第三开关、该第六开关及该第七开关截止。
优选地，当该第二开关导通时，该第四开关、该第五开关及该第八开关截止，且该第三开关、该第六开关及该第七开关导通。
优选地，信号处理电路，另包含：一放大器，包含一第一输入端，耦接于该第七开关及该第八开关，一第二输入端，耦接于该操作电压端，及一输出端，输出一输出信号；及一反馈电容，耦接于该放大器的该第一输入端及该放大器的该输出端之间；其中该输出信号是对应于该输入信号。
优选地，信号处理电路，另包含：一积分电路，耦接于该放大器，根据该输出信号执 行一积分操作以产生一结果信号。
优选地，该缓冲器设置于一面板，该第一开关、该第二开关、该第一电容及该第二电容设置于一集成电路，且该集成电路位于该面板之外。
优选地，该缓冲器的该输出端耦接于一面板，该缓冲器、该第一开关、该第二开关、该第一电容及该第二电容设置于一集成电路，且该集成电路位于该面板之外。
优选地，信号处理电路，另包含：一积分电路，耦接于该放大器，根据对应于N个时段的该输出信号执行N次积分操作；其中该缓冲器设置于一面板，该第一开关、该第二开关、该第三开关、该第四开关、该第五开关、该第六开关、该第七开关、该第八开关、该第一电容、该第二电容、该放大器及该积分电路设置于一集成电路，该集成电路位于该面板之外，该集成电路须使用一第一操作时间传输一笔数据，该缓冲器须使用一第二操作时间传输该笔数据，该第二操作时间为该第一操作时间的n倍，n为大于零的正数，且N为不大于n的最大正整数。
附图说明
图1及图2为实施例中，信号处理电路的示意图。
图3为图1及图2的信号处理电路的操作时钟图。
图4为另一实施例中，信号处理电路的示意图。
图5为图1、图2及图4的信号处理电路的信号处理方法的流程图。
图6为另一实施例中，信号处理电路的示意图。
附图标记说明：
100,400,600：信号处理电路
105：缓冲器
110：第一开关
120：第二开关
130：第三开关
140：第四开关
150：第五开关
160：第六开关
170：第七开关
180：第八开关
195：放大器
198：积分电路
500：信号处理方法
C1：第一电容
C2：第二电容
CF：反馈电容
CP：电容
IC：集成电路
P：面板
PT1,PT2,PT3：路径单元
S510,S520,S530：步骤
T1：第一时段
T2：第二时段
T3：第三时段
T4：第四时段
VCM：操作电压端
VIN：输入信号
VOUT,VOUT(0),VOUT(2),VOUT(3)：输出信号
VR：参考电压端
VRR：结果信号
VX：外部信号
具体实施方式
图1及图2为实施例中，信号处理电路100的示意图。图1中，输入信号Vin是通过路径单元PT1被采样；而图2中，输入信号Vin是通过路径单元PT2被采样，相关细节如下述。本文所述各开关及各电容可包含第一端及第二端，相关耦接方式如下述。
如图1及图2所示，信号处理电路100可包含缓冲器105及路径单元PT1及PT2。路径单元PT1可包含第一开关110及第一电容C1，且路径单元PT2可包含第二开关120及第二电容C2。
缓冲器105可包含输入端及输出端，其中输入端接收外部信号Vx，输出端输出输入信号Vin。
第一开关110及第二开关的第一端可耦接于缓冲器105的输出端。第一电容C1的第一端可耦接于第一开关110的第二端。第二电容C2的第一端可耦接于第二开关120的第二端。第一开关110及第二开关120可交互导通，不同时导通。
如图1及图2所示，路径单元PT1可另包含第三开关130、第五开关150及第七开关170。路径单元PT2可另包含第四开关140、第六开关160及第八开关180。
第三开关130的第一端可耦接于第一开关110的第二端，且第二端可耦接于参考电压端VR。第四开关140的第一端可耦接于第二开关120的第二端，且第二端可耦接于参考电压端VR。第五开关150的第一端可耦接于操作电压端VCM，且第二端可耦接于第一电容C1的第二端。第六开关160的第一端可耦接于第二电容C2的第二端，且第二端可耦 接于操作电压端VCM。第七开关170的第一端可耦接于第一电容C1的第二端。第八开关180的第一端可耦接于第二电容C2的第二端，且第二端可耦接于第七开关170的第二端。
如图1所示，当第一开关110导通时，第四开关140、第五开关150及第八开关180导通，而第二开关120、第三开关130、第六开关160及第七开关170截止。
可以理解的，如图2所示，当该第二开关120导通时，第一开关110、第四开关140、第五开关150及第八开关180截止，且第三开关130、第六开关160及第七开关170导通。
在另一实施例中，信号处理电路100可另包含放大器195、反馈电容Cf及积分电路198。
放大器195的第一输入端可耦接于第七开关170的第二端，第二输入端可耦接于操作电压端VCM，且输出端可输出输出信号Vout，其中输出信号Vout对应于输入信号Vin。
反馈电容Cf的第一端可耦接于放大器195的第一输入端，且第二端可耦接于放大器195的输出端。
积分电路198可根据输出信号Vout执行积分操作，以产生结果信号VRR。
图3为图1及图2的信号处理电路100的操作时钟图。图3中，对应于第一时段T1、第二时段T2、第三时段T3的输出信号Vout是分别表示为Vout(1)、Vout(2)及Vout(3)。对应于第一时段T1之前的时段(下文称为第零时段)的输出信号Vout可表示为Vout(0)。如图1、图2及图3所示，信号处理电路100的操作可如下述。
于第一时段T1，信号处理电路100的开关的状态可如图1所示，第一开关110导通，第二开关120截止，输入信号Vin可通过第一开关110被传送至第一电容C1，从而逐渐存储于第一电容C1。
于第一时段T1，第一电容c1是采样输入信号Vin，且放大器195可产生对应于第一时段T1之前的时段(即第零时段)的输出信号vout(0)。第零时段被采样及存储于第二电容C2的信号，可通过第八开关180传至放大器195，如图3所示，输入信号Vout(0)的电平可随之上升。第一时段T1中，积分电路198可使用输出信号V(0)执行积分操作。
于第一时段T1后的第二时段T2，信号处理电路100的开关的状态可如图2所示，第一开关110截止，第二开关120导通，输入信号Vin可通过第二开关120被传送至第二电容C2，从而存储于第二电容C2。
于第二时段T2，第二电容c2可采样对应于第二时段T2的输入信号Vin。于第二时段T2中，在第一时段T1采样的信号可通过第七开关170传送到放大器195，放大器195可产生对应于第一时段T1的输出信号Vout(1)，且积分电路198可使用输出信号Vout(1)执行积分操作。
于第二时段T2后的第三时段T3，如图1及图3所示，相似于第一时段T1，第一开关110可导通，第二开关120可截止，输入信号Vin可通过第一开关110及第一电容C1被采样。而于第三时段T3中，放大器195可产生对应于第二时段的输出信号Vout(2)，且积分电路198可使用输出信号vout(2)执行积分操作。
于第三时段T3后的第四时段T4，如图2及图3所示，相似于第二时段T2，第一开关110可截止，第二开关120可导通，输入信号Vin可通过第二开关120及第二电容C2被采样。而于第四时段T4中，放大器195可产生对应于第三时段的输出信号Vout(3)，且积分电路198可使用输出信号vout(3)执行积分操作。
换言之，根据实施例，信号处理电路100可允许使用多个路径单元，同步执行信号的采样及积分，从而达到流水线化(pipeline)的同步处理。如图1及图2所示，当通过路径单元PT1采样信号时，放大器195可根据前一时段通过路径PT2采样的信号，产生输出信号Vout，以使积分电路198可据以同步执行积分操作。而当通过路径单元PT2采样信号时，放大器195可根据前一时段通过路径PT1采样的信号，产生输出信号Vout，以使积分电路198可据以同步执行积分操作。
如上述，当选择第一开关110或第二开关120其中之一进行输入信号VIN的采样时，通过未被选择的另一开关于前一时段中所产生的输出信号VOUT则被积分电路198用以执行积分。当积分电路198执行积分时，可等待信号由缓冲器105逐渐传来，从而达到同步操作。
于图1及图2的实施例，缓冲器105可设置于面板P，且第一开关110至第八开关180、第一电容C1、第二电容C2、反馈电容Cf、放大器195及积分电路198可设置于集成电路ic，其中，集成电路ic可位于面板p之外。
一般而言，信号于面板p的传送速度，远低于信号于集成电路ic的传送速度，不利于信号处理。而通过图1至图3所述的电路及操作方式，可提高信号处理的速度，及改善分辨率。
于图1及图2的实施例中，若集成电路ic须使用第一操作时间传输一笔数据，位于面板p的缓冲器105须使用第二操作时间传输同一笔数据，且第二操作时间为第一操作时间的n倍，则积分电路198可根据对应于N个时段的输出信号Vout执行N次积分操作。其中，n为大于零的正数，且N为不大于n的最大正整数，可表示为N＝floor(n)或
Figure PCTCN2020108664-appb-000001
原本于现有技术中使用单次采样收集的数据，于此实施例中可分为N次采样而得到，而多次采样到的噪声可于积分过程中互相消减，可提高讯杂比，且可等效地将输出信号Vout的分辨率提升至n1/2倍。
图4是另一实施例中，信号处理电路400的示意图。信号处理电路400可相似于图1及图2的信号处理电路100。然而，信号处理电路400中，缓冲器105的输出端可耦接于面板P，且缓冲器105、第一开关110至第八开关180、第一电容C1、第二电容C2、反馈电容Cf、放大器195及积分电路198可设置于集成电路ic，其中，集成电路ic可位于面板p之外。举例而言，信号处理电路400可用于触控应用。
图4是相似于图1，即第一开关110导通的情境。另一情境中，图4的开关的状态亦可如图2所示，于此不重述相关操作。
图4中，电容cp可表示面板p的负载。一般而言，由于面板p的负载较大，会拖累 缓冲器105的信号传输。通过使用信号处理电路400，可于采样信号时，同时等待面板P进入稳态，及使用对应于前一时段的输出信号Vout执行积分，亦可改善信号处理的速度及分辨率。
图1、图2及图4所述的各开关可为晶体管开关。若使用N型晶体管开关，可施加高电压至开关的控制端，以导通开关。若使用P型晶体管开关，可施加低电压至开关的控制端，以导通开关。
图5是图1的信号处理电路100及图4的信号处理电路400的信号处理方法500的流程图。信号处理方法500可包含以下步骤：
S510：导通第一开关110、第四开关140、第五开关150及第八开关180，且截止第二开关120、第三开关130、第六开关160及第七开关170；
S520：截止第一开关110、第四开关140、第五开关150及第八开关180，导通第二开关120、第三开关130、第六开关160及第七开关170，放大器195产生对应于前一时段的输出信号Vout，且积分电路198根据对应于前一时段的输出信号Vout执行积分操作；及
S530：导通第一开关110、第四开关140、第五开关150及第八开关180，截止第二开关120、第三开关130、第六开关160及第七开关170，放大器195产生对应于前一时段的输出信号Vout，且积分电路198根据对应于前一时段的输出信号Vout执行积分操作。
其中，举例而言，步骤S510可为初始步骤，且对应于图1。步骤S520可对应于图2及图3的第二时段T2及第四时段T4。步骤S530可对应于图1及图3的第一时段T1及第三时段T3。
步骤S520及S530可循环执行，从而以乒乓方式控制路径单元PT1及PT2对应的开关。相关的原理及技术效果可如上文，不另重述。
图6是另一实施例中，信号处理电路600的示意图。信号处理电路600可相似于信号处理电路100，但另包含路径单元PT3。图6中，当通过路径单元PT1至PT3的两路径采样信号时，积分电路198可同步根据通过先前采样的信号，执行积分操作，从而改善处理速度与分辨率。相关细节不另重述。
综上，通过使用实施例提供的信号处理电路100、400及600，及信号处理方法500，可同步采样输入信号，及根据先前所得的输出信号执行积分，从而减低面板P及集成电路ic的信号传输速度不一致所产生的问题，且可提高信号的分辨率，对于减少本领域的难题，实有助益。
以上所述仅为本实用新型的优选实施例，凡依本实用新型权利要求所做的变化与修饰，皆应属本实用新型的涵盖范围。

Claims (9)

  1. 一种信号处理电路，其特征在于，包含：
    一缓冲器，接收一外部信号及据以产生一输入信号，该缓冲器包含一输入端，接收该外部信号，及一输出端，输出该输入信号；
    一第一电容；
    一第二电容；
    一第一开关，耦接于该缓冲器的该输出端及该第一电容之间；及
    一第二开关，耦接于该缓冲器的该输出端及该第二电容之间；
    其中，该第一开关及该第二开关交互导通。
  2. 如权利要求1所述的信号处理电路，其特征在于，另包含：
    一第三开关，耦接于该第一开关及一参考电压端之间；
    一第四开关，耦接于该第二开关及该参考电压端之间；
    一第五开关，耦接于该第一电容及一操作电压端之间；
    一第六开关，耦接于该第二电容及该操作电压端之间；
    一第七开关，耦接于该第一电容及该第五开关；及
    一第八开关，包含耦接于该第二电容及该第七开关之间。
  3. 如权利要求2所述的信号处理电路，其特征在于，当该第一开关导通时，该第四开关、该第五开关及该第八开关导通，且该第三开关、该第六开关及该第七开关截止。
  4. 如权利要求2所述的信号处理电路，其特征在于，当该第二开关导通时，该第四开关、该第五开关及该第八开关截止，且该第三开关、该第六开关及该第七开关导通。
  5. 如权利要求2所述的信号处理电路，其特征在于，另包含：
    一放大器，包含一第一输入端，耦接于该第七开关及该第八开关，一第二输入端，耦接于该操作电压端，及一输出端，输出一输出信号；及
    一反馈电容，耦接于该放大器的该第一输入端及该放大器的该输出端之间；
    该输出信号是对应于该输入信号。
  6. 如权利要求5所述的信号处理电路，其特征在于，另包含：
    一积分电路，耦接于该放大器，根据该输出信号执行一积分操作以产生一结果信号。
  7. 如权利要求1至6的任一所述的信号处理电路，其特征在于，该缓冲器设置于一面板，该第一开关、该第二开关、该第一电容及该第二电容设置于一集成电路，且该集成电路位于该面板之外。
  8. 如权利要求1至6的任一所述的信号处理电路，其特征在于，该缓冲器的该输出端耦接于一面板，该缓冲器、该第一开关、该第二开关、该第一电容及该第二电容设置于一集成电路，且该集成电路位于该面板之外。
  9. 如权利要求5所述的信号处理电路，其特征在于，另包含：
    一积分电路，耦接于该放大器，根据对应于N个时段的该输出信号执行N次积分操 作；
    其中该缓冲器设置于一面板，该第一开关、该第二开关、该第三开关、该第四开关、该第五开关、该第六开关、该第七开关、该第八开关、该第一电容、该第二电容、该放大器及该积分电路设置于一集成电路，该集成电路位于该面板之外，该集成电路须使用一第一操作时间传输一笔数据，该缓冲器须使用一第二操作时间传输该笔数据，该第二操作时间为该第一操作时间的n倍，n为大于零的正数，且N为不大于n的最大正整数。
PCT/CN2020/108664 2020-01-13 2020-08-12 信号处理电路 WO2021143122A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/792,395 US20230041756A1 (en) 2020-01-13 2020-08-12 Signal processing circuit

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US202062960153P 2020-01-13 2020-01-13
US62/960,153 2020-01-13

Publications (1)

Publication Number Publication Date
WO2021143122A1 true WO2021143122A1 (zh) 2021-07-22

Family

ID=72859072

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/108664 WO2021143122A1 (zh) 2020-01-13 2020-08-12 信号处理电路

Country Status (4)

Country Link
US (1) US20230041756A1 (zh)
CN (2) CN111817706A (zh)
TW (2) TWM605320U (zh)
WO (1) WO2021143122A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI779595B (zh) 2021-05-06 2022-10-01 瑞昱半導體股份有限公司 訊號偵測電路

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110309235A1 (en) * 2010-06-18 2011-12-22 Canon Kabushiki Kaisha A/d converter, solid-state image sensor using plurality of a/d converters and driving method of a/d converter
CN102944724A (zh) * 2012-12-07 2013-02-27 上海市电力公司 一种电流电压转换器
CN104202049A (zh) * 2014-08-19 2014-12-10 合肥宁芯电子科技有限公司 循环型模数转换器
CN106712754A (zh) * 2015-08-04 2017-05-24 意法半导体研发(深圳)有限公司 用于mos的自适应本体偏置的动态阈值发生器
CN106788276A (zh) * 2015-12-29 2017-05-31 深圳市汇顶科技股份有限公司 转换电路及检测电路

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5159341A (en) * 1991-03-12 1992-10-27 Analog Devices, Inc. Two phase sampling for a delta sigma modulator
US6037887A (en) * 1996-03-06 2000-03-14 Burr-Brown Corporation Programmable gain for delta sigma analog-to-digital converter
US7106241B1 (en) * 2005-09-28 2006-09-12 Sigmatel, Inc. Controlled sampling module and method for use therewith
KR100911652B1 (ko) * 2007-02-13 2009-08-10 삼성전자주식회사 집적 회로, 상기 집적 회로를 포함하는 소스 드라이버, 및 상기 소스 드라이버를 포함하는 디스플레이 장치
US8184184B2 (en) * 2008-12-08 2012-05-22 Omnivision Technologies, Inc. Analog multiplexer configured to reduce kickback perturbation in image sensor readout
KR102092904B1 (ko) * 2013-11-06 2020-03-24 삼성전자주식회사 스위치드-커패시터 적분기, 이의 동작 방법, 및 이를 포함하는 장치들
KR102243635B1 (ko) * 2014-11-21 2021-04-26 엘지디스플레이 주식회사 터치 센싱 회로와 이를 이용한 표시장치 및 터치 센싱 방법
US10331282B2 (en) * 2016-12-30 2019-06-25 Qualcomm Incorporated Highly configurable front end for touch controllers

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110309235A1 (en) * 2010-06-18 2011-12-22 Canon Kabushiki Kaisha A/d converter, solid-state image sensor using plurality of a/d converters and driving method of a/d converter
CN102944724A (zh) * 2012-12-07 2013-02-27 上海市电力公司 一种电流电压转换器
CN104202049A (zh) * 2014-08-19 2014-12-10 合肥宁芯电子科技有限公司 循环型模数转换器
CN106712754A (zh) * 2015-08-04 2017-05-24 意法半导体研发(深圳)有限公司 用于mos的自适应本体偏置的动态阈值发生器
CN106788276A (zh) * 2015-12-29 2017-05-31 深圳市汇顶科技股份有限公司 转换电路及检测电路

Also Published As

Publication number Publication date
TWI778397B (zh) 2022-09-21
TW202127806A (zh) 2021-07-16
CN212413136U (zh) 2021-01-26
CN111817706A (zh) 2020-10-23
US20230041756A1 (en) 2023-02-09
TWM605320U (zh) 2020-12-11

Similar Documents

Publication Publication Date Title
US7675439B2 (en) Serial/parallel data conversion apparatus and method thereof
CN104617957A (zh) 异步逐次逼近型模数转换器
US20090174586A1 (en) Analog to digital converter with dynamically reconfigurable conversion resolution
US10116318B1 (en) Method and system for asynchronous clock generation for successive approximation analog-to-digital converter (SAR ADC)
TW201322643A (zh) 共用電容的積分電路與類比轉數位電路及其操作方法
WO2021143122A1 (zh) 信号处理电路
CN105278776A (zh) 电容电压信息感测电路及其相关抗噪声触控电路
US20210305953A1 (en) Amplifier circuit with distributed dynamic chopping
CN114094996A (zh) 一种校准电路、校准方法、接口和相关设备
US20110148500A1 (en) Sample hold circuit and method thereof for eliminating offset voltage of analog signal
CN105070318A (zh) 一种应用于逐次逼近型模数转换器的高速移位寄存器
Bistritz Testing stability of 2-D discrete systems by a set of real 1-D stability tests
CN109815181B (zh) 一种基于axi协议接口的任意位宽转换方法及装置
US10742196B2 (en) Apparatus and method for performing digital infinite impulse filtering
US10969912B2 (en) Capacitive sensing and sampling circuit and sensing and sampling method thereof
CN108881749B (zh) 一种基于相关双采样的像素单元电路及其相关双采样方法
CN112148655B (zh) 多位数据跨时钟域的处理方法及装置
CN104753520A (zh) 侦测电路与侦测方法
TW202023191A (zh) 除彈跳電路
CN215005738U (zh) 一种数据转换器件验证系统的adc测试电路
TW202114394A (zh) 訊號偵測電路與訊號偵測方法
US11900879B2 (en) Sensing circuit with enhanced dynamic range and accuracy
US11677593B1 (en) Sampler with built-in DFE and offset cancellation
CN110995026B (zh) 一种有源整流器
CN113131938B (zh) 应用于触控检测的积分互容电路及其数据处理方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20913223

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20913223

Country of ref document: EP

Kind code of ref document: A1