WO2021142829A1 - 电荷泵电路、芯片以及电子设备 - Google Patents

电荷泵电路、芯片以及电子设备 Download PDF

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Publication number
WO2021142829A1
WO2021142829A1 PCT/CN2020/072981 CN2020072981W WO2021142829A1 WO 2021142829 A1 WO2021142829 A1 WO 2021142829A1 CN 2020072981 W CN2020072981 W CN 2020072981W WO 2021142829 A1 WO2021142829 A1 WO 2021142829A1
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WIPO (PCT)
Prior art keywords
pad
charge pump
pin
flying capacitor
capacitor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2020/072981
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English (en)
French (fr)
Inventor
刘诗雨
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen Goodix Technology Co Ltd
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Shenzhen Goodix Technology Co Ltd
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Application filed by Shenzhen Goodix Technology Co Ltd filed Critical Shenzhen Goodix Technology Co Ltd
Priority to PCT/CN2020/072981 priority Critical patent/WO2021142829A1/zh
Priority to CN202080001515.7A priority patent/CN111837324B/zh
Publication of WO2021142829A1 publication Critical patent/WO2021142829A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of DC power input into DC power output
    • H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
    • H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
    • H02M3/06—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/44—Circuits or arrangements for compensating for electromagnetic interference in converters or inverters

Definitions

  • the embodiments of the present application relate to the field of circuits, and in particular, to a charge pump circuit, a chip, and an electronic device.
  • the integrated circuit chip usually uses a charge pump (charge pump) circuit to perform voltage step-up or step-down processing.
  • charge pump charge pump
  • the flying capacitor or output capacitor in the charge pump circuit will generate a peak transient current with a duration as short as a few nanoseconds (ns) and an amplitude as high as hundreds of milliamperes (mA).
  • ns nanoseconds
  • mA milliamperes
  • the electromagnetic field and electromagnetic wave generated by the current will cause interference to other circuit modules near the chip, especially the antenna that is extremely sensitive to electromagnetic interference (EMI), which greatly reduces the performance of electronic equipment, so that the designed chip cannot meet the requirements of the application side.
  • EMI electromagnetic interference
  • embodiments of the present application provide a charge pump circuit, a chip, and an electronic device to solve the technical problem that the charge pump module in the prior art causes electromagnetic interference to other circuit modules near the chip.
  • a charge pump circuit in a first aspect, includes:
  • the first charge pump module and the second charge pump module are The first charge pump module and the second charge pump module;
  • the first charge pump module includes a first control module, a first output capacitor, and a fourth pad.
  • the first control module is connected to the first output capacitor through the fourth pad.
  • the first control module uses To control the charging and discharging of the first output capacitor;
  • the second charge pump module includes a second control module, a second output capacitor, and a fifth pad.
  • the second control module is connected to the second output capacitor through the fifth pad.
  • the second control module uses To control the charging and discharging of the second output capacitor;
  • the second output capacitor When the first output capacitor is in a charged state, the second output capacitor is in a discharged state, or the first output capacitor is in a discharged state and the second output capacitor is in a charged state, the fourth pad and The fifth pad is placed next to each other; or
  • the fourth pad and A grounding module is placed between the fifth pads.
  • the fourth pad and the fifth pad are placed in close proximity such that the distance between the fourth pad and the fifth pad is less than a distance of one pad.
  • the first charge pump module further includes a fourth pin, and the first control module is connected to the fourth pin through the fourth pad;
  • the second charge pump module further includes a fifth pin, and the second control module is connected to the fifth pin through the fifth pad.
  • the grounding module includes a sixth pad and a sixth pin, the sixth pad is located between the fourth pad and the fifth pad, and the first Six pins are located between the fourth pin and the fifth pin.
  • the current direction of the grounding module is opposite to the current direction of the first output capacitor and the second output capacitor.
  • the first charge pump module further includes a first flying capacitor
  • the second charge pump module further includes a second flying capacitor
  • the distance between the CN1 terminal of the first flying capacitor and the CP2 terminal of the second flying capacitor is no more than 2 weldings.
  • the distance between the disks, or the distance between the CP1 end of the first flying capacitor and the CN2 end of the second flying capacitor does not exceed the distance of 2 pads; or
  • the distance between the CN1 terminal of the first flying capacitor and the CP2 terminal of the second flying capacitor does not exceed the distance of 2 pads, or the first flying capacitor
  • the distance between the CP1 end of the flying capacitor and the CN2 end of the second flying capacitor does not exceed the distance of two pads.
  • the distance between the CN1 terminal of the first flying capacitor and the CN2 terminal of the second flying capacitor is no more than two weldings.
  • the distance between the disks, or the distance between the CP1 end of the first flying capacitor and the CP2 end of the second flying capacitor does not exceed the distance of 2 pads; or
  • the distance between the CN1 terminal of the first flying capacitor and the CN2 terminal of the second flying capacitor does not exceed the distance of 2 pads, or the first flying capacitor
  • the distance between the CP1 end of the flying capacitor and the CP2 end of the second flying capacitor does not exceed the distance of two pads.
  • the first charge pump module and the second charge pump module are both located in the upper left corner, the upper right corner, the lower left corner, or the lower right corner of the chip.
  • the first charge pump module and the second charge pump module are placed separately, and are respectively located in the upper left corner, upper right corner, lower left corner, or lower right corner of the chip.
  • the charge pump circuit further includes internal wiring of the chip, bonding wiring and PCB wiring.
  • the second end of the first output capacitor is grounded to GND, the first end of the first output capacitor is connected to the fourth pin through the PCB trace, and the The four pins are connected to the fourth pad through the bonding wire;
  • the second terminal of the second output capacitor is grounded to GND, the first terminal of the second output capacitor is connected to the fifth pin through the PCB trace, and the fifth pin is through the bonding wire Connected to the fifth pad.
  • the first charge pump module includes a first flying capacitor, a seventh pin, an eighth pin, a seventh pad, and an eighth pad;
  • the second charge pump module includes a second flying capacitor, a ninth pin, a tenth pin, a ninth pad, and a tenth pad;
  • the seventh pad is connected to the seventh pin through a bonding wire, and the seventh pin is connected to the CP1 terminal of the first flying capacitor through the PCB trace.
  • the CN1 terminal of a flying capacitor is connected to the eighth pin through the PCB trace, and the eighth pin is connected to the eighth pad through a bonding wire;
  • the ninth pad is connected to the ninth pin through a bonding wire, and the ninth pin is connected to the CP2 terminal of the second flying capacitor through the PCB trace.
  • the CN2 terminal of the second flying capacitor is connected to the tenth pin through the PCB wiring, and the tenth pin is connected to the tenth pad through a bonding wire.
  • the chip includes: a top metal layer; power lines and/or ground lines are arranged on the top metal layer.
  • the chip includes: a non-top metal layer; the internal wiring of the chip is arranged on the non-top metal layer.
  • the distance between the seventh pad and the eighth pad is less than the distance of one pad, or the distance between the ninth pad and the tenth pad is less than one pad.
  • the distance of the disk is less than the distance of the eighth pad, or the distance between the ninth pad and the tenth pad is less than one pad.
  • the first charge pump, the second charge pump, and the internal wiring of the chip are located in the chip.
  • the first output capacitor, the second output capacitor, the first flying capacitor, the second flying capacitor, and the PCB wiring are located outside the chip.
  • the output voltage of the charge pump circuit is provided to a low-voltage linear voltage stabilizing circuit.
  • a chip in a second aspect, includes the charge pump circuit of the above-mentioned first aspect.
  • the chip is a touch chip.
  • an electronic device in a third aspect, includes the chip of the second aspect described above.
  • different charge pump circuits are provided according to the current directions of the first output capacitor and the second output capacitor.
  • the first output capacitor module and the second output capacitor module are placed in close proximity or a grounding module is placed in the middle to reduce the loop area, or form a loop antenna with inverted current, so as to reduce electromagnetic interference and improve chip performance. performance.
  • FIG. 1 is a schematic diagram of the structure of a charge pump circuit in an embodiment of the application
  • FIG. 2 is a specific schematic diagram of the structure of the charge pump circuit in FIG. 1;
  • FIG. 3 is a schematic diagram of the structure of the charge pump circuit in the first embodiment of the present application.
  • FIG. 4 is a schematic diagram of the structure of the charge pump circuit in the second embodiment of the present application.
  • FIG. 5 is a schematic diagram of the structure of the charge pump circuit in the third embodiment of the present application.
  • FIG. 6 is a schematic diagram of the structure of the charge pump circuit in the fourth embodiment of the present application.
  • FIG. 7 is a schematic diagram of the structure of the charge pump circuit in the fifth embodiment of the present application.
  • FIG. 8 is a schematic diagram of the structure of the charge pump circuit in the sixth embodiment of the present application.
  • FIG. 9 is a schematic diagram of the structure of the charge pump circuit in the seventh embodiment of the present application.
  • FIG. 10 is a schematic diagram of the structure of a charge pump circuit combining the first embodiment and the seventh embodiment of the present application.
  • the flying capacitor C fly and the output capacitor C out in the charge pump circuit are periodically charged and discharged to obtain a stable output voltage Vout after being boosted or bucked.
  • the two ends of the flying capacitor C fly are generally divided into the CP end and the CN end.
  • the CP end is the end connected to the positive plate of the flying capacitor
  • the CN end is the end connected to the negative plate of the flying capacitor.
  • the non-grounded end of the output capacitor C out provides a stable boosted or stepped output voltage for the external circuit.
  • the charge pump circuit can provide the output voltage to the low-voltage linear regulator circuit, and the low-voltage linear regulator
  • the circuit outputs a stable voltage to the Tx module and/or Rx module.
  • the Tx module and/or Rx module are used to provide driving voltage to the electrodes of the touch sensor.
  • the electrodes of the touch sensor are driving electrodes (Tx) and/or sensing electrodes (Rx) .
  • the CN terminal, CP terminal, CN1 terminal, CP1 terminal, CN2 terminal, and CP2 terminal in the embodiments of this application are all used to clearly describe the current direction.
  • CN terminal, CN1 terminal and CN2 terminal indicate the terminal connected to the negative plate of the flying capacitor
  • CP The terminal, the CP1 terminal, and the CP2 terminal represent the terminals connected to the positive plate of the flying capacitor, and this application uses this as an example for related description.
  • the required flying capacitor C fly and output capacitor C out are generally large, about hundreds of nanofarads (nF) to several microfarads ( ⁇ F). If such a large capacitor is used It will occupy a very large area inside the chip, which makes the cost very high. Therefore, the flying capacitor C fly and the output capacitor C out must be external.
  • the external flying capacitor C fly and the output capacitor C out need to be connected to the charge pump control circuit by some wires.
  • the wires include the internal wiring of the chip, pads, bonding wires, pins, and printed circuit boards (Printed Circuit Board (PCB) wiring or Flexible Printed Circuit ( FPC) wiring, etc., these wirings form several effective loop antennas.
  • PCB printed Circuit Board
  • FPC Flexible Printed Circuit
  • the transient current that the charge pump charges and discharges the flying capacitor C fly and the output capacitor C out lasts only a few nanoseconds (ns), and the amplitude is as high as hundreds of milliamps (mA), and its high frequency components will be effective on the loop antenna.
  • the electromagnetic radiation which interferes with other electromagnetic-sensitive circuits and devices around the chip, such as the antenna of the terminal, makes it unable to work normally.
  • the present application provides a charge pump circuit.
  • the charge pump circuit specifically includes: a first charge pump module and a second charge pump module; the first charge pump module includes a first control module, a first output capacitor, and a fourth pad.
  • the first control module is used to control the charging and discharging of the first output capacitor;
  • the second charge pump module includes a second control module, a second output capacitor and a fifth pad, and the second control module is used to control the The second output capacitor is charged and discharged; when the first output capacitor is charged, the second output capacitor is discharged, or the first output capacitor is discharged and the second output capacitor is charged, the fourth pad and the The fifth pad is placed next to each other; or when the first output capacitor is charged, the second output capacitor is charged, or the first output capacitor is discharged, and the second output capacitor is discharged, the fourth pad A grounding module is placed between the fifth bonding pad.
  • different charge pump circuits are provided in this application to reduce the loop area of the loop antenna and/or reduce the high-frequency current in the loop antenna, so that the charge pump generates Electromagnetic interference can be greatly reduced, so that the impact of the chip on other sensitive circuit modules such as antennas is greatly reduced, so that the chip can meet the requirements of the application side.
  • FIG. 1 is a schematic diagram of the structure of a charge pump circuit in an embodiment of the application.
  • the charge pump circuit 10 includes a control module 11, a flying capacitor module 12 and an output capacitor module 13.
  • the control module 11 is respectively connected to the flying capacitor module 12 and the output capacitor module 13 through the internal wiring 14 of the chip.
  • the charge pump module 20 includes a control module, a flying capacitor module, and an output capacitor module.
  • the control module includes a control circuit 21, an analog power supply AVDD, an analog ground AGND, a clock signal CLK, and other required signal lines (not shown in the figure).
  • the control circuit 21 is powered by an analog power supply AVDD and an analog ground AGND.
  • the flying capacitor module includes a flying capacitor C fly , a first pad 212, a second pad 217, a first pin 214, and a second pin 216.
  • the trace 211 is connected to the control circuit 21, the other end of the first pad 212 is connected to the first pin 214 through the bonding wire 213, and the first pin 214 is connected to the CP terminal of the flying capacitor C fly through the PCB trace or the FPC trace 215 ,
  • the CN terminal of the flying capacitor C fly is connected to the second pin 216 through the PCB trace or the FPC trace 215, the second pin 216 is connected to one end of the second pad 217 through the bonding wire 213, and the other of the second pad 217
  • One end is connected to the control circuit 21 through the internal wiring 211 of the chip.
  • the output capacitor module includes an output capacitor C out , a third pad 219 and a third pin 218.
  • One end of the third pad 219 is connected to the control circuit 21 through the internal wiring 211 of the chip, and the other end of the third pad 219 is bonded line 213 connecting the third pin 218, a third pin 218 or via PCB traces FPC traces 215 connecting the first end of the output capacitor C out, a second end of the output capacitor C out is to go through the FPC cable or PCB traces 215 Ground GND.
  • the charge pump 21, the internal wiring 211 of the chip, the first pad 212, the second pad 217, and the third pad 219 are located inside the chip, and the flying capacitor C fly , the output capacitor C out , the PCB wiring or the FPC wiring 215 are located Outside the chip, the pads output signals to the pins through the bonding wires 213, and the pins output the output signals to the PCB traces or the FPC traces 215.
  • the first pad 212, the second pad 217, and the third pad 219 are respectively connected to the control circuit 21 through the internal wiring 211 of the chip.
  • the first terminal of the output capacitor C out is used as the output voltage terminal of the charge pump module.
  • the wiring 215 outside the chip may be one of PCB wiring or FPC wiring.
  • PCB wiring that is, the PCB wiring described below includes PCB wiring and FPC There are two situations for wiring.
  • FIG. 3 is a schematic diagram of the circuit structure that can reduce the electromagnetic interference of the charge pump in the first embodiment of the present application.
  • This embodiment is used for charging the first output capacitor C out1 in the first charge pump module and discharging the second output capacitor C out2 of the second charge pump module or discharging the first output capacitor C out1 and charging the second output capacitor C out2
  • the first output capacitor C out1 is in the charged state
  • the current flows from the fourth pad 321 to the GND through the first output capacitor C out1 , and at the same time, the second output capacitor C out2 is in a discharged state, and the current flows from GND through the second output
  • the capacitor C out2 flows to the fifth pad 326, or when the second output capacitor C out2 is in a charged state
  • the current flows from the fifth pad 326 to the GND through the second output capacitor C out2
  • the first output capacitor C out1 is in a discharged state
  • the current flows from GND to the fourth pad 321 through the first output capacitor C out1.
  • the potentials of the PCB traces, the internal traces of the chip, the pins, and the pads connected to one end of the output capacitor are all output voltages.
  • the output of the fourth pad 321 is used as the output voltage Vout1 of the first charge pump module
  • the fifth The output of the pad 326 is used as the output voltage Vout2 of the second charge pump module.
  • the embodiment of the present application is described by taking an example in which the first output capacitor C out1 is in a charged state and the second output capacitor C out2 is in a discharged state.
  • the embodiment of the present application takes two charge pump modules as an example for description.
  • the two charge pump modules are respectively a first charge pump module and a second charge pump module, and the first charge pump module includes a first control module and a first charge pump module.
  • Output capacitor module The first output capacitor module includes a first output capacitor C out1 , a fourth pin 323 and a fourth pad 321.
  • the first control module is connected to the first output capacitor C out1 through the fourth pad 321;
  • the charge pump module includes a second control module and a second output capacitor module.
  • the second output capacitor module includes a second output capacitor C out2 , a fifth pin 328 and a fifth pad 326.
  • the second control module passes through the fifth pad 326 Connected to the second output capacitor C out2.
  • the second end of the first output capacitor C out1 is grounded to GND, the first end of the first output capacitor C out1 is connected to the fourth pin 323 through the PCB trace 324, and the fourth pin 323 is connected to the fourth pin through the bonding wire 322.
  • the disk 321 is connected.
  • the second end of the second output capacitor C out2 is grounded to GND, the first end of the second output capacitor C out2 is connected to the fifth pin 328 through a PCB trace 329, and the fifth pin 328 is connected to the fifth pin through a bonding wire 327.
  • Disk 326 is connected.
  • the fourth pad 321 of the first charge pump module and the fifth pad 326 of the second charge pump module are placed next to each other.
  • the fourth pad 321 and the fifth pad 326 are separated by a distance of one pad.
  • No traces are provided on the disk, for example, no other pads are placed between the fourth pad 321 and the fifth pad 326 or the distance between the fourth pad 321 and the fifth pad 326 is less than one pad, so that
  • the loop area formed by the PCB traces 329 is the smallest, thereby reducing electromagnetic interference from the two charge pumps. The smaller the area of the loop antenna, the smaller the influence of electromagnetic interference.
  • FIG. 4 is a schematic diagram of a circuit structure that can reduce electromagnetic interference of a charge pump in a second embodiment of the present application.
  • This embodiment is used when the first output capacitor C out1 of the first charge pump module and the second output capacitor C out2 of the second charge pump module are simultaneously charged or discharged simultaneously, that is, the first output capacitor C out1 is in a charged state
  • the second output capacitor C out2 is in a charged state
  • the current flows from the fifth pad 416 to the GND through the second output capacitor C out2.
  • the direction of current is opposite to that of the first output capacitor and the second output capacitor.
  • the current of the grounding module flows from the off-chip ground terminal GND of the PCB trace 423 to the chip of the sixth pad 420 through the sixth pin 422 Ground terminal GND; or when the first output capacitor C out1 is in a discharged state, the current flows from GND through the first output capacitor C out1 to the fourth pad 411, and at the same time, the second output capacitor C out2 is discharged, and the current flows from GND through the second The output capacitor C out2 flows to the fifth pad 416, and the current direction of the grounding module is opposite to that of the first output capacitor and the second output capacitor.
  • the embodiment of the present application is described with an example in which the first output capacitor C out1 is in a charged state and the second output capacitor C out2 is in a charged state.
  • the embodiment of the present application takes two charge pump modules as an example for description.
  • the two charge pump modules are respectively a first charge pump module and a second charge pump module, and the first charge pump module includes a first control module and a first charge pump module.
  • Output capacitor module the first output capacitor module includes a first output capacitor C out1 , a fourth pin 413 and a fourth pad 411;
  • the second charge pump module includes a second control module and a second output capacitor module, the second output capacitor
  • the module includes a second output capacitor C out2 , a fifth pin 418 and a fifth pad 416.
  • the second end of the first output capacitor C out1 is grounded to GND, the first end of the first output capacitor C out1 is connected to the fourth pin 413 through the PCB trace 414, and the fourth pin 413 is connected to the fourth pin through the bonding wire 412. Disk 411 is connected.
  • the second end of the second output capacitor C out2 is grounded to GND, the first end of the second output capacitor C out2 is connected to the fifth pin 418 through a PCB trace 419, and the fifth pin 418 is connected to the fifth pin through a bonding wire 417.
  • Disk 416 is connected.
  • a grounding module is placed between the first output capacitor module and the second output capacitor module.
  • the grounding module includes a sixth pad 420 and a sixth pin 422. One end of the sixth pad 420 is connected to the ground terminal GND in the chip. The other end of the pad 420 is connected to the sixth pin 422 through a bonding wire 421, and the sixth pin 422 is connected to the off-chip ground GND through a PCB trace 423.
  • the sixth pad 420 is located between the fourth pad 411 and Between the fifth pads 416, the sixth pin 422 is located between the fourth pin 413 and the fifth pin 418.
  • the current direction of the grounding module is opposite to that of the first output capacitor C out1 and the second output capacitor C out2 .
  • the current direction of the grounding module flows from the in-chip ground terminal GND of the sixth pad 420 to the PCB through the fourth pin 422
  • the off-chip ground terminal GND of line 423, the connection between the first charge pump module and the grounding module, and the second charge pump module and the grounding module respectively form two loop antennas with inverted currents, which can make the electromagnetic field and The electromagnetic waves cancel each other out, reducing the electromagnetic interference from the charge pump.
  • the present application also provides a charge pump circuit structure.
  • the first charge pump module further includes a first flying capacitor module
  • the second charge pump module further includes a second flying capacitor module; according to the first flying capacitor module
  • Different charge pump circuit structures are set up with the current direction of the second flying capacitor module. Specifically, the description will be given by taking FIG. 5 and FIG. 6 as an example.
  • FIG. 5 is a schematic diagram of a circuit structure that can reduce electromagnetic interference of a charge pump in a third embodiment of the present application. This embodiment is used for charging the first flying capacitor C fly1 in the third charge pump module and discharging the second flying capacitor C fly2 of the fourth charge pump module or discharging the first flying capacitor C fly1 and charging the second flying capacitor C fly2.
  • the first flying capacitor C fly1 is in the charging state, the current flows from the CP1 terminal through the first flying capacitor C fly1 to the CN1 terminal.
  • the second flying capacitor C fly2 is in a discharged state, and the current flows from the CN2 terminal through the second flying capacitor.
  • the embodiment of the present application is described with an example in which the first flying capacitor C fly1 is in a charged state and the second flying capacitor C fly2 is in a discharged state.
  • the embodiment of the present application takes two charge pump modules as an example for description, and the two charge pump modules are respectively a third charge pump module and a fourth charge pump module.
  • the third charge pump module includes a first control module and a first flying capacitor module.
  • the first flying capacitor module includes a first flying capacitor C fly1 , a seventh pin 513, an eighth pin 516, a seventh pad 511 and an eighth Pad 515, the first control module is connected to the positive plate of the first flying capacitor through the seventh pad 511, and the first control module is connected to the negative plate of the first flying capacitor C fly1 through the eighth pad 515, where the seventh pad 511512 seventh pin 513 and connected through bond wires, the seventh pin 513 is connected through the PCB trace 514 and the CP1 of the first flying capacitor C fly1, a first end of the flying capacitor CN1 C fly1 by PCB traces 514 It is connected to the eighth pin 516.
  • the eighth pin 516 is connected to the eighth pad 515 through a bonding wire 512.
  • the seventh pad 511 and the seventh pin 513 are the CP1 terminals of the first flying capacitor C fly1.
  • the pad 515 and the eighth pin 516 are the CN1 terminals of the first flying capacitor C fly1.
  • the fourth charge pump module includes a second control module and a second flying capacitor module.
  • the second flying capacitor module includes a second flying capacitor Cfly2 , a ninth pin 519, a tenth pin 522, a ninth pad 517, and a tenth flying capacitor.
  • the pad 521, the second control module is connected to the positive plate of the second flying capacitor C fly2 through the ninth pad 519, and the second control module is connected to the negative plate of the second flying capacitor C fly2 through the tenth pad 521, where, ninth pads 517 by bond wire 518 is connected to the ninth pin 519, pin 519 is connected to a ninth wiring 520 through the PCB and CP2 terminal of the second capacitor C fly2 of flying, fly CN2 terminal of the second capacitor C fly2 by The PCB trace 520 is connected to the tenth pin 522, and the tenth pin 522 is connected to the tenth pad 521 through a bonding wire 518.
  • the ninth pad 517 and the ninth pin 519 are CP2 of the second flying capacitor C fly2.
  • the tenth pad 521 and the tenth pin 522 are the CN2 end of the second flying capacitor C fly2.
  • the two ends of the first flying capacitor C fly1 of the third charge pump module and the two ends of the second flying capacitor C fly2 of the fourth charge pump module are arranged in order, from left to right: CP1, CN1, CP2 Terminal, CN2 terminal, or CN1 terminal, CP1 terminal, CN2 terminal, CP2 terminal, wherein there may be a certain interval between the first flying capacitor module and the second flying capacitor module, and the interval may be the distance of multiple pads, for example , The interval is not more than the distance of 2 pads.
  • the distance between the CN1 terminal of the first flying capacitor and the CP2 terminal of the second flying capacitor does not exceed the distance of 2 pads, or the distance between the CP1 terminal of the first flying capacitor and the CN2 terminal of the second flying capacitor does not exceed the distance of 2 pads That is, the eighth pad 515 and the ninth pad 517 may be separated by a distance of 2 pads, a distance of 1 pad, or a distance of 0 pads.
  • the eighth pad 515 and the ninth pad 517 may be separated by a distance of 2 pads, a distance of 1 pad, or a distance of 0 pads.
  • FIG. 6 is a schematic diagram of a circuit structure that can reduce electromagnetic interference of a charge pump in a fourth embodiment of the present application.
  • This second flying capacitor C fly2 a first embodiment of a flying capacitor C fly1 third and fourth charge pump module in the case where the charge pump modules while simultaneously charging or discharging, i.e., a first flying capacitor in a charged state C fly1
  • the second flying capacitor C fly2 is in a charged state, and the current flows from the CP2 terminal through the second flying capacitor C fly2 to the CN2 terminal, or the first flying capacitor C
  • fly1 is in the discharging state, current flows from the CN1 terminal through the first flying capacitor C fly1 to the CP1 terminal.
  • the second flying capacitor C fly2 is in a discharged state, and the current flows from the CN2 terminal to the CP2 terminal through the second flying capacitor C fly2.
  • the embodiment of the present application is described by taking an example in which the third charge pump module charges the first flying capacitor C fly1 and the fourth charge pump module is also charging the second flying capacitor C fly2.
  • the embodiment of the present application takes two charge pump modules as an example for description, and the two charge pump modules are respectively a third charge pump module and a fourth charge pump module.
  • the third charge pump module includes a first flying capacitor module, and the first flying capacitor module includes a first flying capacitor Cfly1 , a seventh pin 613, an eighth pin 616, a seventh pad 611, and an eighth pad 615, wherein , a seventh pad 611 through line 612 and binding 613 is connected to the seventh pin, the seventh pin 613 is connected through the PCB trace 614 and the CP1 of the first flying capacitor C fly1, CN1 a first end of the fly capacitor C fly1
  • the eighth pin 616 is connected to the eighth pin 616 through the PCB trace 614, the eighth pin 616 is connected to the eighth pad 615 through the bonding wire 612, the seventh pad 611 and the seventh pin 613 are the first flying capacitor C fly1
  • the CP1 terminal, the eighth pad 615 and the eighth pin 616 are the CN1 terminal of the first flying capacitor C fly1.
  • the fourth charge pump module includes a second flying capacitor module, and the second flying capacitor module includes a second flying capacitor Cfly2 , a ninth pin 619, a tenth pin 622, a ninth pad 617, and a tenth pad 621, wherein , ninth and ninth pin pads 617,618 are connected by bond wires 619, 619 connected to the ninth pin PCB traces 620 and a second terminal CN2 of the flying capacitor C fly2, CP2 of the second end of the fly capacitor C fly2
  • the tenth pin 622 is connected to the tenth pin 622 through the PCB trace 620, and the tenth pin 622 is connected to the tenth pad 621 through the bonding wire 618.
  • the ninth pad 617 and the ninth pin 619 are the second flying capacitors C fly2 .
  • the CN2 end, the tenth pad 621 and the tenth pin 622 are the CP2 end of the second flying capacitor C fly2 .
  • the distance between the CN1 end of the first flying capacitor and the CP2 end of the second flying capacitor is no more than 2 pads.
  • the distance may be 2 pads, 1 pad, or 0 pads between the eighth pad 615 and the tenth pad 621, or it may be between the eighth pin 616 and the tenth pin 622.
  • the two ends of the first flying capacitor C fly1 of the third charge pump module and the two ends of the second flying capacitor C fly2 of the fourth charge pump module are arranged in order, from left to right: CP1, CN1, CN2 Terminal, CP2 terminal, or CN1 terminal, CP1 terminal, CP2 terminal, CN2 terminal, wherein there may be a certain interval between the first flying capacitor module and the second flying capacitor module, and the interval may be the distance of multiple pads, preferably Yes, the interval is not more than the distance of 2 pads.
  • the distance between the CN1 terminal of the first flying capacitor and the CN2 terminal of the second flying capacitor does not exceed the distance of 2 pads, or the distance between the CP1 terminal of the first flying capacitor and the CP2 terminal of the second flying capacitor does not exceed 2 pads That is, the eighth pad 615 and the ninth pad 617 may be separated by 2 pad distances, 1 pad distance, or 0 pad distances.
  • the current direction of the first flying capacitor module and the second flying capacitor module are reversed, and two loops formed by two charge pump modules
  • the radiated electromagnetic field of the antenna and the electromagnetic wave are just antiphase, so as to cancel each other in the far area, and reduce the electromagnetic interference from the third charge pump module and the fourth charge pump module.
  • FIG. 7 is a schematic diagram of a circuit structure that can reduce electromagnetic interference of a charge pump in a fifth embodiment of the present application.
  • the chip 711 includes a silicon chip 710
  • the charge pump module includes a control module 712, a flying capacitor module, and an output capacitor module.
  • the flying capacitor module includes a flying capacitor C fly , a first pad 714, a second pad 718, a first pin 716 and a second pin 719. One end of the first pad 714 is connected to the control module 712 through the internal wiring 713 of the chip.
  • the output capacitor module includes an output capacitor C out , a third pad 720 and a third pin 721.
  • One end of the third pad 720 is connected to the control module 712 through the internal wiring 713 of the chip, and the other end of the third pad 720 is bonded line 715 connecting the third pin 721, a third pin 721 to go through the PCB line 717 connected to a first end of the output capacitor C out, and a second terminal of the output capacitor C out through the PCB trace 717 ground GND.
  • the traces 713, bonding wires 715, and PCB traces 717 inside the chip should all be as short as possible.
  • the first pad 714 and the second pad 718 of the flying capacitor C fly should be placed next to each other, that is, no other pads or the first pad 714 and the second pad are placed between the first pad 714 and the second pad 718.
  • the distance between the disks 718 is less than the distance of one pad, so the loop area of the loop antenna formed by the flying capacitor C fly connection can be reduced as much as possible, thereby reducing the electromagnetic interference from the charge pump.
  • two pads are usually used to lay on the same pin through two bonding wires, so that the resistance and inductance of the bonding wire can be reduced.
  • Parallel connection reduces the impedance by half.
  • any pin of the flying capacitor C fly is not connected to two pads and two bonding wires at the same time, but a single pad and a single bonding wire should be connected.
  • the resistance and inductance of the bonding wire can block the high-frequency current from the control module 712 from flowing to the outside of the chip, thereby reducing the high-frequency current in the loop antenna, and Reduce electromagnetic interference from the charge pump module.
  • FIG. 8 is a schematic diagram of a circuit structure that can reduce electromagnetic interference of a charge pump in a sixth embodiment of the present application.
  • the chip includes a top metal layer 82 and a non-top metal layer.
  • the non-top metal layer includes a silicon base layer 81, an insulating layer 83 under the top metal layer 82, and a sub-layer under the insulating layer 83, second only to the top metal layer 82
  • the metal layer 84 and other metal layers (not shown in the figure). Flying capacitors and output capacitors are connected to the control module through their respective PCB traces, pins, bonding wires, pads, and internal wiring of the chip. Avoid placing flying capacitors and output capacitors on the top metal of the chip.
  • the wiring of the flying capacitor and the output capacitor inside the chip is set on the non-top metal layer, that is, the internal wiring of the chip is set on the sub-layer metal layer 84 or other metals that are closer to the silicon base layer 81 than the sub-layer metal layer 84 Layer (not shown in the figure), and the top metal layer 82 is used to set the ground line or the power line.
  • flying capacitors and output capacitors have high-frequency currents on the internal traces of the chip, and high-frequency currents will preferentially choose paths with lower impedance. Flying capacitors and output capacitors are connected to the ground within the chip.
  • the coupling capacitor formed by the power line allows high-frequency current to flow preferentially, avoiding it from flowing to the wiring outside the chip and causing greater EMI.
  • the top metal layer 82 forms a shielding layer by arranging ground wires and power wires to reduce electromagnetic interference from inside the chip.
  • FIG. 9 is a schematic diagram of a circuit structure that can reduce electromagnetic interference of a charge pump in a seventh embodiment of the present application.
  • the chip 911 includes a silicon chip 910, and the charge pump module includes a control module 912, a flying capacitor module, and an output capacitor module.
  • the flying capacitor module includes a flying capacitor Cfly , a first pad 914, a second pad 918, a first pin 916, and a second pin 919. One end of the first pad 914 is connected to the control module 912 through the internal wiring 913 of the chip.
  • the output capacitor module includes an output capacitor C out , a third pad 920 and a third pin 921.
  • One end of the third pad 920 is connected to the control module 912 through the internal wiring 913 of the chip, and the other end of the third pad 920 is bonded line 915 connecting the third pin 921, a third pin 921 to go through the PCB line 917 connected to a first end of the output capacitor C out, and a second terminal of the output capacitor C out through the PCB trace 917 ground GND.
  • the charge pump module is located at a corner of the chip 911, and the length of the internal wiring 913 between the charge pump 912 and the pad is set as short as possible.
  • the charge pump module 912 shown in the figure is located at the lower left corner of the chip 911, and may also be located at the upper left corner, the upper right corner or the lower right corner of the chip 911.
  • the coupling opportunities between the charge pump 912 and its internal wiring 913 and other circuits in the chip 911 can be minimized, thereby preventing the charge pump 912 from outputting high-frequency currents through other circuit modules of the chip 911 and causing electromagnetic interference.
  • FIG. 10 is an example of the combination of the first, third, and seventh embodiments. Be explained.
  • the chip 1011 includes a silicon chip 1010
  • the first charge pump module includes a first control module 1012, a flying capacitor module, and an output capacitor module.
  • the flying capacitor module of the first charge pump module includes a first flying capacitor Cfly1 , a first pad 1014, a second pad 1030, a first pin 1016, and a second pin 1029.
  • the internal trace 1013 is connected to the first control module 1012, the other end of the first pad 1014 is connected to the first pin 1016 through a bonding wire 1015, and the first pin 1016 is connected to the CP1 of the first flying capacitor C fly1 through the PCB trace 1017
  • the CN1 terminal of the first flying capacitor C fly1 is connected to the second pin 1029 through the PCB trace 1017, and the second pin 1029 is connected to the second pad 1030 through the bonding wire 1015.
  • the output capacitor module of the first charge pump module includes a first output capacitor C out1 , a third pad 1028 and a third pin 1025.
  • the third pad 1028 is connected to the first control module 1012 through the internal wiring 1013 of the chip. the other end by binding the three line pad 1028 1015 1025 connecting the third pin, the third pin connecting the first end 1025 of the first output capacitor C out1 via PCB traces 1017, a second of the first output capacitor C out1
  • the terminal is grounded to GND through PCB trace 1017.
  • the second charge pump module includes a second control module 1018, a flying capacitor module, and an output capacitor module.
  • the flying capacitor module of the second charge pump module includes a second flying capacitor Cfly2 , a fourth pad 1020, a fifth pad 1032, a fourth pin 1022, and a fifth pin 1033.
  • the internal trace 1019 is connected to the second control module 1018, the other end of the fourth pad 1020 is connected to the fourth pin 1022 through the bonding wire 1021, and the fourth pin 1022 is connected to the CN2 of the second flying capacitor C fly2 through the PCB trace 1023
  • the CP2 terminal of the second flying capacitor C fly2 is connected to the fifth pin 1033 through the PCB trace 1023, and the fifth pin 1033 is connected to the fifth pad 1032 through the bonding wire 1021.
  • the output capacitor module includes a second output capacitor C out2 , a sixth pad 1027 and a sixth pin 1026.
  • One end of the sixth pad 1027 is connected to the second control module 1018 through the internal wiring 1019 of the chip, and the other of the sixth pad 1027 sixth pin 1026 has one end connected via bond wires 1021, 1026 through the sixth pin PCB trace a first end connected to the second output line 1023 of the capacitor C out2, a second terminal of the second output capacitor C out2 by PCB traces 1021 Ground GND.
  • the first charge pump module and the second charge pump module are both located at the lower left corner of the chip 1011. Of course, they can also be located at the upper left corner, upper right corner or lower right corner of the chip 1011 at the same time, or the first charge pump module and the second charge pump module are respectively located Located in different corners of the chip 1011.
  • the third pad 1028 of the first output capacitor C out1 and the second output capacitor C The sixth pad 1027 of out2 should be placed next to each other, that is, no other pads should be placed between the third pad 1028 and the sixth pad 1027 or the distance between the third pad 1028 and the sixth pad 1027 is less than one pad Distance to make the third pad 1028, bonding wire 1015, third pin 1025, PCB trace 1017 and the sixth pad 1027, bonding wire 1021, and second charge pump module of the first charge pump module
  • the ring area formed by the six pins 1026 and the PCB trace 1023 is the smallest, thereby reducing electromagnetic interference from the two charge pumps.
  • the first charge output capacitor C out1 and a second output capacitor C out2 discharge, the first capacitor C fly1 flying in a discharged state and the second fly capacitor C fly2 in a charged state, therefore, the first two of the fly capacitor C fly1
  • the terminals and the two ends of the second flying capacitor C fly2 are arranged in order, from left to right: CP1, CN1, CP2, CN2, or CN1, CP1, CN2, and CP2.
  • the coupling opportunities between the charge pump 1012 and its internal wiring 1013 and other circuits in the chip 1011 can be minimized to prevent the charge pump 1012 from passing through the chip.
  • 1011's other circuit modules output high-frequency currents to generate electromagnetic interference, reducing the impact of electromagnetic interference.
  • electromagnetic interference is further reduced, and the performance of the chip is significantly improved.

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Abstract

一种电荷泵电路、触控芯片以及电子设备，电荷泵电路包括：第一电荷泵模块和第二电荷泵模块；第一电荷泵模块包括第一控制模块、第一输出电容(Cout1)和第四焊盘(321)；第二电荷泵模块包括第二控制模块、第二输出电容和第五焊盘(326)；当所述第一输出电容(Cout1)处于充电状态、所述第二输出电容(Cout2)处于放电状态，或所述第一输出电容(Cout1)处于放电状态、所述第二输出电容(Cout2)处于充电状态时，所述第四焊盘(321)和所述第五焊盘(326)紧邻放置；或者当所述第一输出电容(Cout1)处于充电状态、所述第二输出电容(Cout2)处于充电状态，或所述第一输出电容(Cout1)处于放电状态、所述第二输出电容(Cout2)处于放电状态时，所述第四焊盘(321)和所述第五焊盘(326)之间放置一个接地模块。该电路结构减小了电磁干扰，提高了芯片的性能。

Description

电荷泵电路、芯片以及电子设备 技术领域
本申请实施例涉及电路领域，尤其涉及一种电荷泵电路、芯片以及电子设备。
背景技术
目前，集成电路芯片通常使用电荷泵(charge pump)电路进行升压或降压处理。电荷泵电路中的飞电容或输出电容在充电或放电的过程中，会产生持续时间短至数纳秒(ns)、幅值高达数百毫安(mA)的尖峰瞬态电流，此瞬态电流产生的电磁场和电磁波会对芯片附近的其他电路模块形成干扰，尤其对电磁干扰(Electromagnetic Interference，EMI)极其敏感的天线，大大降低电子设备的性能，从而使设计出的芯片无法满足应用端的要求。
发明内容
有鉴于此，本申请实施例提供一种电荷泵电路、芯片以及电子设备，用以解决现有技术中的电荷泵模块给芯片附近的其他电路模块形成电磁干扰的技术问题。
第一方面，提供了一种电荷泵电路，所述电荷泵电路包括：
第一电荷泵模块和第二电荷泵模块；
第一电荷泵模块包括第一控制模块、第一输出电容和第四焊盘，所述第一控制模块通过所述第四焊盘与所述第一输出电容连接，所述第一控制模块用于控制对所述第一输出电容充电和放电；
第二电荷泵模块包括第二控制模块、第二输出电容和第五焊盘，所述第二控制模块通过所述第五焊盘与所述第二输出电容连接，所述第二控制模块用于控制对所述第二输出电容充电和放电；
当所述第一输出电容处于充电状态、所述第二输出电容处于放电状态，或者所述第一输出电容处于放电状态、所述第二输出电容处于充电状态时，所述第四焊盘和所述第五焊盘紧邻放置；或者
当所述第一输出电容处于充电状态、所述第二输出电容处于充电状态，或者所述第一输出电容处于放电状态、所述第二输出电容处于放电状态时，所述第四焊盘和所述第五焊盘之间放置一个接地模块。
在一种可能的实现方式中，所述第四焊盘与所述第五焊盘紧邻放置为所述第四焊盘与所述第五焊盘之间的间隔小于一个焊盘的距离。
在一种可能的实现方式中，第一电荷泵模块还包括第四引脚，所述第一控制模块通过所述第四焊盘与所述第四引脚连接；
第二电荷泵模块还包括第五引脚，所述第二控制模块通过所述第五焊盘与所述第五引脚连接。
在一种可能的实现方式中，所述接地模块包括第六焊盘和第六引脚，所述第六焊盘位于所述第四焊盘和所述第五焊盘之间，所述第六引脚位于所述第四引脚和所述第五引脚之间。
在一种可能的实现方式中，所述接地模块的电流方向与所述第一输出电容、所述第二输出电容的电流方向相反。
在一种可能的实现方式中，第一电荷泵模块还包括第一飞电容，第二电荷泵模块还包括第二飞电容。
在一种可能的实现方式中，当第一飞电容处于充电状态，第二飞电容处于放电状态时，所述第一飞电容的CN1端和第二飞电容的CP2端的间隔不超过2个焊盘的距离，或所述第一飞电容的CP1端和第二飞电容的CN2端的间隔不超过2个焊盘的距离；或者
当第一飞电容处于放电状态，第二飞电容处于充电状态时，所述第一飞电容的CN1端和第二飞电容的CP2端的间隔不超过2个焊盘的距离，或所述第一飞电容的CP1端和第二飞电容的CN2端的间隔不超过2个焊盘的距离。
在一种可能的实现方式中，当第一飞电容处于充电状态，第二飞电容处于充电状态时，所述第一飞电容的CN1端和第二飞电容的CN2端的间隔不超过2个焊盘的距离，或所述第一飞电容的CP1端和第二飞电容的CP2端的间隔不超过2个焊盘的距离；或者
当第一飞电容处于放电状态，第二飞电容处于放电状态时，所述第一飞电容的CN1端和第二飞电容的CN2端的间隔不超过2个焊盘的距离，或所述第一飞电容的CP1端和第二飞电容的CP2端的间隔不超过2个焊盘的距离。
在一种可能的实现方式中，所述第一电荷泵模块和所述第二电荷泵模块均位于芯片的左上角、右上角、左下角或右下角。
在一种可能的实现方式中，所述第一电荷泵模块和第二电荷泵模块分开 放置，分别位于芯片的左上角、右上角、左下角或右下角。
在一种可能的实现方式中，电荷泵电路还包括芯片内部走线、绑定线和PCB走线。
在一种可能的实现方式中，所述第一输出电容的第二端接地GND，所述第一输出电容的第一端通过所述PCB走线与所述第四引脚相连、所述第四引脚通过所述绑定线与所述第四焊盘相连；
所述第二输出电容的第二端接地GND，所述第二输出电容的第一端通过所述PCB走线与所述第五引脚相连、所述第五引脚通过所述绑定线与所述第五焊盘相连。
在一种可能的实现方式中，所述第一电荷泵模块包括第一飞电容、第七引脚、第八引脚、第七焊盘以及第八焊盘；
所述第二电荷泵模块包括第二飞电容、第九引脚、第十引脚、第九焊盘以及第十焊盘；
所述第七焊盘通过一根所述绑定线与所述第七引脚相连，所述第七引脚通过所述PCB走线与所述第一飞电容的CP1端相连，所述第一飞电容的CN1端通过所述PCB走线与所述第八引脚相连，所述第八引脚通过一根所述绑定线与所述第八焊盘相连；
所述第九焊盘通过一根所述绑定线与所述第九引脚相连，所述第九引脚通过所述PCB走线与所述第二飞电容的CP2端相连，所述第二飞电容的CN2端通过所述PCB走线与所述第十引脚相连，所述第十引脚通过一根所述绑定线与所述第十焊盘相连。
在一种可能的实现方式中，芯片包括：顶层金属层；电源线和/或地线设置在所述顶层金属层。
在一种可能的实现方式中，所述芯片包括：非顶层金属层；所述芯片内部走线设置在所述非顶层金属层。
在一种可能的实现方式中，所述第七焊盘和所述第八焊盘的间隔小于一个焊盘的距离，或者所述第九焊盘和所述第十焊盘的间隔小于一个焊盘的距离。
在一种可能的实现方式中，所述第一电荷泵、所述第二电荷泵以及所述芯片内部走线位于所述芯片内。
在一种可能的实现方式中，所述第一输出电容、第二输出电容、第一飞电容、第二飞电容以及PCB走线位于所述芯片外。
在一种可能的实现方式中，所述电荷泵电路的输出电压提供给低压线性稳压电路。
第二方面，提供了一种芯片，所述芯片包括上述第一方面的电荷泵电路。
在一种可能的实现方式中，所述芯片为触控芯片。
第三方面，提供了一种电子设备，所述电子设备包括上述第二方面的芯片。
基于上述技术方案，通过根据第一输出电容和第二输出电容的电流方向，设置不同的电荷泵电路。在不同情况下，对第一输出电容模块和第二输出电容模块进行紧邻放置或者中间设置接地模块，减小环形面积，或者形成电流反相的环形天线，使得减小电磁干扰，提高了芯片的性能。
附图说明
后文将参照附图以示例性而非限制性的方式详细描述本申请实施例的一些具体实施例。附图中相同的附图标记标示了相同或类似的部件或部分。本领域技术人员应该理解，这些附图未必是按比例绘制的。附图中：
图1为本申请实施例中电荷泵电路结构示意图；
图2为图1中电荷泵电路结构具体示意图；
图3是本申请第一实施例中电荷泵电路结构示意图；
图4是本申请第二实施例中电荷泵电路结构示意图；
图5是本申请第三实施例中电荷泵电路结构示意图；
图6是本申请第四实施例中电荷泵电路结构示意图；
图7是本申请第五实施例中电荷泵电路结构示意图；
图8是本申请第六实施例中电荷泵电路结构示意图；
图9是本申请第七实施例中电荷泵电路结构示意图；
图10是本申请第一实施例和第七实施例相结合电荷泵电路结构示意图。
具体实施方式
下面将结合附图，对本申请中的技术方案进行描述。
电荷泵电路中的飞电容C fly和输出电容C out周期性的充电和放电，以此获得稳定的经过升压或降压后的输出电压Vout。根据电荷泵电路的工作原理，飞电容C fly两端一般分为CP端和CN端，CP端为与飞电容正极板相连的一端，CN端为与飞电容负极板相连的一端，飞电容C fly处于充电状态时，电流从CP端经过飞电容C fly流向CN端，飞电容C fly处于放电状态时，即飞电容C fly给输出电容C out进行充电时，电流从CN端经过飞电容C fly流向CP端。输出电容 C out的非接地端为外部电路提供稳定的经过升压或降压后的输出电压，例如对于触控芯片，电荷泵电路可将输出电压提供给低压线性稳压电路，低压线性稳压电路输出稳定的电压给Tx模块和/或Rx模块，Tx模块和/或Rx模块用于给触摸传感器的电极提供驱动电压，触摸传感器的电极为驱动电极(Tx)和/或感应电极(Rx)。本申请实施例CN端、CP端、CN1端、CP1端、CN2端以及CP2端均用来清楚描述电流方向，例如，CN端、CN1端和CN2端表示与飞电容负极板相连的一端，CP端、CP1端和CP2端表示与飞电容正极板相连的一端，本申请以此为例进行相关说明。为了提高电荷泵电路的带负载能力，所需要的飞电容C fly和输出电容C out一般较大，约为数百纳法(nF)至几个微法(μF)，这么大的电容若做于芯片内部会占据非常大的面积，使得成本非常高，因此飞电容C fly和输出电容C out必须外置。外置的飞电容C fly和输出电容C out需由一些连线连接到电荷泵控制电路，其中，连线包括芯片内部走线，焊盘，绑定线，引脚，以及印刷电路板(Printed Circuit Board，PCB)走线或柔性印刷电路板(Flexible Printed Circuit ，FPC)走线等，这些连线形成若干有效的环形天线。而电荷泵给飞电容C fly和输出电容C out充放电的瞬态电流持续时间只有几纳秒(ns)，幅度高达数百毫安(mA)，其高频分量会在环形天线上形成有效的电磁辐射，从而干扰芯片周围的对电磁敏感的其他电路和器件，比如终端的天线，使其无法正常工作。
本申请提供一种电荷泵电路，电荷泵电路具体包括：第一电荷泵模块和第二电荷泵模块；第一电荷泵模块包括第一控制模块、第一输出电容和第四焊盘，所述第一控制模块用于控制对所述第一输出电容充电和放电；第二电荷泵模块包括第二控制模块、第二输出电容和第五焊盘，所述第二控制模块用于控制对所述第二输出电容充电和放电；当第一输出电容充电、所述第二输出电容放电，或者所述第一输出电容放电、所述第二输出电容充电时，所述第四焊盘和所述第五焊盘紧邻放置；或者当所述第一输出电容充电、所述第二输出电容充电，或者所述第一输出电容放电、所述第二输出电容放电时，所述第四焊盘和所述第五焊盘之间放置一个接地模块。
本申请根据第一输出电容和第二输出电容的电流方向，设置不同的电荷泵电路，以减小环形天线的环路面积和/或减小环形天线中的高频电流，使得电荷泵产生的电磁干扰可以大幅度降低，从而芯片对天线等其他敏感电路模块产生的影响大大降低，使得芯片可满足应用端的要求。
图1为本申请实施例中电荷泵电路结构示意图。电荷泵电路10包括控制模块11、飞电容模块12和输出电容模块13。控制模块11通过芯片内部走线 14分别连接飞电容模块12和输出电容模块13。
具体的，请参见图2，图2为图1中电荷泵电路结构具体示意图。电荷泵模块20包括控制模块、飞电容模块和输出电容模块。其中，控制模块包括控制电路21，模拟电源AVDD、模拟地AGND以及时钟信号CLK和其他所需的信号线(图中未示出)，控制电路21由模拟电源AVDD和模拟地AGND给其供电，由时钟信号CLK进行驱动；飞电容模块包括飞电容C fly、第一焊盘212、第二焊盘217、第一引脚214和第二引脚216，第一焊盘212的一端通过芯片内部走线211连接控制电路21，第一焊盘212的另一端通过绑定线213连接第一引脚214、第一引脚214通过PCB走线或FPC走线215连接飞电容C fly的CP端，飞电容C fly的CN端通过PCB走线或FPC走线215连接第二引脚216，第二引脚216通过绑定线213连接第二焊盘217的一端，第二焊盘217的另一端通过芯片内部走线211连接控制电路21。输出电容模块包括输出电容C out、第三焊盘219和第三引脚218，第三焊盘219的一端通过芯片内部走线211连接控制电路21，第三焊盘219的另一端通过绑定线213连接第三引脚218，第三引脚218通过PCB走线或FPC走线215连接输出电容C out的第一端，输出电容C out的第二端通过PCB走线或FPC走线215接地GND。电荷泵21、芯片内部走线211，第一焊盘212、第二焊盘217以及第三焊盘219位于芯片内部，飞电容C fly、输出电容C out、PCB走线或FPC走线215位于芯片外部，焊盘通过绑定线213输出信号给引脚，引脚将输出信号输出至PCB走线或FPC走线215。所述第一焊盘212、第二焊盘217以及第三焊盘219通过芯片内部走线211分别连接至控制电路21。输出电容C out的第一端作为电荷泵模块的输出电压端，当然，第三引脚218、第三焊盘219以及与第三焊盘219相连的绑定线和芯片内部走线的电位也为输出电压Vout的电位。根据实际应用需要，芯片外部的走线215可能为PCB走线或FPC走线中的一种，为描述方便，以下简称PCB走线，即下面所述的PCB走线均包含PCB走线和FPC走线两种情形。
图3是本申请第一实施例中可降低电荷泵电磁干扰的电路结构示意图。本实施例用于第一电荷泵模块中的第一输出电容C out1充电和第二电荷泵模块的第二输出电容C out2放电或者第一输出电容C out1放电和第二输出电容C out2充电的情况，即第一输出电容C out1处于充电状态时，电流从第四焊盘321经过第一输出电容C out1流向GND，同时，第二输出电容C out2处于放电状态，电流从GND经过第二输出电容C out2流向第五焊盘326，或者第二输出电容C out2处于充电状态时，电流从第五焊盘326经过第二输出电容C out2流向GND，同时，第一输出电容C out1处于放电状态，电流从GND经过第一输出电容C out1流向第 四焊盘321。输出电容一端相连的PCB走线、芯片内部走线、引脚以及焊盘的电位均为输出电压，比如，以第四焊盘321的输出作为第一电荷泵模块的输出电压Vout1，以第五焊盘326的输出作为第二电荷泵模块的输出电压Vout2。本申请实施例是以第一输出电容C out1处于充电状态、第二输出电容C out2处于放电状态为例进行说明。优选的，本申请实施例以两个电荷泵模块为例进行说明，两个电荷泵模块分别为第一电荷泵模块和第二电荷泵模块，第一电荷泵模块包括第一控制模块和第一输出电容模块，第一输出电容模块包括第一输出电容C out1、第四引脚323和第四焊盘321，第一控制模块通过第四焊盘321与第一输出电容C out1连接；第二电荷泵模块包括第二控制模块和第二输出电容模块，第二输出电容模块包括第二输出电容C out2、第五引脚328和第五焊盘326，第二控制模块通过第五焊盘326与所述第二输出电容C out2连接。第一输出电容C out1的第二端接地GND，第一输出电容C out1的第一端通过PCB走线324与第四引脚323相连、第四引脚323通过绑定线322与第四焊盘321相连。第二输出电容C out2的第二端接地GND，第二输出电容C out2的第一端通过PCB走线329与第五引脚328相连、第五引脚328通过绑定线327与第五焊盘326相连。第一电荷泵模块的第四焊盘321和第二电荷泵模块的第五焊盘326紧邻放置，例如，第四焊盘321与第五焊盘326之间间隔一个焊盘的距离，该焊盘不设置走线，又例如，第四焊盘321与第五焊盘326之间不放置其它焊盘或者第四焊盘321与第五焊盘326之间间隔小于一个焊盘的距离，使其第一电荷泵模块的第四焊盘321、绑定线322、第四引脚323、PCB走线324和第二电荷泵模块的第五焊盘326、绑定线327、第五引脚328、PCB走线329构成的环形面积最小，从而降低来自两个电荷泵的电磁干扰。环形天线的面积越小，电磁干扰影响越小。
图4是本申请第二实施例中可降低电荷泵电磁干扰的电路结构示意图。此实施例用于第一电荷泵模块中的第一输出电容C out1和第二电荷泵模块的第二输出电容C out2处于同时充电或者同时放电的情况，即第一输出电容C out1处于充电状态时，电流从第四焊盘411经过第一输出电容C out1流向GND，同时，第二输出电容C out2处于充电状态，电流从第五焊盘416经过第二输出电容C out2流向GND，接地模块的电流方向与第一输出电容、第二输出电容的电流方向相反，此时接地模块的电流从PCB走线423的芯片外接地端GND通过第六引脚422流向第六焊盘420的芯片内接地端GND；或者第一输出电容C out1处于放电状态时，电流从GND经过第一输出电容C out1流向第四焊盘411，同时，第二输出电容C out2处于放电，电流从GND经过第二输出电容C out2流向第五焊盘416， 接地模块的电流方向与第一输出电容、第二输出电容的电流方向相反，此时接地模块的电流从第六焊盘420的芯片内接地端GND通过第六引脚422流向PCB走线423的芯片外接地端GND。本申请实施例是以第一输出电容C out1处于充电状态、第二输出电容C out2处于充电状态为例进行说明。优选的，本申请实施例以两个电荷泵模块为例进行说明，两个电荷泵模块分别为第一电荷泵模块和第二电荷泵模块，第一电荷泵模块包括第一控制模块和第一输出电容模块，第一输出电容模块包括第一输出电容C out1、第四引脚413和第四焊盘411；第二电荷泵模块包括第二控制模块和第二输出电容模块，第二输出电容模块包括第二输出电容C out2、第五引脚418和第五焊盘416。第一输出电容C out1的第二端接地GND，第一输出电容C out1的第一端通过PCB走线414与第四引脚413相连、第四引脚413通过绑定线412与第四焊盘411相连。第二输出电容C out2的第二端接地GND，第二输出电容C out2的第一端通过PCB走线419与第五引脚418相连、第五引脚418通过绑定线417与第五焊盘416相连。第一输出电容模块和第二输出电容模块之间放置一接地模块，该接地模块包括第六焊盘420和第六引脚422，第六焊盘420的一端连接芯片内接地端GND，第六焊盘420的另一端通过绑定线421与第六引脚422相连、第六引脚422通过PCB走线423连接芯片外接地端GND，其中，第六焊盘420位于第四焊盘411和第五焊盘416之间，第六引脚422位于第四引脚413和第五引脚418之间。接地模块的电流方向与第一输出电容C out1、第二输出电容C out2的电流方向相反，接地模块的电流方向从第六焊盘420的芯片内接地端GND通过第四引脚422流向PCB走线423的芯片外接地端GND，第一电荷泵模块与接地模块、第二电荷泵模块与接地模块之间的连线分别形成两个电流反相的环形天线，从而可以使得远区的电磁场和电磁波相互抵消，降低来自电荷泵的电磁干扰。
本申请还提供一种电荷泵电路结构，在电荷泵电路结构中，第一电荷泵模块还包括第一飞电容模块，第二电荷泵模块还包括第二飞电容模块；根据第一飞电容模块和第二飞电容模块的电流方向，设置不同的电荷泵电路结构。具体以图5和图6为例进行说明。
图5是本申请第三实施例中可降低电荷泵电磁干扰的电路结构示意图。此实施例用于第三电荷泵模块中的第一飞电容C fly1充电和第四电荷泵模块的第二飞电容C fly2放电或者第一飞电容C fly1放电和第二飞电容C fly2充电的情况，即第一飞电容C fly1处于充电状态时，电流从CP1端经过第一飞电容C fly1流向CN1端，同时，第二飞电容C fly2处于放电状态，电流从CN2端经过第二飞电容C fly2流向CP2端，或者第一飞电容C fly1处于放电状态时，电流从CN1端经过第一 飞电容C fly1流向CP1端，同时，第二飞电容C fly2处于充电状态，电流从CP2端经过第二飞电容C fly2流向CN2端。本申请实施例是以第一飞电容C fly1处于充电状态、第二飞电容C fly2处于放电状态为例进行说明。优选的，本申请实施例以两个电荷泵模块为例进行说明，两个电荷泵模块分别为第三电荷泵模块和第四电荷泵模块。第三电荷泵模块包括第一控制模块和第一飞电容模块，第一飞电容模块包括第一飞电容C fly1、第七引脚513、第八引脚516、第七焊盘511以及第八焊盘515，第一控制模块通过第七焊盘511连接第一飞电容的正极板，第一控制模块通过第八焊盘515连接第一飞电容C fly1的负极板，其中，第七焊盘511通过绑定线512与第七引脚513相连，第七引脚513通过PCB走线514与第一飞电容C fly1的CP1端相连，第一飞电容C fly1的CN1端通过PCB走线514与第八引脚516相连，第八引脚516通过绑定线512与第八焊盘515相连，第七焊盘511和第七引脚513为第一飞电容C fly1的CP1端，第八焊盘515和第八引脚516为第一飞电容C fly1的CN1端。第四电荷泵模块包括第二控制模块和第二飞电容模块，第二飞电容模块包括第二飞电容C fly2、第九引脚519、第十引脚522、第九焊盘517以及第十焊盘521，第二控制模块通过第九焊盘519连接第二飞电容C fly2的正极板，所述第二控制模块通过第十焊盘521连接第二飞电容C fly2的负极板，其中，第九焊盘517通过绑定线518与第九引脚519相连，第九引脚519通过PCB走线520与第二飞电容C fly2的CP2端相连，第二飞电容C fly2的CN2端通过PCB走线520与第十引脚522相连，第十引脚522通过绑定线518与第十焊盘521相连，第九焊盘517和第九引脚519为第二飞电容C fly2的CP2端，第十焊盘521和第十引脚522为第二飞电容C fly2的CN2端。第三电荷泵模块的第一飞电容C fly1的两端和第四电荷泵模块的第二飞电容C fly2的两端按顺序依次排列，从左至右依次为：CP1端、CN1端、CP2端、CN2端，或者CN1端、CP1端、CN2端、CP2端，其中，第一飞电容模块和第二飞电容模块之间可以有一定间隔，该间隔可以为多个焊盘的距离，例如，该间隔为不超过2个焊盘的距离。第一飞电容的CN1端和第二飞电容的CP2端的间隔不超过2个焊盘的距离，或第一飞电容的CP1端和第二飞电容的CN2端的间隔不超过2个焊盘的距离，即第八焊盘515和第九焊盘517之间可以间隔为2个焊盘距离、1个焊盘距离或者间隔0个焊盘距离。通过设置第一飞电容和第二飞电容两端和焊盘的连接方式，使第一飞电容模块和第二飞电容模块的电流方向反相，由两个电荷泵模块形成的两个环形天线的辐射电磁场和电磁波刚好也反相，从而在远区相互抵消，而降低来自第三电荷泵模块和第四电荷泵模块的电磁干扰。
图6是本申请第四实施例中可降低电荷泵电磁干扰的电路结构示意图。此实施例用于第三电荷泵模块中的第一飞电容C fly1和第四电荷泵模块的第二飞电容C fly2处于同时充电或者同时放电的情况，即第一飞电容C fly1处于充电状态时，电流从CP1端经过第一飞电容C fly1流向CN1端，同时，第二飞电容C fly2处于充电状态，电流从CP2端经过第二飞电容C fly2流向CN2端，或者第一飞电容C fly1处于放电状态时，电流从CN1端经过第一飞电容C fly1流向CP1端，同时，第二飞电容C fly2处于放电状态，电流从CN2端经过第二飞电容C fly2流向CP2端。本申请实施例是以第三电荷泵模块给第一飞电容C fly1充电、第四电荷泵模块也在给第二飞电容C fly2充电为例进行说明。优选的，本申请实施例以两个电荷泵模块为例进行说明，两个电荷泵模块分别为第三电荷泵模块和第四电荷泵模块。第三电荷泵模块包括第一飞电容模块，第一飞电容模块包括第一飞电容C fly1、第七引脚613、第八引脚616、第七焊盘611以及第八焊盘615，其中，第七焊盘611通过绑定线612与第七引脚613相连，第七引脚613通过PCB走线614与第一飞电容C fly1的CP1端相连，第一飞电容C fly1的CN1端通过PCB走线614与第八引脚616相连，第八引脚616通过绑定线612与第八焊盘615相连，第七焊盘611和第七引脚613为第一飞电容C fly1的CP1端，第八焊盘615和第八引脚616为第一飞电容C fly1的CN1端。第四电荷泵模块包括第二飞电容模块，第二飞电容模块包括第二飞电容C fly2、第九引脚619、第十引脚622、第九焊盘617以及第十焊盘621，其中，第九焊盘617通过绑定线618与第九引脚619相连，第九引脚619通过PCB走线620与第二飞电容C fly2的CN2端相连，第二飞电容C fly2的CP2端通过PCB走线620与第十引脚622相连，第十引脚622通过绑定线618与第十焊盘621相连，第九焊盘617和第九引脚619为第二飞电容C fly2的CN2端，第十焊盘621和第十引脚622为第二飞电容C fly2的CP2端，所述第一飞电容的CN1端和第二飞电容的CP2端的间隔不超过2个焊盘的距离可以是第八焊盘615和第十焊盘621之间的间隔了2个焊盘、1个焊盘或0个焊盘，或者也可以是第八引脚616和第十引脚622之间的间隔了2个焊盘、1个焊盘或0个焊盘；所述第一飞电容的CP1端和第二飞电容的CN2端的间隔不超过2个焊盘的距离可以是第七焊盘611和第九焊盘617之间的间隔了2个焊盘、1个焊盘或0个焊盘，或者也可以是第七引脚613和第九引脚619之间的间隔了2个焊盘、1个焊盘或0个焊盘；所述第一飞电容的CN1端和第二飞电容的CN2端的间隔不超过2个焊盘的距离可以是第八焊盘615和第九焊盘617之间的间隔了2个焊盘、1个焊盘或0个焊盘，或者也可以是第八引脚616和第九引脚619之间的间隔了2个焊盘、1个焊盘或0 个焊盘；所述第一飞电容的CP1端和第二飞电容的CP2端的间隔不超过2个焊盘的距离可以是第七焊盘611和第十焊盘621之间的间隔了2个焊盘、1个焊盘或0个焊盘，或者也可以是第七引脚613和第十引脚622之间的间隔了2个焊盘、1个焊盘或0个焊盘。第三电荷泵模块的第一飞电容C fly1的两端和第四电荷泵模块的第二飞电容C fly2的两端按顺序依次排列，从左至右依次为：CP1端、CN1端、CN2端、CP2端，或者CN1端、CP1端、CP2端、CN2端，其中，第一飞电容模块和第二飞电容模块之间可以有一定间隔，该间隔可以为多个焊盘的距离，优选的，该间隔为不超过2个焊盘的距离。第一飞电容的CN1端和第二飞电容的CN2端的间隔不超过2个焊盘的距离，或所述第一飞电容的CP1端和第二飞电容的CP2端的间隔不超过2个焊盘的距离，即第八焊盘615和第九焊盘617之间可以间隔2个焊盘距离、1个焊盘距离或者间隔0个焊盘距离。通过设置第一飞电容和第二飞电容两端和焊盘的连接方式，使第一飞电容模块和第二飞电容模块的的电流方向反相，由两个电荷泵模块形成的两个环形天线的辐射电磁场和电磁波刚好反相，从而在远区相互抵消，而降低来自第三电荷泵模块和第四电荷泵模块的电磁干扰。
图7是本申请第五实施例中可降低电荷泵电磁干扰的电路结构示意图。芯片711包括硅片710，电荷泵模块包括控制模块712、飞电容模块和输出电容模块。飞电容模块包括飞电容C fly、第一焊盘714、第二焊盘718、第一引脚716和第二引脚719，第一焊盘714的一端通过芯片内部走线713连接控制模块712，第一焊盘714的另一端通过绑定线715连接第一引脚716、第一引脚716通过PCB走线717连接飞电容C fly的CP端，飞电容C fly的CN端通过PCB走线717连接第二引脚719，第二引脚719通过绑定线715连接第二焊盘718。输出电容模块包括输出电容C out、第三焊盘720和第三引脚721，第三焊盘720的一端通过芯片内部走线713连接控制模块712，第三焊盘720的另一端通过绑定线715连接第三引脚721，第三引脚721通过PCB走线717连接输出电容C out的第一端，输出电容C out的第二端通过PCB走线717接地GND。芯片内部的走线713、绑定线715和PCB走线717都应尽可能短。飞电容C fly的第一焊盘714和第二焊盘718应紧邻放置，即第一焊盘714和第二焊盘718之间不放置任何其他焊盘或者第一焊盘714与第二焊盘718之间间隔小于一个焊盘的距离，如此由飞电容C fly连线形成的环形天线的回路面积可尽可能减小，从而可降低来自电荷泵的电磁干扰。此外，在实际的版图设计中，为降低绑定线上的阻抗，通常会使用两个焊盘通过两条绑定线打在同一个引脚上，如此可将绑定线上的电阻和电感并联，将阻抗降低一半。但是，为降低来自电荷泵的电磁干扰，飞电容C fly 的任意一个引脚不同时连接两个焊盘和两条绑定线，而应连接单个焊盘和单条绑定线。通过将一个引脚设置连接单个焊盘和单条绑定线，绑定线上的电阻和电感可以阻挡来自控制模块712的高频电流往芯片外部流动，从而降低环形天线中的高频电流，而降低来自电荷泵模块的电磁干扰。
图8是本申请第六实施例中可降低电荷泵电磁干扰的电路结构示意图。芯片包括顶层金属层82和非顶层金属层，非顶层金属层包括硅片基底层81、顶层金属层82下的绝缘层83和位于绝缘层83下面的、仅次于顶层金属层82的次层金属层84以及其他金属层(图中未示出)。飞电容和输出电容均通过各自的PCB走线、引脚、绑定线、焊盘以及芯片内部走线连接到控制模块，应避免将飞电容和输出电容在芯片内部的走线设置在顶层金属层82，否则其产生的电磁场和电磁波会直接向外辐射，使得电磁干扰较大。将飞电容和输出电容在芯片内部的走线设置在非顶层金属层，即将芯片内部走线设置在次层金属层84或比次层金属层84还要靠硅片基底层81方向的其他金属层(图中未示出)，且将顶层金属层82用来设置接地线或电源线。这是因为，飞电容和输出电容在芯片内部的走线上存在高频电流，而高频电流会优先选择阻抗较低的路径走，飞电容和输出电容在芯片内部的走线与地线和电源线形成的耦合电容会让高频电流优先选择流过，避免其流至芯片外部的走线而造成EMI较大。此外，顶层金属层82通过设置地线和电源线使其形成一层屏蔽层，减小来自芯片内部的电磁干扰。
图9是本申请第七实施例中可降低电荷泵电磁干扰的电路结构示意图。芯片911包括硅片910，电荷泵模块包括控制模块912、飞电容模块和输出电容模块。飞电容模块包括飞电容C fly、第一焊盘914、第二焊盘918、第一引脚916和第二引脚919，第一焊盘914的一端通过芯片内部走线913连接控制模块912，第一焊盘914的另一端通过绑定线915连接第一引脚916、第一引脚916通过PCB走线917连接飞电容C fly的CP端，飞电容C fly的CN端通过PCB走线917连接第二引脚919，第二引脚919通过绑定线915连接第二焊盘918。输出电容模块包括输出电容C out、第三焊盘920和第三引脚921，第三焊盘920的一端通过芯片内部走线913连接控制模块912，第三焊盘920的另一端通过绑定线915连接第三引脚921，第三引脚921通过PCB走线917连接输出电容C out的第一端，输出电容C out的第二端通过PCB走线917接地GND。电荷泵模块位于芯片911的一角，且电荷泵912与焊盘之间的芯片内部走线913的长度设置得尽可能短。图中所示电荷泵模块912位于芯片911的左下角，也可位于芯片911的左上角、右上角或者右下角。如此可尽量减少电荷泵912及其芯片内部走线 913与芯片911中其他电路的耦合机会，从而防止电荷泵912通过芯片911的其他电路模块输出高频电流，而产生电磁干扰。
以上实施例可以以任意方式结合，可以是2个实施例相结合，也可以是多个实施例相结合，图10是以第一实施例、第三实施例和第七实施例相结合为例进行说明。
请参考图10，芯片1011包括硅片1010，第一电荷泵模块包括第一控制模块1012、飞电容模块和输出电容模块。第一电荷泵模块的飞电容模块包括第一飞电容C fly1、第一焊盘1014、第二焊盘1030、第一引脚1016和第二引脚1029，第一焊盘1014的一端通过芯片内部走线1013连接第一控制模块1012，第一焊盘1014的另一端通过绑定线1015连接第一引脚1016、第一引脚1016通过PCB走线1017连接第一飞电容C fly1的CP1端，第一飞电容C fly1的CN1端通过PCB走线1017连接第二引脚1029，第二引脚1029通过绑定线1015连接第二焊盘1030。第一电荷泵模块的输出电容模块包括第一输出电容C out1、第三焊盘1028和第三引脚1025，第三焊盘1028的一端通过芯片内部走线1013连接第一控制模块1012，第三焊盘1028的另一端通过绑定线1015连接第三引脚1025，第三引脚1025通过PCB走线1017连接第一输出电容C out1的第一端，第一输出电容C out1的第二端通过PCB走线1017接地GND。第二电荷泵模块包括第二控制模块1018、飞电容模块和输出电容模块。第二电荷泵模块的飞电容模块包括第二飞电容C fly2、第四焊盘1020、第五焊盘1032、第四引脚1022和第五引脚1033，第四焊盘1020的一端通过芯片内部走线1019连接第二控制模块1018，第四焊盘1020的另一端通过绑定线1021连接第四引脚1022、第四引脚1022通过PCB走线1023连接第二飞电容C fly2的CN2端，第二飞电容C fly2的CP2端通过PCB走线1023连接第五引脚1033，第五引脚1033通过绑定线1021连接第五焊盘1032。输出电容模块包括第二输出电容C out2、第六焊盘1027和第六引脚1026，第六焊盘1027的一端通过芯片内部走线1019连接第二控制模块1018，第六焊盘1027的另一端通过绑定线1021连接第六引脚1026，第六引脚1026通过PCB走线1023连接第二输出电容C out2的第一端，第二输出电容C out2的第二端通过PCB走线1021接地GND。第一电荷泵模块和第二电荷泵模块均位于芯片1011的左下角，当然，也可同时位于芯片1011的左上角、右上角或者右下角，或者第一电荷泵模块和第二电荷泵模块分别位于芯片1011的不同角落。当第一电荷泵模块中的第一输出电容C out1充电和第二电荷泵模块中的第二输出电容C out2放电时，第一输出电容C out1的第三焊盘1028和第二输出电容C out2的第六焊盘1027应紧邻放置，即第三焊盘1028与第六焊盘1027之间不要放置 其它焊盘或第三焊盘1028与第六焊盘1027之间间隔小于一个焊盘的距离，使其第一电荷泵模块的第三焊盘1028、绑定线1015、第三引脚1025、PCB走线1017和第二电荷泵模块的第六焊盘1027、绑定线1021、第六引脚1026、PCB走线1023构成的环形面积最小，从而降低来自两个电荷泵的电磁干扰。环形天线的面积越小，电磁干扰影响越小。此外，当第一输出电容C out1充电和第二输出电容C out2放电时，第一飞电容C fly1处于放电状态和第二飞电容C fly2处于充电状态，因此，第一飞电容C fly1的两端和第二飞电容C fly2的两端按顺序依次排列，从左至右依次为：CP1端、CN1端、CP2端、CN2端，或者CN1端、CP1端、CN2端、CP2端，可使远处的电磁场刚好抵消，从而减小电磁干扰。与此同时，通过将第一电荷泵模块和第二电荷泵模块设置在角落，可尽量减少电荷泵1012及其芯片内部走线1013与芯片1011中其他电路的耦合机会，防止电荷泵1012通过芯片1011的其他电路模块输出高频电流而产生电磁干扰，降低电磁干扰带来的影响。通过多个实施例的结合方式，进一步降低了电磁干扰，显著提高了芯片的性能。
以上仅为本申请的实施例而已，并不用于限制本申请。对于本领域技术人员来说，本申请可以有各种更改和变化。凡在本申请的精神和原理之内所作的任何修改、等同替换、改进等，均应包含在本申请的权利要求范围之内。

Claims (22)

  1. 一种电荷泵电路，其特征在于，包括：
    第一电荷泵模块和第二电荷泵模块；
    第一电荷泵模块包括第一控制模块、第一输出电容和第四焊盘，所述第一控制模块通过所述第四焊盘与所述第一输出电容连接，所述第一控制模块用于控制对所述第一输出电容充电和放电；
    第二电荷泵模块包括第二控制模块、第二输出电容和第五焊盘，所述第二控制模块通过所述第五焊盘与所述第二输出电容连接，所述第二控制模块用于控制对所述第二输出电容充电和放电；
    当所述第一输出电容处于充电状态、所述第二输出电容处于放电状态，或者所述第一输出电容处于放电状态、所述第二输出电容处于充电状态时，所述第四焊盘和所述第五焊盘紧邻放置；或者
    当所述第一输出电容处于充电状态、所述第二输出电容处于充电状态，或者所述第一输出电容处于放电状态、所述第二输出电容处于放电状态时，所述第四焊盘和所述第五焊盘之间放置一个接地模块。
  2. 根据权利要求1所述的电荷泵电路，其特征在于，所述第四焊盘与所述第五焊盘紧邻放置为所述第四焊盘与所述第五焊盘之间的间隔小于一个焊盘的距离。
  3. 根据权利要求1所述的电荷泵电路，其特征在于，
    第一电荷泵模块还包括第四引脚，所述第一控制模块通过所述第四焊盘与所述第四引脚连接；
    第二电荷泵模块还包括第五引脚，所述第二控制模块通过所述第五焊盘与所述第五引脚连接。
  4. 根据权利要求3所述的电荷泵电路，其特征在于，
    所述接地模块包括第六焊盘和第六引脚，其中，所述第六焊盘位于所述第四焊盘和所述第五焊盘之间，所述第六引脚位于所述第四引脚和所述第五引脚之间。
  5. 根据权利要求1所述的电荷泵电路，其特征在于，
    所述接地模块的电流方向与所述第一输出电容、所述第二输出电容的电流方向相反。
  6. 根据权利要求1所述的电荷泵电路，其特征在于，
    第一电荷泵模块还包括第一飞电容，第二电荷泵模块还包括第二飞电容。
  7. 根据权利要求6所述的电荷泵电路，其特征在于，
    当第一飞电容处于充电状态，第二飞电容处于放电状态时，所述第一飞电容的CN1端和第二飞电容的CP2端的间隔不超过2个焊盘的距离，或所述第一飞电容的CP1端和第二飞电容的CN2端的间隔不超过2个焊盘的距离；或者
    当第一飞电容处于放电状态，第二飞电容处于充电状态时，所述第一飞电容的CN1端和第二飞电容的CP2端的间隔不超过2个焊盘的距离，或所述第一飞电容的CP1端和第二飞电容的CN2端的间隔不超过2个焊盘的距离。
  8. 根据权利要求6所述的电荷泵电路，其特征在于，
    当第一飞电容处于充电状态，第二飞电容处于充电状态时，所述第一飞电容的CN1端和第二飞电容的CN2端的间隔不超过2个焊盘的距离，或所述第一飞电容的CP1端和第二飞电容的CP2端的间隔不超过2个焊盘的距离；或者
    当第一飞电容处于放电状态，第二飞电容处于放电状态时，所述第一飞电容的CN1端和第二飞电容的CN2端的间隔不超过2个焊盘的距离，或所述第一飞电容的CP1端和第二飞电容的CP2端的间隔不超过2个焊盘的距离。
  9. 根据权利要求1所述的电荷泵电路，其特征在于，
    所述第一电荷泵模块和所述第二电荷泵模块均位于芯片的左上角、右上角、左下角或右下角。
  10. 根据权利要求1所述的电荷泵电路，其特征在于，
    所述第一电荷泵模块和第二电荷泵模块分开放置，分别位于芯片的左上角、右上角、左下角或右下角。
  11. 根据权利要求3所述的电荷泵电路，其特征在于，还包括
    芯片内部走线、绑定线和PCB走线。
  12. 根据权利要求11所述的电荷泵电路，其特征在于，
    所述第一输出电容的第二端接地，所述第一输出电容的第一端通过所述PCB走线与所述第四引脚相连、所述第四引脚通过所述绑定线与所述第四焊盘相连；
    所述第二输出电容的第二端接地，所述第二输出电容的第一端通过所述PCB走线与所述第五引脚相连、所述第五引脚通过所述绑定线与所述第五焊盘相连。
  13. 根据权利要求11所述的电荷泵电路，其特征在于，
    所述第一电荷泵模块包括第一飞电容、第七引脚、第八引脚、第七焊盘以及第八焊盘；
    所述第二电荷泵模块包括第二飞电容、第九引脚、第十引脚、第九焊盘以及第十焊盘；
    所述第七焊盘通过一根所述绑定线与所述第七引脚相连，所述第七引脚通过所述PCB走线与所述第一飞电容的CP1端相连，所述第一飞电容的CN1端通过所述PCB走线与所述第八引脚相连，所述第八引脚通过一根所述绑定线与所述第八焊盘相连；
    所述第九焊盘通过一根所述绑定线与所述第九引脚相连，所述第九引脚通过所述PCB走线与所述第二飞电容的CP2端相连，所述第二飞电容的CN2端通过所述PCB走线与所述第十引脚相连，所述第十引脚通过一根所述绑定线与所述第十焊盘相连。
  14. 根据权利要求1所述的电荷泵电路结构，其特征在于，
    芯片包括：顶层金属层；电源线和/或地线设置在所述顶层金属层。
  15. 根据权利要求14所述的电荷泵电路，其特征在于，
    所述芯片包括：非顶层金属层；所述芯片内部走线设置在所述非顶层金属层。
  16. 根据权利要求13所述的电荷泵电路，其特征在于，
    所述第七焊盘和所述第八焊盘的间隔小于一个焊盘的距离，或者所述第九焊盘和所述第十焊盘的间隔小于一个焊盘的距离。
  17. 根据权利要求13所述的电荷泵电路结构，其特征在于，
    所述第一控制模块、所述第二控制模块以及所述芯片内部走线位于所述芯片内。
  18. 根据权利要求13所述的电荷泵电路结构，其特征在于，
    所述第一输出电容、第二输出电容、第一飞电容、第二飞电容以及PCB走线位于所述芯片外。
  19. 根据权利要求1所述的电荷泵电路结构，其特征在于，所述电荷泵电路的输出电压提供给低压线性稳压电路。
  20. 一种芯片，其特征在于，包括如权利要求1-19中任意一项所述的电荷泵电路。
  21. 根据权利要求20所述的芯片，其特征在于，所述芯片为触控芯片。
  22. 一种电子设备，其特征在于，包括：如权利要求20或21所述的芯片。
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