WO2021134828A1 - 像素驱动电路、驱动方法及其显示面板 - Google Patents

像素驱动电路、驱动方法及其显示面板 Download PDF

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WO2021134828A1
WO2021134828A1 PCT/CN2020/071816 CN2020071816W WO2021134828A1 WO 2021134828 A1 WO2021134828 A1 WO 2021134828A1 CN 2020071816 W CN2020071816 W CN 2020071816W WO 2021134828 A1 WO2021134828 A1 WO 2021134828A1
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row
pixel
capacitor
scan signal
stage
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PCT/CN2020/071816
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English (en)
French (fr)
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付舰航
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深圳市华星光电半导体显示技术有限公司
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Publication of WO2021134828A1 publication Critical patent/WO2021134828A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]

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  • This application relates to the field of display technology, and more specifically, to a pixel driving circuit, a driving method and a display panel thereof.
  • driving circuits for display devices have become an important research hotspot.
  • a display device driven by a current type its luminous brightness depends on the gate-source current flowing through the Driving TFT (driving thin film transistor).
  • Driving TFT driving thin film transistor
  • the slope of the brightness-current curve of the LED is very large, and a weak current change will cause a brightness change that is perceptible to the human eye. Therefore, if the Micro LED panel adopts the traditional driving circuit, it is difficult to accurately control the driving current of the LED, and the display accuracy is low.
  • an embodiment of the present invention provides a pixel driving circuit, including:
  • the first thin film transistor the gate of the first thin film transistor is connected to the first node, the source is connected to the second node, and the drain is used to connect to the high voltage of the power supply;
  • a second thin film transistor the gate of the second thin film transistor is used to connect to the scan signal of the Nth row of pixels, the source is connected to the first node, and the drain is used to connect to the data signal;
  • the first capacitor one end of the first capacitor is connected to the first node, and the other end is connected to the third node;
  • the third thin film transistor, the gate of the third thin film transistor is used to access the scan signal of the pixel in the N+1th row, the source is connected to the third node, and the drain is connected to the second node;
  • a second capacitor one end of the second capacitor is connected to the third node, and the other end is connected to the fourth node;
  • a fourth thin film transistor the gate of the fourth thin film transistor is used to access the scan signal of the pixel in the N+2th row, the source is connected to the fourth node, and the drain is connected to the second node;
  • a third capacitor one end of the third capacitor is connected to the fourth node, and the other end is connected to the second node;
  • the light-emitting diode, the anode of the light-emitting diode is connected to the second node, and the cathode is used to connect the low voltage of the power supply.
  • the embodiment of the present invention also provides a pixel driving method applied to the above-mentioned pixel driving circuit, which includes the following steps:
  • the LED is controlled to emit light
  • the display period of one frame is sequentially divided into the first stage, the second stage, the third stage, the fourth stage, the fifth stage, and the sixth stage.
  • an embodiment of the present invention also provides a display panel including a pixel driving circuit; the pixel driving circuit includes:
  • the first thin film transistor the gate of the first thin film transistor is connected to the first node, the source is connected to the second node, and the drain is used to connect to the high voltage of the power supply;
  • a second thin film transistor the gate of the second thin film transistor is used to connect to the scan signal of the Nth row of pixels, the source is connected to the first node, and the drain is used to connect to the data signal;
  • the first capacitor one end of the first capacitor is connected to the first node, and the other end is connected to the third node;
  • the third thin film transistor, the gate of the third thin film transistor is used to access the scan signal of the pixel in the N+1th row, the source is connected to the third node, and the drain is connected to the second node;
  • a second capacitor one end of the second capacitor is connected to the third node, and the other end is connected to the fourth node;
  • a fourth thin film transistor the gate of the fourth thin film transistor is used to access the scan signal of the pixel in the N+2th row, the source is connected to the fourth node, and the drain is connected to the second node;
  • a third capacitor one end of the third capacitor is connected to the fourth node, and the other end is connected to the second node;
  • the light-emitting diode, the anode of the light-emitting diode is connected to the second node, and the cathode is used to connect the low voltage of the power supply.
  • the gate of the first thin film transistor is connected to the first node, the source is connected to the second node, and the drain is used to connect to the high voltage of the power supply; the gate of the second thin film transistor is used to Access to the scan signal of the Nth row of pixels, the source is connected to the first node, and the drain is used to access the data signal; one end of the first capacitor is connected to the first node, and the other end is connected to the third node; the gate of the third thin film transistor Used to connect to the scan signal of the N+1th row of pixels, the source is connected to the third node, and the drain is connected to the second node; one end of the second capacitor is connected to the third node, and the other end is connected to the fourth node; The gate is used to access the scan signal of the pixel in the N+2 row, the source is connected to the third and fourth nodes, and the drain is connected to the second node; one end of the third capacitor is connected to the fourth node;
  • This application can control the on and off of the second thin film transistor, the third thin film transistor, and the fourth thin film transistor, perform two-level capacitor discharge and charge distribution among the capacitors (the first capacitor, the second capacitor, and the third capacitor).
  • the precise control of the drive current of the LED in the display panel further improves the display accuracy.
  • Fig. 1 is a schematic diagram of a conventional 2T1C pixel driving circuit
  • Fig. 2 is a schematic diagram of a brightness-current curve of an LED in an embodiment
  • FIG. 3 is a schematic diagram of a first structure of a pixel driving circuit in an embodiment
  • FIG. 4 is a schematic diagram of the equivalent circuit of the first stage of the pixel driving circuit in an embodiment
  • FIG. 5 is a schematic diagram of an equivalent circuit of the second stage of the pixel driving circuit in an embodiment
  • FIG. 6 is a schematic diagram of an equivalent circuit of the third stage of the pixel driving circuit in an embodiment
  • FIG. 7 is a schematic diagram of an equivalent circuit of the fourth stage of the pixel driving circuit in an embodiment
  • FIG. 8 is a schematic diagram of an equivalent circuit of the fifth stage of the pixel driving circuit in an embodiment
  • FIG. 9 is a schematic diagram of a second structure of a pixel driving circuit in an embodiment.
  • FIG. 10 is a schematic flowchart of a pixel driving method in an embodiment.
  • FIG. 1 is a schematic diagram of a common driving pixel circuit of a micro light emitting diode or an organic light emitting diode.
  • This 2T1C pixel circuit mainly includes a thin film transistor T1 as a driving thin film transistor (TFT), a thin film transistor T2 as a switching thin film transistor, a storage capacitor C and a light emitting diode LED.
  • the light emitting diode LED can be a micro light emitting diode or an organic light emitting diode
  • thin film transistor T2 is controlled by the scan signal SCAN of the corresponding row of pixels to control whether the corresponding data signal V data is input.
  • FIG. 2 it is a schematic diagram of the brightness-current curve of the LED.
  • the slope of the brightness-current curve of the LED is very large, and a weak current change will cause a brightness change perceptible to the human eye. Therefore, if the micro-light-emitting diode display panel adopts a traditional driving circuit, such as the circuit shown in FIG. 1, the driving current of the LED must be controlled very accurately, which is more difficult. Because the resolution of the output voltage of the source chip is limited, it is difficult to accurately control the LED current to generate enough gray levels.
  • the pixel drive circuit proposed in this application improves the original pixel drive circuit.
  • the improved pixel drive circuit adds two capacitors and two thin film transistors on the basis of the original pixel drive circuit.
  • the storage capacitors in some pixel circuits are connected in series, and the two additional thin film transistors are respectively connected to the common point between two adjacent capacitors and the source of the driving thin film transistor (N-type), which can achieve a lower output voltage resolution
  • the source chip carries out fine current control, which greatly improves the display efficiency.
  • a pixel driving circuit including:
  • the first thin film transistor 310 the gate of the first thin film transistor 310 is connected to the first node G, the source is connected to the second node S, and the drain is used to connect to the high voltage of the power supply;
  • the second thin film transistor 320 the gate of the second thin film transistor 320 is used for accessing the scan signal of the Nth row of pixels, the source is connected to the first node G, and the drain is used for accessing the data signal;
  • the first capacitor 330 one end of the first capacitor 330 is connected to the first node G, and the other end is connected to the third node A;
  • the third thin film transistor 340, the gate of the third thin film transistor 340 is used to access the scan signal of the pixel in the N+1th row, the source is connected to the third node A, and the drain is connected to the second node S;
  • One end of the second capacitor 350 is connected to the third node A, and the other end is connected to the fourth node B;
  • the fourth thin film transistor 360 the gate of the fourth thin film transistor 360 is used to access the scan signal of the pixel in the N+2th row, the source is connected to the fourth node B, and the drain is connected to the second node S;
  • the third capacitor 370 one end of the third capacitor 370 is connected to the fourth node B, and the other end is connected to the second node S;
  • the light emitting diode 380, the anode of the light emitting diode 380 is connected to the second node S, and the cathode is used to connect to the low voltage of the power supply.
  • the first node G refers to a common connection point between the first thin film transistor 310, the second thin film transistor 320, and the first capacitor 330.
  • the second node S refers to a common connection point between the first thin film transistor 310, the third thin film transistor 340, the fourth thin film transistor 360, the third capacitor 370 and the light emitting diode 380.
  • the third node A refers to a common connection point between the first capacitor 330, the second capacitor 350, and the third thin film transistor 340.
  • the fourth node B refers to a common connection point between the second capacitor 350, the third capacitor 370, and the fourth thin film transistor 360.
  • the scan signal of the Nth row of pixels may be provided to the gate of the second thin film transistor 320 through the scan control line of the Nth row of pixels.
  • the scan signal of the N+1th row of pixels may be provided to the gate of the third thin film transistor 340 through the scan control line of the N+1th row of pixels.
  • the scan signal of the N+2th row of pixels can be provided to the gate of the fourth thin film transistor 360 through the scan control line of the N+2th row of pixels.
  • the data signal may be provided to the source of the second thin film transistor 320 through the data control line.
  • N is a positive integer greater than or equal to 1.
  • the gate of the first thin film transistor 310 is connected to the first node G, the source is connected to the second node S, and the drain is used to connect to the high voltage of the power supply; the gate of the second thin film transistor 320
  • the electrode is used to connect to the scan signal of the Nth row of pixels, the source is connected to the first node G, and the drain is used to connect to the data signal; one end of the first capacitor 330 is connected to the first node G, and the other end is connected to the third node A;
  • the gate of the third thin film transistor 340 is used to access the scan signal of the pixel in the N+1th row, the source is connected to the third node A, and the drain is connected to the second node S; one end of the second capacitor 350 is connected to the third node A, The other end is connected to the fourth node B; the gate of the fourth thin film transistor 360 is used to access the scanning signal of the N+2th row of pixels, the source is connected to the
  • the two-level capacitor discharge and the charge between the capacitors are performed. Distribution, to achieve precise control of the drive current of the LED in the display panel, and to further improve the display accuracy.
  • the driving timing of the pixel driving circuit includes five stages: in the first stage, the scan signal of the pixel in the Nth row remains high, and the scan signal of the pixel in the N+1th row and the N+2th pixel are maintained at a high level.
  • the scanning signals of the pixels of the row are kept low respectively; in the second stage, the scanning signals of the pixels of the Nth row are kept low, the scanning signals of the pixels of the N+1th row keep high, and the scanning of the pixels of the N+2th row The signal remains low; in the third stage, the scan signal of the pixel in the Nth row remains low, the scan signal of the pixel in the N+1 row remains low, and the scan signal of the pixel in the N+2 row remains low ; In the fourth stage, the scan signal of the pixel in the Nth row remains low, the scan signal of the pixel in the N+1 row remains low, and the scan signal of the pixel in the N+2 row remains high; in the fifth stage , The scan signal of the pixel in the Nth row is kept at a low level, the scan signal of the pixel in the N+1th row is kept at a low level, and the scan signal of the pixel in the N+2th row is kept at a low level.
  • U 1 is the voltage of the first capacitor C1
  • U A is the voltage of the equivalent capacitor CA
  • C 1 is the capacitance of the first capacitor C1
  • C A is the equivalent capacitance CA of the capacitor.
  • the scan signal SCANn of the Nth row pixel is turned off, the scan signal SCANn+1 of the N+1th row pixel is turned on, and the scan signal SCANn+ of the N+2th row pixel 2 is turned off, the third thin film transistor T3 is turned on, and the equivalent circuit diagram is shown in FIG. 5. Wherein the equivalent capacitance CA discharges capacitor C1 of the first voltage U 1 is maintained unchanged.
  • the scan signal SCANn of the pixel in the Nth row is turned off, the scan signal SCANn+1 of the pixel in the N+1th row is turned off, the third thin film transistor T3 is turned off, and the charge is again between the equivalent capacitor CA and the first capacitor C1.
  • the equivalent circuit diagram is shown in Figure 6. At this time, the circuit satisfies the following relationship:
  • the scan signal SCANn of the Nth row pixel is turned off, the scan signal SCANn+1 of the N+1th row pixel is turned off, and the scan signal SCANn+ of the N+2th row pixel 2 is turned on, the fourth thin film transistor T4 is turned on, and the equivalent circuit diagram is shown in FIG. 7.
  • the first capacitor C1 and the second capacitor C2 connected in series are equivalent to an equivalent capacitor CB.
  • the third capacitor C3 is discharged, and the capacitance of the equivalent capacitor CB remains unchanged U B ′.
  • the voltage relationship of the two capacitors on the equivalent circuit is:
  • U′ 3 is the voltage of the third capacitor C3
  • U B ′ is the voltage of the equivalent capacitor CB
  • C 3 is the capacitance of the third capacitor C1
  • C B is the capacitance of the equivalent capacitor CB.
  • the scan signal SCANn of the pixel in the Nth row is turned off, the scan signal SCANn+1 of the pixel in the N+1 row is turned off, the scan signal SCANn+2 of the pixel in the Nth row is turned off, and the fourth thin film transistor T4 is turned off.
  • the equivalent circuit diagram is shown in Figure 8. At this time, the circuit satisfies the following relationship:
  • a lower-resolution source IC can be used to perform finer current control, to achieve precise control of the driving current of the LED in the display panel, and to further improve the display accuracy. It can meet the driving requirements of Micro LED and other light-emitting diodes, and can be applied to various display panels such as OLED.
  • a pixel driving circuit includes a second thin film transistor 920, a first thin film transistor 910, a first capacitor 930, a third thin film transistor 940, and a second thin film transistor.
  • the pixel driving circuit further includes a fifth thin film transistor 990; the gate of the fifth thin film transistor 990 is connected to the control signal, the source is connected to the second node s, and the drain is used to connect to the reference voltage.
  • a control signal can be provided to the gate of the fifth thin film transistor through a control line (Pre-charge).
  • the pixel driving circuit of the above embodiment improves the traditional 3T1C pixel circuit, and can realize fine current control by using a source chip with a lower output voltage resolution.
  • the two-level capacitor discharge and the charge distribution among the capacitors are performed , To achieve precise control of the drive current of the LED in the display panel, and further improve the display accuracy.
  • the driving timing of the pixel driving circuit includes five stages: in the first stage, the control signal is maintained at a high level, the scanning signal of the pixel in the Nth row is maintained at a high level, and the pixel in the N+1th row is maintained at a high level.
  • the scan signal and the scan signal of the pixel in the N+2 row are kept low respectively; in the second stage, the control signal is kept low, the scan signal of the pixel in the N row remains low, and the pixel in the N+1 row is scanned The signal remains high, and the scan signal of the pixel in row N+2 remains low; in the third stage, the control signal remains low, the scan signal of the pixel in row N remains low, and the pixel in row N+1 The scan signal of the pixel in the Nth row remains low, and the scan signal of the pixel in the N+2th row remains low; in the fourth stage, the control signal remains low, and the scan signal of the pixel in the Nth row remains low, and the scan signal of the pixel in the N+1th row remains low.
  • the scan signal of the pixel in the row remains low, and the scan signal of the pixel in the N+2 row remains high; in the fifth stage, the control signal remains low, the scan signal of the pixel in the Nth row remains low, and the scan signal of the pixel in the Nth row remains low.
  • the scan signal of the pixel in the +1 row remains low, and the scan signal of the pixel in the N+2th row remains low.
  • the current flowing through the light-emitting diode is:
  • V ref is the reference voltage connected to the source of the fifth thin film transistor.
  • a lower-resolution source IC (source IC) can be used to perform finer current control, to achieve precise control of the driving current of the LED in the display panel, and to further improve the display accuracy.
  • the light emitting diode is OLED (organic light emitting diode), Micro LED (micro light emitting diode), Mini LED (mini light emitting diode) or ⁇ LED (micro light emitting diode).
  • a pixel driving method which includes the following steps:
  • step S110 the first capacitor, the second capacitor, and the third capacitor are charged separately in the first stage.
  • Step S120 keeping the voltage value of the first capacitor unchanged in the second stage, and respectively discharging the second capacitor and the third capacitor.
  • Step S130 performing charge distribution among the first capacitor, the second capacitor, and the third capacitor in the third stage.
  • Step S140 keeping the voltage values of the first capacitor and the second capacitor unchanged in the fourth stage, and discharging the third capacitor.
  • Step S150 performing charge distribution among the first capacitor, the second capacitor, and the third capacitor in the fifth stage.
  • step S160 the light emitting diode is controlled to emit light in the sixth stage.
  • the display period of one frame is sequentially divided into the first stage, the second stage, the third stage, the fourth stage, the fifth stage and the sixth stage.
  • the step of separately charging the first capacitor, the second capacitor, and the third capacitor in the first stage includes:
  • the steps of separately discharging the second capacitor and the third capacitor include:
  • the scanning signal of the pixels in the Nth row is controlled to maintain a low level, the scanning signals of the pixels in the N+1th row are maintained at a high level, and the scanning signals of the pixels in the N+2th row are maintained at a low level;
  • the step of performing charge distribution among the first capacitor, the second capacitor and the third capacitor in the third stage includes:
  • the step of discharging the third capacitor includes:
  • the step of performing charge distribution among the first capacitor, the second capacitor, and the third capacitor in the fifth stage includes:
  • the scan signal of the pixel in the Nth row is controlled to maintain a low level
  • the scan signal of the pixel in the N+1th row is maintained at a low level
  • the scan signal of the pixel in the N+2th row is maintained at a low level.
  • the two-stage capacitor discharge and the charge distribution among the capacitors are performed. , To achieve precise control of the drive current of the LED in the display panel, and further improve the display accuracy.
  • steps in the flowchart of FIG. 10 are displayed in sequence as indicated by the arrows, these steps are not necessarily performed in sequence in the order indicated by the arrows. Unless specifically stated in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least part of the steps in FIG. 10 may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution of these sub-steps or stages The sequence is not necessarily performed sequentially, but may be performed alternately or alternately with at least a part of other steps or sub-steps or stages of other steps.
  • a display panel is also provided, and the display panel includes the pixel driving circuit as described above.
  • this application is particularly suitable for miniature light-emitting diode display panels, but is not limited to this, and can be applied to various current-driven display panels, such as organic light-emitting diode display panels, mini LED display panels, which can be improved Drive current control accuracy.
  • a display device is also provided, and the display device includes the above-mentioned display panel.
  • the display panel is an OLED display panel, a Micro LED display panel, a Mini LED display panel or a ⁇ LED display panel.
  • Non-volatile memory may include read only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory.
  • Volatile memory may include random access memory (RAM) or external cache memory.
  • RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous chain Channel (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

Abstract

本申请公开了一种像素驱动电路、驱动方法及其显示面板，该像素驱动电路包括：第一薄膜晶体管，第二薄膜晶体管，第一电容，第三薄膜晶体管，第二电容，第四薄膜晶体管，第三电容以及发光二极管。其中，第四薄膜晶体管的栅极用于接入第N+2行像素的扫描信号，源极连接第三四节点，漏极连接第二节点；本申请能够通过控制第二薄膜晶体管、第三薄膜晶体管和第四薄膜晶体管的通断，进行两级电容放电及各个电容(第一电容、第二电容和第三电容)之间电荷分配，实现精确控制显示面板中发光二极管的驱动电流，进一步提高了显示精度。

Description

像素驱动电路、驱动方法及其显示面板 技术领域
本申请涉及显示技术领域，更具体地说，涉及一种像素驱动电路、驱动方法及其显示面板。
背景技术
随着显示设备的发展，对于显示设备的驱动电路成为了重要的研究热点。对于电流型驱动的显示设备，其发光亮度取决于流过Driving TFT(驱动型薄膜晶体管)的栅源电流。例如，采用传统驱动电路应用于Micro LED显示面板，LED的亮度-电流曲线斜率很大，微弱的电流变化就会引起人眼可察觉的亮度改变。因此Micro LED面板如果采用传统驱动电路，难以精确控制LED的驱动电流，显示精度低。
技术问题
在实现过程中，发明人发现传统技术中至少存在如下问题：采用传统驱动电路，难以精确控制显示面板中LED的驱动电流，显示精度低。
技术解决方案
基于此，有必要针对传统的采用传统驱动电路，难以精确控制显示面板中LED的驱动电流，显示精度低的问题，提供一种像素驱动电 路、驱动方法及其显示面板。
为了实现上述目的，本发明实施例提供了一种像素驱动电路，包括：
第一薄膜晶体管，第一薄膜晶体管的栅极连接第一节点，源极连接第二节点，漏极用于接入电源高电压；
第二薄膜晶体管，第二薄膜晶体管的栅极用于接入第N行像素的扫描信号，源极连接第一节点，漏极用于接入数据信号；
第一电容，第一电容的一端连接第一节点，另一端连接第三节点；
第三薄膜晶体管，第三薄膜晶体管的栅极用于接入第N+1行像素的扫描信号，源极连接第三节点，漏极连接第二节点；
第二电容，第二电容的一端连接第三节点，另一端连接第四节点；
第四薄膜晶体管，第四薄膜晶体管的栅极用于接入第N+2行像素的扫描信号，源极连接第四节点，漏极连接第二节点；
第三电容，第三电容的一端连接第四节点，另一端连接第二节点；
发光二极管，发光二极管的阳极连接第二节点，阴极用于接入电源低电压。
另一方面，本发明实施例还提供了一种应用于上述的像素驱动电路的像素驱动方法，包括以下步骤：
在第一阶段分别对第一电容、第二电容和第三电容充电；
在第二阶段保持第一电容的电压值不变，分别对第二电容和第三电容放电；
在第三阶段对第一电容、第二电容和第三电容之间进行电荷分配；
在第四阶段保持第一电容和第二电容的电压值不变，对第三电容放电；
在第五阶段对第一电容、第二电容和第三电容之间进行电荷分配；
在第六阶段控制发光二极管进行发光；
其中，一帧的显示周期被顺序地划分为第一阶段、第二阶段、第三阶段、第四阶段、第五阶段和第六阶段。
另一方面，本发明实施例还提供了一种显示面板，包括像素驱动电路；像素驱动电路包括：
第一薄膜晶体管，第一薄膜晶体管的栅极连接第一节点，源极连接第二节点，漏极用于接入电源高电压；
第二薄膜晶体管，第二薄膜晶体管的栅极用于接入第N行像素的扫描信号，源极连接第一节点，漏极用于接入数据信号；
第一电容，第一电容的一端连接第一节点，另一端连接第三节点；
第三薄膜晶体管，第三薄膜晶体管的栅极用于接入第N+1行像素的扫描信号，源极连接第三节点，漏极连接第二节点；
第二电容，第二电容的一端连接第三节点，另一端连接第四节点；
第四薄膜晶体管，第四薄膜晶体管的栅极用于接入第N+2行像素的扫描信号，源极连接第四节点，漏极连接第二节点；
第三电容，第三电容的一端连接第四节点，另一端连接第二节点；
发光二极管，发光二极管的阳极连接第二节点，阴极用于接入电源低电压。
有益效果
上述的像素驱动电路的各实施例中，基于第一薄膜晶体管的栅极连接第一节点，源极连接第二节点，漏极用于接入电源高电压；第二薄膜晶体管的栅极用于接入第N行像素的扫描信号，源极连接第一节点，漏极用于接入数据信号；第一电容的一端连接第一节点，另一端连接第三节点；第三薄膜晶体管的栅极用于接入第N+1行像素的扫描信号，源极连接第三节点，漏极连接第二节点；第二电容的一端连接第三节点，另一端连接第四节点；第四薄膜晶体管的栅极用于接入第N+2行像素的扫描信号，源极连接第三四节点，漏极连接第二节点；第三电容的一端连接第四节点，另一端连接第二节点；发光二极管的阳极连接第二节点，阴极用于接入电源低电压，进而能够实现采用较低输出电压分辨率的源极芯片进行精细的电流控制。本申请能够通过控制第二薄膜晶体管、第三薄膜晶体管和第四薄膜晶体管的通断，进行两级电容放电及各个电容(第一电容、第二电容和第三电容)之间电荷分配，实现精确控制显示面板中LED的驱动电流，进一步提高了显示精度。
附图说明
下面将结合附图及实施例对本申请作进一步说明，附图中：
图1为传统2T1C像素驱动电路的示意图；
图2为一个实施例中LED的亮度-电流曲线示意图；
图3为一个实施例中像素驱动电路的第一结构示意图；
图4为一个实施例中像素驱动电路第一阶段的等效电路示意图；
图5为一个实施例中像素驱动电路第二阶段的等效电路示意图；
图6为一个实施例中像素驱动电路第三阶段的等效电路示意图；
图7为一个实施例中像素驱动电路第四阶段的等效电路示意图；
图8为一个实施例中像素驱动电路第五阶段的等效电路示意图；
图9为一个实施例中像素驱动电路的第二结构示意图；
图10为一个实施例中像素驱动方法的流程示意图。
本发明的实施方式
为了对本申请的技术特征、目的和效果有更加清楚的理解，现对照附图详细说明本申请的具体实施方式。
传统的像素驱动电路如图1所示，其为一种常见的微发光二极管或者有机发光二极管的驱动像素电路示意图。此2T1C像素电路主要包括作为驱动薄膜晶体管(TFT)的薄膜晶体管T1，作为开关薄膜晶体管的薄膜晶体管T2，存储电容C以及发光二极管LED，发光二极管LED可以是微发光二极管或者有机发光二极管，薄膜晶体管T2由相应行像素的扫描信号SCAN控制开关与否，以控制是否输入相应的数据信号V data。采用此像素电路，在发光阶段，流过LED的电流I LED由薄膜晶体管T1控制，可以表示为I LED＝k(V data-V LED-V th) 2，其中，k为与工艺和设计相关的参数，V data为源极芯片(Source IC)输出的数据信号的电压，V LED为LED上的电压，V th为薄膜晶体管T1的阈值电压。
如图2所示，其为LED的亮度-电流曲线示意图，对于微发光二 极管显示面板来说，LED的亮度-电流曲线斜率很大，微弱的电流变化就会引起人眼可察觉的亮度改变。因此微发光二极管显示面板如果采用传统驱动电路，例如图1所示电路，必须非常精确控制LED的驱动电流，难度较大。因为源极芯片输出电压的分辨率有限，难以精确控制LED电流，使其产生足够多的灰阶。
而本申请提出的一种像素驱动电路，改进了原有的像素驱动电路，改进后的像素驱动电路在原有像素驱动电路基础上增加两个电容以及两个薄膜晶体管，增加的两个电容与原有的像素电路中的存储电容串联，增加的两个薄膜晶体管分别连接于相邻两个电容之间的公共点以及驱动薄膜晶体管(N型)的源极，能够实现采用较低输出电压分辨率的源极芯片进行精细的电流控制，极大的提高显示效率。
在一个实施例中，如图3所示，提供了一种像素驱动电路，包括：
第一薄膜晶体管310，第一薄膜晶体管310的栅极连接第一节点G，源极连接第二节点S，漏极用于接入电源高电压；
第二薄膜晶体管320，第二薄膜晶体管320的栅极用于接入第N行像素的扫描信号，源极连接第一节点G，漏极用于接入数据信号；
第一电容330，第一电容330的一端连接第一节点G，另一端连接第三节点A；
第三薄膜晶体管340，第三薄膜晶体管340的栅极用于接入第N+1行像素的扫描信号，源极连接第三节点A，漏极连接第二节点S；
第二电容350，第二电容350的一端连接第三节点A，另一端连接第四节点B；
第四薄膜晶体管360，第四薄膜晶体管360的栅极用于接入第N+2行像素的扫描信号，源极连接第四节点B，漏极连接第二节点S；
第三电容370，第三电容370的一端连接第四节点B，另一端连接第二节点S；
发光二极管380，发光二极管380的阳极连接第二节点S，阴极用于接入电源低电压。
其中，第一节点G指的是第一薄膜晶体管310、第二薄膜晶体管320和第一电容330之间的共用连接点。第二节点S指的是第一薄膜晶体管310、第三薄膜晶体管340、第四薄膜晶体管360、第三电容370和发光二极管380之间的共用连接点。第三节点A指的是第一电容330、第二电容350和第三薄膜晶体管340之间的共用连接点。第四节点B指的是第二电容350、第三电容370和第四薄膜晶体管360之间的共用连接点。
具体地，可通过第N行像素的扫描控制线向第二薄膜晶体管320的栅极提供第N行像素的扫描信号。可通过第N+1行像素的扫描控制线向第三薄膜晶体管340的栅极提供第N+1行像素的扫描信号。可通过第N+2行像素的扫描控制线向第四薄膜晶体管360的栅极提供第N+2行像素的扫描信号。可通过数据控制线向第二薄膜晶体管320的源极提供数据信号。
需要说明的是，N为大于或等于1的正整数。
上述的像素驱动电路的实施例中，基于第一薄膜晶体管310的栅极连接第一节点G，源极连接第二节点S，漏极用于接入电源高电压； 第二薄膜晶体管320的栅极用于接入第N行像素的扫描信号，源极连接第一节点G，漏极用于接入数据信号；第一电容330的一端连接第一节点G，另一端连接第三节点A；第三薄膜晶体管340的栅极用于接入第N+1行像素的扫描信号，源极连接第三节点A，漏极连接第二节点S；第二电容350的一端连接第三节点A，另一端连接第四节点B；第四薄膜晶体管360的栅极用于接入第N+2行像素的扫描信号，源极连接第四节点B，漏极连接第二节点S；第三电容370的一端连接第四节点B，另一端连接第二节点S；发光二极管380的阳极连接第二节点S，阴极用于接入电源低电压，进而能够实现采用较低输出电压分辨率的源极芯片进行精细的电流控制。通过控制第二薄膜晶体管320、第三薄膜晶体管340和第四薄膜晶体管360的通断，进行两级电容放电及各个电容(第一电容330、第二电容350和第三电容370)之间电荷分配，实现精确控制显示面板中LED的驱动电流，进一步提高了显示精度。
在一个具体的实施例中，像素驱动电路的驱动时序包括五个阶段：在第一阶段，第N行像素的扫描信号保持高电平，第N+1行像素的扫描信号和第N+2行像素的扫描信号分别保持低电平；在第二阶段，第N行像素的扫描信号保持低电平，第N+1行像素的扫描信号保持高电平，第N+2行像素的扫描信号保持低电平；在第三阶段，第N行像素的扫描信号保持低电平，第N+1行像素的扫描信号保持低电平，第N+2行像素的扫描信号保持低电平；在第四阶段，第N行像素的扫描信号保持低电平，第N+1行像素的扫描信号保持低电平，第N+2 行像素的扫描信号保持高电平；在第五阶段，第N行像素的扫描信号保持低电平，第N+1行像素的扫描信号保持低电平，第N+2行像素的扫描信号保持低电平。
具体而言，在第一阶段，当第N行像素的扫描信号SCANn打开，第一节点充入电压V data，流过第一薄膜晶体管T1的电流(即流过发光二极管的电流)是I LED＝k(V data-V LED-V th) 2，此时第三薄膜晶体管T3和第四薄膜晶体管T4都关断，可将串联的第二电容C2和第三电容C3等效为一个等效电容CA，此时等效电路如图4所示。其中，等效电路上两个电容的电压关系式为：
U 1/U A＝C A/C 1
U 1+U A＝V data-V S
根据上述关系式可以得到：
Figure PCTCN2020071816-appb-000001
其中，U 1为第一电容C1的电压，U A为等效电容CA的电压，C 1为第一电容C1的电容，C A为等效电容CA的电容。
在第二阶段，当扫描至第N+1行时，第N行像素的扫描信号SCANn关闭，第N+1行像素的扫描信号SCANn+1打开，第N+2行像素的扫描信号SCANn+2关闭，第三薄膜晶体管T3导通，等效电路图如图5所示。其中，等效电容CA放电，第一电容C1的电压维持U 1不变。
在第三阶段，第N行像素的扫描信号SCANn关闭，第N+1行像素的扫描信号SCANn+1关闭，第三薄膜晶体管T3关断，电荷再次在等效电容CA和第一电容C1之间平均分配，等效电路图如图6所示。 此时电路满足如下关系：
C 1+U 1＝Q 1
U' 1C 1+U' AC A＝Q 1
U' 1C 1＝U' AC A
根据上述关系式可以得到：
Figure PCTCN2020071816-appb-000002
代入
Figure PCTCN2020071816-appb-000003
可得到：
Figure PCTCN2020071816-appb-000004
在第四阶段，当扫描至第N+2行时，第N行像素的扫描信号SCANn关闭，第N+1行像素的扫描信号SCANn+1关闭，第N+2行像素的扫描信号SCANn+2打开，第四薄膜晶体管T4导通，等效电路图如图7所示。其中，将串联的第一电容C1和第二电容C2等效为一个等效电容CB。第三电容C3放电，等效电容CB的电容维持U B′不变。等效电路上两个电容的电压关系式为：
U B'/U 3'＝C 3/C B
Figure PCTCN2020071816-appb-000005
根据上述关系式可以得到：
Figure PCTCN2020071816-appb-000006
其中，U′ 3为第三电容C3的电压，U B′为等效电容CB的电压，C 3为第三电容C1的电容，C B为等效电容CB电容。
在第五阶段，第N行像素的扫描信号SCANn关闭，第N+1行像素的扫描信号SCANn+1关闭，第N行像素的扫描信号SCANn+2关闭， 第四薄膜晶体管T4关断，电荷再次在CB和C3之间平均分配，等效电路图如图8所示。此时电路满足如下关系：
C B+U B′＝Q B′
U' BC B+U' 3C 3＝Q B'
U′ BC B＝U′ 3C 3
根据上述关系式可以得到：
Figure PCTCN2020071816-appb-000007
代入
Figure PCTCN2020071816-appb-000008
可得到：
Figure PCTCN2020071816-appb-000009
进而可得到最终流过发光二极管的电流为：
Figure PCTCN2020071816-appb-000010
上述实施例中相较于传统驱动电路的LED电流，需要更大的V data才能产生相同的电流。因此可以使用较低分辨率的源极芯片(source IC)进行更精细的电流控制，实现精确控制显示面板中LED的驱动电流，进一步提高了显示精度。满足Micro LED等发光二极管的驱动需求，可以应用于OLED等各种显示面板。
在一个实施例中，如图9所示，提供了一种像素驱动电路，该像素驱动电路包括第二薄膜晶体管920，第一薄膜晶体管910，第一电容930，第三薄膜晶体管940，第二电容950，第四薄膜晶体管960，第三电容970以及发光二极管980。该像素驱动电路还包括第五薄膜晶体管990；第五薄膜晶体管990的栅极连接控制信号，源极连接第二节点s，漏极用于接入参考电压。
其中，可通过控制线(Pre-charge)向第五薄膜晶体管的栅极提供控制信号。
上述实施例的的像素驱动电路改进了传统的3T1C像素电路，能够实现采用较低输出电压分辨率的源极芯片进行精细的电流控制。通过控制第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管和第五薄膜晶体管的通断，进行两级电容放电及各个电容(第一电容、第二电容和第三电容)之间电荷分配，实现精确控制显示面板中LED的驱动电流，进一步提高了显示精度。
在一个具体的实施例中，像素驱动电路的驱动时序包括五个阶段：在第一阶段，控制信号保持高电平，第N行像素的扫描信号保持高电平，第N+1行像素的扫描信号和第N+2行像素的扫描信号分别保持低电平；在第二阶段，控制信号保持低电平，第N行像素的扫描信号保持低电平，第N+1行像素的扫描信号保持高电平，第N+2行像素的扫描信号保持低电平；在第三阶段，控制信号保持低电平，第N行像素的扫描信号保持低电平，第N+1行像素的扫描信号保持低电平，第N+2行像素的扫描信号保持低电平；在第四阶段，控制信号保持低电平，第N行像素的扫描信号保持低电平，第N+1行像素的扫描信号保持低电平，第N+2行像素的扫描信号保持高电平；在第五阶段，控制信号保持低电平，第N行像素的扫描信号保持低电平，第N+1行像素的扫描信号保持低电平，第N+2行像素的扫描信号保持低电平。
具体而言，在第五阶段，流过发光二极管的电流为：
Figure PCTCN2020071816-appb-000011
其中，V ref为接入第五薄膜晶体管的源极的参考电压。
上述实施例中相较于传统驱动电路的LED电流，需要更大的V data才能产生相同的电流。因此可以使用较低分辨率的源极芯片(source IC)进行更精细的电流控制，实现精确控制显示面板中LED的驱动电流，进一步提高了显示精度。
在一个实施例中，发光二极管为OLED(有机发光二极管)，Micro LED(微型发光二极管)，Mini LED(迷你型发光二极管)或μLED(微型发光二极管)。
在一个实施例中，如图10所示，提供了一种像素驱动方法，包括以下步骤：
步骤S110，在第一阶段分别对第一电容、第二电容和第三电容充电。
步骤S120，在第二阶段保持第一电容的电压值不变，分别对第二电容和第三电容放电。
步骤S130，在第三阶段对第一电容、第二电容和第三电容之间进行电荷分配。
步骤S140，在第四阶段保持第一电容和第二电容的电压值不变，对第三电容放电。
步骤S150，在第五阶段对第一电容、第二电容和第三电容之间进行电荷分配。
步骤S160，在第六阶段控制发光二极管进行发光。
其中，一帧的显示周期被顺序地划分为第一阶段、第二阶段、第 三阶段、第四阶段、第五阶段和第六阶段。
在一个具体的实施例中，在第一阶段分别对第一电容、第二电容和第三电容充电的步骤包括：
在第一阶段，控制第N行像素的扫描信号保持高电平，第N+1行像素的扫描信号和第N+2行像素的扫描信号分别保持低电平；
在第二阶段保持第一电容的电压值不变，分别对第二电容和第三电容放电的步骤包括：
在第二阶段，控制第N行像素的扫描信号保持低电平，第N+1行像素的扫描信号保持高电平，第N+2行像素的扫描信号保持低电平；
在第三阶段对第一电容、第二电容和第三电容之间进行电荷分配的步骤包括：
在第三阶段，控制第N行像素的扫描信号保持低电平，第N+1行像素的扫描信号保持低电平，第N+2行像素的扫描信号保持低电平；
在第四阶段保持第一电容和第二电容的电压值不变，对第三电容放电的步骤包括：
在第四阶段，控制第N行像素的扫描信号保持低电平，第N+1行像素的扫描信号保持低电平，第N+2行像素的扫描信号保持高电平；
在第五阶段对第一电容、第二电容和第三电容之间进行电荷分配的步骤包括：
在第六阶段，控制第N行像素的扫描信号保持低电平，第N+1行像素的扫描信号保持低电平，第N+2行像素的扫描信号保持低电平。
上述实施例中，通过控制第二薄膜晶体管、第三薄膜晶体管和第 四薄膜晶体管的通断，进行两级电容放电及各个电容(第一电容、第二电容和第三电容)之间电荷分配，实现精确控制显示面板中LED的驱动电流，进一步提高了显示精度。
应该理解的是，虽然图10的流程图中的各个步骤按照箭头的指示依次显示，但是这些步骤并不是必然按照箭头指示的顺序依次执行。除非本文中有明确的说明，这些步骤的执行并没有严格的顺序限制，这些步骤可以以其它的顺序执行。而且，图10中的至少一部分步骤可以包括多个子步骤或者多个阶段，这些子步骤或者阶段并不必然是在同一时刻执行完成，而是可以在不同的时刻执行，这些子步骤或者阶段的执行顺序也不必然是依次进行，而是可以与其它步骤或者其它步骤的子步骤或者阶段的至少一部分轮流或者交替地执行。
另一方面，还提供了一种显示面板，该显示面板包括如上述任一项的像素驱动电路。
关于显示面板的具体限定可以参见上文中对于像素驱动电路的限定，在此不再赘述。
需要说明的是，本申请特别适用于微型发光二极管显示面板，但不限于此，可以应用于各种电流驱动显示面板，如有机发光二极管显示面板，迷你发光二极管(Mini LED)显示面板，可提升驱动电流控制精度。
在一个实施例中，还提供了一种显示装置，该显示装置包括如上述的显示面板。
在一个实施例中，显示面板为OLED显示面板，Micro LED显示面 板，Mini LED显示面板或μLED显示面板。
关于显示装置的具体限定可以参见上文中对于像素驱动电路及显示面板的限定，在此不再赘述。
本领域普通技术人员可以理解实现上述实施例方法中的全部或部分流程，是可以通过计算机程序来指令相关的硬件来完成，所述的计算机程序可存储于一非易失性计算机可读取存储介质中，该计算机程序在执行时，可包括如上述各除法运算方法的实施例的流程。其中，本申请所提供的各实施例中所使用的对存储器、存储、数据库或其它介质的任何引用，均可包括非易失性和/或易失性存储器。非易失性存储器可包括只读存储器(ROM)、可编程ROM(PROM)、电可编程ROM(EPROM)、电可擦除可编程ROM(EEPROM)或闪存。易失性存储器可包括随机存取存储器(RAM)或者外部高速缓冲存储器。作为说明而非局限，RAM以多种形式可得，诸如静态RAM(SRAM)、动态RAM(DRAM)、同步DRAM(SDRAM)、双数据率SDRAM(DDRSDRAM)、增强型SDRAM(ESDRAM)、同步链路(Synchlink)DRAM(SLDRAM)、存储器总线(Rambus)直接RAM(RDRAM)、直接存储器总线动态RAM(DRDRAM)、以及存储器总线动态RAM(RDRAM)等。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (12)

  1. 一种像素驱动电路，其中，包括：
    第一薄膜晶体管，所述第一薄膜晶体管的栅极连接第一节点，源极连接第二节点，漏极用于接入电源高电压；
    第二薄膜晶体管，所述第二薄膜晶体管的栅极用于接入第N行像素的扫描信号，源极连接所述第一节点，漏极用于接入数据信号；
    第一电容，所述第一电容的一端连接所述第一节点，另一端连接第三节点；
    第三薄膜晶体管，所述第三薄膜晶体管的栅极用于接入第N+1行像素的扫描信号，源极连接所述第三节点，漏极连接所述第二节点；
    第二电容，所述第二电容的一端连接所述第三节点，另一端连接第四节点；
    第四薄膜晶体管，所述第四薄膜晶体管的栅极用于接入第N+2行像素的扫描信号，源极连接所述第四节点，漏极连接所述第二节点；
    第三电容，所述第三电容的一端连接所述第四节点，另一端连接第二节点；
    发光二极管，所述发光二极管的阳极连接所述第二节点，阴极用于接入电源低电压。
  2. 根据权利要求1所述的像素驱动电路，其中，所述像素驱动电路的驱动时序包括五个阶段：在第一阶段，所述第N行像素的扫描信号保持高电平，所述第N+1行像素的扫描信号和所述第N+2行像素的扫描信号分别保持低电平；在第二阶段，所述第N行像素的扫描 信号保持低电平，所述第N+1行像素的扫描信号保持高电平，所述第N+2行像素的扫描信号保持低电平；在第三阶段，所述第N行像素的扫描信号保持低电平，所述第N+1行像素的扫描信号保持低电平，所述第N+2行像素的扫描信号保持低电平；在第四阶段，所述第N行像素的扫描信号保持低电平，所述第N+1行像素的扫描信号保持低电平，所述第N+2行像素的扫描信号保持高电平；在第五阶段，所述第N行像素的扫描信号保持低电平，所述第N+1行像素的扫描信号保持低电平，所述第N+2行像素的扫描信号保持低电平。
  3. 根据权利要求1所述的像素驱动电路，其中，还包括第五薄膜晶体管；
    所述第五薄膜晶体管的栅极连接控制信号，源极连接所述第二节点，漏极用于接入参考电压。
  4. 根据权利要求3所述的像素驱动电路，其中，所述像素驱动电路的驱动时序包括五个阶段：在第一阶段，所述控制信号保持高电平，所述第N行像素的扫描信号保持高电平，所述第N+1行像素的扫描信号和所述第N+2行像素的扫描信号分别保持低电平；在第二阶段，所述控制信号保持低电平，所述第N行像素的扫描信号保持低电平，所述第N+1行像素的扫描信号保持高电平，所述第N+2行像素的扫描信号保持低电平；在第三阶段，所述控制信号保持低电平，所述第N行像素的扫描信号保持低电平，所述第N+1行像素的扫描信号保持低电平，所述第N+2行像素的扫描信号保持低电平；在第四阶段，所述控制信号保持低电平，所述第N行像素的扫描信号保持低电 平，所述第N+1行像素的扫描信号保持低电平，所述第N+2行像素的扫描信号保持高电平；在第五阶段，所述控制信号保持低电平，所述第N行像素的扫描信号保持低电平，所述第N+1行像素的扫描信号保持低电平，所述第N+2行像素的扫描信号保持低电平。
  5. 根据权利要求1所述的像素驱动电路，其中，所述发光二极管为OLED，Micro LED，Mini LED或μLED。
  6. 一种应用于根据权利要求1所述的像素驱动电路的像素驱动方法，其中，包括以下步骤：
    在第一阶段分别对第一电容、第二电容和第三电容充电；
    在第二阶段保持所述第一电容的电压值不变，分别对所述第二电容和所述第三电容放电；
    在第三阶段对所述第一电容、所述第二电容和所述第三电容之间进行电荷分配；
    在第四阶段保持所述第一电容和所述第二电容的电压值不变，对所述第三电容放电；
    在第五阶段对所述第一电容、所述第二电容和所述第三电容之间进行电荷分配；
    在第六阶段控制发光二极管进行发光；
    其中，一帧的显示周期被顺序地划分为所述第一阶段、所述第二阶段、所述第三阶段、所述第四阶段、所述第五阶段和所述第六阶段。
  7. 根据权利要求6所述的像素驱动方法，其中，所述在第一阶段分别对第一电容、第二电容和第三电容充电的步骤包括：
    在第一阶段，控制所述第N行像素的扫描信号保持高电平，所述第N+1行像素的扫描信号和所述第N+2行像素的扫描信号分别保持低电平；
    所述在第二阶段保持所述第一电容的电压值不变，分别对所述第二电容和所述第三电容放电的步骤包括：
    在第二阶段，控制所述第N行像素的扫描信号保持低电平，所述第N+1行像素的扫描信号保持高电平，所述第N+2行像素的扫描信号保持低电平；
    所述在第三阶段对所述第一电容、所述第二电容和所述第三电容之间进行电荷分配的步骤包括：
    在第三阶段，控制所述第N行像素的扫描信号保持低电平，所述第N+1行像素的扫描信号保持低电平，所述第N+2行像素的扫描信号保持低电平；
    所述在第四阶段保持所述第一电容和所述第二电容的电压值不变，对所述第三电容放电的步骤包括：
    在第四阶段，控制所述第N行像素的扫描信号保持低电平，所述第N+1行像素的扫描信号保持低电平，所述第N+2行像素的扫描信号保持高电平；
    所述在第五阶段对所述第一电容、所述第二电容和所述第三电容之间进行电荷分配的步骤包括：
    在第五阶段，控制所述第N行像素的扫描信号保持低电平，所述第N+1行像素的扫描信号保持低电平，所述第N+2行像素的扫描信 号保持低电平。
  8. 一种显示面板，其中，包括像素驱动电路；所述像素驱动电路包括：
    第一薄膜晶体管，所述第一薄膜晶体管的栅极连接第一节点，源极连接第二节点，漏极用于接入电源高电压；
    第二薄膜晶体管，所述第二薄膜晶体管的栅极用于接入第N行像素的扫描信号，源极连接所述第一节点，漏极用于接入数据信号；
    第一电容，所述第一电容的一端连接所述第一节点，另一端连接第三节点；
    第三薄膜晶体管，所述第三薄膜晶体管的栅极用于接入第N+1行像素的扫描信号，源极连接所述第三节点，漏极连接所述第二节点；
    第二电容，所述第二电容的一端连接所述第三节点，另一端连接第四节点；
    第四薄膜晶体管，所述第四薄膜晶体管的栅极用于接入第N+2行像素的扫描信号，源极连接所述第四节点，漏极连接所述第二节点；
    第三电容，所述第三电容的一端连接所述第四节点，另一端连接第二节点；
    发光二极管，所述发光二极管的阳极连接所述第二节点，阴极用于接入电源低电压。
  9. 根据权利要求8所述的显示面板，其中，所述像素驱动电路的驱动时序包括五个阶段：在第一阶段，所述第N行像素的扫描信号保持高电平，所述第N+1行像素的扫描信号和所述第N+2行像素的 扫描信号分别保持低电平；在第二阶段，所述第N行像素的扫描信号保持低电平，所述第N+1行像素的扫描信号保持高电平，所述第N+2行像素的扫描信号保持低电平；在第三阶段，所述第N行像素的扫描信号保持低电平，所述第N+1行像素的扫描信号保持低电平，所述第N+2行像素的扫描信号保持低电平；在第四阶段，所述第N行像素的扫描信号保持低电平，所述第N+1行像素的扫描信号保持低电平，所述第N+2行像素的扫描信号保持高电平；在第五阶段，所述第N行像素的扫描信号保持低电平，所述第N+1行像素的扫描信号保持低电平，所述第N+2行像素的扫描信号保持低电平。
  10. 根据权利要求8所述的显示面板，其中，所述像素驱动电路还包括第五薄膜晶体管；
    所述第五薄膜晶体管的栅极连接控制信号，源极连接所述第二节点，漏极用于接入参考电压。
  11. 根据权利要求10所述的显示面板，其中，所述像素驱动电路的驱动时序包括五个阶段：在第一阶段，所述控制信号保持高电平，所述第N行像素的扫描信号保持高电平，所述第N+1行像素的扫描信号和所述第N+2行像素的扫描信号分别保持低电平；在第二阶段，所述控制信号保持低电平，所述第N行像素的扫描信号保持低电平，所述第N+1行像素的扫描信号保持高电平，所述第N+2行像素的扫描信号保持低电平；在第三阶段，所述控制信号保持低电平，所述第N行像素的扫描信号保持低电平，所述第N+1行像素的扫描信号保持低电平，所述第N+2行像素的扫描信号保持低电平；在第四阶段，所 述控制信号保持低电平，所述第N行像素的扫描信号保持低电平，所述第N+1行像素的扫描信号保持低电平，所述第N+2行像素的扫描信号保持高电平；在第五阶段，所述控制信号保持低电平，所述第N行像素的扫描信号保持低电平，所述第N+1行像素的扫描信号保持低电平，所述第N+2行像素的扫描信号保持低电平。
  12. 根据权利要求8所述的显示面板，其中，所述发光二极管为OLED，Micro LED，Mini LED或μLED。
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