WO2021129877A1 - 译码方法、装置、网络设备及存储介质 - Google Patents

译码方法、装置、网络设备及存储介质 Download PDF

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WO2021129877A1
WO2021129877A1 PCT/CN2020/140278 CN2020140278W WO2021129877A1 WO 2021129877 A1 WO2021129877 A1 WO 2021129877A1 CN 2020140278 W CN2020140278 W CN 2020140278W WO 2021129877 A1 WO2021129877 A1 WO 2021129877A1
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data
unit
data unit
soft
bits
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PCT/CN2020/140278
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English (en)
French (fr)
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戴笠
郭震巍
邓波
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深圳市中兴微电子技术有限公司
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Priority to EP20907202.4A priority Critical patent/EP4084338A4/en
Priority to KR1020227025481A priority patent/KR20220119468A/ko
Priority to JP2022539294A priority patent/JP2023508449A/ja
Priority to US17/789,265 priority patent/US11843396B2/en
Publication of WO2021129877A1 publication Critical patent/WO2021129877A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105—Decoding
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/63—Joint error correction and other techniques
    • H03M13/635—Error control coding in combination with rate matching
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2703—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques the interleaver involving at least two directions
    • H03M13/2707—Simple row-column interleaver, i.e. pure block interleaving
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2778—Interleaver using block-wise interleaving, e.g. the interleaving matrix is sub-divided into sub-matrices and the permutation is performed in blocks of sub-matrices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/3769—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35 using symbol combining, e.g. Chase combining of symbols received twice or more
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/63—Joint error correction and other techniques
    • H03M13/6306—Error control coding in combination with Automatic Repeat reQuest [ARQ] and diversity transmission, e.g. coding schemes for the multiple transmission of the same information or the transmission of incremental redundancy
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/63—Joint error correction and other techniques
    • H03M13/635—Error control coding in combination with rate matching
    • H03M13/6362—Error control coding in combination with rate matching by puncturing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H04L1/0047—Decoding adapted to other signal detection operation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0067—Rate matching
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0067—Rate matching
    • H04L1/0068—Rate matching by puncturing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0071—Use of interleaving
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/12—Arrangements for detecting or preventing errors in the information received by using return channel
    • H04L1/16—Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals
    • H04L1/18—Automatic repetition systems, e.g. Van Duuren systems
    • H04L1/1812—Hybrid protocols; Hybrid automatic repeat request [HARQ]
    • H04L1/1819—Hybrid protocols; Hybrid automatic repeat request [HARQ] with retransmission of additional or different redundancy
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/276—Interleaving address generation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/45—Soft decoding, i.e. using symbol reliability information
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/12—Arrangements for detecting or preventing errors in the information received by using return channel
    • H04L1/16—Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals
    • H04L1/18—Automatic repetition systems, e.g. Van Duuren systems
    • H04L1/1829—Arrangements specially adapted for the receiver end
    • H04L1/1835—Buffer management

Definitions

  • This application relates to the field of communications, in particular to a decoding method, device, network equipment and storage medium.
  • the function of rate matching is to adjust the code rate output by the channel encoder so that the number of bits output by the rate matching module matches the number of bits that can be carried by the physical resources allocated by the system.
  • the rate matching process is generally accompanied by interleaving. Interleaving is used to scramble the coded data to discretize the error and reduce the difficulty of error correction processing when a signal error occurs, thereby protecting the coded data and improving the stability of the coding performance.
  • the 3GPP NR protocol uses Low Density Parity Check Code (LDPC) for uplink and downlink traffic channels. After encoding, rate matching is performed first, and then interleaving. These processes are all based on code block (Code Block, LDPC). CB) is a unit, the rate matching uses a rate matching mechanism based on a circular buffer, and the interleaving uses the commonly used packet interleaving of R rows and C columns. De-interleaving and de-rate matching are the inverse processes of rate matching and interleaving.
  • LDPC Low Density Parity Check Code
  • Zc soft bits are usually read in one cycle for processing, that is, the de-rate matching or the decoder needs to combine Zc soft bits together, which indirectly requires the de-rate matching process to have x/Z Addressing operations such as c or x%Z c , where x is the position of the soft bit in the decoder, and Z c is the lifting factor used in LDPC encoding, corresponding to 8 values, all of which are prime numbers, leading to this
  • the addressing operation is complicated to implement.
  • This application provides methods, devices, network equipment and storage media for decoding.
  • An embodiment of the present application provides a decoding method, including:
  • Decoding is performed according to the soft bit encoding position, the first data unit and the second data unit to obtain decoded data.
  • An embodiment of the present application provides a decoding device, including:
  • the data receiving module before deinterleaving is set to receive the data before deinterleaving and the soft bit coding position
  • a first data unit generating module configured to divide the data before deinterleaving to obtain a first data unit
  • the second data unit generating module is configured to obtain punctured data and obtain a second data unit according to the punctured data.
  • the pre-deinterleaved data and the punctured data are based on the soft bit encoding position Determined in the coded data;
  • the decoding data determining module is configured to perform decoding according to the soft bit encoding position, the first data unit and the second data unit to obtain decoded data.
  • An embodiment of the present application provides a network device, including: at least one processor and a memory; the processor is configured to execute a program stored in the memory to implement any one of the methods in the embodiments of the present application.
  • the embodiment of the present application provides a storage medium storing a computer program, and when the computer program is executed by a processor, any one of the methods in the embodiments of the present application is implemented.
  • FIG. 1 is a flowchart of the interaction between the sending end and the receiving end in an embodiment of the application
  • Figure 2 is a flowchart of a decoding method in an embodiment of the application
  • FIG. 3 is a schematic diagram of an encoded data structure in an embodiment of the application.
  • Figure 4 is a schematic diagram of an application scenario to which an embodiment of the application is applicable
  • FIG. 5 is a schematic diagram of a soft bit storage format in an embodiment of the application.
  • Fig. 6 is a sequence diagram of unit processing in an embodiment of the application.
  • FIG. 7 is a schematic diagram of data after rate matching in an embodiment of the application.
  • FIG. 8 is a schematic diagram of an interleaving matrix in an embodiment of this application.
  • FIG. 9 is a schematic diagram of another interleaving matrix in an embodiment of the application.
  • FIG. 10 is a schematic diagram of a decoding device in an embodiment of the application.
  • the sending end generates a Cyclic Redundancy Check (CRC) according to the transmission block to be sent, divides the transmission block into CBs as transmission units, and calculates the CRC of each CB.
  • CRC Cyclic Redundancy Check
  • LDPC Low Density Parity Check
  • the receiving end respectively performs fast Fourier transform, channel estimation and demodulation, descrambling and decoding block cascade according to the received data, and then deinterleaves the data corresponding to each code block, and performs deinterleaving on the obtained data before deinterleaving.
  • the data is subjected to de-rate matching and soft merging to obtain the to-be-decoded data, and then the to-be-decoded data is LDPC decoded to obtain the decoded data, where the decoded data and the encoded data are the same.
  • the obtained code block is subjected to CRC verification, and the multiple code blocks that have passed the CRC verification are divided into decoding blocks to obtain transmission blocks.
  • CRC verification is performed on the transmission block, and the transmission block that will pass the verification is the data actually sent by the sending end, and the receiving end can perform subsequent processing on the data.
  • BG1 base graph 1
  • BG2 base graph 2
  • the LDPC lifting factor Zc used in the CB encoding can be uniquely determined according to K′ and the base picture.
  • Zc is determined by the sum of the number of information bits and CRC check bits contained in a code block, and the LDPC base picture (value 1 or 2).
  • the system bits are:
  • the remaining bits are check bits generated according to the LDPC check matrix.
  • N cb N
  • N cb is the actual size of the circular buffer in the rate matching based on the limited buffer
  • k 0 is the start position of the rate matching of different redundancy versions, and the size corresponding to k 0 (that is, how many soft bits are included between the K′-2Z c soft bits) is an integer multiple of Zc.
  • the number of bits output after the code block rate is matched that is, the actual number of bits sent by the transmitter, and the value needs to be an integer multiple of Q m.
  • Q m is the modulation order
  • E is the number of bits output after rate matching, which can be evenly divisible by Q m.
  • the code block cascade, scrambling, modulation, layer mapping, inverse fast Fourier transform and other processing are performed, and the processing is sent through the antenna.
  • the soft bits in the Q m row of 1 column are all modulated to the same constellation point.
  • Figure 2 is a flow chart of the decoding method provided by an embodiment of the application. This embodiment is applicable to the case of deinterleaving and de-rate matching the communication data at the receiving end of the communication data.
  • the method can be translated from the embodiment of the application.
  • the code device is executed, which can be implemented in software and/or hardware, and can generally be integrated into network equipment. As shown in Figure 2, it specifically includes:
  • the data before deinterleaving can be soft bits.
  • the data before deinterleaving is actually the bit data that the transmitter writes into the interleaving matrix in rows and reads out in columns.
  • One bit at the transmitter corresponds to a soft bit at the receiver.
  • the data before deinterleaving should be the same as the interleaved data obtained by the sender interleaving the CB, but because of the air interface transmission, the data received by the receiver may not be correct, that is, the data before deinterleaving may not be the same as the interleaved data.
  • the soft bit coding position includes at least the position of each soft bit in the coded data (that is, the decoded data) in the data before deinterleaving.
  • the soft bit coding position can be determined according to the received interleaving matrix, or it can be directly sent from the sending end to the receiving end.
  • the coded data is the data after the sending end is coded and before the rate matching and interleaving.
  • de-rate matching and soft combining of the received data before de-interleaving are performed to obtain the data to be decoded, and the process of decoding the data to be decoded.
  • the data to be decoded is used to decode the decoded data, and the encoded data is the same as the data to be decoded. In fact, before decoding, it needs to be restored to encoded data that has not undergone any processing, so as to achieve accurate decoding.
  • the soft bit refers to the bit that the receiver does not make a decision after receiving the signal, but directly outputs the analog quantity for quantization.
  • the first data unit includes at least two soft bits, and is used to combine the soft bits as a processing unit for de-rate matching and soft combining.
  • Dividing the data before deinterleaving is actually grouping all soft bits included in the data before deinterleaving.
  • the sequence of S120 can be adjusted with S130, and can be performed after S130 or simultaneously with S130, which is not specifically limited in the embodiment of the present application.
  • rate matching means that the transmitting end will repeat bits or puncture bits to match the carrying capacity of the physical channel.
  • Punching is to remove the bits that cannot be carried by the physical channel as redundant data, and at the same time, move the following soft bits forward one bit in turn; repetition is to achieve the effect of repetition by cyclically fetching the numbers in the buffer, and the repeated bits are not Not adjacent.
  • the reverse of rate matching is to recover the knocked-out bits and merge the repeated bits. Among them, both punching and repetition are optional.
  • the rate matching in the embodiment of the present application is a rate matching mechanism based on a circular buffer.
  • the punctured data is the soft bits that are knocked out during the rate matching process.
  • the punctured data is used to combine with the data before deinterleaving to generate the same data to be decoded as the encoded data.
  • the second data unit includes at least two soft bits, which are used to combine the soft bits as a processing unit that is discarded in the encoded data, and are used to combine with the first data unit to form data to be decoded.
  • the coded data can be considered as a soft bit sequence, and the data before deinterleaving is obtained through rate matching, where the data deleted from the coded data belongs to the punctured data.
  • the coded data includes systematic bits, padding bits (3) and parity bits.
  • the first 2Zc bits included in the system bits are fixed as punctured data.
  • the systematic bits may also include other punctured data
  • the check bits may also contain other punctured data.
  • the other punctured data included in the system bit, the punctured data included in the check bit, and the padding bit may or may not exist.
  • the first 2Zc bits are fixed as punctured data, but the recovery operation of the punctured data does not belong to the de-rate matching. The restoring operation of the punctured data belongs to the solution rate matching.
  • the soft bit coding position includes the position of each soft bit in the coded data in the data before deinterleaving and the position of each soft bit in the coded data in the punctured data.
  • the coded data completes the rate matching process, and then performs operations such as interleaving. Therefore, the encoded data can be targeted to the soft bit encoding position, and the punctured data can be determined according to the position of the soft bit located in the punctured data in the encoded data.
  • the data before deinterleaving may include various forms of data, for example, data obtained by repetitive soft bits; data obtained by retransmitted soft bits; data obtained by non-repetitive soft bits.
  • the repeated, retransmitted and non-repetitive soft bits are located in the data before deinterleaving. Therefore, the positions of the repeated, retransmitted and non-repetitive soft bits in the coded data can be used to determine the data before deinterleaving. The position of the soft bit in the encoded data.
  • the repeated soft bits actually appear repeatedly, that is, there are multiple soft bits in the data before deinterleaving that have the same position in the coded data.
  • the unit lengths of the first data unit and the second data unit are both target lengths, the target length is determined according to a lifting factor, and the target length satisfies the lifting factor correlation Divide conditions.
  • the target length is used to determine the maximum number of soft bits included in the first data unit and the second data unit.
  • the boosting factor may refer to the boosting factor used for encoding in the sending end, which represents the multiple of the expansion of the number of bits.
  • the length of the configuration unit is the target length, and is determined according to the lifting factor, the length of the unit can be reasonably configured, and the length of each unit is the same, which facilitates the addressing of the soft bits in the unit.
  • the receiving end processes a CB, and when the CB is decoded correctly, the process of de-interleaving and de-rate matching of the CB is ended.
  • the historical combined data stored in the CB in the HARQ is usually cleared.
  • the associated data of the code block can be deleted when the data associated code block is processed, or the code block identifier can be added to the associated data of the code block to distinguish the associated data of the code block from the next code block. data.
  • the code block identifier is used to mark the effective interval of each code block.
  • the receiving end After the receiving end receives all the transmitted data, it is stored in the HARQ in a circular buffer format, and stored in the LDPC decoder in the original order after encoding. Since the decoding is for 1 Zc data each time, an address needs to store Zc soft bits. When the last address is stored, the total number of received soft bits belonging to the last address is less than Zc, and 0 can be filled to make the number of soft bits of the last address equal to Zc.
  • the target length needs to meet the divisible condition associated with the lifting factor, indicating that the lifting factor can be divisible by the target length, so that the data of one data unit does not belong to different Zc, thereby ensuring that one data
  • the data of the unit does not span 2 Zc, which can be matched with the storage format in the LDPC decoder.
  • the data of n data units is exactly equal to the Zc soft bits that can be stored in an address, which is guaranteed not to exceed one address, thereby reducing processing Complexity.
  • the target length is the ratio of the lifting factor to the power of a set value of 2
  • the first number is less than or equal to a set number threshold
  • the set number threshold is based on the operating frequency and Available resources are determined.
  • the CB uses LDPC encoding
  • the lifting factor is the lifting factor of the LDPC encoding.
  • Zc is determined by the sum of the number of information bits and CRC check bits contained in a code block, and the LDPC base picture (value 1 or 2).
  • the length of the configuration unit is the target length, and is determined according to the lifting factor, the length of the unit can be reasonably configured, and the length of each unit is the same, which facilitates the addressing of the soft bits in the unit.
  • the target length is the ratio of the lifting factor to the power of a set value of 2
  • the first number is less than or equal to a set number threshold
  • the set number threshold is based on the operating frequency and Available resources are determined.
  • the target length is Zs.
  • the set threshold is A, Zs ⁇ A, A is determined according to the working frequency and available resources, and the set value is m. Specifically, Zs is determined according to the following process:
  • the length of the unit can be reasonably configured to avoid too many or too few soft bits to be processed at one time, thereby improving the rate matching efficiency of the soft bits.
  • S140 Perform decoding according to the soft bit encoding position, the first data unit and the second data unit to obtain decoded data.
  • the soft bit coding position, the first data unit and the second data unit are used to determine the data to be decoded.
  • the first data unit and the second data unit may be combined to form data to be decoded, and the data to be decoded is decoded to obtain decoded data.
  • the combination method requires knowledge of the positional relationship between the first data unit and the second data unit, and the soft bit in the first data unit and the second data unit can be determined according to the soft bit coding position in the coded data (that is, to be translated). Therefore, the first data unit and the second data unit can be arranged according to the position relationship to obtain the data to be decoded.
  • the decoding according to the soft bit encoding position, the first data unit, and the second data unit includes: according to the soft bit encoding position and each of the The first soft bit in the first data unit determines the unit coding position of each of the first data units; according to the soft bit coding position and the first soft bit in each second data unit, each of the second soft bits is determined
  • the unit coding position of the data unit; according to each unit coding position, the first data unit and the second data unit are respectively stored at the matching storage address in the decoder to arrange the first data unit and The second data unit forms data to be decoded, so that the decoder decodes the data to be decoded.
  • the first data unit and the second data unit can be considered as soft bit sequences.
  • the position of the first soft bit in the coded data in the soft bit sequence can be used as the position of the soft bit sequence in the coded data, that is, the unit coding position of the unit.
  • the position of each unit except the first soft bit can be determined according to the order between the soft bits, that is, the relative position, and the unit encoding position.
  • the first soft bit is written in the storage address corresponding to the unit encoding position, and the next soft bit is written in the address offset by 1 bit from the storage address, and then sequentially After the subsequent offset address, the subsequent soft bits are written, and so on, the soft bits in the unit are written into the decoder one by one in order.
  • the matching storage address in the decoder corresponds to the unit encoding position.
  • the unit coding positions of each first data unit and each second data unit are respectively stored in matching positions, so as to realize the arrangement of each first data unit and each second data unit according to the unit coding position while storing, thereby realizing splicing Combine to form data to be decoded.
  • each first data unit and each second data unit By determining the unit coding position of each first data unit and each second data unit according to the soft bit coding position, and correspondingly storing each first data unit and each second data unit in a storage address matching the unit coding position, the first data unit and each second data unit are arranged and combined in the decoder to ensure accurate solution rate matching, so as to accurately splice and form the data to be decoded.
  • the decoding method, device, network equipment, and storage medium provided by the embodiments of the present application form multiple first data units by dividing the soft bits in the data before deinterleaving, and obtain the punctured data at the same time, and perform soft Bit division, generate multiple second data units, and form and decode data to be decoded according to the soft bit encoding position, the first data unit and the second data unit, so as to realize the processing of multiple soft bit forming units and solve
  • the de-rate matching process needs to be processed one by one soft bit, which leads to the low efficiency of de-rate matching, which can reduce the situation of individual addressing of each soft bit in the de-rate matching and decoding process, and can increase the solution rate. Matching and decoding efficiency.
  • the receiving the data before deinterleaving and dividing the data before deinterleaving to obtain the first data unit includes: multiple parallel receiving soft bits output by the deinterleaving matrix in columns; Each channel of received soft bits is stored to generate a plurality of third data units; according to a set number of clock cycles, each of the third data units is sequentially soft-combined to form a plurality of first data units.
  • the data before deinterleaving is obtained from the deinterleaving matrix.
  • the de-interleaving matrix is output in columns. There are Qm rows in the interleaving matrix, and Qm soft bits are output in each column.
  • Multiple channels receive the soft bits outputted in columns before de-interleaving, and each channel can receive at most one soft bit within a set number of clock cycles.
  • Each channel stores the received soft bits according to the receiving order, that is, the soft bits stored in one channel are soft bits in a row in the deinterleaving matrix.
  • Qm serial-parallel conversion modules can be configured, and each serial-parallel conversion module works in parallel, and each serial-parallel conversion module processes a row of the deinterleaving matrix to realize multiple parallel reception of soft bits and sequential storage, thereby independently completing the third data unit
  • the soft bits are collected to form a third data unit.
  • determine the position of the first soft bit received in the third data unit in the encoded data and use this position as the unit encoding position of the third data unit, and send the formed third data unit to the next A processing module performs subsequent processing.
  • Qm serial-to-parallel conversion modules can generate third data units that are integer multiples of Qm.
  • a serial processing method is adopted to process each third data unit in turn.
  • soft combining refers to combining based on Hybrid Automatic Repeat request (HARQ).
  • HARQ Hybrid Automatic Repeat request
  • the sender needs to wait for the receiver to feedback and accept the correct message. If there is no feedback, the sender will retransmit the data packet or part of the data packet to ensure that the receiver can receive the correct data packet.
  • the receiving end may merge the matched buffered data in the HARQ memory, and the merged unit is used as the first data unit, and at the same time, the first data unit is a valid data unit that is correctly transmitted.
  • the method for determining the sequence of the serial processing may be: according to a set rule (such as polling), a third data unit formed by one channel is selected as the processing unit in order for processing.
  • a set rule such as polling
  • the clock cycle of the set number of cycles is used as the processing frequency of the third data unit, that is, as the selection frequency of the third data unit formed by selecting one channel from the multiple channels.
  • the clock cycle of the set number of cycles can be set as required. Generally, one clock cycle is not long enough to complete a processing task of a third data unit, and multiple clock cycles can be selected as one processing cycle to complete a processing task of a third data unit.
  • the soft bits are converted into units, and at the same time, by serially processing each third data unit, the processing in the form of units is realized and the soft bits are improved.
  • the processing efficiency By receiving the soft bits output from the de-interleaving matrix in parallel, and sequentially storing the soft bits to form a third data unit, the soft bits are converted into units, and at the same time, by serially processing each third data unit, the processing in the form of units is realized and the soft bits are improved. The processing efficiency.
  • the sequential storage of each received soft bit to generate a plurality of third data units includes: if the received target soft bit satisfies the filling bit start neighboring condition, then The target soft bit generates the current third data unit for the last soft bit received, and continues to receive the next soft bit to generate the next third data unit.
  • the encoded data may include padding bits, and the padding bits are not in the data before deinterleaving. Therefore, when storing the data before deinterleaving, the position of the padding bits can be reserved in the current third data unit, and according to the received The next soft bit generates the next third data unit. Wherein, if the target soft bit happens to be the last soft bit in the current third data unit, there is no need to reserve the position of the padding bit in the current third data unit, and the current third data unit is directly generated. A new third data unit is formed according to the next soft bit received, and the next soft bit received at the same time is the first soft bit of the third data unit.
  • the third data unit can be constructed in advance, and the received soft bits are filled in it, and at the same time, the soft bits are not filled in the positions of the filling bits, and the positions are reserved.
  • the starting neighbor condition of the stuffing bit is used to determine whether the position of the received soft bit in the coded data that is offset by the target length is the position of the stuffing bit.
  • the target soft bit refers to the soft bit whose position in the coded data is offset from the target length as the position of the stuffing bit.
  • the target soft bit is used to determine whether to end the acquisition of the soft bit in the current third data unit.
  • the current third data unit refers to the third data unit currently to be generated.
  • the current third data unit may use the target soft bit as the last soft bit received from the data before deinterleaving. If the target soft bit is the last soft bit in the current third data unit, the current third data is directly generated Unit; if not, reserve the position of the padding bit to generate the current third data unit. At this time, the number of soft bits in the data before deinterleaving included in the current third data unit is less than the target length.
  • the soft bits in the encoded data can be numbered according to the sequence, and the sequence number is used as the position of the soft bits.
  • the starting neighboring condition of the stuffing bit includes whether the position of the soft bit in the coded data is K'-2Z c -1. If the position of the soft bit is K'-2Z c -1, it is determined that the soft bit satisfies the initial neighboring condition of the filling bit.
  • the soft merging of the third data unit to form the first data unit includes: querying in the set to be merged according to the unit coding position corresponding to the third data unit The unit to be merged that matches the third data unit is merged to obtain the first data unit; according to the first data unit, the matched unit to be merged is updated in the set to be merged, and the unit to be merged is The unit length of the merging unit is the target length, the unit to be merged is used to store historical merged data, and the historical merged data is used to merge with soft bits in the third data unit to update the third data unit Medium soft bit.
  • the set to be merged is used to store historical merged data, and the historical merged data is stored in the form of units to be merged.
  • the initial value of the historical merged data is 0.
  • the data transmitted for the first time can be stored in the set to be merged as historical merged data. If the receiving end can decode correctly, the decoded data will be decoded for subsequent processing, and the set to be merged The data in can be reset, or a new set to be merged can be configured for the next CB. If the receiving end finds that it cannot decode correctly, it requests the sending end to retransmit the data, where the retransmitted data can be all the data in the CB or part of the data in the CB.
  • the receiving end merges the data from the second retransmission and the stored data for the first transmission, that is, the historical merged data, and updates the historical merged data according to the merged data, and performs decoding. If it is decoded correctly, then The decoded data is decoded for subsequent processing; if it cannot be decoded correctly, continue to request retransmission of the data and repeat the above steps.
  • the historical merged data is actually the data obtained by merging the historically transmitted data. There may be errors in the data before deinterleaving, and the correspondingly formed third data unit has errors. At this time, corrections can be made according to the historical merged data to ensure that the correct first data unit is formed.
  • the set to be combined is located in the HARQ memory, and the storage position of the unit to be combined in the HARQ memory corresponds to the unit encoding position of the third data unit. Therefore, the matching unit to be combined can be queried in the HARQ memory according to the unit coding position of the third data unit.
  • the soft merging in the embodiment of the present application is to read the unit to be merged that matches the third data unit from the HARQ memory.
  • the soft bits in the unit to be combined and the soft bits in the third data unit are in one-to-one correspondence, and the combination is completed in parallel.
  • Replace the soft bits in the third data unit with the merged soft bits to obtain the first data unit and send it to the decoder for storage.
  • One-time soft merge operation is to read the unit to be merged that matches the third data unit from the HARQ memory.
  • the unit to be merged in the soft merge set By configuring the storage address of the unit to be merged in the soft merge set to correspond to the unit encoding position of the third data unit, the unit to be merged that matches the third data unit can be accurately searched and merged, thereby realizing the third data unit as the unit.
  • Soft merge operation improves the efficiency of soft merge operation and improves data reliability.
  • the number of cycles is the same as the target cycle number, or is determined according to one-half of the target cycle number, the set cycle number is an integer, and the target cycle number includes the number of cycles from the beginning to the third
  • the data unit is soft-combined to the number of clock cycles corresponding to the length of time required to generate the first data unit.
  • P can be Q or Q/2, if Q is an odd number , Then P is the value of Q/2 rounded up.
  • Q is the number of target cycles, and P is the number of set cycles.
  • the processing frequency of the third data unit can be flexibly realized.
  • the number of set cycles is determined according to one-half of the number of target cycles, and the number of set cycles is an integer; and the third data unit is soft-combined to form
  • the first data unit includes: if the first data obtained from the currently processed third data unit is determined according to the unit encoding position corresponding to the currently processed third data unit and the unit encoding position corresponding to the previous third data unit If the unit meets the repetitive rate matching condition, the unit to be merged to which the currently processed third data unit matches is determined according to the unit to be merged corresponding to the previous third data unit.
  • the repetitive rate matching condition is used to determine whether the soft bits in two consecutive third data units in the serial processing are the same. Specifically, the determination can be made based on whether the unit codes corresponding to the two third data units are the same. If the unit encoding position corresponding to the currently processed third data unit is the same as the unit encoding position corresponding to the previous third data unit, it indicates that the soft bits in the two third data units are the same, and it is determined that the currently processed third data unit satisfies Repeat the rate matching condition.
  • a third data unit starts to be read from the HARQ memory, to complete the soft merge, and finally write back to the same address for the target cycle number.
  • the unit to be merged corresponding to the two third data units that meet the repetitive rate matching condition is actually the same, and the unit to be merged read from the HARQ memory by the second processed third data unit is actually not updated.
  • the first data unit obtained by the first processed third data unit can be directly used as the unit to be merged obtained by the second processed third data unit, which can reduce waiting for read updates from the set to be merged.
  • the acquiring the punctured data and generating the second data unit according to the punctured data includes: generating a plurality of zero-setting units, each of the zero-setting units included The soft bit is 0, the unit length of the zero-setting unit is the target length, the total number of soft bits included in each zero-setting unit is the product of the lifting factor and 2, and the unit encoding position corresponding to each zero-setting unit In the unit encoding position corresponding to each of the first data units; if there are padding bits in the encoded data, the padding bits are obtained and the padding unit is generated, and the unit length of the padding unit is the target length; if there is a unit that satisfies the repetition rate If there is a redundant version pre-punctured bit in the first data unit or the encoded data that matches the condition, the redundant version pre-bit is obtained, and the redundant version pre-unit is generated, and the unit length of the redundant version pre-unit is the target Length, the unit encoding position corresponding to each of the redundant
  • the encoded data may include zero-set soft bits (1), redundant version pre-punched bits (2), padding bits (3), and redundant version post-punched bits (5).
  • the zero-setting soft bit (1) is a soft bit that must be included in the coded data.
  • the coded data may include at least one of the redundant version pre-punctured bits (2), padding bits (3), and redundant version post-punctured bits (5), or none of them.
  • the actual data sent by the sending end to the receiving end is the data before deinterleaving (4), and the data before deinterleaving (4) does not include the padding bit (3).
  • the subsequent data (6) is the transmission data after this CB.
  • the positions of soft bits in the coded data are counted from 0 in Fig. 3. Since the first 2Z c soft bits in the encoded data are punctured and will not be sent to the receiving end, statistics can be started directly from the first soft bit after the first 2Z c soft bits.
  • k 0 is the start position of the rate matching of different redundancy versions
  • k1 is the end position of the redundancy version of this transmission
  • Nr is the CB in the multiple redundancy versions that have been received
  • all the soft bits received are The maximum position in the circular buffer, Nr ⁇ Ncb.
  • K' is the sum of the information bits contained in a CB and the number of CRC check bits.
  • Ncb is the end position of the circular buffer.
  • the zero-setting unit is a unit formed by dividing the zero-setting soft bit (1), and all the soft bits included in the zero-setting unit are 0.
  • the unit coding positions of all zero-setting units are before the circular buffer in the coded data, that is, before the deinterleaving data (4), each soft bit is before the position of the coded data, that is, before the deinterleaving data (4) is formed Before the unit encoding position of the first data unit.
  • the target length is Zs
  • the number of zero-setting units is 2Zc.
  • the zero-setting unit is a data unit formed by the fixed first 2Zc soft bits in the systematic bits.
  • the stuffing unit is a unit formed by dividing stuffing bits (3).
  • the stuffing bit (3) can be obtained from the local storage, and can also be read from the HARQ memory.
  • the stuffing bit (3) is usually a soft bit predetermined by the sender and the receiver.
  • the padding bit (3) is located between the punctured bit (2) before the redundancy version and the punctured bit (5) after the redundancy version, and is located in the middle of the data (4) before deinterleaving.
  • the unit encoding position is located between the unit encoding positions of the first data unit. Specifically, the start position of the stuffing bit (3) in the encoded data is K'-2Zc, and the end position is K-2Zc, and the unit coding position of the corresponding stuffing unit is between K'-2Zc and K-2Zc.
  • the punctured bit (2) before the redundancy version can be read from the HARQ memory.
  • the unit before the redundancy version is a unit formed by dividing the punctured bit (2) before the redundancy version.
  • the start position of the punctured bit (2) before the redundancy version in the encoded data is 0 and the end position is k 0 , and the unit encoding position of the corresponding unit before the redundancy version is between 0 and k 0 .
  • the punctured bit before the redundancy version (2) the data before deinterleaving (4) each soft bit is before the position of the encoded data, and the unit encoding position of the corresponding unit before the redundancy version is formed in the data before deinterleaving (4) Before the unit encoding position of the first data unit.
  • the punctured bit (5) after the redundancy version can be read from the HARQ memory.
  • the post-redundancy version unit is a unit formed by dividing the post-redundancy version punctured bit (5).
  • the starting position of the punctured bit (5) after the redundancy version in the coded data is k 1
  • the ending position is N r
  • the unit coding position of the unit after the corresponding redundancy version is between k 1 and N r .
  • the second data unit is obtained to ensure the accuracy of the restored punctured data.
  • the restored punctured data is replaced by soft bits according to the unit form. Recovery, improve the speed of solution rate matching.
  • the HARQ memory can directly store the redundant version pre-punched bits according to the redundant version pre-unit, thereby directly reading the redundant version pre-unit from the HARQ memory.
  • the HARQ memory can directly store the redundant version and punctured bits according to the redundant version unit, thereby directly reading the redundant version unit from the HARQ memory.
  • processing procedure of each unit can be realized by the module as shown in FIG. 4.
  • the decoding block cascade module completes the decoding block segmentation, and outputs Q m soft bits in the same column of the deinterleaving matrix every clock cycle.
  • the decoding block concatenation module outputs from the de-interleaving matrix to the Q m serial-to-parallel conversion module in parallel by column.
  • Each serial-to-parallel conversion module is set to receive the data divided by the decoding block to realize Q m parallel processing.
  • Each channel independently completes the collection of Zs soft bits to form a third data unit and send it to the de-interleaving arbitration module for processing.
  • the de-interleaving arbitration module is set to select one of the third data units after the serial-to-parallel conversion of the Qm channel is completed, and serially send it to the de-rate matching module for processing.
  • the de-rate matching module is configured to complete the HARQ combining process for the first data unit (including Zs soft bits) sent by the de-interleaving arbitration module, and complete the de-rate matching (punctured rate matching).
  • the HARQ memory is responsible for providing the unit to be combined for the de-rate matching module, the decoder is used for decoding, and the decoder is an LDPC decoder.
  • Zs is not arbitrarily set.
  • the decoder performs processing in units of Zc data processing blocks. If Zc cannot be divisible by Zs, this will cause the Zs data to belong to different processing blocks, which greatly increases the complexity of data processing.
  • Zs can be configured to divide Zc, ensuring that Zs data will not span two processing blocks, and reducing the complexity of data processing.
  • a unit identifier can be configured for each unit, and a bit identifier can be configured for the soft bits in the unit, and each soft bit is determined by the unit identifier and the bit identifier. That is, each soft bit in the unit can be determined by querying which unit, and then determining which soft bit is in the unit after determining the unit.
  • Kp_nZs[i] floor((K′-2Zc)/Zs)
  • K_nZs[i] floor((K-2Zc)/Zs)
  • Ncb_nZs[i] floor(Ncb/Zs)
  • Nr_nZs[i] floor(Nr/Zs)
  • the front-level demodulation module because one constellation point demodulation of each layer corresponds to Q m soft bits, the i-th soft bit corresponds to the i-th row of the de-interleaving matrix, and i takes 0, 1, ... Q m -1.
  • the demodulation module in each cycle may output nL layer soft bits at the same time, and nL takes the value 1, 2, 3 or 4.
  • the descrambling module processes the nL layer serially, and outputs 1 layer of soft bits in turn every clock cycle.
  • each serial-to-parallel conversion module processes the i-th soft bit, and each channel receives at most 1 soft bit per clock cycle, and i takes 0, 1,...Q m -1;
  • the purpose of the serial-to-parallel conversion is to collect Zs soft bits to form a unit according to the address a and the offset address, as a processing unit for subsequent rate matching and HARQ processing.
  • the soft bits in the i-th Zs length unit are:
  • Each unit includes address a and offset o counters, where address a is the unit code position.
  • the loop waits for the soft bits until each serial-to-parallel conversion module has collected and processed the E/Qm soft bits, and then the de-interleaving processing of the CB is ended.
  • the soft bit is stored in the o-th position of the unit, and the address a and offset o of the unit are updated.
  • the initial value of o is 0, and the processing is performed as follows:
  • o is equal to Zs, it means that the collection of a unit is over, then the collected Zs soft bits are used as a third data unit and the address ar is used as the unit code position and sent to the de-interleaving arbitration module, and then the serial-to-parallel conversion module is stored and cleared.
  • o is equal to Kp_oZs[0] and a is equal to Kp_nZs[0], it indicates that the next soft bit of the current soft bit in the encoded data is at the start of the stuffing bit and needs to be skipped, that is, the next soft bit received is The soft bit after the end position of the stuffing bit.
  • flag is equal to 1
  • o is equal to Kp_oZs[0] and a is equal to Kp_nZs[0], it indicates that the next soft bit of the current soft bit in the encoded data is at the start position of the padding bit, that is, the position corresponding to K′-2Zc in Figure 3, It needs to be skipped, that is, the next soft bit received is the soft bit after the end position of the stuffing bit. If flag is equal to 1, the soft bit stored in the serial-to-parallel conversion module is sent to the de-interleaving arbitration module as a third data unit and the address ar is used as the unit code position.
  • o is equal to Ncb_oZs and a is equal to Ncb_nZs, it indicates that the current soft bit is at the end of the circular buffer, that is, at the position corresponding to Ncb in Figure 3, and needs to be cycled to the 0 position.
  • flag is equal to 1
  • the soft bit stored in the serial-to-parallel conversion module is sent to the de-interleaving arbitration module as a third data unit and the address ar is used as the unit code position. After that, the related storage of the serial-to-parallel conversion module is cleared, and the flag is set to 0; at the same time, o is set to 0, and a is also set to 0.
  • the de-interleaving arbitration module records the number of one or more channels to be processed according to the writing situation of the Q m channel serial-to-parallel conversion module. Then, every P clock cycles (P>0), according to the polling mechanism, one third data unit and the unit code position ar are selected from the multiple data channels and sent to the de-rate matching module for processing, and the number of the selected channels is Remove from pending tasks.
  • Q is 4 and P is 2; the specific timing is shown in Figure 6.
  • the data after the data is deleted is 0-9567, among which the padding bits are 7616-7679, the remaining soft bits are 0-7615, and 7680- 9567.
  • the padding bits are deleted, and the remaining soft bits are repeated 4 times to form rate-matched data.
  • the rate-matched data has a total of 4*11840 bits, which is the actual bit sent The number is 4*11840.
  • the data after the rate matching is interleaved, that is, it is written in rows and read out in columns.
  • the interleaving matrix has 4 rows (the same number of cycles) and a total of 11840 columns.
  • the interleaving matrix has 4 rows (the same number of cycles) and a total of 11839 columns.
  • each row in the interleaving matrix is 0-7615 (the area filled with vertical lines), 7680-1-1903 (the area filled with diagonal lines), that is, different rows of the interleaving matrix, the same column soft bit storage location the same.
  • the rows of the interlaced matrix are: 0-7615 (the area filled with vertical lines), 7680-11902 (the area filled with oblique lines); 11903 (the area filled with oblique lines), 0-7615 (the area filled with vertical lines) Line area), 7680-11901 (area filled with diagonal lines); 11902-11903 (area filled with diagonal lines), 0-7615 (area filled with vertical lines), 7680-11900 (area filled with diagonal lines); 11901 -11903 (area filled with diagonal lines), 0-7615 (area filled with vertical lines), 7680-11899 (area filled with diagonal lines), that is, different rows of the interlaced matrix, and soft bits in different columns are stored at the same location .
  • the prior art when performing repeated resolution rate
  • each row of soft bits is received in parallel within 1 clock cycle and processed serially, that is, after the data units obtained from different rows are serially processed, it is only necessary to judge the length of two adjacent Zs in the processing process at most. Whether the unit coding positions of the units are the same, if they are the same, directly on the merge result corresponding to the previous Zs-length unit, and then merge into the next Zs-length unit, no need to query and read from the set to be merged again The corresponding unit to be merged saves the time for querying and reading from the set to be merged and the amount of processed data.
  • the output soft bits are 0,0,0,0,1,1,1,1,2,2,2,2....
  • 4 consecutive This processing corresponds to the data unit whose unit coding position is 0. Therefore, there is no need to consider row-by-row judgment, and only two adjacent data units in the processing process can be used, which greatly reduces the complexity of understanding rate matching.
  • the interleaving matrix shown in Figure 9 the output soft bits are 0,11903,11902,11901,1,0,11903,11902...
  • the data unit is 5 intervals, repeating once, because the latter data unit During processing, the data of the previous data unit has been written into HARQ, and the latter data unit can directly read the corresponding data from HARQ, and the repetitive rate matching and merging process is naturally completed. There is no need to perform repeated rate matching judgments, which improves the efficiency of rate matching resolution.
  • the de-rate matching actually reads the Zs soft bits corresponding to ar from the HARQ memory according to the address ar of the de-interleaving arbitration module, that is, the unit to be merged.
  • the two groups of Zs soft bits formed in the third data unit and the unit to be merged are merged in parallel in one-to-one correspondence, and Zs HARQ merging modules are required for parallel processing.
  • Zs merged results that is, the first data unit will be written into the unit position of the LDPC decoder with an address of 2+(ar/2 m ), and the soft bits of the first data unit will be sequentially written in order Write to the location of ar%2 m in the location of the unit.
  • the storage is performed in units, that is, the first data unit is written into the matching unit position.
  • the addressing of the unit position is implemented as a shift selector, which is simple to implement.
  • the first data unit is written back to the HARQ memory corresponding to ar, and the corresponding unit to be merged is overwritten.
  • the unit encoding position ap corresponding to the padding unit is actually taken in the address range Kp_nZs ⁇ Kp_nZs-1 in the encoded data, and sequentially written into the LDPC decoder address as 2+(ap/2 m )
  • the soft bits of the stuffing unit are sequentially written in the unit position at the address ap% 2 m in the order.
  • the written value of each soft bit is the maximum positive value that can be represented.
  • the redundant version pre-punched bits that match the unit encoding position ap to generate the redundant version pre-unit Obtain from the HARQ memory the redundant version pre-punched bits that match the unit encoding position ap to generate the redundant version pre-unit.
  • the unit coding position ap of the unit before the redundancy version is actually taken in the address range 0 ⁇ k_nZs[0]-1 in the coded data, and sequentially written into the unit whose LDPC decoder address is 2+(ap/2 m)
  • the soft bits in the unit are written in order in the unit position at the address ap%2 m .
  • the unit encoding position ap of the unit after the redundancy version is actually taken in the address interval k1_nZs ⁇ Nr_nZs in the encoded data, and written into the unit position of the LDPC decoder address 2+(ap/2 m ) in turn, and the unit The soft bits are sequentially written in the unit position at the address ap%2 m in sequence.
  • the first data unit and the second data unit are stored according to the positional relationship in the encoded data, arranged and spliced into the data to be decoded, so that the decoder can decode to obtain the decoded data.
  • the timing can refer to FIG. 6, a rectangle is one clock cycle, at this time, Q is 4 clock cycles, and P is two clock cycles. Every two clock cycles, the de-interleaving arbitration module selects a third data unit and inputs it to the de-rate matching module for processing. In the duration shown in Fig. 6, the de-interleaving arbitration module serially inputs the selected 7 third data units into the de-rate matching module for sequential processing.
  • the query of the unit to be merged is started according to the 0th third data unit; in the second P period, the 0th third data unit matched Unit to be merged; in the third period of P, perform soft merge on the 0th third data unit, and start the query of the unit to be merged according to the first third data unit; in the fourth period of P, The first data unit formed by soft merging of the 0th third data unit is written back to the HARQ memory and/or written into the decoder, and at the same time, the unit to be merged that matches the first third data unit is obtained. And so on.
  • the second data unit can be generated and stored in the decoder in any period of P.
  • FIG. 10 is a schematic diagram of a decoding device provided by an embodiment of the application.
  • This embodiment is a corresponding device for implementing the decoding method provided in any of the foregoing embodiments of this application, and the device may be set in a network device.
  • the pre-deinterleaving data receiving module 310 is configured to receive the pre-deinterleaving data and the soft bit coding position;
  • the first data unit generating module 320 is configured to divide the data before deinterleaving to obtain the first data unit
  • the second data unit generating module 330 is configured to obtain punctured data, and obtain a second data unit according to the punctured data.
  • the data before deinterleaving and the punctured data are coded according to the soft bit The position is determined in the coded data;
  • the decoded data determining module 340 is configured to decode according to the soft bit encoding position, the first data unit and the second data unit to obtain decoded data.
  • the decoding method, device, network equipment, and storage medium provided by the embodiments of the present application form multiple first data units by dividing the soft bits in the data before deinterleaving, and obtain the punctured data at the same time, and perform soft Bit division, generate multiple second data units, and form and decode data to be decoded according to the soft bit encoding position, the first data unit and the second data unit, so as to realize the processing of multiple soft bit forming units and solve
  • the de-rate matching process needs to be processed one by one soft bit, which leads to the low efficiency of de-rate matching, which can reduce the situation of individual addressing of each soft bit in the de-rate matching and decoding process, and can increase the solution rate. Matching and decoding efficiency.
  • the decoded data determining module 340 is further configured to: determine the value of each first data unit according to the soft bit encoding position and the first soft bit in each first data unit Unit encoding position; determine the unit encoding position of each second data unit according to the soft bit encoding position and the first soft bit in each of the second data units; respectively, according to each of the unit encoding positions
  • a data unit and the second data unit are stored at matching storage addresses in the decoder to arrange the first data unit and the second data unit to form the data to be decoded, so that the decoding The decoder decodes the data to be decoded.
  • the unit lengths of the first data unit and the second data unit are both a target length, and the target length is determined according to a lifting factor.
  • the target length is the ratio of the lifting factor to the power of a set value of 2
  • the first number is less than or equal to a set number threshold
  • the set number threshold is determined according to the operating frequency and available resources .
  • the first data unit generating module 320 is further configured to: receive the soft bits output by the deinterleaving matrix in multiple channels in parallel; store the soft bits received in each channel in sequence, and generate multiple third data units. Data unit; according to a set number of clock cycles, sequentially soft-combine each of the third data units to form a plurality of first data units.
  • the first data unit generating module 320 is further configured to: if the received target soft bit meets the filling bit start neighboring condition, use the target soft bit as the last received soft bit.
  • the soft bit generates the current third data unit, and continues to receive the next soft bit to generate the next third data unit.
  • the first data unit generation module 320 is further configured to: according to the unit encoding position corresponding to the third data unit, query the to-be-combined set for the to-be-combined data unit that matches the third data unit. Merge unit and merge to obtain a first data unit; according to the first data unit, update the matched unit to be merged in the set to be merged, and the unit length of the unit to be merged is the target length
  • the unit to be merged is used for storing historical merged data, and the historical merged data is used for merging with soft bits in the third data unit to update the soft bits in the third data unit.
  • the number of set cycles is the same as the number of target cycles, or is determined according to one-half of the number of target cycles, the number of set cycles is an integer, and the number of target cycles includes the
  • the third data unit is soft-combined to the number of clock cycles corresponding to the time required to generate the first data unit.
  • the number of set cycles is determined according to one-half of the number of target cycles, and the number of set cycles is an integer; the first data unit generating module 320 is further set as follows: The unit encoding position corresponding to the processed third data unit and the unit encoding position corresponding to the previous third data unit are determined, and the first data unit obtained from the currently processed third data unit satisfies the repetitive rate matching condition. The unit to be merged corresponding to the previous third data unit is determined to be the unit to be merged that matches the currently processed third data unit.
  • the second data unit generating module 330 is further configured to generate a plurality of zero-setting units, each soft bit included in the zero-setting unit is 0, and the unit length of the zero-setting unit is Target length, the total number of soft bits included in each zero-setting unit is the product of the lifting factor and 2, and the unit encoding position corresponding to each zero-setting unit precedes the unit encoding position corresponding to each first data unit; If there are padding bits in the encoded data, obtain padding bits and generate padding units.
  • the unit length of the padding unit is the target length; if there is a first data unit that meets the repetitive rate matching condition or the encoded data exists Punch the bits before the redundancy version to obtain the bits before the redundancy version, and generate the unit before the redundancy version, the unit length of the unit before the redundancy version is the target length, and each unit corresponds to the unit before the redundancy version.
  • the encoding position is before the unit encoding position corresponding to each of the first data units; if there is a first data unit that satisfies the repetitive rate matching condition or the encoded data has redundant version post-punctured bits, then the redundant version is obtained The last bit, and generate a redundant version of the unit, the unit length of the redundant version of the unit is the target length, and the unit encoding position corresponding to each of the redundant version of the unit is corresponding to each of the first data unit The unit encoding position.
  • the foregoing decoding device can execute the decoding method provided by the embodiments of the present application, and has the functional modules and beneficial effects corresponding to the executed decoding method.
  • the present application provides a network device.
  • the network device includes a processor and a memory; the processor is configured to execute a program stored in the memory to implement the method in the foregoing embodiment.
  • the network equipment is the power supply equipment for the equipment.
  • the memory can be configured to store software programs, computer-executable programs, and modules, such as program instructions/modules corresponding to the decoding method in the embodiments of the present application.
  • the memory may mainly include a program storage area and a data storage area, where the program storage area may store an operating system and an application program required by at least one function; the data storage area may store data created according to the use of the terminal, etc.
  • the memory may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one magnetic disk storage device, a flash memory device, or other non-volatile solid-state storage devices.
  • the memory may further include a memory remotely provided with respect to the processor, and these remote memories may be connected to the device through a network. Examples of the aforementioned networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.
  • the present application provides a storage medium that stores a computer program, and when the computer program is executed by a processor, the method in the foregoing embodiment is implemented.
  • the computer storage medium of the embodiment of the present invention may adopt any combination of one or more computer-readable media.
  • the computer-readable medium may be a computer-readable signal medium or a computer-readable storage medium.
  • the computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or device, or a combination of any of the above. More specific examples of computer-readable storage media (non-exhaustive list) include: electrical connections with one or more wires, portable computer disks, hard disks, RAM, Read Only Memory (ROM), erasable Erasable Programmable Read Only Memory (EPROM), flash memory, optical fiber, portable CD-ROM, optical storage device, magnetic storage device, or any suitable combination of the above.
  • the computer-readable storage medium can be any tangible medium that contains or stores a program, and the program can be used by or in combination with an instruction execution system, apparatus, or device.
  • the computer-readable signal medium may include a data signal propagated in baseband or as a part of a carrier wave, and computer-readable program code is carried therein. This propagated data signal can take many forms, including, but not limited to, electromagnetic signals, optical signals, or any suitable combination of the foregoing.
  • the computer-readable signal medium may also be any computer-readable medium other than the computer-readable storage medium.
  • the computer-readable medium may send, propagate, or transmit the program for use by or in combination with the instruction execution system, apparatus, or device .
  • the program code contained on the computer-readable medium can be transmitted by any suitable medium, including, but not limited to, wireless, wire, optical cable, radio frequency (Radio Frequency, RF), etc., or any suitable combination of the above.
  • suitable medium including, but not limited to, wireless, wire, optical cable, radio frequency (Radio Frequency, RF), etc., or any suitable combination of the above.
  • the computer program code used to perform the operations of the present invention can be written in one or more programming languages or a combination thereof.
  • the programming languages include object-oriented programming languages—such as Java, Smalltalk, C++, and also conventional Procedural programming language-such as "C" language or similar programming language.
  • the program code can be executed entirely on the user's computer, partly on the user's computer, executed as an independent software package, partly on the user's computer and partly executed on a remote computer, or entirely executed on the remote computer or server.
  • the remote computer may be connected to the user's computer through any kind of network including LAN or WAN, or may be connected to an external computer (for example, using an Internet service provider to connect through the Internet).
  • user terminal encompasses any suitable type of wireless user equipment, such as a mobile phone, a portable data processing device, a portable web browser, or a vehicle-mounted mobile station.
  • the various embodiments of the present application can be implemented in hardware or dedicated circuits, software, logic or any combination thereof.
  • some aspects may be implemented in hardware, while other aspects may be implemented in firmware or software that may be executed by a controller, microprocessor, or other computing device, although the present application is not limited thereto.
  • Computer program instructions can be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source code written in any combination of one or more programming languages or Object code.
  • ISA instruction set architecture
  • the block diagram of any logic flow in the drawings of the present application may represent program steps, or may represent interconnected logic circuits, modules, and functions, or may represent a combination of program steps and logic circuits, modules, and functions.
  • the computer program can be stored on the memory.
  • the memory can be of any type suitable for the local technical environment and can be implemented using any suitable data storage technology, such as but not limited to read only memory (ROM), random access memory (RAM), optical storage devices and systems (digital multi-function optical discs) DVD or CD) etc.
  • Computer-readable media may include non-transitory storage media.
  • the data processor can be any type suitable for the local technical environment, such as but not limited to general-purpose computers, special-purpose computers, microprocessors, digital signal processors (DSP), application-specific integrated circuits (ASIC), programmable logic devices (FGPA) And processors based on multi-core processor architecture.
  • DSP digital signal processors
  • ASIC application-specific integrated circuits
  • FGPA programmable logic devices

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Abstract

本申请提出一种译码方法、装置、网络设备及存储介质。该方法包括：接收解交织前数据和软比特编码位置；划分所述解交织前数据，得到第一数据单元；获取被打孔数据，并根据所述被打孔数据，得到第二数据单元，所述解交织前数据和所述被打孔数据根据所述软比特编码位置在编码数据中确定；根据所述软比特编码位置、所述第一数据单元和所述第二数据单元进行译码，得到译码数据。

Description

译码方法、装置、网络设备及存储介质 技术领域
本申请涉及通信领域，具体涉及一种译码方法、装置、网络设备及存储介质。
背景技术
在通信系统中，速率匹配的作用是调整信道编码器输出的码率，使速率匹配模块输出的比特数与系统分配的物理资源所能承载的比特数相符合。速率匹配过程中一般伴随交织，交织用于打乱编码数据，以在信号发生错误时，将错误离散化，降低纠错处理的难度，从而保护编码数据，以提高编码性能的稳定性。
3GPP NR协议在上下行业务信道采用低密度校验矩阵编码(Low Density Parity Check Code，LDPC)，编码后先进行了速率匹配，然后再交织，这几个过程都是以码块(Code Block，CB)为单位的，速率匹配采用了基于循环缓存器的速率匹配机制，交织采用了常用的R行C列的分组交织。解交织、解速率匹配是速率匹配、交织的逆过程。LDPC译码为了满足吞吐率要求，通常一个周期要读取Zc个软比特进行处理,即解速率匹配或译码器需要将Zc个软比特组合到一起，间接要求解速率匹配过程有x/Z c或者x％Z c等寻址操作，其中，x为软比特在译码器的位置，而Z c为LDPC编码使用的提升因子，对应有8种取值，且都是质数，导致这种寻址操作实现复杂。
发明内容
本申请提供用于译码方法、装置、网络设备及存储介质。
本申请实施例提供一种译码方法，包括：
接收解交织前数据和软比特编码位置；
划分所述解交织前数据，得到第一数据单元；
获取被打孔数据，并根据所述被打孔数据，得到第二数据单元，所述解交织前数据和所述被打孔数据根据所述软比特编码位置在编码数据中确定；
根据所述软比特编码位置、所述第一数据单元和所述第二数据单元进行译码，得到译码数据。
本申请实施例提供一种译码装置，包括：
解交织前数据接收模块，设置为接收解交织前数据和软比特编码位置；
第一数据单元生成模块，设置为划分所述解交织前数据，得到第一数据单元；
第二数据单元生成模块，设置为获取被打孔数据，并根据所述被打孔数据，得到第二数据单元，所述解交织前数据和所述被打孔数据根据所述软比特编码位置在编码数据中确定；
译码数据确定模块，设置为根据所述软比特编码位置、所述第一数据单元和所述第二数据单元进行译码，得到译码数据。
本申请实施例提供一种网络设备，包括：至少一个处理器以及存储器；所述处理器设置为执行存储器中存储的程序，以实现本申请实施例中的任意一种方法。
本申请实施例提供一种存储介质，所述存储介质存储有计算机程序，所述计算机程序被处理器执行时实现权利要求本申请实施例中的任意一种方法。
关于本申请的以上实施例和其他方面以及其实现方式，在附图说明、具体实施方式和权利要求中提供更多说明。
附图说明
图1为本申请实施例中的发送端和接收端交互的流程图；
图2为本申请实施例中的译码方法的流程图；
图3为本申请实施例中的编码数据结构的示意图；
图4为本申请实施例所适用的应用场景的示意图；
图5为本申请实施例中的软比特存储格式的示意图；
图6为本申请实施例中的单元处理的时序图；
图7为本申请实施例中的速率匹配后数据的示意图；
图8为本申请实施例中的一种交织矩阵的示意图；
图9为本申请实施例中的另一种交织矩阵的示意图；
图10为本申请实施例中的译码装置的示意图。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚明白，下文中将结合附图对本申请的实施例进行详细说明。需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互任意组合。
在介绍本申请实施例提供的技术方案之前，为方便理解，先介绍发送端与接收端的通信过程涉及的数据处理，具体如图1所示，
发送端根据待发送的传输块生成循环冗余校验码(Cyclic Redundancy Check，CRC)，并将传输块分割形成CB作为传输单元，计算每个CB的CRC。对各码块进行低密度奇偶校验(Low Density Parity Check，LDPC)编码，得到CB对应的编码数据，并对编码数据依次经过速率匹配和交织，并将输出结果进行级联，依次进行加扰、调制、快速傅里叶逆变换，以设定频率进行发射，通过无线空口发送至接收端。
接收端根据接收到的数据分别依次进行快速傅里叶变换、信道估计和解调、解扰和解码块级联，之后将每个码块对应的数据进行解交织，并对得到的解交织前数据进行解速率匹配和软合并，从而得到待译码数据，之后对待译码数据进行LDPC译码，得到译码数据，其中，译码数据和编码数据相同。最后将得到的码块进行CRC验证，并将通过CRC验证的多个 码块进行解码块分割，获取传输块。同时对传输块进行CRC验证，将通过验证的传输块，即为发送端实际发送的数据，接收端可以针对该数据进行后续处理。
其中，
设一个CB所有系统比特和CRC校验比特加起来为K′个比特，其中，有L个CRC校验比特(L>0)，对应序列如下：
c 0，c 1，c 2，......c K′-1
目前协议规定LDPC校验矩阵有2类，基图1(BG1)或基图2(BG2)。
基图确定后，根据K′以及基图可以唯一确定该CB编码时使用的LDPC提升因子Zc。
提升因子Zc可以基于公式Zc＝a×2 j确定，其中j＝0,1,...,7，且Zc≤384，同时a为质数，a为集合{2,3,5,7,9,11,13,15}中的任意一个。Zc由一个码块包含的信息比特和CRC校验比特数之和，以及LDPC基图(取值1或2)确定。
在LDPC编码后，也就是速率匹配前的N个比特序列为：
d 0，d 1，d 2，......d N-1
其中，系统比特为：
Figure PCTCN2020140278-appb-000001
可见，系统比特为：
Figure PCTCN2020140278-appb-000002
固定被打孔，不会发送到接收端。
填充比特(Filler Bits)位置为(包括K-K′个填充比特)：
d s＝<NULL>，s＝K′-2Z c，...，K-1
其中，当基图1时，K＝22Z c；当基图2时，K＝10Z c。
其余比特为根据LDPC校验矩阵生成的校验比特。
其次，进行速率匹配。
设E为速率匹配后输出的比特数，则速率匹配过程为：
Figure PCTCN2020140278-appb-000003
其中，N cb≤N，N cb为基于有限缓存的速率匹配中的循环缓存实际大小；
k 0为不同冗余版本的速率匹配起始位置，k 0对应的大小(即与第K′-2Z c个软比特之间包括多少个软比特)为Zc的整数倍。
该码块速率匹配后输出的比特数，即发送端实际发送比特数，取值需为Q m的整数倍。
再次，进行交织：
Figure PCTCN2020140278-appb-000004
其中，Q m为调制阶数，E为速率匹配后输出的比特数，能被Q m整除。
该交织为行列交织器，其中行数R＝Q m；列数C＝E/Q m。
最后，进行码块级联，加扰，调制，层映射，快速傅里叶逆变换等处 理，通过天线发送处理。调制时，1列Q m行个软比特都被调制到同一个星座点。
实施例
图2为本申请实施例提供的译码方法的流程图，本实施例可适用于在通信数据的接收端对通信数据进行解交织和解速率匹配的情况，该方法可以由本申请实施例提供的译码装置来执行，该装置可采用软件和/或硬件的方式实现，并一般可集成网络设备中。如图2所示，具体包括：
S110，接收解交织前数据和软比特编码位置。
解交织前数据可以是软比特。解交织前数据实际是发送端按行写入交织矩阵，按列读出的比特数据，发送端的一个比特对应接收端一个软比特。解交织前数据应当与发送端对CB进行交织得到的交织数据相同，但由于经过空口传输，接收端接收到的数据不一定正确，即解交织前数据不一定与交织数据相同。
软比特编码位置至少包括解交织前数据中各软比特在编码数据(也即译码数据)中的位置。软比特编码位置可以根据接收到的交织矩阵确定，也可以直接由发送端发送至接收端。编码数据即为发送端进行编码之后，且在进行速率匹配和交织之前的数据。
本申请实施例的译码过程对接收解交织前数据进行解速率匹配和软合并得到待译码数据，并对待译码数据进行译码的过程。待译码数据用于译码得到译码数据，编码数据和待译码数据相同。实际上，在进行译码之前，需要先恢复成未经过任何处理的编码数据，从而实现准确译码。
软比特是指接收端在接收到信号之后，不进行判决，直接输出模拟量进行量化的比特。
S120，划分所述解交织前数据，得到第一数据单元。
第一数据单元包括至少两个软比特，用于对软比特进行组合，作为解 速率匹配和软合并的处理单元进行处理。
划分所述解交织前数据，实际是将解交织前数据包括的全部软比特进行分组。
S130，获取被打孔数据，并根据所述被打孔数据，生成第二数据单元，其中，所述解交织前数据和所述被打孔数据根据所述软比特编码位置在编码数据中确定。
其中，S120的顺序可以与S130进行调整，可以在S130之后，也可以与S130同时进行，对此，本申请实施例不作具体限制。
实际上，本申请实施例中速率匹配是发送端将重复比特或者打孔比特，以匹配物理信道的承载能力。打孔是将物理信道不能承载的比特作为冗余数据打掉，同时，将后面的软比特依次前移一位；重复是通过在缓存器中循环取数来达到重复的效果，重复的比特并不相邻。解速率匹配相反，恢复被打掉的比特并将重复的比特合并。其中，打孔和重复都是可选的。本申请实施例中速率匹配为基于循环缓存器的速率匹配机制。
被打孔数据为在速率匹配过程中被打掉的软比特。被打孔数据用于和解交织前数据进行组合生成与编码数据相同的待译码数据。
第二数据单元包括至少两个软比特，用于对软比特进行组合，作为编码数据中被打掉的处理单元，以及用于与第一数据单元进行组合形成待译码数据。
实际上，编码数据可以认为是软比特序列，经过速率匹配得到解交织前数据，其中，从编码数据中删除的数据属于被打孔数据。如图3所示，编码数据包括系统比特、填充比特(3)和校验比特。其中，在通信标准中，系统比特中包括的前2Zc个比特固定为被打孔数据。此外，系统比特还可能包括其他被打孔数据，校验比特中也可以存在其他被打孔数据。需要说明的是，系统比特包括的其他被打孔数据，校验比特包括的被打孔数据和填充比特均可以存在，也可以不存在。其中，前2Zc个比特固定为被 打孔数据，但该被打孔数据的恢复操作不属于解速率匹配。其余被打孔数据的恢复操作属于解速率匹配。
软比特编码位置包括解交织前数据中各软比特在编码数据中的位置和被打孔数据中各软比特在编码数据中的位置。编码数据完成速率匹配过程，之后再进行交织等操作。从而，编码数据可以针对软比特编码位置，根据位于被打孔数据中的软比特在编码数据中的位置，确定被打孔数据。而解交织前数据可以包括多种形式的数据，例如，获取重复的软比特并进行重复形成的数据；获取重传的软比特形成的数据；获取不重复的软比特形成的数据等。其中，重复的、重传以及不重复的软比特位于解交织前数据中，由此，可以根据重复的、重传以及不重复的软比特在编码数据中的位置，确定解交织前数据中各软比特在编码数据中的位置。其中，重复的软比特实际是重复出现的，也即解交织前数据中存在多个软比特在编码数据中的位置相同。
在一个示例性的实施例方式中，所述第一数据单元和所述第二数据单元的单元长度均为目标长度，所述目标长度根据提升因子确定，所述目标长度满足所述提升因子关联的整除条件。
目标长度用于确定第一数据单元和第二数据单元包括的软比特的最大数量。提升因子可以是指在发送端中编码所使用的提升因子，表征比特数扩大的倍数。
通过配置单元的长度均为目标长度，且根据提升因子确定，可以合理配置单元的长度，同时每个单元的长度相同，方便对单元中的软比特进行寻址。
实际上，接收端是针对一个CB进行处理，当CB译码正确时，结束对该CB的解交织和解速率匹配的过程。
在CB第一次传输时，通常对HARQ中该CB中存储的历史合并数据清零。可以在解交织前数据关联的码块处理完成时，删除该码块的关联数 据，或者为给码块的关联数据添加码块标识，以区分该码块的关联数据与下一码块的关联数据。其中，码块标识用于标记各码块的有效区间。
接收端接收到传输的所有数据以后，以循环缓存的格式存储到HARQ中，并以编码后的原始顺序存储到LDPC译码器中。由于译码每次处理时是针对1个Zc的数据，由此，一个地址需要存放Zc个软比特。当存储到最后一个地址时，接收到的属于最后一个地址的软比特的总数量小于Zc，可以填充0，以使最后一个地址的软比特的数量等于Zc。
其中，在一个可选的实施例中，目标长度需要满足提升因子关联的整除条件，表明提升因子可以被目标长度整除，从而一个数据单元的数据不存在属于不同的Zc的情况，从而保证一个数据单元的数据不会跨2个Zc，可以配合在LDPC译码器中的存储格式，n个数据单元的数据正好等于一个地址可存储的Zc个软比特，保证不会超出一个地址，从而减少处理的复杂度。
在一个示例性的实施例方式中，所述目标长度为提升因子与2的设定值次方的比值，所述第一数量小于等于设定数量阈值，所述设定数量阈值根据工作频率和可用资源确定。
示例性的，CB使用LDPC编码，提升因子为LDPC编码的提升因子。
提升因子Zc可以基于公式Zc＝a×2 j确定，其中j＝0,1,...,7，且Zc≤384，同时a为质数，a为集合{2,3,5,7,9,11,13,15}中的任意一个。Zc由一个码块包含的信息比特和CRC校验比特数之和，以及LDPC基图(取值1或2)确定。
通过配置单元的长度均为目标长度，且根据提升因子确定，可以合理配置单元的长度，同时每个单元的长度相同，方便对单元中的软比特进行寻址。
在一个示例性的实施例方式中，所述目标长度为提升因子与2的设定值次方的比值，所述第一数量小于等于设定数量阈值，所述设定数量阈值 根据工作频率和可用资源确定。
具体的，目标长度为Zs。设定阈值为A，Zs≤A，A根据工作频率和可用资源确定，设定值为m。具体的，Zs根据如下过程确定：
Zs＝Zc；
m＝0；
如果Zs大于A，则将Zs＝Zs/2，m＝m+1，重复此过程，直到Zs满足Zs≤A。
通过根据提升因子确定目标长度，可以合理配置单元的长度，避免一次处理的软比特太多或太少，从而提高软比特的速率匹配效率。
S140，根据所述软比特编码位置、所述第一数据单元和所述第二数据单元进行译码，得到译码数据。
软比特编码位置、第一数据单元和第二数据单元用于确定待译码数据。具体的，第一数据单元和第二数据单元可以进行组合形成待译码数据，对该待译码数据进行译码，得到译码数据。可以理解的是，组合方式需要知道第一数据单元和第二数据单元的位置关系，可以根据软比特编码位置确定第一数据单元和第二数据单元中的软比特在编码数据(也即待译码数据)中的位置，由此，可以按照位置关系将第一数据单元和第二数据单元进行排列，得到待译码数据。
在一个示例性的实施例方式中，所述根据所述软比特编码位置、所述第一数据单元和所述第二数据单元进行译码，包括：根据所述软比特编码位置以及各所述第一数据单元中首个软比特，确定各所述第一数据单元的单元编码位置；根据所述软比特编码位置以及各所述第二数据单元中首个软比特，确定各所述第二数据单元的单元编码位置；根据各所述单元编码位置分别将所述第一数据单元和所述第二数据单元存储在译码器中匹配的存储地址处，以排列所述第一数据单元和所述第二数据单元，形成待译 码数据，以使所述译码器对所述待译码数据进行译码。
其中，第一数据单元和第二数据单元可以认为是软比特序列。可以用软比特序列中首个软比特在编码数据中的位置作为该软比特序列在编码数据中的位置，也即单元的单元编码位置。各单元中除首个软比特的位置可以根据软比特之间的次序，也即相对位置，以及单元编码位置确定。
相应的，在对各单元进行存储时，在单元编码位置对应的存储地址写入首个软比特，并在该存储地址的偏移1位的地址中写入下一软比特，而后，依次在后续偏移地址后写入后续的软比特，依次类推，将单元中的软比特按照次序一一写入译码器中。
译码器中匹配的存储地址与单元编码位置对应。按照各第一数据单元和各第二数据单元的单元编码位置分别存储在匹配的位置处，从而在存储的同时实现按照单元编码位置排列各第一数据单元和各第二数据单元，从而实现拼接组合形成待译码数据。
通过根据软比特编码位置确定各第一数据单元和各第二数据单元的单元编码位置，并对应将各第一数据单元和各第二数据单元存储在与单元编码位置匹配的存储地址中，以使在译码器中排列组合各第一数据单元和各第二数据单元，保证解速率匹配准确，从而准确拼接形成待译码数据。
本申请实施例所提供的译码方法、装置、网络设备及存储介质，通过对解交织前数据中的软比特进行划分，形成多个第一数据单元，同时获取被打孔数据，并进行软比特划分，生成多个第二数据单元，并按照软比特编码位置、第一数据单元和第二数据单元形成待译码数据并进行译码，从而实现将多个软比特形成单元进行处理，解决了现有技术中解速率匹配过程中需要按照逐个软比特进行处理导致解速率匹配的效率低的问题，可以减少解速率匹配和译码过程中逐个软比特单独寻址的情况，可以提高解速率匹配和译码效率。
在一个示例性的实施例方式中，所述接收解交织前数据，并划分所述解交织前数据，得到第一数据单元，包括：多路并行接收解交织矩阵按列输出的软比特；顺序存储每路接收到的软比特，生成多个第三数据单元；按照设定周期数量的时钟周期，依次对各所述第三数据单元进行软合并，形成多个第一数据单元。
实际上，解交织前数据是从解交织矩阵中获取的。解交织矩阵是按列输出，交织矩阵中一共有Qm个行，每列输出Qm个软比特。多路并行接收解交织前按列输出的软比特，在一个设定周期数量的时钟周期内，每路最多接收一个软比特。每路分别按照接收顺序存储接收到的软比特，也即一路存储的软比特是解交织矩阵中的一行中软比特。
可以配置Qm个串并转换模块，各串并转换模块并行工作，每个串并转换模块处理解交织矩阵的一行，以实现多路并行接收软比特，并顺序存储，从而独立完成第三数据单元的软比特收集，形成一个第三数据单元。同时根据软比特位置，确定第三数据单元中接收到的首个软比特在编码数据中的位置，并将该位置作为第三数据单元的单元编码位置，和形成的第三数据单元发送至下一处理模块进行后续处理。
Qm个串并转换模块，可以生成Qm的整数倍的第三数据单元。在第三数据单元的处理过程中，采用串行处理方式，依次对各第三数据单元分别进行处理。
其中，软合并是指基于混合自动重传请求(Hybrid Automatic Repeat request，HARQ)的合并。实际上，发送端在发送数据包之后需要等待接收端反馈接受正确的消息，如果没有反馈，发送端会重传该数据包或者该数据包的部分，保证接收端能够接收到正确的数据包。接收端可以在获取第三数据单元后，从HARQ存储器中匹配的缓存数据进行合并，合并后的单元作为第一数据单元，同时，该第一数据单元为传输正确的有效数据单元。
其中，串行处理的次序的确定方式可以是：按照设定规则(如轮询)依次从多路中选取1路形成的第三数据单元作为处理单元，进行处理。
设定周期数量的时钟周期，用于作为第三数据单元的处理频率，也即作为从多路中选取1路形成的第三数据单元的选择频率。设定周期数量的时钟周期可以根据需要进行设定。通常一个时钟周期的时长不够完成一个第三数据单元的处理任务，可以选择多个时钟周期作为一个处理周期，完成一个第三数据单元的处理任务。
通过并行接收解交织矩阵输出的软比特，并顺序存储软比特形成第三数据单元，将软比特转换成单元，同时通过串行处理各第三数据单元，实现以单元形式进行处理，提高软比特的处理效率。
在一个示例性的实施例方式中，所述顺序存储每路接收到的软比特，生成多个第三数据单元，包括：如果接收到的目标软比特满足填充比特起始相邻条件，则以所述目标软比特为接收到的最后一个软比特生成当前第三数据单元，并继续接收下一个软比特，以生成下一第三数据单元。
实际上，编码数据可以包括填充比特，而填充比特不在解交织前数据中，从而在存储解交织前数据时，可以在当前第三数据单元中预留出填充比特的位置，并根据接收到的下一软比特，生成下一第三数据单元。其中，如果目标软比特正好为当前第三数据单元中的最后一个软比特，则无需在当前第三数据单元中预留出填充比特的位置，直接生成当前第三数据单元。根据接收的下一个软比特形成新的第三数据单元，同时接收到的下一个软比特为第三数据单元的首个软比特。
实际上，可以预先构建第三数据单元，并在其中填充接收到的软比特，同时在填充比特的位置上不填充软比特，预留出位置。
填充比特起始相邻条件用于确定接收到的软比特在编码数据中的位置偏移目标长度的位置是否为填充比特的位置。目标软比特是指在编码数据中的位置偏移目标长度的位置为填充比特的位置的软比特。目标软比特 用于确定是否结束当前第三数据单元中的软比特的获取。当前第三数据单元，是指当前待生成的第三数据单元。当前第三数据单元可以将该目标软比特作为从解交织前数据中接收到的最后一个软比特，如果目标软比特为当前第三数据单元中的最后一个软比特，则直接生成当前第三数据单元；如果不是，则预留出填充比特的位置，生成当前第三数据单元，此时，该当前第三数据单元中包括的属于解交织前数据中的软比特的数量小于目标长度。
实际上，可以对编码数据中的软比特按照排序进行编号，序号作为软比特的位置。
具体的，填充比特起始相邻条件包括软比特在编码数据中的位置是否为K′-2Z c-1。如果软比特的位置为K′-2Z c-1，确定该软比特满足填充比特起始相邻条件。
继续接收下一软比特，并将该软比特作为新的第三数据单元的首个软比特，以生成新的第三数据单元。
通过在第三数据单元中预留出填充比特的位置，可以保证第三数据单元中的软比特在编码数据中的位置均是连续的，从而在后续排列第三数据单元时，可以准确进行排列，避免一个第三数据单元中包括不连续的多个软比特，导致相应的第一数据单元需要进行分割处理才能进行排列组合，可以直接以第一数据单元为单位进行排列组合，从而提高第一数据单元的处理效率。
在一个示例性的实施例方式中，所述对所述第三数据单元进行软合并，形成第一数据单元，包括：根据所述第三数据单元对应的单元编码位置，在待合并集合中查询与所述第三数据单元匹配的待合并单元，并进行合并，得到第一数据单元；根据所述第一数据单元，在所述待合并集合中更新所述匹配的待合并单元，所述待合并单元的单元长度为所述目标长度，所述 待合并单元用于存储历史合并数据，所述历史合并数据用于与所述第三数据单元中软比特进行合并，以更新所述第三数据单元中软比特。
待合并集合用于存储历史合并数据，历史合并数据是以待合并单元的形式存储。历史合并数据的初始值为0，可以将第一次传输的数据存入待合并集合，作为历史合并数据，如果接收端可以正确译码，则译码得到译码数据进行后续处理，待合并集合中的数据可以重置，或者为下一CB配置新的待合并集合。如果接收端发现无法正确译码，请求发送端重传数据，其中，该重传数据可以是CB中的全部数据，也可以是CB中的部分数据。接收端根据第二次重传的与存储的第一次传输的数据，也即历史合并数据，进行合并，并根据合并后的数据更新历史合并数据，以及进行译码，如果正确译码，则译码得到译码数据进行后续处理；如果无法正确译码，继续请求重传数据，重复上述步骤。
历史合并数据实际为将历史传输的数据进行合并后的数据。在解交织前数据中可能存在错误，相应形成的第三数据单元存在错误，此时可以根据历史合并数据进行修正，保证形成正确的第一数据单元。
待合并集合位于HARQ存储器，待合并单元在HARQ存储器的存储位置与第三数据单元的单元编码位置对应。由此，可以根据第三数据单元的单元编码位置，在HARQ存储器中查询匹配的待合并单元。
实际上，本申请实施例中的软合并为，从HARQ存储器中读取与第三数据单元匹配的待合并单元。待合并单元中的软比特和第三数据单元中的软比特进行一一对应，并行完成合并。将第三数据单元中的软比特替换为合并后的软比特，得到第一数据单元发送至译码器中存储，同时拷贝一份写回HARQ存储器中，更新原来的待合并单元，以便进行下一次的软合并操作。
通过配置软合并集合中的待合并单元的存储地址与第三数据单元的单元编码位置对应，从而准确查询第三数据单元匹配的待合并单元并进行 合并，从而实现以第三数据单元为单位进行软合并操作，提高软合并操作的效率，提高数据可靠性。
在一个示例性的实施例方式中，与目标周期数量相同，或者根据目标周期数量的二分之一确定，所述设定周期数量为整数，所述目标周期数量包括从开始对所述第三数据单元进行软合并到生成第一数据单元所需时长对应的时钟周期数量。
具体的，假设一个第三数据单元完成从HARQ存储器中启动读取，到完成软合并，并最终写回同一个地址的时钟周期数为Q，P可以取Q或Q/2，若Q为奇数，则P为Q/2向上取整之后的数值。Q即为目标周期数量，P为设定周期数量。
通过配置设定周期数量，可以灵活实现第三数据单元处理的频率。
在一个示例性的实施例方式中，所述设定周期数量根据目标周期数量的二分之一确定，所述设定周期数量为整数；所述对所述第三数据单元进行软合并，形成第一数据单元，包括：如果根据当前处理的第三数据单元对应的单元编码位置和前一第三数据单元对应的单元编码位置，确定由所述当前处理的第三数据单元得到的第一数据单元满足重复速率匹配条件，则根据所述前一第三数据单元对应的待合并单元，确定所述当前处理的第三数据单元匹配的待合并单元。
重复速率匹配条件用于判断串行处理的连续两个第三数据单元中的软比特是否相同，具体的，可以根据这两个第三数据单元对应的单元编码是否相同来进行判断。如果当前处理的第三数据单元对应的单元编码位置和前一第三数据单元对应的单元编码位置相同，表明这两个第三数据单元中的软比特相同，确定当前处理的第三数据单元满足重复速率匹配条件。
实际上，一个第三数据单元从HARQ存储器中启动读取，到完成软合并，并最终写回同一个地址的时长为目标周期数量。设定周期数量为目 标周期数量的二分之一，或二分之一取整后的数值，表明在一个第三数据单元未完成写回同一个地址的过程中，另外一个第三数据单元开始进行处理，即从HARQ存储器中启动读取相应待合并单元。此时，满足重复速率匹配条件的两个第三数据单元对应的待合并单元实际是同一个，第二个处理的第三数据单元从HARQ存储器中读取的待合并单元实际是未更新的，由此，可以直接根据第一个处理的第三数据单元得到的第一数据单元作为第二个处理的第三数据单元得到的待合并单元进行合并，可以减少从待合并集合中等待读取更新后的待合并单元的处理时间和读取次数。
此外，如果设定周期数量为目标周期数量，此时，任意连续两个第三数据单元中，一个第三数据单元形成第一数据单元并写回之后，另一个第三数据单元才开始处理，从而，重复速率匹配对这两个第三数据单元的处理没有影响。
在一个示例性的实施例方式中，所述获取被打孔数据，并根据所述被打孔数据，生成第二数据单元，包括：生成多个置零单元，所述置零单元包括的各软比特为0，所述置零单元的单元长度为目标长度，各所述置零单元总共包括的软比特的数量为提升因子与2的乘积，各所述置零单元对应的单元编码位置前于各所述第一数据单元对应的单元编码位置；如果所述编码数据中存在填充比特，则获取填充比特，并生成填充单元，所述填充单元的单元长度为目标长度；如果存在满足重复速率匹配条件的第一数据单元或者所述编码数据中存在冗余版本前打孔比特，则获取冗余版本前比特，并生成冗余版本前单元，所述冗余版本前单元的单元长度为目标长度，各所述冗余版本前单元分别对应的单元编码位置均前于各所述第一数据单元对应的单元编码位置；如果存在满足重复速率匹配条件的第一数据单元或者所述编码数据中存在冗余版本后打孔比特，则获取冗余版本后比特，并生成冗余版本后单元，所述冗余版本后单元的单元长度为目标长度，各所述冗余版本后单元分别对应的单元编码位置均后于各所述第一数据 单元对应的单元编码位置。
具体如图3所示，编码数据中可以包括置零软比特(1)、冗余版本前打孔比特(2)、填充比特(3)和冗余版本后打孔比特(5)。其中，置零软比特(1)是编码数据中必须包括的软比特。编码数据可以包括冗余版本前打孔比特(2)、填充比特(3)和冗余版本后打孔比特(5)中的至少一项，或者均不包括。其中，发送端向接收端发送的实际数据为解交织前数据(4)，其中，解交织前数据(4)中不包括填充比特(3)。此外，后续数据(6)为本CB之后的传输数据。
通常，编码数据中软比特的位置是从图3中的0开始统计。由于编码数据中固定前2Z c个软比特被打孔，不会发送到接收端，从而可以直接从前2Z c个软比特之后的第一个软比特开始统计。k 0为不同冗余版本的速率匹配起始位置，k1为本次传输的冗余版本的结束位置，Nr为该CB在已经接收到的多个冗余版本中，接收到的所有软比特在循环缓存中位置最大值，Nr≤Ncb。在使用LDPC编码时，当基图1时，K＝22Z c；当基图2时，K＝10Z c。K′为一个CB包含的信息比特和CRC校验比特数之和。Ncb为循环缓存的结束位置。
相应的，置零单元为对置零软比特(1)进行划分形成的单元，置零单元包含的全部软比特均为0。且所有置零单元的单元编码位置均在编码数据中的循环缓存之前，也即在解交织前数据(4)各个软比特在编码数据的位置之前，也即在解交织前数据(4)形成的第一数据单元的单元编码位置之前。具体的，目标长度为Zs，则置零单元的数量为2Zc个。置零单元为系统比特中固定的前2Zc个软比特形成的数据单元。
填充单元为对填充比特(3)进行划分形成的单元。填充比特(3)可以从本地存储中获取，还可以从HARQ存储器中读取。填充比特(3)通常为发送端和接收端预先规定的软比特。同时填充比特(3)位于冗余版本前打孔比特(2)、和冗余版本后打孔比特(5)之间，以及位于解交织 前数据(4)中间，由此形成的填充单元的单元编码位置位于第一数据单元的单元编码位置之间。具体的，填充比特(3)在编码数据中的起始位置为K′-2Zc，结束位置为K-2Zc，相应的填充单元的单元编码位置位于K′-2Zc和K-2Zc之间。
存在满足重复速率匹配条件的第一数据单元，表明E≥N cb-(K-K′)。编码数据中存在冗余版本前打孔比特(2)，表明首个第一数据单元的单元编码位置为0。冗余版本前打孔比特(2)可以从HARQ存储器中读取。冗余版本前单元为对冗余版本前打孔比特(2)进行划分形成的单元。冗余版本前打孔比特(2)在编码数据中的起始位置为0，结束位置为k 0，相应的冗余版本前单元的单元编码位置位于0和k 0之间。同时，冗余版本前打孔比特(2)在解交织前数据(4)各个软比特在编码数据的位置之前，相应的冗余版本前单元的单元编码位置在解交织前数据(4)形成的第一数据单元的单元编码位置之前。
编码数据中存在冗余版本后打孔比特，表明E+k 0≥N cb。冗余版本后打孔比特(5)可以从HARQ存储器中读取。冗余版本后单元为对冗余版本后打孔比特(5)进行划分形成的单元。冗余版本后打孔比特(5)在编码数据中的起始位置为k 1，结束位置为N r，相应的冗余版本后单元的单元编码位置位于k 1和N r之间。同时，冗余版本后打孔比特(5)在解交织前数据(4)各个软比特在编码数据的位置之后，相应的冗余版本后单元的单元编码位置在解交织前数据(4)形成的第一数据单元的单元编码位置之后。
通过配置多个第二数据单元，并按照不同的打孔方式进行恢复，得到第二数据单元，保证恢复的打孔数据的准确性，同时，恢复的打孔数据按照单元形式替换逐个软比特进行恢复，提高解速率匹配的速度。
此外，HARQ存储器中可以直接按照冗余版本前单元存储冗余版本前打孔比特，从而直接从HARQ存储器中读取冗余版本前单元。HARQ存 储器中可以直接按照冗余版本后单元存储冗余版本后打孔比特，从而直接从HARQ存储器中读取冗余版本后单元。
在一个示例中，可以通过如图4所示的模块实现各个单元的处理过程。
解码块级联模块完成解码块分割，每个时钟周期输出解交织矩阵同一列的Q m个软比特。解码块级联模块从解交织矩阵中按列并行输出到Q m路串并转换模块中。
每个串并转换模块，设置为接收解码块分割的数据，实现Q m路并行处理，每一路独立完成Zs个软比特的收集，形成第三数据单元，并发送给解交织仲裁模块进行处理。
解交织仲裁模块，设置为从Qm路串并转换完成后的第三数据单元中选择一个，串行送给解速率匹配模块进行处理。
解速率匹配模块，设置为对解交织仲裁模块送进来的第一数据单元(包括Zs个软比特)完成HARQ合并处理，并完成解速率匹配(打孔速率匹配)。
HARQ存储器负责为解速率匹配模块提供待合并单元，译码器用于译码，其中，译码器为LDPC译码器。具体的，LDPC译码器和HARQ存储器中各软比特的存储格式如图5所示。若Zc＝208，Zs＝13，即每个单元(Bank)依次存储13个软比特，每个Bank高11个软比特位置保留。
实际上，从交织矩阵中，针对每一行，收集到若干个(即Zs个)数据才开始进行处理，不同行收集到的数据，在处理上是串行处理，可以避免读写重读。
其中，Zs并不是随意设置的。实际上译码器是以Zc个数据的处理块为单位进行处理的，如果Zc不能被Zs整除，这会导致Zs个数据属于不同的处理块，大大增加了数据处理的复杂度。由此，可以配置Zs可以整除Zc，保证Zs个数据不会跨2个处理块，减少数据处理的复杂度。
具体的，可以为每个单元配置单元标识，以及为单元中的软比特配置比特标识，通过单元标识和比特标识确定各软比特。也即单元中的各软比特可以通过查询哪个单元，再确定单元之后在单元中查询是哪个软比特确定。
可以配置，每个Zc长度的单元包括(2 m)个Zs长度的单元，根据Zs长度的单元编号Zs_i，直接得到对应Zc长度的单元中的地址Zs_i>>m，以及属于Zc长度的单元中的哪个Zs长度的单元：Zs_i％(2 m)；从而，每个Zs长度的单元的寻址变得非常简单。例如，Zs为16，则Zc/Zs＝24，则需要计算Zs_i/24和Zs_i％24，这样计算都比较简单，从而简化了寻址操作。
首先，计算目标长度Zs＝a×2 m，且Zs≤A较优的，A取24。
其次，计算解交织前数据的起始位置相关参数，即解交织矩阵中各行第一列中的软比特位于哪一个单元，以及在该单元中第几个软比特。
具体的，设定解交织矩阵中每一行软比特在循环缓存中的位置为ks[i]，则：
ks_nZs[i]＝floor(ks[i]/Zs)
ks_oZs[i]＝ks[i]％Zs
其中i＝0,1,...Qm-1。
相应的，本次传输冗余版本的结束位置k 0属于的单元：
k1 nZs[i]＝floor(k1/Zs)
再次，计算填充比特相对位置K′、K以及有限循环缓存速率匹配N cb处的软比特属于的单元以及单元中的第几个软比特：
Kp_nZs[i]＝floor((K′-2Zc)/Zs)
Kp_oZs[i]＝K′％Zs
K_nZs[i]＝floor((K-2Zc)/Zs)
K_oZs[i]＝K％Zs
Ncb_nZs[i]＝floor(Ncb/Zs)
Ncb_oZs[i]＝Ncb％Zs
最后，计算实际使用的循环缓存大小Nr属于哪一个单元：
Nr_nZs[i]＝floor(Nr/Zs)
(1)解交织过程：
前级解调模块，因为每层的一个星座点解调对应Q m个软比特，第i个软比特对应解交织矩阵第i行，i取0,1,...Q m-1。每个循环的解调模块可能同时输出nL层软比特，nL取值1,2,3或4。解扰模块将nL层串行处理，每个时钟周期依次输出1层的软比特。
Qm个串并转换模块并行工作，每个串并转换模块处理第i路软比特，每一路每个时钟周期最多接收1个软比特，i取0,1,...Q m-1；
串并转换的目的是根据地址a以及偏移地址，收集Zs个软比特形成一个单元，作为后续解速率匹配，以及HARQ处理的处理单位。第i个Zs长度的单元中的软比特为：
Zs×a+m，m＝0,1,...Zs-1。
Qm个串并转换模块独立工作，具体处理为：
CB数据到来前，完成Q m个串并转换模块的初始化处理；
每个单元包括地址a和偏移o个计数器，其中，地址a为单元编码位置。
初始化具体是：
a＝ks_nZs[i]
o＝ks_oZs[i]
串并转换模块关联的存储清零；
初始化完成后，循环等待软比特，直至每个串并转换模块都收集并处理完E/Qm个软比特后，结束该CB的解交织处理。
前级模块每送过来1个软比特，将该软比特存入该单元第o个位置，并更新单元的地址a和偏移o，o初始值为0，依次进行处理如下：
ar＝a；
o＝o+1；
flag＝1。
如果o等于Zs，表明说明一个单元收集结束，则将该收集完的Zs个软比特作为一个第三数据单元以及地址ar作为单元编码位置送给解交织仲裁模块，之后串并转换模块相关存储清零，flag置0；同时，o置0，以及a＝a+1。
如果o等于Kp_oZs[0]，并且a等于Kp_nZs[0]，表明当前软比特在编码数据中的下一个软比特在填充比特起始位置，需要跳过，也即接收到的下一软比特为在填充比特结束位置之后的软比特。如果flag等于1，将串并转换模块存储的软比特作为一个第三数据单元以及地址ar作为单元编码位置送给解交织仲裁模块，之后串并转换模块相关存储清零，flag置0；同时，o置K_oZs，并a＝K_nZs。
如果o等于Kp_oZs[0]，并且a等于Kp_nZs[0]，表明当前软比特在编码数据中的下一个软比特在填充比特起始位置，即图3中的K′-2Zc对应的位置处，需要跳过，也即接收到的下一软比特为在填充比特结束位置之后的软比特。如果flag等于1，将串并转换模块存储的软比特作为一个第三数据单元以及地址ar作为单元编码位置送给解交织仲裁模块，之后串并转换模块相关存储清零，flag置0；同时，o置K_oZs，并a＝K_nZs，即图3中的K-2Zc对应的位置处。
如果o等于Ncb_oZs，并且a等于Ncb_nZs，表明当前软比特在循环 缓存的结束位置，即图3中的Ncb对应的位置处，需要循环到0位置。如果flag等于1，将串并转换模块存储的软比特作为一个第三数据单元以及地址ar作为单元编码位置送给解交织仲裁模块，之后串并转换模块相关存储清零，flag置0；同时，o置0，且a也置0。
(2)解交织仲裁：
解交织仲裁模块根据Q m路串并转换模块的写入情况，记录需要处理的一路或多路的编号。然后，每P个时钟周期(P>0)，按轮询机制依次从多路数据选取1路第三数据单元以及单元编码位置ar送给解速率匹配模块进行处理，并且选出来的路数编号从待处理任务中清除。
较优的，Q为4，P取2；具体时序见图6。判断串行处理的连续相邻2个处理的第三数据单元是否是同一个地址ar，如果地址相同，则为重复速率匹配，则后一个第三数据单元不从HARQ存储器中读取待合并单元，直接使用前一个第三数据单元合并后的结果，即形成的第一数据单元继续合并。如果地址不同，则后一个第三数据单元从HARQ读取数据即可。这样，重复速率匹配为只需要判断前后2个处理的第三数据单元是否为重复，大大简化了重复速率匹配的判断和处理。
在一个例子中，K′＝8384，Zc＝384，N cb＝11904，相应的，LDPC编码形成的编码数据包括8448*3+2*384个软比特，其中，前2Zc＝768个软比特作为被打孔数据打掉，中间第8384-8447个软比特均为填充软比特，作为被打孔数据打掉，被打掉后的软比特进行重新编号，前0-767个软比特被打掉，从768个软比特开始重新确定软比特编码位置为0，此时，打掉数据后的数据为0-9567，其中，填充比特为7616-7679，其余软比特为0-7615，以及7680-9567。经过速率匹配，打掉填充比特，并对其余软比特进行4次重复，形成速率匹配后的数据，如图7所示，速率匹配后的数据总共4*11840个比特，也即实际发送的比特的数量为4*11840。对速率匹配后的数据进行交织，即按行写入，按列读出。如图8所示，交织矩阵 为4行(与循环数量相同)，共11840列。如图9所示，交织矩阵为4行(与循环数量相同)，共11839列。
对于图8来说，交织矩阵中各行均为0-7615(填充竖线的区域)、7680-11903(填充斜线的区域)，也即交织矩阵的不同行，相同列的软比特存储的位置相同。对于图9来说，交织矩阵的各行分别为：0-7615(填充竖线的区域)、7680-11902(填充斜线的区域)；11903(填充斜线的区域)、0-7615(填充竖线的区域)、7680-11901(填充斜线的区域)；11902-11903(填充斜线的区域)、0-7615(填充竖线的区域)、7680-11900(填充斜线的区域)；11901-11903(填充斜线的区域)、0-7615(填充竖线的区域)、7680-11899(填充斜线的区域)，也即交织矩阵的不同行，且不同列的软比特存储的位置相同。在现有技术中，在进行重复解速率匹配时，需要逐行判断，但遇到图9的情况，还需要根据列偏移情况逐行查询存储到相同位置的软比特。
而本申请实施例在1个时钟周期内并行接收各行软比特，并串行处理，也即将不同行分别得到的数据单元进行串行处理之后，最多只需要判断处理过程中相邻2个Zs长度的单元的单元编码位置是否相同，如果相同，则直接在前一个Zs长度的单元对应的合并结果上，再合并入后一个Zs长度的单元即可，无需再次从待合并集合中查询和读取相应的待合并单元，节省了从待合并集合中查询和读取的时间和处理数据量。
如图8所示的交织矩阵，输出的软比特分别为0,0,0,0,1,1,1,1,2,2,2,2…，此时串行处理过程中，连续4次处理对应的都是单元编码位置为0的数据单元。从而，不需要考虑逐行判断，仅通过处理过程中相邻的两个数据单元即可，大大降低了解速率匹配的复杂度。
针对其余情况，如图9所示的交织矩阵，输出的软比特分别为0,11903,11902,11901,1,0,11903,11902…数据单元是间隔5个，重复一次，因为后一个数据单元在处理时，前一个数据单元的数据已经写入HARQ， 则后一个数据单元直接从HARQ中读取相应数据即可，自然而然完成重复速率匹配合并处理。也无需进行重复速率匹配的判断，提高解速率匹配的效率。
(3)解速率匹配和HARQ合并
每个CB新传时，在初始化处理时，需要将CB对应的HARQ存储器中存储的待合并单元全部清零，可以直接将相关地址写0，或者使用标志位标识，或者其他任意等价方法实现缓存CB对应的待合并单元。
解速率匹配实际是根据解交织仲裁模块的地址ar，从HARQ存储器中读取ar对应的Zs个软比特，即待合并单元。将第三数据单元和待合并单元中形成的2组Zs个软比特一一对应各自并行完成合并，需要Zs个HARQ合并模块并行处理。合并完成后，Zs个合并后的结果，即第一数据单元将写入LDPC译码器地址为2+(ar/2 m)的单元位置处，并将第一数据单元的软比特按照顺序依次写入该单元位置中地址为ar％2 m的位置处。实际上，在译码器存储时，是按照单元进行存储，也即，将第一数据单元写入匹配的单元位置处，该单元位置的寻址实现上就是移位选择器，实现简单。同时将第一数据单元写回ar对应的HARQ存储器中，并覆盖对应的待合并单元。
此外，在解速率匹配处理第三数据单元的同时，同样以单元为单位，依次完成如下解打孔处理：
3.1)系统比特前2Zc个比特固定打孔，不管是否重复速率匹配，LDPC地址为0～2 m+1-1的所有单元都需要写入0，形成置零单元。
3.2)如果K′＝＝K，该步骤跳过，否则需要进行如下处理：
获取填充比特生成填充单元，填充单元对应的单元编码位置ap实际是在编码数据中地址区间Kp_nZs～Kp_nZs-1中取值，并依次写入LDPC译码器地址为2+(ap/2 m)的单元位置处，将填充单元的软比特按照顺序依次写入该单元位置中地址为ap％2 m的位置处。其中，每个软比特的写入值为能表示的正的最大值。
3.3)如果存在重复速率匹配，即E≥N cb-(K-K′)，或者ks_nZs[0]且 ks_oZs[0]均等于0，则该步骤跳过；否则进行如下处理：
从HARQ存储器中获取与单元编码位置ap匹配的冗余版本前打孔比特生成冗余版本前单元。冗余版本前单元的单元编码位置ap实际是在编码数据中地址区间0～k_nZs[0]-1中取值，并依次写入LDPC译码器地址为2+(ap/2 m)的单元位置处，将单元中软比特按照顺序依次写入该单元位置中地址为ap％2 m的位置处。
3.4)如果存在重复速率匹配，即E≥N cb-(K-K′)，或者E+k 0≥N cb，则该步骤跳过；否则进行如下处理：
从HARQ存储器中获取与单元编码位置ap匹配的冗余版本后打孔比特生成冗余版本后单元。冗余版本后单元的单元编码位置ap实际是在编码数据中地址区间k1_nZs～Nr_nZs中取值，并依次写入LDPC译码器地址为2+(ap/2 m)的单元位置处，将单元中软比特按照顺序依次写入该单元位置中地址为ap％2 m的位置处。
从而实现将第一数据单元和第二数据单元按照在编码数据中的位置关系，进行存储，排列拼接成待译码数据，以使译码器进行译码，得到译码数据。
具体的，时序可以参考图6，一个矩形为一个时钟周期，此时，Q为4个时钟周期，P为两个时钟周期。每间隔两个时钟周期，解交织仲裁模块选择一个第三数据单元输入到解速率匹配模块中进行处理。在图6显示的时长中，解交织仲裁模块一共将选择了7个第三数据单元串行输入到解速率匹配模块中进行依次处理。具体的，在第一个P的周期内，在HARQ存储器中，根据第0个第三数据单元启动待合并单元查询；在第二个P的周期内，获取第0个第三数据单元匹配的待合并单元；在第三个P的周期内，对第0个第三数据单元进行软合并，同时根据第1个第三数据单元启动待合并单元查询；在第四个P的周期内，将第0个第三数据单元软合并形成的第一数据单元写回HARQ存储器中和/或写入译码器中，同时，获取第1个第三数据单元匹配的待合并单元。以此类推。此外，第二数据单 元可以在任何P的周期内生成并存储在译码器中。
图10为本申请实施例提供的一种译码装置的示意图。本实施例是实现本申请上述任意实施例提供的译码方法的相应装置，该装置可以设置于网络设备中。
解交织前数据接收模块310，设置为接收解交织前数据和软比特编码位置；
第一数据单元生成模块320，设置为划分所述解交织前数据，得到第一数据单元；
第二数据单元生成模块330，设置为获取被打孔数据，并根据所述被打孔数据，得到第二数据单元，所述解交织前数据和所述被打孔数据根据所述软比特编码位置在编码数据中确定；
译码数据确定模块340，设置为根据所述软比特编码位置、所述第一数据单元和所述第二数据单元进行译码，得到译码数据。
本申请实施例所提供的译码方法、装置、网络设备及存储介质，通过对解交织前数据中的软比特进行划分，形成多个第一数据单元，同时获取被打孔数据，并进行软比特划分，生成多个第二数据单元，并按照软比特编码位置、第一数据单元和第二数据单元形成待译码数据并进行译码，从而实现将多个软比特形成单元进行处理，解决了现有技术中解速率匹配过程中需要按照逐个软比特进行处理导致解速率匹配的效率低的问题，可以减少解速率匹配和译码过程中逐个软比特单独寻址的情况，可以提高解速率匹配和译码效率。
在一种实施方式中，所述译码数据确定模块340，还设置为：根据所述软比特编码位置以及各所述第一数据单元中首个软比特，确定各所述第一数据单元的单元编码位置；根据所述软比特编码位置以及各所述第二数据单元中首个软比特，确定各所述第二数据单元的单元编码位置；根据各 所述单元编码位置分别将所述第一数据单元和所述第二数据单元存储在译码器中匹配的存储地址处，以排列所述第一数据单元和所述第二数据单元，形成待译码数据，以使所述译码器对所述待译码数据进行译码。
在一种实施方式中，所述第一数据单元和所述第二数据单元的单元长度均为目标长度，所述目标长度根据提升因子确定。
在一种实施方式中，所述目标长度为提升因子与2的设定值次方的比值，所述第一数量小于等于设定数量阈值，所述设定数量阈值根据工作频率和可用资源确定。
在一种实施方式中，所述第一数据单元生成模块320，还设置为：多路并行接收解交织矩阵按列输出的软比特；顺序存储每路接收到的软比特，生成多个第三数据单元；按照设定周期数量的时钟周期，依次对各所述第三数据单元进行软合并，形成多个第一数据单元。
在一种实施方式中，所述第一数据单元生成模块320，还设置为：如果接收到的目标软比特满足填充比特起始相邻条件，则以所述目标软比特为接收到的最后一个软比特生成当前第三数据单元，并继续接收下一个软比特，以生成下一第三数据单元。
在一种实施方式中，所述第一数据单元生成模块320，还设置为：根据所述第三数据单元对应的单元编码位置，在待合并集合中查询与所述第三数据单元匹配的待合并单元，并进行合并，得到第一数据单元；根据所述第一数据单元，在所述待合并集合中更新所述匹配的待合并单元，所述待合并单元的单元长度为所述目标长度，所述待合并单元用于存储历史合并数据，所述历史合并数据用于与所述第三数据单元中软比特进行合并，以更新所述第三数据单元中软比特。
在一种实施方式中，所述设定周期数量与目标周期数量相同，或者根据目标周期数量的二分之一确定，所述设定周期数量为整数，所述目标周期数量包括从开始对所述第三数据单元进行软合并到生成第一数据单元 所需时长对应的时钟周期数量。
在一种实施方式中，所述设定周期数量根据目标周期数量的二分之一确定，所述设定周期数量为整数；所述第一数据单元生成模块320，还设置为：如果根据当前处理的第三数据单元对应的单元编码位置和前一第三数据单元对应的单元编码位置，确定由所述当前处理的第三数据单元得到的第一数据单元满足重复速率匹配条件，则根据所述前一第三数据单元对应的待合并单元，确定所述当前处理的第三数据单元匹配的待合并单元。
在一种实施方式中，所述第二数据单元生成模块330，还设置为：生成多个置零单元，所述置零单元包括的各软比特为0，所述置零单元的单元长度为目标长度，各所述置零单元总共包括的软比特的数量为提升因子与2的乘积，各所述置零单元对应的单元编码位置前于各所述第一数据单元对应的单元编码位置；如果所述编码数据中存在填充比特，则获取填充比特，并生成填充单元，所述填充单元的单元长度为目标长度；如果存在满足重复速率匹配条件的第一数据单元或者所述编码数据中存在冗余版本前打孔比特，则获取冗余版本前比特，并生成冗余版本前单元，所述冗余版本前单元的单元长度为目标长度，各所述冗余版本前单元分别对应的单元编码位置均前于各所述第一数据单元对应的单元编码位置；如果存在满足重复速率匹配条件的第一数据单元或者所述编码数据中存在冗余版本后打孔比特，则获取冗余版本后比特，并生成冗余版本后单元，所述冗余版本后单元的单元长度为目标长度，各所述冗余版本后单元分别对应的单元编码位置均后于各所述第一数据单元对应的单元编码位置。
上述译码装置可执行本申请实施例所提供的译码方法，具备执行的译码方法相应的功能模块和有益效果。
本申请提供一种网络设备，所述网络设备包括处理器以及存储器；所述处理器设置为执行存储器中存储的程序，以实现上述实施例中的方法。 其中，网络设备为设备供电的电源设备。
存储器作为一种计算机可读存储介质，可设置为存储软件程序、计算机可执行程序以及模块，如本申请实施例中的译码方法对应的程序指令/模块。
存储器可主要包括存储程序区和存储数据区，其中，存储程序区可存储操作系统、至少一个功能所需的应用程序；存储数据区可存储根据终端的使用所创建的数据等。此外，存储器可以包括高速随机存取存储器，还可以包括非易失性存储器，例如至少一个磁盘存储器件、闪存器件、或其他非易失性固态存储器件。在一些实例中，存储器可进一步包括相对于处理器远程设置的存储器，这些远程存储器可以通过网络连接至设备。上述网络的实例包括但不限于互联网、企业内部网、局域网、移动通信网及其组合。
本申请提供一种存储介质，所述存储介质存储有计算机程序，所述计算机程序被处理器执行时实现上述实施例中的方法。
本发明实施例的计算机存储介质，可以采用一个或多个计算机可读的介质的任意组合。计算机可读介质可以是计算机可读信号介质或者计算机可读存储介质。计算机可读存储介质例如可以是——但不限于——电、磁、光、电磁、红外线、或半导体的系统、装置或器件，或者任意以上的组合。计算机可读存储介质的更具体的例子(非穷举的列表)包括：具有一个或多个导线的电连接、便携式计算机磁盘、硬盘、RAM、只读存储器(Read Only Memory，ROM)、可擦式可编程只读存储器(Erasable Programmable Read Only Memory，EPROM)、闪存、光纤、便携式CD-ROM、光存储器件、磁存储器件、或者上述的任意合适的组合。在本文件中，计算机可读存储介质可以是任何包含或存储程序的有形介质，该程序可以被指令执行系统、装置或者器件使用或者与其结合使用。
计算机可读的信号介质可以包括在基带中或者作为载波一部分传播的数据信号，其中承载了计算机可读的程序代码。这种传播的数据信号可以采用多种形式，包括——但不限于——电磁信号、光信号或上述的任意合适的组合。计算机可读的信号介质还可以是计算机可读存储介质以外的任何计算机可读介质，该计算机可读介质可以发送、传播或者传输用于由指令执行系统、装置或者器件使用或者与其结合使用的程序。
计算机可读介质上包含的程序代码可以用任何适当的介质传输，包括——但不限于——无线、电线、光缆、无线电频率(RadioFrequency，RF)等等，或者上述的任意合适的组合。
可以以一种或多种程序设计语言或其组合来编写用于执行本发明操作的计算机程序代码，所述程序设计语言包括面向对象的程序设计语言—诸如Java、Smalltalk、C++，还包括常规的过程式程序设计语言—诸如“C”语言或类似的程序设计语言。程序代码可以完全地在用户计算机上执行、部分地在用户计算机上执行、作为一个独立的软件包执行、部分在用户计算机上部分在远程计算机上执行、或者完全在远程计算机或服务器上执行。在涉及远程计算机的情形中，远程计算机可以通过任意种类的网络——包括LAN或WAN——连接到用户计算机，或者，可以连接到外部计算机(例如利用因特网服务提供商来通过因特网连接)。
以上所述，仅为本申请的示例性实施例而已，并非用于限定本申请的保护范围。
本领域内的技术人员应明白，术语用户终端涵盖任何适合类型的无线用户设备，例如移动电话、便携数据处理装置、便携网络浏览器或车载移动台。
一般来说，本申请的多种实施例可以在硬件或专用电路、软件、逻辑或其任何组合中实现。例如，一些方面可以被实现在硬件中，而其它方面 可以被实现在可以被控制器、微处理器或其它计算装置执行的固件或软件中，尽管本申请不限于此。
本申请的实施例可以通过移动装置的数据处理器执行计算机程序指令来实现，例如在处理器实体中，或者通过硬件，或者通过软件和硬件的组合。计算机程序指令可以是汇编指令、指令集架构(ISA)指令、机器指令、机器相关指令、微代码、固件指令、状态设置数据、或者以一种或多种编程语言的任意组合编写的源代码或目标代码。
本申请附图中的任何逻辑流程的框图可以表示程序步骤，或者可以表示相互连接的逻辑电路、模块和功能，或者可以表示程序步骤与逻辑电路、模块和功能的组合。计算机程序可以存储在存储器上。存储器可以具有任何适合于本地技术环境的类型并且可以使用任何适合的数据存储技术实现，例如但不限于只读存储器(ROM)、随机访问存储器(RAM)、光存储器装置和系统(数码多功能光碟DVD或CD光盘)等。计算机可读介质可以包括非瞬时性存储介质。数据处理器可以是任何适合于本地技术环境的类型，例如但不限于通用计算机、专用计算机、微处理器、数字信号处理器(DSP)、专用集成电路(ASIC)、可编程逻辑器件(FGPA)以及基于多核处理器架构的处理器。
通过示范性和非限制性的示例，上文已提供了对本申请的示范实施例的详细描述。但结合附图和权利要求来考虑，对以上实施例的多种修改和调整对本领域技术人员来说是显而易见的，但不偏离本发明的范围。因此，本发明的恰当范围将根据权利要求确定。

Claims (13)

  1. 一种译码方法，包括：
    接收解交织前数据和软比特编码位置；
    划分所述解交织前数据，得到第一数据单元；
    获取被打孔数据，并根据所述被打孔数据，得到第二数据单元，所述解交织前数据和所述被打孔数据根据所述软比特编码位置在编码数据中确定；
    根据所述软比特编码位置、所述第一数据单元和所述第二数据单元进行译码，得到译码数据。
  2. 根据权利要求1所述的方法，其中，所述根据所述软比特编码位置、所述第一数据单元和所述第二数据单元进行译码，包括：
    根据所述软比特编码位置以及各所述第一数据单元中首个软比特，确定各所述第一数据单元的单元编码位置；
    根据所述软比特编码位置以及各所述第二数据单元中首个软比特，确定各所述第二数据单元的单元编码位置；
    根据各所述单元编码位置分别将所述第一数据单元和所述第二数据单元存储在译码器中匹配的存储地址处，以排列所述第一数据单元和所述第二数据单元，形成待译码数据；
    通过所述译码器对所述待译码数据进行译码。
  3. 根据权利要求1所述的方法，其中，所述第一数据单元和所述第二数据单元的单元长度均为目标长度，所述目标长度根据提升因子确定。
  4. 根据权利要求3所述的方法，其中，所述目标长度为提升因子与2的设定值次方的比值，所述第一数量小于等于设定数量阈值，所述设定数量阈值根据工作频率和可用资源确定。
  5. 根据权利要求2所述的方法，其中，所述接收解交织前数据，并划分所述解交织前数据，得到第一数据单元，包括：
    多路并行接收交织矩阵按列输出的软比特；
    顺序存储每路接收到的软比特，生成多个第三数据单元；
    按照设定周期数量的时钟周期，依次对各所述第三数据单元进行软合并，形成多个第一数据单元。
  6. 根据权利要求5所述的方法，其中，所述顺序存储每路接收到的软比特，生成多个第三数据单元，包括：
    如果接收到的目标软比特满足填充比特起始相邻条件，则以所述目标软比特为接收到的最后一个软比特生成当前第三数据单元，并继续接收下一个软比特，以生成下一第三数据单元。
  7. 根据权利要求5所述的方法，其中，所述对所述第三数据单元进行软合并，形成第一数据单元，包括：
    根据所述第三数据单元对应的单元编码位置，在待合并集合中查询与所述第三数据单元匹配的待合并单元，并进行合并，得到第一数据单元；
    根据所述第一数据单元，在所述待合并集合中更新所述匹配的待合并单元，所述待合并单元的单元长度为目标长度，所述待合并单元用于存储历史合并数据，所述历史合并数据用于与所述第三数据单元中软比特进行合并，以更新所述第三数据单元中软比特。
  8. 根据权利要求5所述的方法，其中，所述设定周期数量与目标周期数量相同，或者根据目标周期数量的二分之一确定，所述设定周期数量为整数，所述目标周期数量包括从开始对所述第三数据单元进行软合并到生成第一数据单元所需时长对应的时钟周期数量。
  9. 根据权利要求8所述的方法，其中，所述设定周期数量根据目标周期数量的二分之一确定，所述设定周期数量为整数；
    所述对所述第三数据单元进行软合并，形成第一数据单元，包括：
    如果根据当前处理的第三数据单元对应的单元编码位置和前一第三数据单元对应的单元编码位置，确定由所述当前处理的第三数据单元得到 的第一数据单元满足重复速率匹配条件，则根据所述前一第三数据单元对应的待合并单元，确定所述当前处理的第三数据单元匹配的待合并单元。
  10. 根据权利要求2所述的方法，其中，所述获取被打孔数据，并根据所述被打孔数据，生成第二数据单元，包括：
    生成多个置零单元，所述置零单元包括的各软比特为0，所述置零单元的单元长度为目标长度，各所述置零单元总共包括的软比特的数量为提升因子与2的乘积，各所述置零单元对应的单元编码位置前于各所述第一数据单元对应的单元编码位置；
    如果所述编码数据中存在填充比特，则获取填充比特，并生成填充单元，所述填充单元的单元长度为目标长度；
    如果存在满足重复速率匹配条件的第一数据单元或者所述编码数据中存在冗余版本前打孔比特，则获取冗余版本前比特，并生成冗余版本前单元，所述冗余版本前单元的单元长度为目标长度，各所述冗余版本前单元分别对应的单元编码位置均前于各所述第一数据单元对应的单元编码位置；
    如果存在满足重复速率匹配条件的第一数据单元或者所述编码数据中存在冗余版本后打孔比特，则获取冗余版本后比特，并生成冗余版本后单元，所述冗余版本后单元的单元长度为目标长度，各所述冗余版本后单元分别对应的单元编码位置均后于各所述第一数据单元对应的单元编码位置。
  11. 一种译码装置，包括：
    解交织前数据接收模块，设置为接收解交织前数据和软比特编码位置；
    第一数据单元生成模块，设置为划分所述解交织前数据，得到第一数据单元；
    第二数据单元生成模块，设置为获取被打孔数据，并根据所述被打孔数据，得到第二数据单元，所述解交织前数据和所述被打孔数据根据所述 软比特编码位置在编码数据中确定；
    译码数据确定模块，设置为根据所述软比特编码位置、所述第一数据单元和所述第二数据单元进行译码，得到译码数据。
  12. 一种网络设备，所述网络设备包括至少一个处理器以及存储器；
    所述处理器设置为执行存储器中存储的程序，以实现权利要求1-10任一项所述的方法。
  13. 一种存储介质，所述存储介质存储有计算机程序，所述计算机程序被处理器执行时实现权利要求1-10任一项所述的方法。
PCT/CN2020/140278 2019-12-26 2020-12-28 译码方法、装置、网络设备及存储介质 WO2021129877A1 (zh)

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