WO2021129726A1 - 微型发光二极管外延片、显示阵列及其制作方法 - Google Patents

微型发光二极管外延片、显示阵列及其制作方法 Download PDF

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Publication number
WO2021129726A1
WO2021129726A1 PCT/CN2020/138951 CN2020138951W WO2021129726A1 WO 2021129726 A1 WO2021129726 A1 WO 2021129726A1 CN 2020138951 W CN2020138951 W CN 2020138951W WO 2021129726 A1 WO2021129726 A1 WO 2021129726A1
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layer
emitting diode
substrate
insulating layer
driving circuit
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PCT/CN2020/138951
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English (en)
French (fr)
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兰叶
吴志浩
李鹏
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华灿光电(苏州）有限公司
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Publication of WO2021129726A1 publication Critical patent/WO2021129726A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0095—Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate

Definitions

  • the present disclosure relates to the field of semiconductor technology, in particular to a miniature light-emitting diode epitaxial wafer, a display array and a manufacturing method thereof.
  • Micro LED (English: Micro LED) refers to ultra-small light-emitting diodes with a side length of 10 micrometers to 100 micrometers. They are small in size and can be arranged more densely to greatly increase the resolution of the display. Micro LEDs have self-luminous characteristics. , Micro LED displays have good performance in terms of high brightness, high contrast, fast response and power saving, and are likely to further occupy the small-pitch display market in the future.
  • a Micro LED display array includes a circuit board and a plurality of Micro LED chips.
  • the circuit board includes a substrate and a driving circuit layer and an insulating layer sequentially stacked on the substrate, and the plurality of Micro LED chips are arranged on the insulating layer at intervals.
  • the material of the insulating layer is silicon dioxide, and the insulating layer is provided with through holes connecting the Micro LED chip and the corresponding driving circuit in the driving circuit layer.
  • the embodiments of the present disclosure provide a miniature light-emitting diode epitaxial wafer, a display array, and a manufacturing method thereof, which can effectively dissipate the heat generated by the Micro LED chip, and promote the popularization and stable use of the Micro LED on small-pitch displays.
  • the technical solution is as follows:
  • embodiments of the present disclosure provide a manufacturing method of a micro light-emitting diode display array, and the manufacturing method includes:
  • a circuit board is provided, the circuit board includes a substrate and a driving circuit layer on the substrate; an insulating layer is formed on the driving circuit layer, and the insulating layer is formed of a liquid insulating material mixed with diamond particles; A plurality of through holes extending to the driving circuit layer are opened in the insulating layer, and conductive material is filled in the plurality of through holes; a plurality of micro light emitting diode chips are arranged on the insulating layer, so that the micro light emitting diode The chip is connected with the corresponding driving circuit in the driving circuit layer through the conductive material in the corresponding through hole.
  • the driving circuit layer has a solder layer on a surface away from the substrate; the forming an insulating layer on the driving circuit layer includes: coating the driving circuit layer with liquid insulation mixed with diamond particles Material; curing the liquid insulating material at a first set temperature to form a pre-cured layer; heating the pre-cured layer and applying pressure on the pre-cured layer toward the drive circuit layer until the pre-cured A part of the diamond particles located on the solder layer in the layer is embedded in the solder layer; the pre-cured layer is cured at a second set temperature, the second set temperature is higher than the first set temperature .
  • the manufacturing method further includes: etching the insulating layer until a part of the diamond particles is close to the micro light emitting diode chip from the insulating layer Exposed from the surface.
  • the liquid insulating material is spin-coated glass SOG.
  • the arranging a plurality of miniature light emitting diode chips on the insulating layer includes: arranging a plurality of semiconductor devices on the insulating layer and pressing and heating the plurality of semiconductor devices to heat the plurality of semiconductor devices.
  • a semiconductor device is bonded to the circuit board, and each of the semiconductor devices includes a P-type electrode, a hole generating layer, an active layer, an electron generating layer, and a first buffer layer sequentially stacked on the insulating layer
  • the substrate, the P-type electrodes in the plurality of semiconductor devices are respectively connected to the corresponding drive circuit through the conductive material in the corresponding through holes; the substrate and the buffer layer in the plurality of semiconductor devices are removed; N-type electrodes are formed on the electron generation layers of the plurality of semiconductor devices to form a plurality of miniature light-emitting diode chips.
  • the surface of the P-type electrode opposite to the insulating layer is a solder layer; and the pressure and heating of the plurality of semiconductor devices are used to bond the plurality of semiconductor devices to the circuit board.
  • it includes: applying pressure toward the insulating layer on the plurality of semiconductor devices under heating until the diamond particles are embedded in the solder layer of the P-type electrode.
  • the substrate is a transparent substrate
  • the removing the substrates in the plurality of semiconductor devices includes: removing the substrates in the plurality of semiconductor devices by means of laser lift-off.
  • the semiconductor device further includes a laser consuming layer located between the substrate and the first buffer layer, and the laser consuming layer is formed by alternately stacking a plurality of polycrystalline layers and a plurality of band gap layers ,
  • the growth temperature of the plurality of polycrystalline layers increases layer by layer along the direction from the substrate to the electron generation layer, and the forbidden band width of the plurality of forbidden band layers extends from the substrate to the The direction of the electron generation layer increases layer by layer.
  • the thickness of the band gap layer is negatively correlated with a difference in band gap width
  • the difference in band gap width is the band gap width of the corresponding band gap layer and the band gap width of the quantum well in the active layer The absolute value of the difference.
  • the semiconductor device further includes a second buffer layer located between the substrate and the laser consuming layer, and the thickness of the second buffer layer is greater than the thickness of the first buffer layer.
  • the thickness of the second buffer layer is greater than 0.5 microns.
  • an embodiment of the present disclosure provides a micro light emitting diode display array, including a circuit board and a plurality of micro light emitting diode chips.
  • the circuit board includes a substrate, a driving circuit layer, and an insulating layer.
  • the insulating layer is sequentially laminated on the substrate, the insulating layer is provided with a through hole extending to the driving circuit layer, the through hole is filled with a conductive material, and the plurality of micro light emitting diode chips are arranged on the
  • the insulating layer is connected to the corresponding driving circuit in the driving circuit layer through the conductive material in the corresponding through holes of the plurality of through holes, and the insulating layer is formed of a liquid insulating material mixed with diamond particles.
  • the thickness of the portion of the insulating layer that does not contain diamond particles is smaller than the particle size of the diamond particles.
  • the driving circuit layer has a solder layer on a surface away from the substrate, and at least part of the diamond particles is embedded in the solder layer.
  • the micro light emitting diode chip includes a P-type electrode, a hole generating layer, an active layer, an electron generating layer, and an N-type electrode stacked on the insulating layer in sequence, and the P-type electrode is opposite to the insulating layer.
  • the P-type electrode is opposite to the insulating layer.
  • the liquid insulating material is spin-coated glass SOG.
  • embodiments of the present disclosure provide a miniature light-emitting diode epitaxial wafer, which includes a transparent substrate and a first buffer layer, an electron generation layer, an active layer, and a hole generation layer sequentially stacked on the transparent substrate
  • the micro light emitting diode epitaxial wafer further includes a laser consuming layer laminated between the first buffer layer and the transparent substrate, and the laser consuming layer is alternately laminated with a plurality of polycrystalline layers and a plurality of band gap layers
  • the growth temperature of the plurality of polycrystalline layers rises layer by layer along the direction from the transparent substrate to the electron generation layer, and the forbidden band width of the plurality of forbidden band layers increases from the transparent substrate.
  • the direction from the bottom to the electron generating layer increases layer by layer.
  • the thickness of the band gap layer is negatively correlated with a difference in band gap width
  • the difference in band gap width is the band gap width of the corresponding band gap layer and the band gap width of the quantum well in the active layer The absolute value of the difference.
  • the micro light emitting diode epitaxial wafer further includes a second buffer layer laminated between the transparent substrate and the laser consuming layer, and the thickness of the second buffer layer is greater than that of the first buffer layer.
  • the thickness of a buffer layer is greater than that of the first buffer layer.
  • the thickness of the second buffer layer is above 0. micrometer.
  • FIG. 1 is a flowchart of a manufacturing method of a miniature light-emitting diode display array provided by an embodiment of the present disclosure
  • FIG. 2 is a flowchart of a manufacturing method of a miniature light-emitting diode display array provided by an embodiment of the present disclosure
  • FIG. 3 is a structural schematic diagram of bonding a plurality of semiconductor devices and a circuit board together by an insulating layer provided by an embodiment of the present disclosure
  • step 204 is a schematic diagram of the structure of the display array after step 204 provided by an embodiment of the present disclosure is executed;
  • FIG. 5 is a schematic diagram of the structure of the display array after the execution of step 205 according to an embodiment of the present disclosure
  • FIG. 6 is a schematic structural diagram of a miniature light-emitting diode epitaxial wafer provided by an embodiment of the present disclosure
  • FIG. 7 is a schematic diagram of the structure of a laser consuming layer provided by an embodiment of the present disclosure.
  • FIG. 1 is a flowchart of a manufacturing method of a miniature light-emitting diode display array provided by an embodiment of the disclosure. See Figure 1, the manufacturing method includes:
  • step 101 a circuit board is provided, and the circuit board includes a substrate and a driving circuit layer on the substrate.
  • the driving circuit layer includes a plurality of driving circuits arranged in an array, and each driving circuit corresponds to a micro light emitting diode chip, and the driving circuit is used for controlling the corresponding micro light emitting diode chip to emit light.
  • each driving circuit includes at least one thin film transistor, such as a thin film metal oxide semiconductor field-effect transistor (MOSFET).
  • MOSFET thin film metal oxide semiconductor field-effect transistor
  • the embodiment of the present disclosure does not limit the hierarchical structure of the driving circuit layer, as long as a driving circuit for controlling the light emission of a plurality of micro light emitting diode chips can be formed.
  • a silicon wafer is used as the substrate to directly form a drive circuit on the substrate; or a silicon carbide wafer or a ceramic wafer is used as the substrate.
  • materials such as silicon and gallium arsenide can be made on the substrate to form the drive circuit.
  • step 102 an insulating layer is formed on the driving circuit layer, and the insulating layer is formed of a liquid insulating material mixed with diamond particles.
  • the liquid insulating material is a spin-on glass (English: spin on glass coating, SOG for short) layer.
  • the insulating layer is formed of liquid insulating material mixed with diamond particles
  • the liquid insulating material mixed with diamond particles can be coated on the drive circuit layer, and then the liquid insulating material mixed with diamond particles can be solidified to form the insulation Floor.
  • step 103 a plurality of through holes extending to the driving circuit layer are opened in the insulating layer, and a conductive material is filled in the plurality of through holes.
  • the position of the through hole in the insulating layer corresponds to the position of the pad on the driving circuit layer, and each pad is formed with a corresponding through hole, so that the pad can pass through the conductive material in the corresponding through hole and the micro light emitting diode Chip connection.
  • the conductive material is a metal material, including but not limited to copper, gold, tin, and the like.
  • a through hole is opened in the insulating layer by dry etching, and a conductive material is formed in the through hole by, for example, electroplating.
  • step 104 a plurality of micro light emitting diode chips are arranged on the insulating layer, so that the micro light emitting diode chips are connected to the corresponding driving circuit in the driving circuit layer through the conductive material in the corresponding through hole.
  • the miniature light-emitting diode chip includes a first electrode, and the first electrode is opposite to the corresponding through hole, thereby facilitating connection with the corresponding pad through the conductive material in the through hole, so as to realize the miniature light-emitting diode chip and the corresponding The connection between the drive circuits.
  • the thermal conductivity of diamond is 1300-2200W/(m*K), which is much higher than the original silicon dioxide, which can effectively conduct Micro LED
  • the heat generated by the chip, and the insulating layer is in a liquid state when formed, can form good contact with diamond particles, reduce the interface thermal resistance, realize an efficient and smooth thermal channel, greatly improve the heat dissipation efficiency, and promote the use of Micro LEDs on small-pitch displays. Promotion and stable use.
  • both diamond and liquid insulating materials are insulating materials, so there is no leakage problem.
  • the first electrode is a P-type electrode as an example for exemplification. In other embodiments, the first electrode may also be an N-type electrode.
  • FIG. 2 is a flowchart of a manufacturing method of a miniature light-emitting diode display array provided by an embodiment of the disclosure. Referring to Figure 2, the manufacturing method includes:
  • a circuit board is provided.
  • the circuit board includes a substrate and a driving circuit layer on the substrate.
  • step 202 an insulating layer is formed on the driving circuit layer.
  • the insulating layer is a spin-on glass (English: spin-on glass coating, abbreviated: SOG) layer mixed with diamond particles.
  • SOG spin-on glass coating
  • the surface of the driving circuit layer away from the substrate has a solder layer, such as a gold layer or a tin layer.
  • the solder layer is the top layer of the pad of the drive circuit for connecting with the Micro LED chip, and part of the solder layer is in contact with the insulating layer, and part is connected with the conductive material in the through hole.
  • this step 202 may include:
  • the pre-cured SOG layer is cured at a second set temperature, and the second set temperature is higher than the first set temperature.
  • the top of the pad of the drive circuit is a solder layer.
  • the hardness of the material used in the solder layer is much lower than that of diamond. Applying pressure on the diamond particles can embed the diamond particles in the solder layer, and the heat can be directly conducted to the drive circuit through the diamond particles.
  • the insulating layer made of liquid insulating material with low thermal conductivity, and make full use of diamond particles with high thermal conductivity to dissipate heat, which greatly improves the thermal conductivity.
  • the insulating layer is in a liquid state during heating, and can form good contact with the diamond particles to match the position change of the diamond particles.
  • the first set temperature may be 300°C
  • the time to solidify the SOG liquid at the first set temperature may be 30 minutes
  • the second set temperature may be 500°C
  • the SOG is cured at the second set temperature
  • the layer time can be 30 minutes.
  • the liquid insulating material is SOG as an example for description, but it is not limited to this.
  • step 203 a through hole extending to the driving circuit layer is opened on the insulating layer, and a conductive material is filled in the through hole.
  • step 103 For related content, refer to step 103, and detailed description is omitted here.
  • step 204 a plurality of semiconductor devices are arranged on the insulating layer at intervals and the plurality of semiconductor devices are pressurized and heated to bond the plurality of semiconductor devices and the circuit board together.
  • each semiconductor device includes a P-type electrode, a hole-generating layer, an active layer, an electron-generating layer, a buffer layer, and a sapphire substrate that are sequentially stacked on an insulating layer.
  • the electrodes are respectively electrically connected with the driving circuit through the conductive material in the through holes.
  • the manufacturing method may further include:
  • the insulating layer is etched until a part of the diamond particles is exposed from the surface of the insulating layer close to the micro light emitting diode chip.
  • the part of the insulating layer except the diamond particles is thinned so that the diamond particles are exposed from the surface of the insulating layer.
  • the P-type electrode of the semiconductor device and the diamond particle In contrast, the heat of the Micro LED chip formed by the semiconductor device can be directly transferred to the diamond particles and dissipated, avoiding the insulating layer with low thermal conductivity, and making full use of the diamond particles with high thermal conductivity to dissipate heat, which greatly improves the heat conduction effect.
  • the insulating layer may be etched until a part of the diamond particles are exposed from the surface of the insulating layer close to the micro light emitting diode chip.
  • the surface of the diamond particles is flush with the surface of the portion of the insulating layer formed of the liquid insulating material. In other examples, the surface of the diamond particles protrudes from the surface of the portion of the insulating layer formed of the liquid insulating material.
  • the surface of the P-type electrode opposite to the insulating layer is a solder layer, such as a gold layer or a tin layer.
  • this step 204 includes: placing a plurality of semiconductor devices on the insulating layer, and P-type electrodes on the protruding diamond particles; under heating, applying pressure toward the insulating layer on the plurality of semiconductor devices until The exposed diamond particles are embedded in the gold layer of the P-type electrode.
  • a plurality of semiconductor devices are pressurized and heated by a bonding machine.
  • the particle size of the diamond particles may be 6 microns
  • the thickness of the part formed of the liquid insulating material in the insulating layer may be 3 microns
  • the depth of the diamond particles embedded in the solder layer of the drive circuit layer may be 1 micron
  • the diamond particles may be from The height of the surface protrusion of the insulating layer may be 1/5 of the particle diameter of the diamond particles.
  • FIG. 3 is a schematic diagram of a structure in which a plurality of semiconductor devices and a circuit board are bonded together by an insulating layer provided by an embodiment of the disclosure.
  • the diamond particles 131 in the insulating layer 13 are respectively embedded in the solder layer of the driving circuit layer 12 and the P-type electrode 21, which can directly transfer the heat of the chip to the driving circuit, completely avoiding liquid insulating materials with low thermal conductivity
  • the formed insulating layer makes full use of diamond particles with high thermal conductivity to dissipate heat, greatly improving the thermal conductivity effect.
  • the P-type electrode is connected with the positive electrode of the power supply to inject current into the chip;
  • the material of the P-type electrode can be a gold-beryllium alloy.
  • the hole generating layer provides holes for recombination light emission, and the material of the hole generating layer may be AlInGaP doped with magnesium.
  • the active layer performs compound light emission of electrons and holes, and the material of the active layer may be undoped AlInGaP.
  • the electron generation layer provides electrons for composite light emission, and the material of the electron generation layer may be AlInGaP doped with silicon.
  • the buffer layer relieves the stress and defects caused by the lattice mismatch between the epitaxial layer and the substrate, and provides a nucleation center.
  • the material of the buffer layer is GaAs.
  • the sapphire substrate plays a supporting role.
  • the semiconductor device may also include a transparent conductive layer, the transparent conductive layer is arranged between the hole generating layer and the P-type electrode, on the one hand, it forms a good ohmic contact with the electrode, and on the other hand, the current injected by the electrode is controlled.
  • the material of the transparent conductive layer may be indium tin oxide (English: Indium tin oxide, ITO for short) or NiAu alloy.
  • the manufacturing method further includes:
  • a buffer layer, an electron generation layer, an active layer and a hole generation layer are sequentially formed on the growth substrate to form an epitaxial wafer;
  • the second step is to bind the hole generating layer to the glass substrate
  • the third step is to remove the growth substrate by wet etching
  • the fourth step is to bind the electron generation layer to the sapphire substrate
  • the fifth step is to remove the glass substrate.
  • the sapphire substrate is transparent, the opaque growth substrate is replaced with a transparent sapphire substrate, so that the sapphire substrate can be subsequently removed by laser lift-off.
  • the sapphire substrate can also be replaced with other transparent substrates, including but not limited to gallium phosphide substrates, silicon carbide substrates, zinc oxide substrates, glass substrates, and the like.
  • metal-organic chemical vapor deposition (English: Metal-organic Chemical Vapor Deposition, abbreviated as: MOCVD) technology can be used to sequentially form a buffer layer, an electron generation layer, and an active layer on the growth substrate. Layer and hole generating layer.
  • MOCVD Metal-organic Chemical Vapor Deposition
  • the growth temperature of the buffer layer may be 300°C.
  • polyimide (English: Polyimide, abbreviated as: PI) tape or SU-8 photoresist can be used to bind the hole generating layer to the glass substrate.
  • PI Polyimide
  • PI tape or SU-8 photoresist can be used to bind the electron generation layer to the sapphire substrate.
  • an etching solution can be used to remove the glass substrate.
  • FIG. 4 is a schematic diagram of the structure of the display array after step 204 is performed according to an embodiment of the present disclosure.
  • the driving circuit layer 12 and the insulating layer 13 are sequentially laminated on the substrate 11, and a plurality of semiconductor devices are arranged on the insulating layer 13 at intervals, and each semiconductor device includes a P-type electrode 21 and a space sequentially laminated on the insulating layer 13.
  • step 205 the substrates in the multiple semiconductor devices are removed by laser lift-off, the first buffer layer is removed by dry etching, and N-type electrodes are arranged on the electron generation layer to form a miniature light-emitting diode chip.
  • FIG. 5 is a schematic diagram of the structure of the display array after step 205 according to an embodiment of the disclosure is performed.
  • the first buffer layer 32 and the substrate 31 in each semiconductor device are provided with an N-type electrode 22 on the electron generation layer 33 to form a Micro LED chip 20.
  • the thermal conductivity of diamond is 1300-2200W/(m*K), which is much higher than the original silicon dioxide and can effectively emit
  • the heat generated by the Micro LED chip, and the SOG is in a liquid state when laid, can form good contact with the diamond particles, avoid interface thermal resistance, achieve an efficient and smooth thermal channel, greatly improve heat dissipation efficiency, and promote the use of Micro LED on small-pitch displays. Promotion and stable use.
  • both diamond and SOG are insulating materials, so there is no leakage problem.
  • a plurality of micro light emitting diode chips can be arranged on the insulating layer.
  • the manufacturing method may further include:
  • a photoresist with a set pattern is formed on the passivation protection material
  • the passivation protection material can be laid using CVD technology, and the patterned photoresist can be formed using photolithography technology.
  • the laser may act on the active layer through the sapphire substrate, causing damage to the active layer and leakage failure, reducing the yield of the chip.
  • the present disclosure makes the following improvements to the semiconductor device:
  • each semiconductor device may further include a laser consuming layer laminated between the first buffer layer and the substrate.
  • the laser consuming layer is formed by alternately stacking a plurality of polycrystalline layers and a plurality of band gap layers.
  • the growth temperature of the crystal layer increases layer by layer along the direction from the substrate to the electron generation layer, and the forbidden band widths of multiple band gap layers increase layer by layer in the direction from the substrate to the electron generation layer.
  • the crystal quality of the polycrystalline layer is poor, which can effectively absorb the laser light passing through the substrate, and prevent the laser from acting on the active layer.
  • the active layer causes damage.
  • the forbidden band width of multiple forbidden band layers increases layer by layer along the direction from the substrate to the electron generating layer, and the forbidden band widths of multiple forbidden band layers are different.
  • the laser light that may be absorbed by the active layer can be replaced with The source layer absorbs to further prevent the laser from acting on the active layer and causing damage to the active layer.
  • the growth temperature of multiple polycrystalline layers increases layer by layer along the direction from the substrate to the electron generation layer, which can gradually improve the crystal quality and provide a better lattice basis for subsequent epitaxial growth.
  • the number of band gap layers can be three, and the three band gap layers are narrow band gap layer, middle band gap layer, wide band gap layer, and narrow band gap layer in the direction from the sapphire substrate to the electron generation layer.
  • the forbidden band width of the layer is smaller than the forbidden band width of the quantum well of the active layer.
  • the forbidden band width of the middle band gap is equal to the forbidden band width of the quantum well of the active layer.
  • the band gap of the wide band gap layer is larger than that of the active layer.
  • the band gap of the quantum well The laser light that may be absorbed by the forbidden band width of the active layer can be replaced by the active layer for absorption, effectively preventing the laser light from acting on the active layer and causing damage to the active layer.
  • the thickness of the band gap layer is negatively correlated with the difference in the band gap, and the difference in band gap is the absolute value of the difference between the band gap of the corresponding band gap and the band gap of the quantum well in the active layer. .
  • the gap between the band gap corresponding to the middle band gap layer is 0, and the gap between the narrow band gap layer and the wide band gap layer corresponds to zero.
  • the band width difference is greater than 0, the thickness of the middle band gap layer is greater than the thickness of the narrow band gap layer, and the thickness of the middle band gap layer is greater than the thickness of the wide band gap layer.
  • the thickness of the corresponding band gap layer is set to be larger to further enhance the protection effect on the active layer.
  • each band gap layer may be composed of a multilayer film whose band gap width gradually changes.
  • the quantum well has a band gap of 1.90 eV
  • the narrow band gap layer can be composed of three layers of films with band gaps of 1.75 eV, 1.80 eV, and 1.85 eV
  • the middle band gap layer can have a band gap of 1.88 eV.
  • the wide band gap layer can be composed of three-layer film with forbidden band widths of 1.95eV, 2.00eV, 2.05eV.
  • Multi-layer films with different band gap widths can effectively absorb various laser photons that may act on the quantum well, so as to maximize the protection of the quantum well.
  • the material of the film can be AlGaInP.
  • the band gap of the film can be increased.
  • the thickness of each thin film may be negatively correlated with the absolute value of the difference between the forbidden band width of the thin film and the quantum well.
  • a film with a band gap of 1.75eV has a thickness of 100 angstroms
  • a film with a band gap of 1.80eV has a thickness of 200 angstroms
  • a film with a band gap of 1.85eV has a thickness of 300 angstroms
  • the band gap is The thickness of the 1.88eV film is 300 angstroms
  • the thickness of the film with a band gap of 1.90 eV is 350 angstroms
  • the thickness of the film with a band gap of 1.92 eV is 300 angstroms
  • the thickness of the film with a band gap of 1.95 eV is 300 angstroms
  • the thickness of a film with a band gap of 2.20 eV is 200 angstroms
  • the thickness of a film with a band gap of 2.05 eV is 100 angstroms.
  • the number of polycrystalline layers can also be three.
  • the growth temperature of the three polycrystalline layers is 300°C, 400°C, and 500°C in sequence. It can not only effectively absorb the laser light passing through the sapphire substrate, but also provide a better lattice basis for the subsequent epitaxial growth.
  • the material of the polycrystalline layer may be GaInP.
  • the semiconductor device further includes a second buffer layer located between the substrate and the laser consuming layer, and the thickness of the second buffer layer is greater than the thickness of the first buffer layer.
  • the thickness of the second buffer layer may be greater than 0.5 microns.
  • it is between 0.5 micrometer and 1 micrometer.
  • the thickness of the first buffer layer may be within 0.5 micrometers, for example 0.2 micrometers.
  • the embodiment of the present disclosure provides a miniature light emitting diode display array, which is suitable for being formed by the manufacturing method shown in FIG. 1 or FIG. 2.
  • the micro light emitting diode display array includes a circuit board 10 and a plurality of micro light emitting diode chips 20.
  • the circuit board 10 includes a substrate 11, a driving circuit layer 12, and an insulating layer 13.
  • the driving circuit layer 12 and the insulating layer 13 are sequentially laminated on the substrate 11 on.
  • the insulating layer 13 is provided with a through hole extending to the driving circuit layer 12, the through hole is filled with conductive material, and a plurality of micro light emitting diode chips 20 are arranged on the insulating layer 13 at intervals and pass through the conductive material and the driving circuit layer in the through hole The corresponding driving circuit in 12 is electrically connected.
  • the insulating layer 13 is formed of a liquid insulating material mixed with diamond particles.
  • the thickness of the portion of the insulating layer that does not contain diamond particles is smaller than the particle size of the diamond particles.
  • the driving circuit layer 12 has a solder layer on a surface away from the substrate 11, and at least a part of the diamond particles are embedded in the solder layer.
  • the micro light emitting diode chip includes a P-type electrode, a hole generation layer, an active layer, an electron generation layer, and an N-type electrode that are sequentially stacked on the insulating layer.
  • the P-type electrode is opposite to the insulating layer as a solder layer, and at least a part of the diamond particles is embedded in the solder layer of the P-type electrode.
  • FIG. 6 is a schematic structural diagram of a miniature light-emitting diode epitaxial wafer provided by an embodiment of the disclosure.
  • the micro light emitting diode epitaxial wafer includes a transparent substrate 31, a first buffer layer 32, an electron generation layer 33, an active layer 34 and a hole generation layer 35 which are sequentially stacked.
  • the micro light emitting diode epitaxial wafer further includes a laser consuming layer 40 laminated between the transparent substrate 31 and the first buffer layer 32.
  • FIG. 7 is a schematic structural diagram of a laser consuming layer provided by an embodiment of the disclosure.
  • the laser consuming layer 40 is formed by alternately stacking a plurality of polycrystalline layers 41 and a plurality of band gap layers 42.
  • the growth temperature of the plurality of polycrystalline layers 41 is gradually along the direction from the sapphire substrate 31 to the electron generation layer 33.
  • the forbidden band width of the plurality of band gap layers 42 increases layer by layer along the direction from the sapphire substrate 31 to the electron generation layer 33.
  • the thickness of the band gap layer is negatively correlated with a difference in band gap width
  • the difference in band gap width is the band gap width of the corresponding band gap layer and the band gap width of the quantum well in the active layer The absolute value of the difference.
  • the micro light emitting diode epitaxial wafer further includes a second buffer layer laminated between the transparent substrate and the laser consuming layer, and the thickness of the second buffer layer is greater than that of the first buffer layer.
  • the thickness of a buffer layer is greater than 0.5 microns. For example, it is between 0.5 micrometer and 1 micrometer.

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Abstract

本公开提供了一种微型发光二极管外延片、显示阵列及其制作方法，属于半导体技术领域。该方法包括：提供电路板，所述电路板包括基板和位于所述基板上的驱动电路层；在所述驱动电路层上形成绝缘层，所述绝缘层采用混有金刚石颗粒的液态绝缘材料形成；在所述绝缘层中开设延伸至所述驱动电路层的多个通孔，并在所述多个通孔内填充导电材料；在所述绝缘层上设置多个微型发光二极管芯片，使得所述微型发光二极管芯片通过对应的通孔中的导电材料与所述驱动电路层中对应的驱动电路连接。

Description

微型发光二极管外延片、显示阵列及其制作方法
本申请要求于2019年12月26日提交的申请号为201911364394.8、发明名称为“微型发光二极管外延片、显示阵列及其制作方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及半导体技术领域，特别涉及一种微型发光二极管外延片、显示阵列及其制作方法。
背景技术
微型发光二极管(英文：Micro LED)是指边长在10微米～100微米的超小型发光二极管，体积小，可以更密集地排列在一起而大幅提高显示器的分辨率，并且Micro LED具有自发光特性，Micro LED显示器在高亮度、高对比度、快速反应和省电等方面都具有良好表现，未来很可能会进一步占据小间距显示器市场。
相关技术中，Micro LED的显示阵列包括电路板和多个Micro LED芯片，电路板包括基板和依次层叠在基板上的驱动电路层和绝缘层，多个Micro LED芯片间隔设置在绝缘层上。绝缘层的材料采用二氧化硅，绝缘层中设有连通Micro LED芯片和驱动电路层中对应的驱动电路的通孔。
在实现本公开的过程中，发明人发现相关技术至少存在以下问题：
在小间距显示器中，大量的Micro LED芯片密集布置在电路板上，工作过程中产生的热量很多。但是二氧化硅的热传导系数为7.6W/(m*K)，热传导效率较低，无法有效散发Micro LED芯片产生的热量，导致小间距显示器长时间使用会存在较大的隐患，不利于Micro LED在小间距显示器上的推广和稳定使用。
发明内容
本公开实施例提供了一种微型发光二极管外延片、显示阵列及其制作方法，可以有效散发Micro LED芯片产生的热量，促进Micro LED在小间距显示器上的推广和稳定使用。所述技术方案如下：
一方面，本公开实施例提供了一种微型发光二极管显示阵列的制作方法，所述制作方法包括：
提供电路板，所述电路板包括基板和位于所述基板上的驱动电路层；在所述驱动电路层上形成绝缘层，所述绝缘层采用混有金刚石颗粒的液态绝缘材料形成；在所述绝缘层中开设延伸至所述驱动电路层的多个通孔，并在所述多个通孔内填充导电材料；在所述绝缘层上设置多个微型发光二极管芯片，使得所述微型发光二极管芯片通过对应的通孔中的导电材料与所述驱动电路层中对应的驱动电路连接。
可选地，所述驱动电路层远离所述基板的表面具有焊料层；所述在所述驱动电路层上形成绝缘层，包括：在所述驱动电路层上涂覆混有金刚石颗粒的液态绝缘材料；在第一设定温度下固化所述液态绝缘材料，形成预固化层；加热所述预固化层并在所述预固化层上施加朝向所述驱动电路层的压力，直到所述预固化层中位于所述焊料层上的金刚石颗粒的一部分嵌入所述焊料层中；在第二设定温度下固化所述预固化层，所述第二设定温度高于所述第一设定温度。
可选地，在所述驱动电路层上形成绝缘层之后，所述制作方法还包括：刻蚀所述绝缘层，直到所述金刚石颗粒的一部分从所述绝缘层的靠近所述微型发光二极管芯片的表面中露出。
可选地，所述液态绝缘材料为旋转涂布玻璃SOG。
可选地，所述在所述绝缘层上设置多个微型发光二极管芯片，包括：在所述绝缘层上设置多个半导体器件并对所述多个半导体器件加压加热，以将所述多个半导体器件与所述电路板键合在一起，每个所述半导体器件包括依次层叠在所述绝缘层上的P型电极、空穴产生层、有源层、电子产生层、第一缓冲层和衬底，所述多个半导体器件中的P型电极分别通过对应的通孔内的导电材料与对应的所述驱动电路连接；去除所述多个半导体器件中的衬底和缓冲层；在所述多个半导体器件的电子产生层上形成N型电极，形成多个微型发光二极管芯片。
可选地，所述P型电极与所述绝缘层相对的表面为焊料层；所述对所述多个半导体器件加压加热，以将所述多个半导体器件与所述电路板键合在一起，包括：在加热的条件下，在所述多个半导体器件上施加朝向所述绝缘层的压力，直到所述金刚石颗粒嵌入所述P型电极的焊料层中。
可选地，所述衬底为透明衬底，所述去除所述多个半导体器件中的衬底， 包括：采用激光剥离的方式去除所述多个半导体器件中的衬底。
可选地，所述半导体器件还包括位于所述衬底和所述第一缓冲层之间的激光消耗层，所述激光消耗层由多个多晶层和多个禁带层交替层叠而成，所述多个多晶层的生长温度沿从所述衬底到所述电子产生层的方向逐层升高，所述多个禁带层的禁带宽度沿从所述衬底到所述电子产生层的方向逐层增大。
可选地，所述禁带层的厚度与禁带宽度差值负相关，所述禁带宽度差值为对应的禁带层的禁带宽度与所述有源层中量子阱的禁带宽度的差值的绝对值。
可选地，所述半导体器件还包括位于所述衬底和所述激光消耗层之间的第二缓冲层，所述第二缓冲层的厚度大于所述第一缓冲层的厚度。
可选地，所述第二缓冲层的厚度在0.5微米以上。
另一方面，本公开实施例提供了一种微型发光二极管显示阵列，包括电路板和多个微型发光二极管芯片，所述电路板包括基板、驱动电路层和绝缘层，所述驱动电路层和所述绝缘层依次层叠在所述基板上，所述绝缘层上设有延伸至所述驱动电路层的通孔，所述通孔内填充有导电材料，所述多个微型发光二极管芯片在所述绝缘层上并通过所述多个通孔中对应的通孔内的导电材料与所述驱动电路层中对应的驱动电路连接，所述绝缘层采用混有金刚石颗粒的液态绝缘材料形成。
可选地，所述绝缘层未包含金刚石颗粒的部分的厚度小于所述金刚石颗粒的粒径。
可选地，所述驱动电路层远离所述基板的表面具有焊料层，所述金刚石颗粒中的至少部分颗粒的一部分嵌入所述焊料层中。
可选地，微型发光二极管芯片包括依次层叠在所述绝缘层上的P型电极、空穴产生层、有源层、电子产生层和N型电极，所述P型电极与所述绝缘层相对的为焊料层，所述金刚石颗粒中的至少部分颗粒的一部分嵌入所述焊料层中。
可选地，所述液态绝缘材料为旋转涂布玻璃SOG。
又一方面，本公开实施例提供了一种微型发光二极管外延片，包括透明衬底和依次层叠在所述透明衬底上的第一缓冲层、电子产生层、有源层和空穴产生层，所述微型发光二极管外延片还包括层叠在所述第一缓冲层和所述透明衬底之间的激光消耗层，所述激光消耗层由多个多晶层和多个禁带层交替层叠而 成，所述多个多晶层的生长温度沿从所述透明衬底到所述电子产生层的方向逐层升高，所述多个禁带层的禁带宽度沿从所述透明衬底到所述电子产生层的方向逐层增大。
可选地，所述禁带层的厚度与禁带宽度差值负相关，所述禁带宽度差值为对应的禁带层的禁带宽度与所述有源层中量子阱的禁带宽度的差值的绝对值。
可选地，微型发光二极管外延片还包括第二缓冲层，所述第二缓冲层层叠在所述透明衬底和所述激光消耗层之间，所述第二缓冲层的厚度大于所述第一缓冲层的厚度。
可选地，所述第二缓冲层的厚度在0.微米以上。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本公开实施例提供的一种微型发光二极管显示阵列的制作方法的流程图；
图2是本公开实施例提供的一种微型发光二极管显示阵列的制作方法的流程图；
图3是本公开实施例提供的绝缘层将多个半导体器件与电路板键合在一起的结构示意图；
图4是本公开实施例提供的步骤204执行之后显示阵列的结构示意图；
图5是本公开实施例提供的步骤205执行之后显示阵列的结构示意图；
图6是本公开实施例提供的一种微型发光二极管外延片的结构示意图；
图7是本公开实施例提供的激光消耗层的结构示意图。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚，下面将结合附图对本公开实施方式作进一步地详细描述。
本公开实施例提供了一种微型发光二极管显示阵列的制作方法。图1为本公开实施例提供的一种微型发光二极管显示阵列的制作方法的流程图。参见图 1，该制作方法包括：
在步骤101中，提供电路板，该电路板包括基板和位于基板上的驱动电路层。
其中，驱动电路层包括多个阵列布置的驱动电路，每个驱动电路对应一个微型发光二极管芯片，该驱动电路用于控制对应的微型发光二极管芯片发光。
示例性地，每个驱动电路包括至少一个薄膜晶体管，例如薄膜金属氧化物半导体场效晶体管(Metal-Oxide-Semiconductor Field-Effect Transistor,MOSFET)。本公开实施例对驱动电路层的层级结构不做限制，只要能够形成用于控制多个微型发光二极管芯片发光的驱动电路即可。
可选地，基板采用硅片，以便在基板上直接形成驱动电路；或者，基板采用碳化硅片或者陶瓷片，此时基板上可以制作硅、砷化镓等材料，以便形成驱动电路。
在步骤102中，在驱动电路层上形成绝缘层，绝缘层采用混有金刚石颗粒的液态绝缘材料形成。
示例性地，液态绝缘材料为旋转涂布玻璃(英文：spin on glass coating，简称：SOG)层。
由于绝缘层采用混有金刚石颗粒的液态绝缘材料形成，所以可以先将混有金刚石颗粒的液态绝缘材料涂覆在驱动电路层上，然后再使混有金刚石颗粒的液态绝缘材料固化，形成该绝缘层。
在步骤103中，在绝缘层中开设延伸至驱动电路层的多个通孔，并在多个通孔内填充导电材料。
其中，绝缘层中通孔的位置与驱动电路层上的焊盘的位置相对应，每个焊盘上对应形成一个通孔，以便于焊盘通过对应的通孔中的导电材料与微型发光二极管芯片连接。
示例性地，导电材料为金属材料，包括但不限于铜、金、锡等。
可选地，在该步骤103中，通过干法刻蚀在绝缘层中开设通孔，通过例如电镀的方式在通孔中形成导电材料。
在步骤104中，在绝缘层上设置多个微型发光二极管芯片，使得微型发光二极管芯片通过对应的通孔中的导电材料与驱动电路层中对应的驱动电路连接。
在本公开实施例中，微型发光二极管芯片包括第一电极，该第一电极与对 应的通孔相对，从而便于通过通孔中的导电材料与对应的焊盘连接，实现微型发光二极管芯片与对应的驱动电路之间的连接。
本公开实施例通过将绝缘层的材料改为混有金刚石颗粒的液态绝缘材料，金刚石的热传导系数为1300～2200W/(m*K)，远高于原来的二氧化硅，可以有效传导Micro LED芯片产生的热量，而且绝缘层形成时呈液态，可以与金刚石颗粒形成良好的接触，减小产生界面热阻，实现高效顺畅的热通道，大幅提高散热效率，促进Micro LED在小间距显示器上的推广和稳定使用。而且金刚石和液态绝缘材料均为绝缘材料，不存在漏电问题。
需要说明的是，下文中，将以第一电极为P型电极为例进行示例性说明，在其他实施例中，第一电极也可以为N型电极。
本公开实施例还提供了一种微型发光二极管显示阵列的制作方法。图2为本公开实施例提供的一种微型发光二极管显示阵列的制作方法的流程图。参见图2，该制作方法包括：
在步骤201中，提供电路板，该电路板包括基板和位于基板上的驱动电路层。
电路板的相关内容，参见前述步骤101，在此省略详细描述。
在步骤202中，在驱动电路层上形成绝缘层。
在本实施例中，绝缘层为混有金刚石颗粒的旋转涂布玻璃(英文：spin on glass coating，简称：SOG)层。
可选地，驱动电路层远离基板的表面具有焊料层，例如金层或者锡层。该焊料层为驱动电路的用于与Micro LED芯片连接的焊盘的顶层，焊料层的部分与绝缘层接触，部分与通孔中的导电材料连接。
相应地，该步骤202可以包括：
在驱动电路层上涂覆混有金刚石颗粒的SOG液体；
在第一设定温度下固化SOG液体，形成预固化的SOG层；
加热预固化的SOG层并在预固化的SOG层上施加朝向驱动电路层的压力，直到位于焊料层上的金刚石颗粒的一部分嵌入焊料层中；
在第二设定温度下固化预固化的SOG层，第二设定温度高于第一设定温度。
驱动电路的焊盘的顶部为焊料层，焊料层采用的材料的硬度远低于金刚石，在金刚石颗粒上施加压力，可以将金刚石颗粒嵌入在焊料层中，热量可以直接 通过金刚石颗粒传导到驱动电路层上，避开热传导系数较低的由液态绝缘材料形成的绝缘层，充分利用热传导系数高的金刚石颗粒进行散热，大幅提高导热效果。而且绝缘层加热过程中呈现液态，可以与金刚石颗粒形成良好的接触，匹配金刚石颗粒的位置变化。
示例性地，第一设定温度可以为300℃，在第一设定温度下固化SOG液体的时间可以为30分钟；第二设定温度可以为500℃，在第二设定温度下固化SOG层的时间可以为30分钟。
需要说明的是，在该步骤202中，以液态绝缘材料为SOG为例进行了说明，但并不以此为限。
在步骤203中，在绝缘层上开设延伸至驱动电路层的通孔，并在通孔内填充导电材料。
相关内容参见步骤103，在此省略详细描述。
在步骤204中，在绝缘层上间隔设置多个半导体器件并对多个半导体器件加压加热，以将多个半导体器件与电路板键合在一起。
在本实施例中，每个半导体器件包括依次层叠在绝缘层上的P型电极、空穴产生层、有源层、电子产生层、缓冲层和蓝宝石衬底，多个半导体器件中的P型电极分别通过通孔内的导电材料与驱动电路电连接。
可选地，在步骤203之后，该制作方法还可以包括：
刻蚀绝缘层，直到金刚石颗粒的一部分从所述绝缘层的靠近所述微型发光二极管芯片的表面中露出。
也即是，对绝缘层中除金刚石颗粒之外的部分进行减薄，使得金刚石颗粒从绝缘层的表面露出，这样，在半导体器件与电路板键合之后，半导体器件的P型电极与金刚石颗粒相抵，由该半导体器件形成的Micro LED芯片的热量可以直接传递到金刚石颗粒上散发出去，避开热传导系数较低的绝缘层，充分利用热传导系数高的金刚石颗粒进行散热，大幅提高导热效果。
可替代地，也可以在绝缘层上开设通孔之前，先刻蚀绝缘层，直到金刚石颗粒的一部分从所述绝缘层的靠近所述微型发光二极管芯片的表面中露出。
在一些示例中，金刚石颗粒的表面与绝缘层中由液态绝缘材料形成的部分的表面齐平。在另一些示例中，金刚石颗粒的表面凸出于绝缘层中由液态绝缘材料形成的部分的表面。
可选地，P型电极与绝缘层相对的表面为焊料层，例如金层或锡层。
相应地，该步骤204包括：将多个半导体器件放置在绝缘层上，P型电极位于凸出的金刚石颗粒上；在加热的条件下，在多个半导体器件上施加朝向绝缘层的压力，直到露出的金刚石颗粒嵌入P型电极的金层中。
示例性地，通过键合机对多个半导体器件加压加热。
示例性地，金刚石颗粒的粒径可以为6微米，绝缘层中由液态绝缘材料形成的部分的厚度可以为3微米，金刚石颗粒嵌入驱动电路层的焊料层的深度可以为1微米，金刚石颗粒从绝缘层的表面凸出的高度可以为金刚石颗粒的粒径的1/5。
图3为本公开实施例提供的绝缘层将多个半导体器件与电路板键合在一起的结构示意图。参见图3，绝缘层13中的金刚石颗粒131分别嵌入驱动电路层12和P型电极21的焊料层中，可以直接将芯片的热量传递到驱动电路，完全避开热传导系数较低的液态绝缘材料形成的绝缘层，充分利用热传导系数高的金刚石颗粒进行散热，大幅提高导热效果。
在实际应用中，P型电极与电源的正极连通，将电流注入芯片中；P型电极的材料可以为金铍合金。空穴产生层提供复合发光的空穴，空穴产生层的材料可以为掺杂镁的AlInGaP。有源层进行电子和空穴的复合发光，有源层的材料可以为未掺杂的AlInGaP。电子产生层提供复合发光的电子，电子产生层的材料可以为掺杂硅的AlInGaP。缓冲层缓解外延层和衬底之间晶格失配产生的应力和缺陷、以及提供成核中心，缓冲层的材料采用GaAs。蓝宝石衬底起到支撑作用。
可选地，半导体器件还可以包括透明导电层，透明导电层设置在空穴产生层和P型电极之间，一方面与电极之间形成良好的欧姆接触，另一方面对电极注入的电流进行扩展。示例性地，透明导电层的材料可以为氧化铟锡(英文：Indium tin oxide，简称：ITO)或者NiAu合金。
可选地，在步骤204之前，该制作方法还包括：
第一步，在生长衬底上依次形成缓冲层、电子产生层、有源层和空穴产生层，形成外延片；
第二步，将空穴产生层绑定到玻璃基板上；
第三步，采用湿法腐蚀的方式去除生长衬底；
第四步，将电子产生层绑定到蓝宝石衬底上；
第五步，去除玻璃基板。
在该实施例中，由于蓝宝石衬底是透明的，所以这里将不透明的生长衬底 替换为透明的蓝宝石衬底，以便后续利用激光剥离的方式去除蓝宝石衬底。需要说明的是，在其他实施例中，蓝宝石衬底也可以被替换为其他透明衬底，包括但不限于磷化镓衬底、碳化硅衬底、氧化锌衬底和玻璃衬底等。
在实际应用中，在第一步中，可以采用金属有机化合物化学气相沉淀(英文：Metal-organic Chemical Vapor Deposition，简称：MOCVD)技术在生长衬底上依次形成缓冲层、电子产生层、有源层和空穴产生层。其中，缓冲层的生长温度可以为300℃。
在第二步中，可以利用聚酰亚胺(英文：Polyimide，简称：PI)胶带或者SU-8光刻胶将空穴产生层绑定到玻璃基板上。
在第四步中，可以利用PI胶带或者SU-8光刻胶将电子产生层绑定到蓝宝石衬底上。
在第五步中，可以使用腐蚀液去除玻璃基板。
图4为本公开实施例提供的步骤204执行之后显示阵列的结构示意图。参见图4，驱动电路层12、绝缘层13依次层叠在基板11上，多个半导体器件间隔设置在绝缘层13上，每个半导体器件包括依次层叠在绝缘层13上的P型电极21、空穴产生层35、有源层34、电子产生层33、第一缓冲层32和衬底31。
在步骤205中，采用激光剥离的方式去除多个半导体器件中的衬底，采用干法刻蚀的方式去除第一缓冲层，并在电子产生层上设置N型电极，形成微型发光二极管芯片。
图5为本公开实施例提供的步骤205执行之后显示阵列的结构示意图。参见图5，各个半导体器件中的第一缓冲层32和衬底31，电子产生层33上设置有N型电极22，形成Micro LED芯片20。
本公开实施例通过将芯片设置的绝缘层的材料改为混有金刚石颗粒的SOG层，金刚石的热传导系数为1300～2200W/(m*K)，远高于原来的二氧化硅，可以有效散发Micro LED芯片产生的热量，而且SOG铺设时呈液态，可以与金刚石颗粒形成良好的接触，避免产生界面热阻，实现高效顺畅的热通道，大幅提高散热效率，促进Micro LED在小间距显示器上的推广和稳定使用。而且金刚石和SOG均为绝缘材料，不存在漏电问题。
通过步骤204至205，即可实现在所述绝缘层上设置多个微型发光二极管芯片。
可选地，该制作方法还可以包括：
在电子产生层上铺设钝化保护材料；
在钝化保护材料上形成设定图形的光刻胶；
湿法腐蚀没有光刻胶覆盖的钝化保护材料，留下的钝化保护材料形成钝化保护层；
去除光刻胶。
示例性地，钝化保护材料可以采用CVD技术铺设，设定图形的光刻胶可以采用光刻技术形成。
在实际应用中，激光在去除蓝宝石衬底的过程中，有可能透过蓝宝石衬底作用在有源层上，导致有源层受到损伤而漏电失效，降低芯片的良率。针对这个问题，本公开对半导体器件进行如下改进：
可选地，每个半导体器件还可以包括层叠在第一缓冲层和衬底之间的激光消耗层，激光消耗层由多个多晶层和多个禁带层交替层叠而成，多个多晶层的生长温度沿从衬底到电子产生层的方向逐层升高，多个禁带层的禁带宽度沿从衬底到电子产生层的方向逐层增大。
通过增设多个多晶层和多个禁带层交替层叠而成的激光消耗层，多晶层的晶体质量较差，可以有效吸收透过衬底的激光，避免激光作用在有源层而对有源层造成损害。而且多个禁带层的禁带宽度沿从衬底到电子产生层的方向逐层增大，多个禁带层的禁带宽度各不相同，可以针对有源层可能吸收的激光，替代有源层进行吸收，进一步避免激光作用在有源层上而对有源层造成损害。另外，多个多晶层的生长温度沿从衬底到电子产生层的方向逐层升高，能够逐步提高晶体质量，可以为后续的外延生长提供较好的晶格基础。
示例性地，禁带层的数量可以为三个，三个禁带层沿从蓝宝石衬底到电子产生层的方向依次为窄禁带层、中禁带层、宽禁带层，窄禁带层的禁带宽度小于有源层的量子阱的禁带宽度，中禁带层的禁带宽度等于有源层的量子阱的禁带宽度，宽禁带层的禁带宽度大于有源层的量子阱的禁带宽度。可以针对有源层的禁带宽度可能吸收的激光，替代有源层进行吸收，有效避免激光作用在有源层上而对有源层造成损害。
可选地，禁带层的厚度与禁带宽度差值负相关，禁带宽度差值为对应的禁带层的禁带宽度与有源层中量子阱的禁带宽度的差值的绝对值。例如，中禁带层的禁带宽度等于有源层的量子阱的禁带宽度，则中禁带层对应的禁带宽度差值为0，而窄禁带层和宽禁带层对应的禁带宽度差值均大于0，则中禁带层的厚 度大于窄禁带层的厚度，且中禁带层的厚度大于宽禁带层的厚度。
禁带宽度差值越小，表示对应的禁带层对有源层的保护作用越强，因此，将对应的禁带层的厚度设置得较大，以进一步增强对有源层的保护作用。
可选地，每个禁带层可以由禁带宽度逐渐变化的多层薄膜组成。例如，量子阱的禁带宽度为1.90eV，窄禁带层可以由禁带宽度依次为1.75eV、1.80eV、1.85eV的三层薄膜组成，中禁带层可以由禁带宽度依次为1.88eV、1.90eV、1.92eV的三层薄膜组成，宽禁带层可以由禁带宽度依次为1.95eV、2.00eV、2.05eV的三层薄膜组成。通过禁带宽度不同的多层薄膜，可以有效吸收可能作用在量子阱上的各种激光光子，最大限度实现对量子阱的保护。
在实际应用中，该薄膜的材料可以为AlGaInP。通过增加薄膜中Al组分的含量，可以增加薄膜的禁带宽度。
可选地，各薄膜的厚度可以与薄膜和量子阱的禁带宽度的差值的绝对值负相关。示例性地，禁带宽度为1.75eV的薄膜的厚度为100埃，禁带宽度为1.80eV的薄膜的厚度为200埃，禁带宽度为1.85eV的薄膜的厚度为300埃；禁带宽度为1.88eV的薄膜的厚度为300埃，禁带宽度为1.90eV的薄膜的厚度为350埃，禁带宽度为1.92eV的薄膜的厚度为300埃；禁带宽度为1.95eV的薄膜的厚度为300埃，禁带宽度为2.20eV的薄膜的厚度为200埃，禁带宽度为2.05eV的薄膜的厚度为100埃。可以针对有源层的禁带宽度可能吸收的激光，替代有源层进行吸收，有效避免激光作用在有源层上而对有源层造成损害。
相应地，多晶层的数量也可以为三个。例如，三个多晶层的生长温度依次为300℃、400℃、500℃。既能有效吸收透过蓝宝石衬底的激光，又能为后续的外延生长提供较好的晶格基础。
在实际应用中，多晶层的材料可以为GaInP。
可选地，该半导体器件还包括位于衬底和激光消耗层之间的第二缓冲层，所述第二缓冲层的厚度大于所述第一缓冲层的厚度。
可选地，第二缓冲层的厚度可以在0.5微米以上。例如在0.5微米至1微米之间。通过将缓冲层的厚度从0.1微米以下增加至0.5微米以上，可以较好地缓解激光去除蓝宝石衬底时产生的应力影响，提高芯片的良率。
示例性地，第一缓冲层的厚度可以在0.5微米以内，例如为0.2微米。
本公开实施例提供了一种微型发光二极管显示阵列，适用于采用图1或图2 所示的制作方法形成。参见图5，微型发光二极管显示阵列包括电路板10和多个微型发光二极管芯片20，电路板10包括基板11、驱动电路层12和绝缘层13，驱动电路层12和绝缘层13依次层叠在基板11上。绝缘层13上设有延伸至驱动电路层12的通孔，通孔内填充有导电材料，多个微型发光二极管芯片20间隔设置在绝缘层13上并通过通孔内的导电材料与驱动电路层12中对应的驱动电路电连接。
在本实施例中，绝缘层13采用混有金刚石颗粒的液态绝缘材料形成。
可选地，所述绝缘层未包含金刚石颗粒的部分的厚度小于所述金刚石颗粒的粒径。
在本公开实施例的一种实现方式中，所述驱动电路层12远离所述基板11的表面具有焊料层，所述金刚石颗粒中的至少部分颗粒的一部分嵌入该焊料层中。
在本公开实施例的另一种实现方式中，微型发光二极管芯片包括依次层叠在所述绝缘层上的P型电极、空穴产生层、有源层、电子产生层和N型电极，所述P型电极与所述绝缘层相对的为焊料层，所述金刚石颗粒中的至少部分颗粒的一部分嵌入P型电极的焊料层中。
在实际应用中，可以同时采用上述两种实现方式。
微型发光二极管显示阵列中各层结构的相关内容参见前述制作方法实施例，在此省略详细描述。
本公开实施例提供了一种微型发光二极管外延片，适用于形成图1或图2所示的制作方法中的微型发光二极管芯片。图6为本公开实施例提供的一种微型发光二极管外延片的结构示意图。参见图6，微型发光二极管外延片包括依次层叠的透明衬底31、第一缓冲层32、电子产生层33、有源层34和空穴产生层35。
在本实施例中，如图6所示，微型发光二极管外延片还包括层叠在透明衬底31和第一缓冲层32之间的激光消耗层40。图7为本公开实施例提供的激光消耗层的结构示意图。参见图7，激光消耗层40由多个多晶层41和多个禁带层42交替层叠而成，多个多晶层41的生长温度沿从蓝宝石衬底31到电子产生层33的方向逐层升高，多个禁带层42的禁带宽度沿从蓝宝石衬底31到电子产生层33的方向逐层增大。
可选地，所述禁带层的厚度与禁带宽度差值负相关，所述禁带宽度差值为对应的禁带层的禁带宽度与所述有源层中量子阱的禁带宽度的差值的绝对值。
可选地，微型发光二极管外延片还包括第二缓冲层，所述第二缓冲层层叠在所述透明衬底和所述激光消耗层之间，所述第二缓冲层的厚度大于所述第一缓冲层的厚度。可选地，所述第二缓冲层的厚度在0.5微米以上。例如在0.5微米至1微米之间。
微型发光二极管外延片中各层结构的相关内容参见前述制作方法实施例，在此省略详细描述。
以上所述仅为本公开的可选实施例，并不用以限制本公开，凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (20)

  1. 一种微型发光二极管显示阵列的制作方法，包括：
    提供电路板，所述电路板包括基板和位于所述基板上的驱动电路层；
    在所述驱动电路层上形成绝缘层，所述绝缘层采用混有金刚石颗粒的液态绝缘材料形成；
    在所述绝缘层中开设延伸至所述驱动电路层的多个通孔，并在所述多个通孔内填充导电材料；
    在所述绝缘层上设置多个微型发光二极管芯片，使得所述微型发光二极管芯片通过对应的通孔中的导电材料与所述驱动电路层中对应的驱动电路连接。
  2. 根据权利要求1所述的制作方法，其中，所述驱动电路层远离所述基板的表面具有焊料层；
    所述在所述驱动电路层上形成绝缘层，包括：
    在所述驱动电路层上涂覆混有金刚石颗粒的液态绝缘材料；
    在第一设定温度下固化所述液态绝缘材料，形成预固化层；
    加热所述预固化层并在所述预固化层上施加朝向所述驱动电路层的压力，直到所述预固化层中位于所述焊料层上的金刚石颗粒的一部分嵌入所述焊料层中；
    在第二设定温度下固化所述预固化层，所述第二设定温度高于所述第一设定温度。
  3. 根据权利要求1或2所述的制作方法，其中，在所述驱动电路层上形成绝缘层之后，所述制作方法还包括：
    刻蚀所述绝缘层，直到所述金刚石颗粒的一部分从所述绝缘层的靠近所述微型发光二极管芯片的表面中露出。
  4. 根据权利要求1至3任一项所述的制作方法，其中，所述液态绝缘材料为旋转涂布玻璃SOG。
  5. 根据权利要求1至4任一项所述的制作方法，其中，所述在所述绝缘层 上设置多个微型发光二极管芯片，包括：
    在所述绝缘层上设置多个半导体器件并对所述多个半导体器件加压加热，以将所述多个半导体器件与所述电路板键合在一起，每个所述半导体器件包括依次层叠在所述绝缘层上的P型电极、空穴产生层、有源层、电子产生层、第一缓冲层和衬底，所述多个半导体器件中的P型电极分别通过对应的通孔内的导电材料与对应的所述驱动电路连接；
    去除所述多个半导体器件中的衬底和缓冲层；
    在所述多个半导体器件的电子产生层上形成N型电极，形成多个微型发光二极管芯片。
  6. 根据权利要求5所述的制作方法，其中，所述P型电极与所述绝缘层相对的表面为焊料层；
    所述对所述多个半导体器件加压加热，以将所述多个半导体器件与所述电路板键合在一起，包括：
    在加热的条件下，在所述多个半导体器件上施加朝向所述绝缘层的压力，直到所述金刚石颗粒嵌入所述P型电极的焊料层中。
  7. 根据权利要求5所述的制作方法，其中，所述衬底为透明衬底，所述去除所述多个半导体器件中的衬底，包括：
    采用激光剥离的方式去除所述多个半导体器件中的衬底。
  8. 根据权利要求7所述的制作方法，其中，所述半导体器件还包括位于所述衬底和所述第一缓冲层之间的激光消耗层，所述激光消耗层由多个多晶层和多个禁带层交替层叠而成，所述多个多晶层的生长温度沿从所述衬底到所述电子产生层的方向逐层升高，所述多个禁带层的禁带宽度沿从所述衬底到所述电子产生层的方向逐层增大。
  9. 根据权利要求8所述的制作方法，其中，所述禁带层的厚度与禁带宽度差值负相关，所述禁带宽度差值为对应的禁带层的禁带宽度与所述有源层中量子阱的禁带宽度的差值的绝对值。
  10. 根据权利要求7至9任一项所述的方法，其中，所述半导体器件还包括位于所述衬底和所述激光消耗层之间的第二缓冲层，所述第二缓冲层的厚度大于所述第一缓冲层的厚度。
  11. 根据权利要求10所述的制作方法，其中，所述第二缓冲层的厚度在0.5微米以上。
  12. 一种微型发光二极管显示阵列，包括电路板(10)和多个微型发光二极管芯片(20)，所述电路板(10)包括基板(11)、驱动电路层(12)和绝缘层(13)，所述驱动电路层(12)和所述绝缘层(13)依次层叠在所述基板(11)上，
    所述绝缘层(13)上设有延伸至所述驱动电路层(12)的通孔，所述通孔内填充有导电材料，所述多个微型发光二极管芯片(20)在所述绝缘层(13)上并通过所述多个通孔中对应的通孔内的导电材料与所述驱动电路层(12)中对应的驱动电路连接，
    所述绝缘层(13)采用混有金刚石颗粒的液态绝缘材料形成。
  13. 根据权利要求12所述的微型发光二极管显示阵列，其中，所述绝缘层未包含金刚石颗粒的部分的厚度小于所述金刚石颗粒的粒径。
  14. 根据权利要求12或13所述的微型发光二极管显示阵列，其中，所述驱动电路层(12)远离所述基板的表面具有焊料层，所述金刚石颗粒中的至少部分颗粒的一部分嵌入所述焊料层中。
  15. 根据权利要求12至14任一项所述的微型发光二极管显示阵列，其中，微型发光二极管芯片包括依次层叠在所述绝缘层上的P型电极、空穴产生层、有源层、电子产生层和N型电极，所述P型电极与所述绝缘层相对的为焊料层，所述金刚石颗粒中的至少部分颗粒的一部分嵌入所述焊料层中。
  16. 根据权利要求12至15任一项所述的微型发光二极管显示阵列，其中，所述液态绝缘材料为旋转涂布玻璃SOG。
  17. 一种微型发光二极管外延片，包括透明衬底(31)和依次层叠在所述透明衬底(31)上的第一缓冲层(32)、电子产生层(33)、有源层(34)和空穴产生层(35)，所述微型发光二极管外延片还包括层叠在所述第一缓冲层(32)和所述透明衬底(31)之间的激光消耗层(40)，所述激光消耗层(40)由多个多晶层(41)和多个禁带层(42)交替层叠而成，所述多个多晶层(41)的生长温度沿从所述透明衬底(31)到所述电子产生层(33)的方向逐层升高，所述多个禁带层(42)的禁带宽度沿从所述透明衬底(31)到所述电子产生层(33)的方向逐层增大。
  18. 根据权利要求17所述的微型发光二极管外延片，其中，所述禁带层的厚度与禁带宽度差值负相关，所述禁带宽度差值为对应的禁带层的禁带宽度与所述有源层中量子阱的禁带宽度的差值的绝对值。
  19. 根据权利要求17或18所述的微型发光二极管外延片，还包括第二缓冲层，所述第二缓冲层层叠在所述透明衬底(31)和所述激光消耗层(40)之间，所述第二缓冲层的厚度大于所述第一缓冲层的厚度。
  20. 根据权利要求19所述的微型发光二极管外延片，其中，所述第二缓冲层的厚度在0.5微米以上。
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