TWI238548B - Light emitting diode and method of making the same - Google Patents

Abstract

A light emitting diode (LED) having two electrodes at the same side and altitude is disclosed. The LED includes a high reflective metal layer therein to reflect those lights emitted from the active layer toward it, an electrical connecting plug, and an isolation channel. The electrical connecting plug connects the first ohmic contact electrode which is buried in the LED structure to the outer surface of the lower cladding layer. The isolation channel spaced the LED from two parts. The first part has the electrical connecting plug and the second part has a second ohmic contact electrode formed on the lower cladding layer. The active layer in the second part actives after a voltage is applied.

Description

1238548 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a light emitting diode (Light Emitting Diode; LED) wafer structure and a manufacturing method thereof, and particularly to an aluminum gallium indium phosphide ( AlGalnP) structure and manufacturing method of light emitting diode. [Prior technology] The traditional aluminum gallium indium light emitting diode has a double heterostructure (Double Heterostructure; DH), and its structure is shown in FIG. 5, which is an n-type gallium (GaAs) substrate (Substrate). On 2 2, a buffer layer 54 is formed first, and then a cladding layer 58 having an aluminum content of 70% to 100% (A1 XG au) 〇51〇 0.5 is formed. 31-i) 〇51. 0.5? Active layer 60, a p-type (AlxGaHUdnuP cladding layer 62 above 70% -100% aluminum content), and a P-type high-gap current spreading layer 64 (Current Spreading Layer). The material can be gallium phosphide, gallium phosphide arsenide, indium gallium phosphide, or shattered gallium, etc. By changing the composition of the active layer 60, the light emitting diode light emission wavelength can be changed, so that the light emitting diode emits light from 6 50 The wavelength from nm red to 5 5 5 nm pure green. However, this traditional light-emitting diode has a disadvantage, that is, the light generated by the active layer is incident on the gallium arsenide substrate 5 2 because the gallium arsenide substrate 5 2 The energy gap is relatively small, so the light incident on the gallium arsenide substrate 52 will be absorbed, and a high-efficiency light-emitting diode cannot be generated. In order to avoid the light absorption of the substrate 54, some literatures have been exposed conventionally.

Page 6 1238548 V. Description of the invention (2) LED technology, however, these technologies have their disadvantages and limitations. For example, Sugawara et al. [Appl. Phys Lett. Vol. 6 Bu 1 775-1 7 7 7 (1 9 9 2)] revealed a method of adding a distributed Bragg reflector 54 (Distributed Bragg Reflector; DBR) in On the gallium arsenide substrate, the light incident on the gallium arsenide substrate is reflected, and the absorption of the gallium arsenide substrate is reduced. However, since the DBR reflective layer 54 can effectively reflect only the light incident on the gallium arsenide substrate perpendicularly, So the effect is not great.

Kish et al. [Appl · Phys Lett. Vol. 64,

The document No. 21, 2839, (19 94), entitled "Very high-f | efficiency semi conductor wafer-bonded transparent-substrate (AlxGahDuInuP / GaP"), reveals a transparent type of wafer bonding Substrate (Transparent-Substrate; TS) (AlxGaduInuP / GaP light-emitting diode. This type of SA 1 G a I η PLED is formed by vapor phase epitaxy (v PE) to form a relatively thick (about 50 / zm) P-type scaled gallium (GaP) window layer, and then using conventional chemical etching method to selectively remove N-type gallium arsenide (GaAs) substrate. Then exposed N-type (AlxGai_x) Q .5InQ 5p lower cladding layer, adhered to the η-type gallium phosphide substrate with a thickness of about 8-10 mi 1. 0 Because this wafer bonding (Wafer Bonding) is a combination of two III-V compound semiconductors It is directly bonded together, so it can be completed by heating and pressing at a higher temperature for a period of time. In terms of luminous brightness, the TS A 1 Gal nP LED prepared in this way is more efficient than traditional absorption substrates

Page 7 1238548 V. Description of the invention (3) (Absorbing-Substrate; AS) AlGaInP LED has more than twice the brightness. However, the disadvantage of this TS A 1 Gal nP LED is that the manufacturing process is too complicated, and usually has a high resistance characteristic of a non-ohmic contact at the bonding interface. Therefore, it is impossible to obtain a high production yield and it is difficult to reduce the manufacturing cost. Another traditional technique, for example, 〇〇 r ng et al. [A p p 1 ·

Phys · Let · ν〇1 · 75, No. 20, 3 0 54 (1 9 9), and the name is "AlGal ηP light-emitting diodes with mirror substrates fabricated by wafer bonding"]. Horng et al. Have disclosed a method for forming a mirror substrate (mirror-substrate; MS) aluminum gallium indium phosphide / metal / silicon dioxide / silicon LED using wafer fusion technology. It uses AuBe / Au as an adhesive material to bond the silicon substrate and the LED stupid layer. However, at an operating current of 20 mA, the luminous intensity of this ms A 1 Gal nP LED is only about 90 mcd, which is still at least 40% lower than that of TS AlGalnP LEDs, so its luminous intensity is not satisfactory. At the same time, the bonded wafers formed by the above methods 丨 丨 丨 —compound semiconductors cannot have electrodes on the same side, and + is suitable for series and parallel use of light-emitting diodes. _ Therefore, another ρ and N electrodes are located on the same side, and the structure is shown in FIG. 6, which includes a buffer layer 54 grown on a GaAs substrate ^ ubStrate 52. The sequence is a P-type (AlxGaJuIn) with a content of 70% to 100%, an active layer of T λ, ^ ^ X a) Q 5 1 η 0.5 P, and an aluminum content of 7000%. cladding layer 62 on sP, a p-type high-gap current

1238548 V. Description of the invention (4) Dispersion layer (Current Spreading Layer) 64. The material of this layer can be phosphide, gallium disc, gallium indium, or gallium. A p-type high-gap current dispersing layer 64 has a P-type ohmic contact electrode 70 and a metal pin layer 74. Another N-type ohmic contact electrode 70 and a metal pin line layer are formed on the light-emitting diode which has been etched into a trench to expose the lower cladding layer 58. The light emitting diode provided by the present invention can solve the above problems. [Summary of the Invention] In summary, the present invention provides a light-emitting diode structure, which includes a multi-layered worm crystal structure having a light-emitting layer, and is combined with a highly thermally conductive substrate through an adhesive layer. The light emitting layer of the diode may be a homostructure (Single heterostructure 'SH), a double heterostructure (DH), or a multiple quantum well structure (Multi quantum we 1 1 s, MQWs). The light emitting diode structure also includes a first ohmic contact metal electrode layer and a second ohmic contact metal electrode layer. The first ohmic contact metal electrode layer is connected to the first metal nail line electrode layer through an electrode connection channel, and the second metal nail line electrode layer is above the first ohmic contact metal electrode layer. The first metal nail electrode layer and the second metal nail electrode layer are located on the same side of the substrate with high thermal conductivity and high reflectivity. And because there are electrode connection channels, the first metal nail electrode layer and the second metal nail electrode layer have the same height level.

Page 9 1238548 V. Description of the invention (5) In addition, the present invention further provides a method for manufacturing the above-mentioned light emitting diode. First, a light emitting diode epitaxial stacked layer is sequentially formed on a temporary substrate, and then a first ohmic contact metal electrode layer and an inter-reflectivity metal layer are formed on the uppermost layer of the system crystal stacked layer. Next, by using an adhesive layer, such as a metal adhesive layer such as In, Au, Ag or other metals, or a resin such as BCB (B-staged bisbenzocyclobutene; BCB), the high reflectance on the epitaxial layer of the light emitting diode is high. The metal reflective layer is combined with a non-conductive dielectric layer on a highly thermally conductive substrate, and then the temporary substrate and the etch stop layer of the light emitting diode are removed. Tightly, two-step button engraving is performed, and the first stage is formed-the electrode connection channel is etched with a channel having a width of about 1 to 3 mi Is, and is etched to the first ohmic contact electrode layer to communicate with the first ohmic contact metal electrode layer. The second / is an isolated trench or isolated island, and the etching width is about 0.2 ~ lmU, Da ^ ▲ ^ ^ points or all of the first-conductive type Lei: layer. The current of the first ohmic contact metal electrode will flow through the activation layer to the second ohmic contact metal electrode, to form a first metal nail wire electrode layer, and let the first metal nail &: The metal electrode layers communicate with each other, and finally a second metal electrode layer and a second metal nailed wire electrode layer are formed. According to one of the advantages of the present invention, the first metal nailed wire electrode layer and the second metal nailed wire are isolated by using a trench or a barrier. Metal nail electrode layers ^ are on the same side and the same height.

1238548 V. Description of the invention (6) Another advantage of the present invention is that it can use the method of isolating trenches or isolating islands, without the traditional rough surface of the entire first etched area, which makes it difficult to identify the conventional direct-line package. Still another advantage of the present invention is that the manufacturing process is simple, so that high-yield and low-cost mass production results can be obtained. Another advantage of the present invention is that after the formation of the first ohmic contact metal electrode layer, better and stable photoelectric characteristics can be obtained through the channel connection. Under the same constant current, there is a smaller voltage, which is better. Current distribution, and better luminous efficiency. [Embodiment] The present invention discloses a light emitting diode structure and a manufacturing method thereof. In order to make the description of the present invention more detailed and complete, reference may be made to the following descriptions in conjunction with the diagrams in FIGS. 1 to 4. First, please refer to FIG. 1. The epitaxial structure of the light-emitting diode of the present invention includes an N-type gallium arsenide (G a As s) substrate 2 that is sequentially stacked. 4. Etching Stop Layer 22, N-type Aluminum Gallium Indium Phosphide (A1XG a Bu X) 〇.5111 (). 5? Clad ((: 13 (1 (1 丨 11)) Layer 2 0 and Aluminum Gallium Indium Phosphide (Six 1 {314) 〇 5 5 η 〇 5P active layer (Ac ti ve Lay er) 1 8, P-type aluminum gallium indium phosphide (A 1 xGa η) 〇5I n 〇5P overlying layer 16 and P-type ohms Ohmic Contact EpitaXial Layer 14. Next, a P-type ohmic contact metal electrode layer 30 is formed on the p-type ohmic contact epitaxial layer 14.

1238548 V. Description of the invention (7) The material of the P-type ohmic contact stupid crystal layer 14 can be Shishenming Ga, Gaoxing Indium, or GaAs, as long as its energy gap is greater than that of active layer 18, it will not absorb The light generated by the active layer, but must have a high carrier concentration to facilitate the formation of ohmic contacts, can be selected as the P-type ohmic contact epitaxial layer i 4. The aluminum content of the above active layer 18 is in the range of χ = 0 to 0.45, and the aluminum content of the upper and lower cladding layers is controlled to be about χ = 〇 · 卜 丨 · 〇. When the content X = 0, the composition of the active layer is Ga () 5lnQ 5P, and the wavelength of the light-emitting diode; I d is about 6 3 5nm. The ratio of the above compounds, such as the active layer (AlxGaix) () 5ln () 5 PMj| is a preferred example, and is not intended to limit the present invention, and the present invention is equally applicable to other ratios. In addition, in the present invention, the structure of the A 丨 Ga j np active layer 丨 8 may be a conventional homostructure (Single Heterostructure), a single heterostructure (Single Heterostructure), or a double heterostructure (Duoble Heterostructure; DH). ) Or Multiple Quantum Well (MQW). In the present invention, the material of the #etched stop layer 22 may be an elemental compound semiconductor, as long as its lattice is often 7 m 24 to avoid differential rows, and the etching rate is 1 = the substrate 24 composed of a gallium arsenide substrate. It can be regarded as an etching process, so it can be used as the etching stopper layer 2 2 by Kunhua.

1238548 V. Description of the invention (8) In the present invention, a preferred material for the etching stop layer 22 may be indium gallium phosphide (I n G a P) or Kunhuaming gallium (a 1 (ja A s)). The etching rate of the n-type scaled aluminum gallium indium lower cladding layer 20 is also much lower than that of the gallium arsenide substrate 24. Therefore, as long as the thickness is thick, another epitaxial layer with a different composition may not be needed. It is used as a money engraving termination layer. Next, a structure as shown in FIG. 2 is provided, which includes an adhesive layer 44, an electrical layer 42, and a thermally conductive substrate 40. The adhesive layer 44 may be a metal adhesive layer, such as In, Au, Ab Ag and other metal or non-metal adhesive layers, such as BCB (B-staged bisbenzocyclobutene; BCB) resin. High thermal conductivity = substrate 40 can be such as silicon (si) wafers, silicon carbide (s + c) wafers , Gallium phosphide (GaP) wafer or Au, Al, Cu metal, etc., and the high reflectivity metal layer, it can be one of Ag, A, Au, etc. Then the P-type ohmic connection has been formed in Figure 1 The light-emitting diode wafer of the point metal electrode layer 30 and the high-conductivity and high-reflectivity substrate 4 of FIG. 2 are adhered by the adhesive layer 44. Good adhesion Insect wafers, then hunt with humid liquid (: sticky 51 ^ 04: 311 20 2: 3 11 20 or 104011: 3 5 11 20 2) rot # to remove the opaque _ gallium arsenide substrate 24 .Etch stop layer 22 if in (jap4

AlGaAs will still absorb light generated by the active layer 18. Therefore, it must also be completely removed with an etchant, or only the portion in contact with the N-type ohmic contact metal electrode layer '36 must be left. Then, two-stage lithography and post-etching techniques are performed to form isolation channels and p-type ohmic contact metal electrode layer 30 electrode connection channels. 1238548 V. Description of the invention (9) First, lithography and etching technology are used to coat the N-type aluminum gallium indium phosphide indium cladding layer 20, break the gallium indium gallium indium activation layer 18, and P-type gallium indium gallium indium. The cladding layer 16 and the P-type ohmic contact worm crystal layer 14 are sequentially engraved from top to bottom to expose an electrode connection channel 3 8 A of the p-type ohmic contact metal electrode layer 30, with a width of about 1 to 3 mi 1. Then 're-use the lithography and surname engraving technique for the second surname engraving from top to bottom to part of the P-type aluminum gallium indium phosphide upper cladding layer 16 (Figure 3) is etched' to form an isolation trench or isolation The island 3 8 B, or the bottom surface of the P-type ohmic contact dummy layer 14 is formed to form an isolation trench or an island 3 8 B (Figure 4), and the etching width is about 0.2 to 1 mi 1.

Next, a photoresist pattern (not shown) is formed to define an N-type ohmic contact metal electrode layer 34 on the N-type aluminum gallium indium phosphide indium cladding layer 20. Please note that the photoresist pattern only has openings in the N-type aluminum gallium indium phosphide indium cladding layer 20 to define the position of the N-type ohmic contact metal electrode layer 34. The rest are covered by a photoresist pattern, including filling the isolation trench or island 3 8 B with the photoresist and the electrode connection channel 3 8 A. Subsequently, an n-type ohmic contact metal electrode layer 34 is formed. Finally, the photoresist and the metal layer formed on the photoresist are removed to define an N-type ohmic contact metal electrode layer 34. ”Subsequently, the method of forming the N-type ohmic contact metal electrode layer 34 is again defined by using a photoresist pattern to define the positions of the two metal pin electrode layers 36 (including the bare N-type ohmic contact metal electrode layer 34). The opening and the exposed part of the n-type aluminum gallium indium phosphide indium cladding layer 20 surrounding the first connection channel 38A and the electrode connection channel 38A are filled with the electrode connection channel 38A. On the exposed N-type aluminum gallium indium phosphide indium cladding layer 20 and on the exposed n-type ohmic contact metal electrode layer 34. Therefore, as shown in the figure, two metal nails are formed.

Page 14 1238548 V. Description of the invention αο) line, the polar layer 36 is on the same side and at the same level south with respect to the highly thermally conductive substrate, as shown in Figures 3 and 4. Finally, annealing is performed to make the N-type ohmic contact metal electrode layer 34 and the lower cladding layer 20 and the P-ohmic contact electrode 30 to form a good ohmic contact with the p-type ohmic contact epitaxial layer. The sequence of steps is not intended to limit the present invention, although anyone skilled in the relevant art may adjust the sequence of steps described above. Example & For example, the formation step of the isolation trench or the isolation island 38B can be moved to the formation of the two metal nailed electrode layers 36 and then performed without changing the diode structure of the present invention. The light wavelength emitted by the aluminum gallium indium light emitting diode obtained according to the present invention is about 635 nm, and its light output power is about 4 mW under an operating current of 20 mA, which is a traditional absorption substrate aluminum gallium indium phosphide light emitting device. The output power of the light wheel of the diode is more than 2 times. The present invention is not limited to high-brightness aluminum gallium indium light emitting diodes. The present invention can also be applied to other light emitting diode materials, such as aluminum gallium red and infrared light emitting diodes. The light-emitting diode of the present invention uses an adhesive layer 44 to join the light-emitting diode and a substrate with high thermal conductivity and high reflectivity 40. Therefore, even if the surface of the light-emitting diode is uneven, the light-emitting diode can be used. The core adhesive layer 44 holds them tightly together. ⑴Using the method of isolating the trench and island, there will be no rough surface of the entire button engraved area, which will cause the problem that the package is not easy to identify.

1238548 V. Description of the invention (11) (2) The voltage can be reduced and the current distribution can be increased under a fixed current to improve the external light emitting efficiency of the light emitting diode. The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of patent application of the present invention. Any other equivalent changes or modifications made without departing from the spirit disclosed by the present invention shall be included in the following Within the scope of patent application.

1238548 on page 16 briefly illustrates the preferred embodiment of the present invention. The following figures will be used to explain in more detail in the following explanatory text: Figures 1 to 4 show a preferred embodiment according to the present invention. Schematic diagram of the manufacturing process of the light-emitting diode; and Figures 5 and 6 are schematic diagrams showing the structure of a traditional light-emitting diode. Figure 5 shows a comparison of the drawing numbers: ❿ 5 2: substrate 5 4: buffer layer 56: dispersed Bragg reflector 5 8 : Lower cladding layer 6 0 ·· active layer 62: upper cladding layer 6 4: high energy gap current dispersion layer 70: P ohm contact metal electrode layer 7 2: N ohm contact metal electrode layer 7 4: metal nail Wire electrode layer 1 4: P-type ohmic contact epitaxial layer 16: P-type aluminum gallium indium phosphide upper cladding layer 18: aluminum gallium indium phosphide active layer 2 0: N-type aluminum gallium indium phosphide Coating 2 2: etch stop layer

Page 17 1238548 Brief description of the drawings 2 4: N-type gallium arsenide substrate 3 0 · P-type ohmic contact metal electrode layer 3 2: High reflectivity metal layer 3 4: N-type ohmic contact metal electrode layer 3 6 : Metal pin electrode layer 38A: Electrode connection channel 3 8 B: Isolated trench or island 4 0 · · Substrate with local thermal conductivity 42: Non-conductive dielectric layer 44: Adhesive layer

Page 18

Claims (1)

1238548 VI. Scope of patent application 1 · A light emitting diode including at least: a cladding layer is sequentially stacked; a first ohmic contact metal electrode layer is formed on the ohmic contact stupid layer light emitting epitaxial multilayer structure, the light emitting epitaxial The multilayer structure includes at least an ohmic contact epitaxial layer, an upper cladding layer, an active layer, and a high reflectivity metal layer formed on the first ohmic contact metal electrode layer and the ohmic contact epitaxial layer. A high thermal conductivity substrate; a dielectric layer formed on the high thermal conductivity substrate; + an adhesive layer which bonds the first ohmic contact metal electrode layer and the non-conductive dielectric layer; A first stud line metal electrode layer and a second ohmic contact metal electrode layer are formed on the lower cladding layer; and the Gan Hai Sx light and sun day and night layer structure has at least an electrode connection channel and an isolation trench formed therein, The electrode connection channel penetrates the light-emitting epitaxial multilayer structure to connect the first ohmic contact metal electrode layer and the first pin-line metal electrode layer, and the isolation trench connects the light-emitting epitaxial multilayer structure. Isolate and deepen the upper cladding layer to make the light-emitting epitaxial multilayer structure into two parts, which are respectively connected to the second ohmic contact metal electrode layer of the light-emitting diode and the first pinned metal electrode. Layer connection. 2. The light-emitting diode according to item 1 in the scope of the patent application, wherein the active layer of the light-emitting epitaxial multilayer structure is homogeneous of aluminum gallium indium phosphide (AlGalnP) Page 19 1238548 6. Scope of patent application One of structure, single heterostructure, double heterostructure or quantum well structure. 3. The light-emitting diode according to item 1 of the scope of patent application, wherein the ohmic contact epitaxial layer is a P-type semiconductor layer, and the first ohmic contact metal electrode layer is a P-type semiconductor layer; the second The ohmic contact metal electrode layer is an N-type semiconductor layer. Φ 4. According to the light-emitting diode described in item 1 of the scope of the patent application, the isolation trench further includes a penetration through the upper cladding layer so that the bottom of the isolation trench reaches the ohmic contact epitaxial layer. 5. The light-emitting diode according to item 1 of the scope of patent application, wherein the substrate is one of an S-Si wafer, a silicon carbide (SiC) wafer, and a gallium phosphide (GaP) wafer. 6. The light-emitting diode according to item 1 of the scope of patent application, wherein the substrate is one of Au, A1, and Cu metal. 7. The light-emitting diode according to item 1 of the scope of patent application, wherein the material of the adhesive layer includes any one of BCB (B-staged bisbenzocyclobutene; BCB) and resin epoxy resin (E p o x y). 8. The light-emitting diode according to item 1 of the scope of patent application, wherein the material of the adhesive layer includes any one of metals such as In, Au, A1. 1238548 p.20 6 'Application for Patent Scope 9 · The light-emitting diode described in item 1 of the patent application scope, wherein the dielectric layer includes aluminum oxide (Al203), silicon dioxide (Si02), or silicon nitride (SiNx) 10. The light-emitting diode according to item 1 of the scope of patent application, wherein the high-reflectivity metal layer is selected from one of metals such as Au, Ag, and the like. 11 · The light-emitting diode according to item 1 of the scope of the patent application, further comprising a second metal pin electrode layer formed on the second ohmic contact metal electrode layer. 1 2 · A method for manufacturing a light-emitting diode, including at least: Tian provides a light-emitting epitaxial multi-spreading structure, the light-emitting epitaxial multilayer structure is sequentially stacked with an ohmic contact epitaxial layer, an upper cladding layer, a An active layer, a lower cladding layer, an etch stop layer, and a temporary substrate; forming a first ohmic contact metal electrode layer on the ohmic contact parasitic layer; an ohmic contact metal electrode layer forming a high reflectivity metal layer on the On the epitaxial layer of the first and ohmic contacts Providing a high thermal conductivity substrate; forming a non-conductive dielectric layer layer on the high thermal conductivity substrate; θ μ ^ adhesive layer bonding the high thermal conductivity substrate conductive type dielectric layer layer and the high reflectivity metal layer and The ohmic contact epitaxial layer; removing the temporary substrate and the stop etch layer; 1238548 6. The scope of the patent application uses lithography and etching techniques to form an electrode connection channel that runs from the lower cladding layer of the light-emitting epitaxial multilayer structure to the P-type ohmic contact metal electrode layer; The lithography and #etching technology form an isolation channel. The isolation channel runs through the light-emitting epitaxial multilayer structure and isolates the island to isolate the material layer passing by the isolation channel into a first part and a second part. The first part includes the electrode. A connection channel; forming a second ohmic contact metal electrode layer on the second part— forming a nail wire metal layer to fill the electrode connection channel to connect the first ohmic contact metal electrode layer and extend to the first A portion of the upper surface of the lower cladding layer forms a first pinned region, and is also formed on the second ohmic contact metal electrode layer to form a second pinned region. 13. The method according to item 12 of the patent application, wherein the second ohmic contact metal electrode layer uses a photoresist pattern to define the position of the first pin line region, and then deposits the metal layer, and then removes the adhesion with tape. The metal layer with poor properties is removed by photoresist. 14. The method according to item 12 of the patent application, wherein the step of forming the second ohmic contact metal electrode layer at least includes using a photoresist pattern to define the position of the first pinned region, and then depositing the second ohmic contact. Metal electrode layer, and then remove the metal layer on the photoresist pattern with tape Page 22 1238548 VI. Patent Application Range 1 5 · The method of item 12 of the patent application range, wherein the step of forming the nailed metal layer includes at least the use of a photoresist pattern to define the position of the second nailed region, and then depositing For the second ohmic contact metal electrode layer, the metal layer on the photoresist pattern is removed by an adhesive tape, and finally the photoresist is removed. 16. The method according to item 12 of the scope of patent application, further comprising performing an annealing step after the formation of the second pin line region and the second pin line region, so that the second ohmic contact metal electrode layer and the The lower cladding layer and the first ohmic contact metal electrode layer and the ohmic contact epitaxial layer form a low resistance ohmic contact. 17. The method according to item 12 of the scope of patent application, wherein the above-mentioned step of forming an isolation channel: further includes etching to stop at the ohmic contact epitaxial layer. 18. The method according to item 12 of the patent application scope, wherein the above-mentioned step of forming the isolation channel can be adjusted after the step of forming the nail metal layer. 19. The method according to item 12 of the scope of patent application, wherein the above-mentioned etching can be dry or wet etching. Page 23