JP2019036662A - Manufacturing method for light-emitting element - Google Patents

Manufacturing method for light-emitting element Download PDF

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JP2019036662A
JP2019036662A JP2017158017A JP2017158017A JP2019036662A JP 2019036662 A JP2019036662 A JP 2019036662A JP 2017158017 A JP2017158017 A JP 2017158017A JP 2017158017 A JP2017158017 A JP 2017158017A JP 2019036662 A JP2019036662 A JP 2019036662A
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石崎 順也
Junya Ishizaki
順也 石崎
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Shin Etsu Handotai Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005Processes
    • H01L33/0093Wafer bonding; Removal of the growth substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
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    • H01L33/0062Processes for devices with an active region comprising only III-V compounds

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Abstract

To provide a manufacturing method for a light-emitting element, by which an unsatisfactory rate of braking is reduced when a light-emitting element is separated from a semiconductor substrate by scribe braking, the semiconductor substrate having a window layer -cum- support substrate not lattice matching.SOLUTION: A manufacturing method for a light-emitting element comprises: forming a light-emitting layer part on a substrate by epitaxial-growing a first semiconductor layer, an active layer, and a second semiconductor layer by use of a lattice matching material; epitaxial-growing a window layer -cum- support substrate by use of a material not lattice matching with the light-emitting layer; removing the substrate; forming a first ohmic electrode; forming a removal part; forming a semiconductor substrate by forming a second ohmic electrode in the removal part; and separating a light-emitting element from the semiconductor substrate by scribe braking. In this method, a groove that is 70 μm or less in the remaining thickness of window layer -cum- support substrate is formed in a surface, opposite the light-emitting layer part formation surface, of the semiconductor substrate, and the light-emitting element is separated by scribe braking.SELECTED DRAWING: Figure 1

Description

本発明は、発光素子の製造方法に関し、特に半導体基板から発光素子をスクライブ・ブレーキングにより分離する工程を含む発光素子の製造方法に関する。   The present invention relates to a method for manufacturing a light emitting element, and more particularly to a method for manufacturing a light emitting element including a step of separating a light emitting element from a semiconductor substrate by scribing and breaking.

チップオンボード(COB)などの製品は、LED素子からの放熱性に優れ、照明等の用途において、採用されるLEDチップ実装方法である。COBなどにLEDを実装する場合、チップを直接ボードに接合するフリップ実装が必須である。フリップ実装を実現するためには、発光素子の一方の面に極性の異なる通電用パッドを設けたフリップチップを作製する必要がある。また、通電用パッドが設けられた面の反対側の面は光取り出し機能を有する材料で構成する必要がある。   Products such as chip-on-board (COB) are excellent in heat dissipation from LED elements, and are LED chip mounting methods employed in applications such as lighting. When mounting an LED on a COB or the like, flip mounting in which a chip is directly bonded to a board is essential. In order to realize flip mounting, it is necessary to manufacture a flip chip in which energization pads having different polarities are provided on one surface of a light emitting element. Further, the surface opposite to the surface provided with the energization pad needs to be made of a material having a light extraction function.

黄色〜赤色LEDでフリップチップを作製する場合、発光層にはAlGaInP系の材料が用いられる。AlGaInP系材料はバルク結晶が存在せず、エピタキシャル法でLED部は形成されるため、出発基板はAlGaInPとは異なる材料が選択される。出発基板はGaAsやGeが選択される場合が多く、これらの基板は可視光に対して光吸収の特性を有するため、フリップチップを作製する場合、出発基板は除去される。   When a flip chip is manufactured using yellow to red LEDs, an AlGaInP-based material is used for the light emitting layer. Since the AlGaInP-based material has no bulk crystal and the LED portion is formed by an epitaxial method, a material different from that of AlGaInP is selected for the starting substrate. In many cases, GaAs or Ge is selected as the starting substrate, and these substrates have a property of absorbing light with respect to visible light. Therefore, when a flip chip is manufactured, the starting substrate is removed.

しかし、発光層を形成するエピタキシャル層は極薄膜のため、出発基板除去後に自立することができない。したがって、発光層に発光波長に対して略透明で窓層としての機能を有し、自立させるために十分の厚さを有する支持基板としての機能を有する材料・構成で、出発基板と置換する必要がある。   However, since the epitaxial layer forming the light emitting layer is an extremely thin film, it cannot stand by itself after the starting substrate is removed. Therefore, it is necessary to replace the starting substrate with a material / structure having a function as a support substrate having a thickness sufficient to make the light emitting layer substantially transparent to the emission wavelength and function as a window layer and to be self-supporting. There is.

窓層兼支持基板の機能を有する置換材料として、GaP,GaAsP,サファイアなどが選択される。前記いずれの材料を選択しても、AlGaInP系材料と異なる材料であるため、格子定数、熱膨張係数やヤング率などの機械的特性はAlGaInP系材料とは異なる。   GaP, GaAsP, sapphire, or the like is selected as a replacement material having a window layer / supporting substrate function. Whichever material is selected, since it is a different material from the AlGaInP-based material, mechanical properties such as lattice constant, thermal expansion coefficient and Young's modulus are different from those of the AlGaInP-based material.

このような技術として、特許文献1には窓層兼支持基板としてGaPを結晶成長して形成する方法が開示されている。   As such a technique, Patent Document 1 discloses a method of forming GaP by crystal growth as a window layer and supporting substrate.

ここで、従来のフリップチップ構造の発光素子の製造方法の一例を図3(a)〜(d)を使って説明する。   Here, an example of a method for manufacturing a conventional light emitting element having a flip chip structure will be described with reference to FIGS.

AlGaInP系エピタキシャルウェーハを製造する場合、最初に、図3(a)に示すように、出発基板300として、例えば[001]方向に15度傾斜したGaAs基板を準備する。次いで、GaAs基板300上に有機金属気相成長(MOVPE)法にて、(AlGa1−xIn1−yP(0≦x≦1,0.4≦y≦0.6)からなる第一半導体層(Nクラッド層)301、(AlGa1−xIn1−yP(0≦x≦1,0.4≦y≦0.6)からなる活性層302、(AlGa1−xIn1−yP(0≦x≦1,0.4≦y≦0.6)からなる第二半導体層(Pクラッド層)303を積層し、発光層部307とする。次いで、GaIn1−yP(0.0≦y≦1.0)からなる中間組成層304、0.5μm以上の厚さを有するGaP窓層305を順次積層する。これらの作製方法はMOVPE法に限定されるものではなく、分子線エピタキシー(MBE)法や、化学線エピタキシー(CBE)法で作製しても良い。 When manufacturing an AlGaInP-based epitaxial wafer, first, as shown in FIG. 3A, for example, a GaAs substrate inclined by 15 degrees in the [001] direction is prepared as a starting substrate 300. Next, (Al x Ga 1-x ) y In 1-y P (0 ≦ x ≦ 1, 0.4 ≦ y ≦ 0.6) is formed on the GaAs substrate 300 by metal organic chemical vapor deposition (MOVPE). A first semiconductor layer (N clad layer) 301 made of, an active layer 302 made of (Al x Ga 1-x ) y In 1-y P (0 ≦ x ≦ 1, 0.4 ≦ y ≦ 0.6), A second semiconductor layer (P clad layer) 303 made of (Al x Ga 1-x ) y In 1-y P (0 ≦ x ≦ 1, 0.4 ≦ y ≦ 0.6) is laminated, and the light emitting layer portion 307. Next, an intermediate composition layer 304 made of Ga y In 1-y P (0.0 ≦ y ≦ 1.0) and a GaP window layer 305 having a thickness of 0.5 μm or more are sequentially stacked. These production methods are not limited to the MOVPE method, and may be produced by a molecular beam epitaxy (MBE) method or a chemical beam epitaxy (CBE) method.

次に、GaP窓層305に接してGaAs1−z(0.0≦z≦0.1)からなる窓層兼支持基板306を形成する。窓層兼支持基板306はMOVPE法あるいはMBE法により形成することも可能だが、安価で成長速度も速いハイドライド気相成長(HVPE)法を好適に用いることができる。厚さは例えば100μm程度とすることができる。 Next, a window layer / support substrate 306 made of GaAs z P 1-z (0.0 ≦ z ≦ 0.1) is formed in contact with the GaP window layer 305. Although the window layer / support substrate 306 can be formed by the MOVPE method or the MBE method, a hydride vapor phase epitaxy (HVPE) method that is inexpensive and has a high growth rate can be preferably used. The thickness can be about 100 μm, for example.

次に、図3(b)に示すように窓層兼支持基板306形成後、化学的エッチングによりAlGaInP系エピタキシャルウェーハのGaAs基板300を除去したウェーハ031を形成する。化学的エッチング液はAlGaInP系材料とエッチング選択性があるものが好ましく、一般にはアンモニア含有エッチャントで除去する。   Next, as shown in FIG. 3B, after the window layer / support substrate 306 is formed, a wafer 031 is formed by removing the GaAs substrate 300 of the AlGaInP-based epitaxial wafer by chemical etching. The chemical etchant preferably has an etching selectivity with respect to the AlGaInP-based material, and is generally removed with an ammonia-containing etchant.

次に、図3(c)に示すようにGaAs基板除去後、ウェーハ031の第一半導体層(下部クラッド層)301上に第一オーミック電極351を形成し、少なくとも第一半導体層(下部クラッド層)301と活性層302の一部を切り欠いた領域(除去部)320を形成した後に、除去部320の一部に第二オーミック電極361を形成する。   Next, as shown in FIG. 3C, after removing the GaAs substrate, a first ohmic electrode 351 is formed on the first semiconductor layer (lower cladding layer) 301 of the wafer 031, and at least the first semiconductor layer (lower cladding layer) is formed. ) After forming a region (removal part) 320 in which a part of 301 and the active layer 302 are cut out, a second ohmic electrode 361 is formed on a part of the removal part 320.

次に、第一半導体層(下部クラッド層)301の、領域(除去部)320以外の領域(非除去部)310のうち、第一オーミック電極351を有しない領域311の少なくとも一部には誘電体部340を設けることができる。また、領域310と領域320の間にある段差部330の少なくとも一部にも誘電体部341を設けることができる。そして領域320のうち、第二オーミック電極361以外の領域321の少なくとも一部には誘電体部342を設けた半導体基板A03を得る。   Next, among the regions (non-removed portions) 310 other than the region (removed portion) 320 of the first semiconductor layer (lower cladding layer) 301, at least part of the region 311 that does not have the first ohmic electrode 351 is dielectric. A body portion 340 can be provided. In addition, the dielectric portion 341 can be provided in at least a part of the step portion 330 between the region 310 and the region 320. In the region 320, a semiconductor substrate A03 provided with a dielectric portion 342 in at least a part of the region 321 other than the second ohmic electrode 361 is obtained.

また、図3(c)では、誘電体部340、341、342全てを有する場合を例示しているが、全てを有する必要はなく、一部のみを有する場合であっても、同様の効果が得られる。また、領域311において、誘電体部340しか有しない構造を例示しているが、誘電体部340と第一半導体層301の領域311との間に光反射膜あるいは光反射部を設けても良く、あるいは、誘電体部340の第一半導体層301の領域311に接しない面側に光反射膜あるいは光反射部を設けてもよい。   FIG. 3C illustrates the case where all of the dielectric portions 340, 341, and 342 are provided. However, it is not necessary to include all of the dielectric portions 340, 341, and 342. can get. Further, although the structure having only the dielectric portion 340 is illustrated in the region 311, a light reflecting film or a light reflecting portion may be provided between the dielectric portion 340 and the region 311 of the first semiconductor layer 301. Alternatively, a light reflecting film or a light reflecting portion may be provided on the surface of the dielectric portion 340 that does not contact the region 311 of the first semiconductor layer 301.

また、領域311において、平坦な面を有する場合を例示しているが、凹凸を有する面を有していてもよい。凹凸を有する面に関しては、ウェットエッチングによる単純粗面、ファセット面を有するファセット粗面、数十μm〜数百nmのピッチを有するフォトリソによるパターン化されたパターン化粗面、数〜数百nmのピッチのトレンチ形状を有するフォトニック粗面とすることができる。   Further, although the case where the region 311 has a flat surface is illustrated, the region 311 may have a surface having unevenness. As for the surface having irregularities, a simple rough surface by wet etching, a faceted rough surface having a facet surface, a patterned rough surface patterned by photolithography having a pitch of several tens of μm to several hundreds of nm, and several to several hundreds of nanometers It can be a photonic rough surface having a pitch trench shape.

また、段差部330、領域(除去部)320及び窓層兼支持基板306は凹凸の無いフラットな面を例示しているが、凹凸を有する面であってもよい。凹凸を有する面に関しては、ウェットエッチングによる単純粗面、ファセット面を有するファセット粗面、数十μm〜数百nmのピッチを有するフォトリソによるパターン化されたパターン化粗面、数〜数百nmのピッチのトレンチ形状を有するフォトニック粗面のいずれであってもよい。また、窓層兼支持基板306表面に何も膜がない構造を示しているが、誘電体から成る反射防止膜を設けてもよい。   Further, although the stepped portion 330, the region (removal portion) 320, and the window layer / support substrate 306 are illustrated as flat surfaces without unevenness, they may be uneven surfaces. As for the surface having irregularities, a simple rough surface by wet etching, a faceted rough surface having a facet surface, a patterned rough surface patterned by photolithography having a pitch of several tens of μm to several hundreds of nm, and several to several hundreds of nanometers Any of photonic rough surfaces having a trench shape with a pitch may be used. Further, although a structure in which there is no film on the surface of the window layer / supporting substrate 306 is shown, an antireflection film made of a dielectric may be provided.

次に、図3(d)に示すように半導体基板A03の第二の面03B面において、ブレーキング予備線381に沿って、スクライブ痕382を付けるスクライブ処理を行う。スクライブ処理は例えば4ポイントのダイヤモンドヘッドを用い、荷重50gにて行なうことができる。スクライブ条件は前述の条件に限定されるものではなく、多ポイントあるいは少ポイントのヘッドを用いても良く、荷重もこの数値に限定されるものでない。   Next, as shown in FIG. 3D, a scribing process is performed on the second surface 03B of the semiconductor substrate A03 along the braking spare line 381 to make a scribe mark 382. The scribing process can be performed using, for example, a 4-point diamond head and a load of 50 g. The scribing conditions are not limited to the above-mentioned conditions. A multi-point or small-point head may be used, and the load is not limited to this value.

また、ダイヤモンドヘッドに限定されず、レーザーアブレーション法によってスクライブを行ってもよい。レーザーアブレーション法を採用する場合、例えば波長355nm、出力0.5Wのレーザーを用いて、スクライブ処理を行うことができる。   The scribing may be performed by a laser ablation method without being limited to the diamond head. When the laser ablation method is employed, for example, a scribing process can be performed using a laser having a wavelength of 355 nm and an output of 0.5 W.

スクライブ処理後、第二の面03B表面に保護シートを乗せ、保護シート面と反対側の面(第一の面03A)から刃を当ててブレーキング処理を実施し、ダイス化して、発光素子を分離することにより、発光素子を製造する。   After the scribing process, the protective sheet is placed on the surface of the second surface 03B, the blade is applied from the surface opposite to the protective sheet surface (first surface 03A), the braking process is performed, and the light emitting element is formed by dicing. A light emitting element is manufactured by separating.

特開2015−005551号公報JP2015-005551A

ところで、窓層兼支持基板をGaP等の格子不整合系の材料で形成した半導体基板では、スクライブ・ブレーキングによるダイス化を行う場合、GaP等の窓層兼支持基板に元々高密度の結晶欠陥(転位)があるため、スクライブ程度の物理力では欠陥線を延ばしづらく、結果としてブレーキング不良ダイスが多発する。   By the way, in a semiconductor substrate in which the window layer / support substrate is formed of a lattice mismatched material such as GaP, when performing dicing by scribing / braking, high density crystal defects are originally formed on the window layer / support substrate such as GaP. Since there is (dislocation), it is difficult to extend the defect line with a physical force of the scribe level, and as a result, many braking failures dies occur.

ブレーキング不良の発生頻度を下げるためには、ブレーキング時に印加する圧力を上げることで、発生頻度を下げることはできるが、欠陥線に基づかない“割れ・破壊”処理になるため、良品率の向上にはつながらない。   In order to reduce the occurrence frequency of braking failures, the frequency of occurrence can be reduced by increasing the pressure applied during braking, but the “cracking / destruction” process is not based on defective lines. It does not lead to improvement.

本発明は上記課題に鑑みてなされたもので、格子不整合系のGaP等の窓層兼支持基板を有する半導体基板から発光素子をスクライブ・ブレーキングにより分離する際、ブレーキング不良率を低減することができる発光素子の製造方法を提供することを目的とする。   The present invention has been made in view of the above problems, and reduces the braking failure rate when a light emitting element is separated from a semiconductor substrate having a window layer / supporting substrate such as a lattice mismatched GaP by scribe / braking. An object of the present invention is to provide a method for manufacturing a light emitting device.

上記目的を達成するために、本発明によれば、基板上に、該基板と格子整合系の材料で少なくとも第一半導体層、活性層、第二半導体層を順次エピタキシャル成長により成長させて発光層部を形成する工程と、該発光層部と格子不整合系の材料で窓層兼支持基板を前記発光層部上にエピタキシャル成長させる窓層兼支持基板形成工程と、前記基板を除去する工程と、前記第一半導体層表面に第一オーミック電極を形成する工程と、少なくとも前記第一半導体層と前記活性層を除去して除去部を形成する工程と、前記除去部の前記第二半導体層または窓層兼支持基板上に第二オーミック電極を形成する工程により、前記窓層兼支持基板上に、少なくとも、前記除去部以外の発光層部と、前記第一オーミック電極、及び前記第二オーミック電極を有する半導体基板を製造し、その後、該半導体基板から、スクライブ・ブレーキングにより発光素子を分離することにより発光素子を製造する発光素子の製造方法において、
前記発光素子の分離を、前記半導体基板の前記発光層部形成面側とは反対側の表面に、前記窓層兼支持基板における残り厚さが70μm以下となる溝を形成し、その後、前記半導体基板の前記発光層部形成面側から、前記半導体基板の表面に前記溝に沿ってスクライブ痕を付け、前記半導体基板に垂直な力を前記溝の全長または一部に加えることで発光素子を分離することを特徴とする発光素子の製造方法を提供する。
In order to achieve the above object, according to the present invention, at least a first semiconductor layer, an active layer, and a second semiconductor layer are sequentially grown by epitaxial growth on a substrate with a lattice-matching material with the substrate. Forming a window layer / support substrate epitaxially on the light emitting layer portion using a material having a lattice mismatch with the light emitting layer portion, removing the substrate, and Forming a first ohmic electrode on the surface of the first semiconductor layer; removing at least the first semiconductor layer and the active layer to form a removal portion; and the second semiconductor layer or window layer of the removal portion. By the step of forming a second ohmic electrode on the supporting substrate, at least the light emitting layer portion other than the removing portion, the first ohmic electrode, and the second ohmic electrode are formed on the window layer supporting substrate. A semiconductor substrate of manufacture, then, from the semiconductor substrate, in the manufacturing method of the light emitting element for producing a light emitting device by separating the light emitting element by scribing braking,
The light emitting element is separated by forming a groove with a remaining thickness of 70 μm or less in the window layer / supporting substrate on the surface of the semiconductor substrate opposite to the light emitting layer portion forming surface side, and then the semiconductor A light-emitting element is separated by making a scribe mark along the groove on the surface of the semiconductor substrate from the light-emitting layer portion forming surface side of the substrate and applying a force perpendicular to the semiconductor substrate to the entire length or a part of the groove. A method for manufacturing a light-emitting element is provided.

このような発光素子の製造方法であれば、半導体基板の前記発光層部形成面側とは反対側の表面に、窓層兼支持基板における残り厚さが70μm以下となる溝を形成することで、発光層部と格子不整合系の材料で窓層兼支持基板をエピタキシャル成長した場合であっても、スクライブ・ブレーキング工程での不良率を低下させることができる。   With such a method of manufacturing a light emitting element, a groove having a remaining thickness of 70 μm or less in the window layer / supporting substrate is formed on the surface of the semiconductor substrate opposite to the light emitting layer portion forming surface. Even when the window layer / supporting substrate is epitaxially grown with a material mismatched with the light emitting layer, the defect rate in the scribe / braking process can be reduced.

またこの場合、前記溝を、湿式エッチングまたはドライエッチングにより形成することが好ましい。   In this case, the groove is preferably formed by wet etching or dry etching.

これらの方法によれば、確実に所望の深さの溝を形成することができる。   According to these methods, a groove having a desired depth can be reliably formed.

本発明の発光素子の製造方法であれば、格子不整合系のGaP等の窓層兼支持基板を有する半導体基板から発光素子をスクライブ・ブレーキングにより分離する際、ブレーキング不良率を低減させることができ、高品質の発光素子を生産性良く製造することができる。   With the method for manufacturing a light emitting device of the present invention, when separating the light emitting device from a semiconductor substrate having a window layer and supporting substrate such as a lattice mismatched GaP by scribe and braking, the braking failure rate is reduced. Thus, a high-quality light-emitting element can be manufactured with high productivity.

本発明の発光素子の製造方法の第一の実施形態を示した概略図である。It is the schematic which showed 1st embodiment of the manufacturing method of the light emitting element of this invention. 本発明の発光素子の製造方法の第二の実施形態を示した概略図である。It is the schematic which showed 2nd embodiment of the manufacturing method of the light emitting element of this invention. 従来の発光素子の製造方法を示した概略図である。It is the schematic which showed the manufacturing method of the conventional light emitting element. 実施例1〜10、及び比較例1〜6について窓層兼支持基板における溝の残り厚さとスクライブ・ブレーキングによる不良率(%)の関係を示したグラフである。It is the graph which showed the relationship between the remaining thickness of the groove | channel in a window layer and support substrate, and the defect rate (%) by scribe braking about Examples 1-10 and Comparative Examples 1-6. 実施例11〜20、及び比較例7〜16について窓層兼支持基板における溝の残り厚さとスクライブ・ブレーキングによる不良率(%)の関係を示したグラフである。It is the graph which showed the relationship between the residual thickness of the groove | channel in a window layer and support substrate, and the defect rate (%) by scribe braking about Examples 11-20 and Comparative Examples 7-16.

上述したように、窓層兼支持基板をGaP等の格子不整合系の材料で形成した半導体基板では、スクライブ・ブレーキングによるダイス化を行う場合、GaP等の窓層兼支持基板に元々高密度の結晶欠陥(転位)があるため、スクライブ程度の物理力では欠陥線を延ばしづらく、結果としてブレーキング不良ダイスが多発するという問題があった。   As described above, in a semiconductor substrate in which the window layer / support substrate is formed of a lattice-mismatched material such as GaP, when dicing is performed by scribing / braking, the window layer / support substrate such as GaP originally has a high density. Therefore, there is a problem in that it is difficult to extend the defect line with a physical force of a scribe level, resulting in frequent occurrence of braking failure dies.

そこで、本発明者はこのような問題を解決すべく鋭意検討を重ねた。その結果、半導体基板の前記発光層部形成面側とは反対側の表面に、前記窓層兼支持基板における残り厚さが70μm以下となる溝を形成し、その後、スクライブ・ブレーキングによるダイス化を行えば、ダイス化による不良率を低下させることができることを見出し、本発明を完成させた。   Therefore, the present inventor has intensively studied to solve such problems. As a result, a groove having a remaining thickness of 70 μm or less in the window layer / supporting substrate is formed on the surface of the semiconductor substrate opposite to the light emitting layer portion forming surface side, and then diced by scribe braking. As a result, it was found that the defect rate due to dicing can be reduced, and the present invention has been completed.

即ち、本発明は、基板上に、該基板と格子整合系の材料で少なくとも第一半導体層、活性層、第二半導体層を順次エピタキシャル成長により成長させて発光層部を形成する工程と、該発光層部と格子不整合系の材料で窓層兼支持基板を前記発光層部上にエピタキシャル成長させる窓層兼支持基板形成工程と、前記基板を除去する工程と、前記第一半導体層表面に第一オーミック電極を形成する工程と、少なくとも前記第一半導体層と前記活性層を除去して除去部を形成する工程と、前記除去部の前記第二半導体層または窓層兼支持基板上に第二オーミック電極を形成する工程により、前記窓層兼支持基板上に、少なくとも、前記除去部以外の発光層部と、前記第一オーミック電極、及び前記第二オーミック電極を有する半導体基板を製造し、その後、該半導体基板から、スクライブ・ブレーキングにより発光素子を分離することにより発光素子を製造する発光素子の製造方法において、
前記発光素子の分離を、前記半導体基板の前記発光層部形成面側とは反対側の表面に、前記窓層兼支持基板における残り厚さが70μm以下となる溝を形成し、その後、前記半導体基板の前記発光層部形成面側から、前記半導体基板の表面に前記溝に沿ってスクライブ痕を付け、前記半導体基板に垂直な力を前記溝の全長または一部に加えることで発光素子を分離することを特徴とする発光素子の製造方法である。
That is, the present invention includes a step of sequentially forming at least a first semiconductor layer, an active layer, and a second semiconductor layer by epitaxial growth on a substrate using a lattice-matching material with the substrate to form a light emitting layer portion, and the light emission. A window layer / support substrate forming step of epitaxially growing a window layer / support substrate on the light emitting layer portion with a layer mismatched material and a layer mismatching material; a step of removing the substrate; and a first surface on the first semiconductor layer surface A step of forming an ohmic electrode; a step of removing at least the first semiconductor layer and the active layer to form a removed portion; and a second ohmic on the second semiconductor layer or window layer / support substrate of the removed portion. By forming an electrode, on the window layer and supporting substrate, at least a light emitting layer portion other than the removal portion, the first ohmic electrode, and the semiconductor substrate having the second ohmic electrode are manufactured, After, from the semiconductor substrate, in the manufacturing method of the light emitting element for producing a light emitting device by separating the light emitting element by scribing braking,
The light emitting element is separated by forming a groove with a remaining thickness of 70 μm or less in the window layer / supporting substrate on the surface of the semiconductor substrate opposite to the light emitting layer portion forming surface side, and then the semiconductor A light-emitting element is separated by making a scribe mark along the groove on the surface of the semiconductor substrate from the light-emitting layer portion forming surface side of the substrate and applying a force perpendicular to the semiconductor substrate to the entire length or a part of the groove. A method of manufacturing a light-emitting element.

以下、本発明の第一の実施形態と第二の実施形態について、図を参照しながら更に詳細に説明するが、本発明はこれに限定されるものではない。なお、第一の実施形態と第二の実施形態は、溝の形成方法が異なるだけであり、それ以外の工程は基本的に同じ方法で行うことができる。まず、第一の実施形態と第二の実施形態の前半の共通な工程について図1(a)〜(c)、図2(a)〜(c)を用いて説明する。   Hereinafter, the first embodiment and the second embodiment of the present invention will be described in more detail with reference to the drawings, but the present invention is not limited thereto. Note that the first embodiment and the second embodiment differ only in the groove formation method, and the other steps can be basically performed by the same method. First, common steps in the first half of the first embodiment and the second embodiment will be described with reference to FIGS. 1 (a) to 1 (c) and FIGS. 2 (a) to 2 (c).

最初に、図1(a)及び図2(a)に示すように、AlGaInP系エピタキシャルウェーハを作製する場合、例えば[001]方向に15度傾斜したGaAs等の出発基板100,200を準備する。   First, as shown in FIGS. 1A and 2A, when an AlGaInP-based epitaxial wafer is manufactured, starting substrates 100 and 200 such as GaAs inclined by 15 degrees in the [001] direction are prepared.

次いで、基板100,200上に、基板100,200と格子整合系の材料で、少なくとも第一半導体層101,201、活性層102,202、第二半導体層103,203を順次エピタキシャル成長により成長させて発光層部107,207を形成する。   Next, at least the first semiconductor layers 101 and 201, the active layers 102 and 202, and the second semiconductor layers 103 and 203 are sequentially grown by epitaxial growth on the substrates 100 and 200 using a material that is lattice-matched with the substrates 100 and 200. The light emitting layer portions 107 and 207 are formed.

具体的には、基板100,200としてGaAs基板を使用した場合には、GaAs基板上に、有機金属気相成長(MOVPE)法により、(AlGa1−xIn1−yP(0≦x≦1,0.4≦y≦0.6)からなるNクラッド層(第一半導体層)101,201、(AlGa1−xIn1−yP(0≦x≦1,0.4≦y≦0.6)からなる活性層102,202、(AlGa1−xIn1−yP(0≦x≦1,0.4≦y≦0.6)からなるPクラッド層(第二半導体層)103,203を順次エピタキシャル成長により成長させて発光層部107,207を形成する。次いで、GaIn1−yP(0.0≦y≦1.0)から成る中間組成層104,204、0.5μm以上の厚さを有するGaPからなる窓層105,205を順次積層することができる。 Specifically, when a GaAs substrate is used as the substrates 100 and 200, (Al x Ga 1-x ) y In 1-y P () is formed on the GaAs substrate by metal organic vapor phase epitaxy (MOVPE). N clad layers (first semiconductor layers) 101, 201 composed of 0 ≦ x ≦ 1, 0.4 ≦ y ≦ 0.6), (Al x Ga 1-x ) y In 1-y P (0 ≦ x ≦ 1, 0.4 ≦ y ≦ 0.6), (Al x Ga 1−x ) y In 1−y P (0 ≦ x ≦ 1, 0.4 ≦ y ≦ 0.6) P-cladding layers (second semiconductor layers) 103 and 203 made of) are sequentially grown by epitaxial growth to form light emitting layer portions 107 and 207. Next, intermediate composition layers 104 and 204 made of Ga y In 1-y P (0.0 ≦ y ≦ 1.0) and window layers 105 and 205 made of GaP having a thickness of 0.5 μm or more are sequentially stacked. be able to.

これらの作製方法はMOVPE法に限定されるものではなく、分子線エピタキシー(MBE)法や、化学線エピタキシー(CBE)法で作製しても良い。   These production methods are not limited to the MOVPE method, and may be produced by a molecular beam epitaxy (MBE) method or a chemical beam epitaxy (CBE) method.

次いで、発光層部107,207と格子不整合系の材料で窓層兼支持基板106,206を発光層部上にエピタキシャル成長させる。具体的には、GaP窓層105,205に接して、発光層部107,207と格子不整合系であるGaAs1−z(0.0≦z≦0.1)窓層兼支持基板106,206をエピタキシャル成長させることで、窓層兼支持基板106,206を発光層部107,207上に形成することができる。窓層兼支持基板106,206はMOVPE法あるいはMBE法により形成することも可能だが、安価で成長速度も速いハイドライド気相成長(HVPE)法を好適に用いることができる。厚さは20〜200μm、例えば100μm程度とすることができる。 Next, the window layer / supporting substrates 106 and 206 are epitaxially grown on the light emitting layer portion using a material having a lattice mismatch with the light emitting layer portions 107 and 207. Specifically, the light emitting layer portions 107 and 207 are in contact with the GaP window layers 105 and 205, and the lattice mismatching system GaAs z P 1-z (0.0 ≦ z ≦ 0.1) window layer and supporting substrate. The window layer / support substrates 106 and 206 can be formed on the light emitting layer portions 107 and 207 by epitaxially growing the layers 106 and 206. Although the window layer / supporting substrates 106 and 206 can be formed by the MOVPE method or the MBE method, a hydride vapor phase epitaxy (HVPE) method which is inexpensive and has a high growth rate can be preferably used. The thickness can be 20 to 200 μm, for example, about 100 μm.

窓層兼支持基板106,206形成後、図1(b)及び図2(b)に示すように、基板100,200を除去する工程を行う。例えば、化学的エッチングによりAlGaInP系エピタキシャルウェーハのGaAs基板100,200を除去し、ウェーハ011,021を形成する。化学的エッチング液はAlGaInP系材料とエッチング選択性があるものが好ましく、一般にはアンモニア含有エッチャントで除去する。   After the window layer / supporting substrates 106 and 206 are formed, a step of removing the substrates 100 and 200 is performed as shown in FIGS. 1 (b) and 2 (b). For example, the GaAs substrates 100 and 200 of the AlGaInP-based epitaxial wafer are removed by chemical etching to form wafers 011 and 021. The chemical etchant preferably has an etching selectivity with respect to the AlGaInP-based material, and is generally removed with an ammonia-containing etchant.

次に、図1(c)及び図2(c)に示すように、基板100,200を除去後、ウェーハ011,021の下部クラッド層(第一半導体層)101,201上に第一オーミック電極151,251を形成し、次いで、少なくとも第一半導体層101,201と活性層102,202を除去して除去部120,220を形成し、除去部120,220の第二半導体層103,203または窓層兼支持基板106,206上に第二オーミック電極161,261を形成する。   Next, as shown in FIGS. 1C and 2C, after removing the substrates 100 and 200, the first ohmic electrode is formed on the lower clad layers (first semiconductor layers) 101 and 201 of the wafers 011 and 021. 151, 251 is formed, and then at least the first semiconductor layers 101, 201 and the active layers 102, 202 are removed to form removed portions 120, 220, and the second semiconductor layers 103, 203 of the removed portions 120, 220 or Second ohmic electrodes 161 and 261 are formed on the window / support substrates 106 and 206.

次に、非除去部(除去部120,220以外の領域)110,210のうち、第一オーミック電極151,251を有しない領域111,211の少なくとも一部には誘電体部140,240を設けることができる。   Next, among the non-removed portions (regions other than the removed portions 120 and 220) 110 and 210, the dielectric portions 140 and 240 are provided in at least a part of the regions 111 and 211 that do not have the first ohmic electrodes 151 and 251. be able to.

また、非除去部110,210と除去部120,220の間にある段差部130,230の少なくとも一部にも誘電体部141,241を設けることができる。   In addition, the dielectric portions 141 and 241 can be provided on at least part of the step portions 130 and 230 between the non-removal portions 110 and 210 and the removal portions 120 and 220.

そして除去部120,220のうち、第二オーミック電極161,261以外の領域121,221の少なくとも一部には誘電体部142,242を設けることができる。以上のように製造された半導体基板A01,A02は、窓層兼支持基板106,206上に、少なくとも、前記除去部120,220以外の発光層部107,207と、前記第一オーミック電極151,251、及び第二オーミック電極161,261を有するものである。   Dielectric portions 142 and 242 may be provided in at least a part of the regions 121 and 221 other than the second ohmic electrodes 161 and 261 in the removal portions 120 and 220. The semiconductor substrates A01 and A02 manufactured as described above are formed on the window layer / support substrates 106 and 206, at least the light emitting layer portions 107 and 207 other than the removal portions 120 and 220, and the first ohmic electrode 151, 251 and second ohmic electrodes 161 and 261.

本実施形態においては、誘電体部140,240、141,241、142,242全てを有する場合を例示しているが、全てを有する必要はなく、一部のみを有する場合であっても、同様の効果が得られる。また、本実施形態においては、第一半導体層101,201の領域111,211において、誘電体部140,240しか有しない構造を例示しているが、誘電体部140,240と第一半導体層101,201の領域111,211との間に光反射膜あるいは光反射部を設けても良く、あるいは、誘電体部140,240の第一半導体層101,201の領域111,211に接しない面側に光反射膜あるいは光反射部を設けてもよい。   In the present embodiment, the case where all of the dielectric portions 140, 240, 141, 241, 142, and 242 are illustrated is illustrated, but it is not necessary to have all, and even if only a portion is included, the same The effect is obtained. Further, in the present embodiment, the structure including only the dielectric portions 140 and 240 in the regions 111 and 211 of the first semiconductor layers 101 and 201 is illustrated, but the dielectric portions 140 and 240 and the first semiconductor layer are illustrated. A light reflecting film or a light reflecting portion may be provided between the regions 111 and 211 of the 101 and 201, or the surfaces of the dielectric portions 140 and 240 that do not contact the regions 111 and 211 of the first semiconductor layers 101 and 201. A light reflecting film or a light reflecting portion may be provided on the side.

また、本実施形態においては、領域111,211において、平坦な面を有する場合を例示しているが、凹凸を有する面を有していてもよい。凹凸を有する面に関しては、ウェットエッチングによる単純粗面、ファセット面を有するファセット粗面、数十μm〜数百nmのピッチを有するフォトリソによるパターン化されたパターン化粗面、数〜数百nmのピッチのトレンチ形状を有するフォトニック粗面とすることができる。   Moreover, in this embodiment, although the area | regions 111 and 211 have illustrated the case where it has a flat surface, you may have the surface which has an unevenness | corrugation. As for the surface having irregularities, a simple rough surface by wet etching, a faceted rough surface having a facet surface, a patterned rough surface patterned by photolithography having a pitch of several tens of μm to several hundreds of nm, and several to several hundreds of nanometers It can be a photonic rough surface having a pitch trench shape.

また、本実施形態においては、段差部130,230、除去部120,220及び窓層兼支持基板106,206は凹凸の無いフラットな面を例示しているが、凹凸を有する面であってもよい。凹凸を有する面に関しては、ウェットエッチングによる単純粗面、ファセット面を有するファセット粗面、数十μm〜数百nmのピッチを有するフォトリソによるパターン化されたパターン化粗面、数〜数百nmのピッチのトレンチ形状を有するフォトニック粗面いずれの場合も含まれる。   Further, in the present embodiment, the stepped portions 130 and 230, the removing portions 120 and 220, and the window layer / supporting substrates 106 and 206 are illustrated as flat surfaces without unevenness, but even with uneven surfaces. Good. As for the surface having irregularities, a simple rough surface by wet etching, a faceted rough surface having a facet surface, a patterned rough surface patterned by photolithography having a pitch of several tens of μm to several hundreds of nm, and several to several hundreds of nanometers The case of any photonic rough surface having a trench shape with a pitch is included.

また、窓層兼支持基板106,206表面に何も膜がない構造を示しているが、誘電体から成る反射防止膜を設けてもよい。   In addition, although a structure in which there is no film on the surface of the window / supporting substrates 106 and 206 is shown, an antireflection film made of a dielectric may be provided.

ここまでは第一実施形態及び第二実施形態は全く同じ工程となる。その後、図1(d)、(e)、図2(d)、(e)のように、半導体基板A01,A02の前記発光層部形成面側とは反対側の表面(即ち、窓層兼支持基板106,206を有する第一の面)01A,02Aに、窓層兼支持基板106,206における残り厚さが70μm以下となる溝180,280を形成し、半導体基板A01,A02の発光層部形成面(01B,02B)側から、半導体基板の表面に溝に沿ってスクライブ痕182,282を付け、半導体基板に垂直な力を溝180,280の全長または一部に加えることで発光素子を分離する工程を行う。溝の形成方法が湿式エッチングの場合(第一実施形態)、ドライエッチングの場合(第二実施形態)に分けて以下に詳述する。   Up to this point, the first embodiment and the second embodiment are exactly the same steps. Thereafter, as shown in FIGS. 1D, 1E, 2D, and 2E, the surface of the semiconductor substrate A01, A02 opposite to the light emitting layer portion forming surface (that is, the window layer) Grooves 180 and 280 having a remaining thickness of 70 μm or less in the window layer / support substrates 106 and 206 are formed in the first surface 01A and 02A having the support substrates 106 and 206, and the light emitting layers of the semiconductor substrates A01 and A02 From the part forming surface (01B, 02B) side, scribe marks 182 and 282 are formed along the groove on the surface of the semiconductor substrate, and a force perpendicular to the semiconductor substrate is applied to the entire length or part of the grooves 180 and 280 The process of isolate | separating is performed. The method for forming the groove will be described in detail below by dividing it into wet etching (first embodiment) and dry etching (second embodiment).

まず、第一実施形態について図1(d)、(e)を用いて説明する。図1(d)に示すように、半導体基板A01の発光層部形成面側とは反対側の表面(即ち、窓層兼支持基板106を有する第一の面)01A上に、SiO膜を1μm形成し、予め付けたブレーキング予備線181の領域が開口したSiOパターン170をフォトリソにより設ける。開口部171の幅は大きければエッチングは容易であるが、例えば25μmとすることができる。開口部171の幅は25μmに限定されるものでなく、エッチング深さに対して1/20以上の幅を有すればよい。 First, a first embodiment will be described using FIGS. 1D and 1E. As shown in FIG. 1D, an SiO 2 film is formed on the surface 01A of the semiconductor substrate A01 opposite to the light emitting layer portion forming surface side (that is, the first surface having the window layer / supporting substrate 106). A SiO 2 pattern 170 having a thickness of 1 μm and opening a preliminarily provided braking spare line 181 is provided by photolithography. Etching is easy if the width of the opening 171 is large, but it can be, for example, 25 μm. The width of the opening 171 is not limited to 25 μm, and may have a width of 1/20 or more with respect to the etching depth.

次にSiOパターン170を有する半導体基板A01の第一の面01Aと反対側の、発光層部形成面側の表面(第二の面)01Bにエレクトロンワックスを塗布し、塩酸と硝酸が1:3の割合で混合されたエッチング溶液の中に投入し、開口部171をエッチングする。5分程度の浸漬で1μm程度のエッチングを行うことが可能である。そしてエッチング溶液を保温しながら所望の溝深さに成る様に時間管理で制御を行う。この時、溝180は、窓層兼支持基板106における残り厚さが70μm以下となるように形成する。 Next, electron wax is applied to the surface (second surface) 01B on the light emitting layer portion forming surface side opposite to the first surface 01A of the semiconductor substrate A01 having the SiO 2 pattern 170, and hydrochloric acid and nitric acid are 1: Into the etching solution mixed at a ratio of 3, the opening 171 is etched. It is possible to perform etching of about 1 μm by immersion for about 5 minutes. Then, control is performed by time management so as to obtain a desired groove depth while keeping the etching solution warm. At this time, the groove 180 is formed so that the remaining thickness of the window layer / supporting substrate 106 is 70 μm or less.

次に、図1(e)に示すように所望の溝深さを設けた半導体基板A01の第二の面01B面において、溝180に沿って(即ち、ブレーキング予備線181に沿って)、スクライブ痕182を付けるスクライブ処理を行う。スクライブ処理は例えば4ポイントのダイヤモンドヘッドを用い、荷重50gにて行なうことができる。スクライブ条件は前述の条件に限定されるものではなく、多ポイントあるいは少ポイントのヘッドを用いても良く、荷重もこの数値に限定されるものでない。   Next, as shown in FIG. 1E, on the second surface 01B surface of the semiconductor substrate A01 provided with a desired groove depth, along the groove 180 (that is, along the braking spare line 181), A scribing process for attaching the scribing mark 182 is performed. The scribing process can be performed using, for example, a 4-point diamond head and a load of 50 g. The scribing conditions are not limited to the above-mentioned conditions. A multi-point or small-point head may be used, and the load is not limited to this value.

また、ダイヤモンドヘッドに限定されず、レーザーアブレーション法によってスクライブを行ってもよい。レーザーアブレーション法を採用する場合、例えば波長355nm、出力0.5Wのレーザーを用いて、スクライブ処理を行うことができる。   The scribing may be performed by a laser ablation method without being limited to the diamond head. When the laser ablation method is employed, for example, a scribing process can be performed using a laser having a wavelength of 355 nm and an output of 0.5 W.

スクライブ処理後、半導体基板A01に垂直な力を溝180の全長または一部に加えることで発光素子を分離する。この際、第二の面01B表面に保護シートを乗せ、保護シート面と反対側の面から刃を当ててブレーキング処理を実施することで、ダイス化することができる。   After the scribing process, the light emitting element is separated by applying a force perpendicular to the semiconductor substrate A01 to the entire length or a part of the groove 180. At this time, a protective sheet is placed on the surface of the second surface 01B, and a cutting process is performed by applying a blade from a surface opposite to the surface of the protective sheet.

次に第二実施形態について図2(d)、(e)を用いて説明する。半導体基板A02の発光層部形成面側とは反対側の表面(即ち、半導体基板A02の窓層兼支持基板206を有する第一の面)02A上に、SiO膜を1μm形成し、予め付けたブレーキング予備線281の領域が開口したフォトレジストパターン290をフォトリソにより設ける。開口部271の幅は大きければエッチングは容易であるが、例えば、25μmとすることができる。開口部271の幅は25μmに限定されるものでなく、エッチング深さに対して1/20以上の幅を有すればよい。 Next, a second embodiment will be described with reference to FIGS. On the surface opposite to the light emitting layer portion forming surface side of the semiconductor substrate A02 (that is, the first surface having the window layer / supporting substrate 206 of the semiconductor substrate A02) 02A, a 1 μm SiO 2 film is formed and attached in advance. A photoresist pattern 290 having an opening in the area of the braking spare line 281 is provided by photolithography. Etching is easy if the width of the opening 271 is large, but can be, for example, 25 μm. The width of the opening portion 271 is not limited to 25 μm, and may have a width of 1/20 or more with respect to the etching depth.

フォトレジストパターン290を有するウェーハA02を弗酸液に投入し、フォトレジストパターン290と略同一のSiOパターン270を得る。SiOパターン270を形成後、フォトレジストパターン290を有機洗浄、アッシングの方法で除去する。 The wafer A02 having the photoresist pattern 290 is put into a hydrofluoric acid solution to obtain a SiO 2 pattern 270 substantially the same as the photoresist pattern 290. After forming the SiO 2 pattern 270, the photoresist pattern 290 is removed by organic cleaning and ashing.

SiOパターン270を有するウェーハA02の第一の面02Aに、例えば塩素プラズマを含有する処理を行い、開口部271をエッチングする。塩素プラズマ源としてCl、プラズマ印加方式としてICPを用いることができる。プラズマ印加出力は例えば150Wとすることができる。そして所望の溝深さに成る様に時間管理で制御を行う。この時、溝280は、窓層兼支持基板206における残り厚さが70μm以下となるように形成する。 For example, a treatment containing chlorine plasma is performed on the first surface 02A of the wafer A02 having the SiO 2 pattern 270, and the opening 271 is etched. Cl 2 can be used as a chlorine plasma source, and ICP can be used as a plasma application method. The plasma application output can be set to 150 W, for example. Control is performed by time management so that a desired groove depth is obtained. At this time, the groove 280 is formed so that the remaining thickness of the window layer / supporting substrate 206 is 70 μm or less.

前記に示した条件はあくまで例示であり、前記の条件に限定されるものでない。塩素プラズマ発生源とガスとしては他にSiClやBClが選択可能であり、プラズマ印加方式としてRIEも選択可能である。出力も50W以上あれば、エッチングを行うことができる。 The conditions shown above are merely examples and are not limited to the above conditions. In addition, SiCl 4 and BCl 3 can be selected as the chlorine plasma generation source and gas, and RIE can also be selected as the plasma application method. If the output is 50 W or more, etching can be performed.

所望の溝深さを設けた半導体基板A02の第一の面02Aと反対側の第二の面02B面において、溝280に沿って(即ち、ブレーキング予備線281に沿って)、スクライブ痕282を付けるスクライブ処理を行う。スクライブ処理は4ポイントのダイヤモンドヘッドを用い、荷重50gにて行うことができる。スクライブ条件は前述の条件に限定されるものではなく、多ポイントあるいは少ポイントのヘッドを用いても良く、荷重もこの数値に限定されるものでない。   On the second surface 02B surface opposite to the first surface 02A of the semiconductor substrate A02 provided with a desired groove depth, along the groove 280 (that is, along the braking reserve line 281), the scribe mark 282 is formed. Perform a scribing process. The scribing process can be performed with a load of 50 g using a 4-point diamond head. The scribing conditions are not limited to the above-mentioned conditions. A multi-point or small-point head may be used, and the load is not limited to this value.

また、ダイヤモンドヘッドに限定されず、レーザーアブレーション法によってスクライブ処理を行ってもよい。レーザーアブレーション法を採用する場合、例えば波長355nm、出力0.5Wのレーザーを用いて、スクライブ処理を行うことができる。   Moreover, it is not limited to a diamond head, You may perform a scribe process by the laser ablation method. When the laser ablation method is employed, for example, a scribing process can be performed using a laser having a wavelength of 355 nm and an output of 0.5 W.

スクライブ処理後、半導体基板A02に垂直な力を溝280の全長または一部に加えることで発光素子を分離する。この際、第二の面02B表面に保護シートを乗せ、保護シート面と反対側の面から刃を当ててブレーキング処理を実施することで、ダイス化することができる。   After the scribing process, the light emitting element is separated by applying a force perpendicular to the semiconductor substrate A02 to the entire length or a part of the groove 280. At this time, the protective sheet is placed on the surface of the second surface 02B, and the cutting process is performed by applying a blade from the surface opposite to the protective sheet surface, whereby dicing can be performed.

上記のように、半導体基板A01,A02の発光層部形成面側とは反対側の表面01A,02Aに、窓層兼支持基板106,206における残り厚さが70μm以下となる溝180,280を形成し、半導体基板の発光層部形成面側から、半導体基板A01,A02の表面に溝に沿ってスクライブ痕182,282を付け、半導体基板に垂直な力を溝180,280の全長または一部に加えることで発光素子を分離することで、格子不整合系GaP等の窓層兼支持基板を有する半導体基板から発光素子をスクライブ・ブレーキングにより分離する際、ブレーキング不良率を低減することができる。   As described above, grooves 180 and 280 having a remaining thickness of 70 μm or less in the window layer / supporting substrates 106 and 206 are formed on the surfaces 01A and 02A opposite to the light emitting layer portion forming surface side of the semiconductor substrates A01 and A02. The scribe marks 182 and 282 are formed along the grooves on the surfaces of the semiconductor substrates A01 and A02 from the light emitting layer portion forming surface side of the semiconductor substrate, and a force perpendicular to the semiconductor substrate is applied to the entire length or part of the grooves 180 and 280. In addition to separating the light emitting element by adding to the semiconductor substrate having the window layer / supporting substrate such as a lattice mismatched GaP or the like, it is possible to reduce the braking failure rate when separating the light emitting element by scribe braking. it can.

窓層兼支持基板における残り厚さが70μmを超える溝を形成した場合や、溝を形成しない場合、及び半導体基板の発光層部形成面側に溝を形成した場合には、ブレーキング不良率が高くなる。   When the groove having a remaining thickness of the window layer / supporting substrate exceeding 70 μm is formed, when the groove is not formed, or when the groove is formed on the light emitting layer portion forming surface side of the semiconductor substrate, the braking failure rate is Get higher.

以下、本発明の実施例及び比較例を示して本発明をより具体的に説明するが、本発明はこれらに限定されるものではない。   EXAMPLES Hereinafter, the present invention will be described more specifically with reference to examples and comparative examples of the present invention, but the present invention is not limited to these.

(実施例1〜5)
図1に示すような本発明の発光素子の製造方法の第一の実施形態に基づいて、発光素子の製造を行った。
まず、図1に示すように、出発基板100としてGaAs(001)からなる基板を準備し、この基板上に、機能層たるダブルヘテロ層(発光層部107)をMOVPE法にて形成した。発光層部107は、下部クラッド層(第一半導体層)101、活性層102、上部クラッド層(第二半導体層)103を順次積層したものとした。
(Examples 1-5)
The light emitting device was manufactured based on the first embodiment of the method for manufacturing the light emitting device of the present invention as shown in FIG.
First, as shown in FIG. 1, a substrate made of GaAs (001) was prepared as a starting substrate 100, and a double hetero layer (light emitting layer portion 107) as a functional layer was formed on the substrate by MOVPE. The light emitting layer portion 107 is formed by sequentially laminating a lower clad layer (first semiconductor layer) 101, an active layer 102, and an upper clad layer (second semiconductor layer) 103.

第一半導体層101は、(AlGa1−xIn1−yP(0.6≦x≦1.0、0.4≦y≦0.6)の組成が選択され、本実施例では、第一半導体層として、n型AlInPクラッド層を0.7μm(ドーピング濃度3.0×1017/cm)、n型Al0.85GaInP層を0.3μm(ドーピング濃度1.0×1017/cm)の2層構造とした。 In the first semiconductor layer 101, a composition of (Al x Ga 1-x ) y In 1-y P (0.6 ≦ x ≦ 1.0, 0.4 ≦ y ≦ 0.6) is selected. In the example, as the first semiconductor layer, an n-type AlInP cladding layer is 0.7 μm (doping concentration 3.0 × 10 17 / cm 3 ), and an n-type Al 0.85 GaInP layer is 0.3 μm (doping concentration 1.0). X10 17 / cm 3 ).

活性層102は、(AlGa1−xIn1−yP(0.15≦x≦0.8、0.4≦y≦0.6)から選択され、波長によって組成x及びyは変更した。本実施例において活性層は、多重活性層を用いた。活性層及び障壁層の膜厚は求める波長により変更され、それぞれ4〜12nmの範囲で波長に合わせて調整した。 The active layer 102 is selected from (Al x Ga 1-x ) y In 1-y P (0.15 ≦ x ≦ 0.8, 0.4 ≦ y ≦ 0.6), and the composition x and y depends on the wavelength. Changed. In this embodiment, a multiple active layer is used as the active layer. The film thicknesses of the active layer and the barrier layer were changed depending on the desired wavelength, and were adjusted according to the wavelength in the range of 4 to 12 nm.

第二半導体層103として、p型AlInPクラッド層を0.9μm(ドーピング濃度3.0×1017/cm)、p型Al0.6GaInP層を0.1μm(ドーピング濃度1.0×1017/cm)の2層構造とした。 As the second semiconductor layer 103, a p-type AlInP clad layer is 0.9 μm (doping concentration 3.0 × 10 17 / cm 3 ), and a p-type Al 0.6 GaInP layer is 0.1 μm (doping concentration 1.0 × 10). 17 / cm 3 ).

発光層部107上には、GaInPからなる緩衝層(中間組成層104)を成膜し、この緩衝層上にGaPからなる窓層兼支持基板106をMOVPE法及びHVPE法にて100μm程度成膜した。   A buffer layer (intermediate composition layer 104) made of GaInP is formed on the light emitting layer 107, and a window layer / support substrate 106 made of GaP is formed on the buffer layer by about 100 μm by MOVPE and HVPE. did.

窓層兼支持基板106を形成した後、図1(b)に示すように、ウェットエッチング法により基板100を除去して自立基板とし、基板100を除去した面に第一オーミック電極151を形成した。第一オーミック電極151は、Si、Zn、Sを含有するAu電極からなり、膜厚は1.5μmとした。   After forming the window layer / supporting substrate 106, as shown in FIG. 1B, the substrate 100 was removed by wet etching to form a self-supporting substrate, and the first ohmic electrode 151 was formed on the surface from which the substrate 100 was removed. . The first ohmic electrode 151 is made of an Au electrode containing Si, Zn, and S, and has a thickness of 1.5 μm.

次に、図1(c)に示すように、発光層部107の一部をフォトリソグラフィー法とエッチング法により切り欠き、発光層領域110(非除去部)と、窓層兼支持基板を露出させた領域(除去部)120とを設けた。   Next, as shown in FIG. 1C, a part of the light emitting layer portion 107 is cut out by a photolithography method and an etching method to expose the light emitting layer region 110 (non-removed portion) and the window layer / support substrate. Area (removal part) 120 is provided.

そして、除去部120の窓層兼支持基板106上に第二オーミック電極161を形成した。第二オーミック電極161は、Beを含有するAu電極からなり、膜厚は1.5μmとした。   Then, the second ohmic electrode 161 was formed on the window layer / supporting substrate 106 of the removal portion 120. The second ohmic electrode 161 was made of an Au electrode containing Be, and the film thickness was 1.5 μm.

次に、図1(d)に示すように半導体基板A01の窓層兼支持基板106を有する第一の面(01A)上に、SiO膜を1μm形成し、ブレーキング予備線181の領域が開口したSiOパターン170をフォトリソにより設けた。開口幅は25μmとした。 Next, as shown in FIG. 1D, a 1 μm SiO 2 film is formed on the first surface (01A) of the semiconductor substrate A01 having the window layer / supporting substrate 106, and the region of the braking spare line 181 is formed. The opened SiO 2 pattern 170 was provided by photolithography. The opening width was 25 μm.

次に、SiOパターン170を有する半導体基板の第一の面(01A)と反対側の第二の面(01B)にエレクトロンワックスを塗布し、塩酸と硝酸が1:3の割合で混合されたエッチング溶液の中に投入し、開口部171をエッチングし溝180を形成した。表1に示すように、溝180の、窓層兼支持基板106における残り厚さ(溝部厚さ)をエッチング時間を変えることによって変化させた。この時、窓層兼支持基板106における残り厚さが70μm以下となるように溝180を形成した。 Next, electron wax was applied to the second surface (01B) opposite to the first surface (01A) of the semiconductor substrate having the SiO 2 pattern 170, and hydrochloric acid and nitric acid were mixed at a ratio of 1: 3. The groove 180 was formed by etching into the etching solution and etching the opening 171. As shown in Table 1, the remaining thickness (groove portion thickness) of the groove 180 in the window layer / supporting substrate 106 was changed by changing the etching time. At this time, the groove 180 was formed so that the remaining thickness in the window layer / supporting substrate 106 was 70 μm or less.

次に、図1(e)に示すように、所望の溝深さを設けた半導体基板の第二の面(01B)において、ブレーキング予備線181に沿ってスクライブ処理を行なった。スクライブ処理は4ポイントのダイヤモンドヘッドを用い、荷重50gにて行なった。   Next, as shown in FIG. 1E, a scribing process was performed along the preliminary braking line 181 on the second surface (01B) of the semiconductor substrate provided with a desired groove depth. The scribing process was performed using a 4-point diamond head with a load of 50 g.

スクライブ処理後、第二の面01B表面に保護シートを乗せ、保護シート面と反対側の面から刃を当ててブレーキング処理を実施し、ダイス化した。   After the scribing treatment, a protective sheet was placed on the surface of the second surface 01B, and a braking treatment was performed by applying a blade from the surface opposite to the protective sheet surface to form a die.

(比較例1〜3)
エッチング時間を変えて、溝の窓層兼支持基板における残り厚さを表1に示す厚さとした以外は実施例1と同様な方法で発光素子の製造を行った。
(Comparative Examples 1-3)
A light emitting device was manufactured in the same manner as in Example 1 except that the etching time was changed and the remaining thickness of the groove window layer / support substrate was changed to the thickness shown in Table 1.

(実施例6〜10)
塩素プラズマを含有する処理を行い開口部をエッチングしたこと、及び溝の窓層兼支持基板における残り厚さを表1に示す厚さとしたことを除き、実施例1と同様な方法で発光素子の製造を行った。塩素プラズマ源としてCl、プラズマ印加方式としてICPを用いた。プラズマ印加出力は150Wとした。そして所望の溝深さになる様に時間管理で制御を行なった。この時、窓層兼支持基板における残り厚さが70μm以下となるようにして溝を形成した。
(Examples 6 to 10)
The light emitting device was fabricated in the same manner as in Example 1, except that the opening was etched by performing treatment containing chlorine plasma, and the remaining thickness of the groove window layer / supporting substrate was set to the thickness shown in Table 1. Manufactured. Cl 2 was used as the chlorine plasma source, and ICP was used as the plasma application method. The plasma application output was 150 W. Control was performed by time management so as to obtain a desired groove depth. At this time, the grooves were formed so that the remaining thickness of the window layer / supporting substrate was 70 μm or less.

(比較例4〜6)
溝の窓層兼支持基板における残り厚さを表1に示す厚さとした以外は、実施例6と同様の方法で発光素子の製造を行った。
(Comparative Examples 4-6)
A light emitting device was manufactured in the same manner as in Example 6 except that the remaining thickness of the groove window layer and supporting substrate was changed to the thickness shown in Table 1.

(実施例11〜15)
窓層兼支持基板の厚さを120μm程度及び溝の窓層兼支持基板における残り厚さを表1に示す厚さとした以外は実施例1と同様の方法で発光素子の製造を行った。
(Examples 11 to 15)
A light emitting device was manufactured in the same manner as in Example 1 except that the thickness of the window layer / support substrate was about 120 μm and the remaining thickness of the groove window layer / support substrate was changed to the thickness shown in Table 1.

(比較例7〜11)
溝の窓層兼支持基板における残り厚さを表1に示す厚さとした以外は実施例11と同様な方法で発光素子の製造を行った。
(Comparative Examples 7 to 11)
A light emitting device was manufactured in the same manner as in Example 11 except that the remaining thickness of the groove window layer and supporting substrate was changed to the thickness shown in Table 1.

(実施例16〜20)
窓層兼支持基板の厚さを120μm程度及び溝の窓層兼支持基板における残り厚さを表1に示す厚さとした以外は、実施例6と同様な方法で発光素子の製造を行った。
(Examples 16 to 20)
A light emitting device was manufactured in the same manner as in Example 6 except that the thickness of the window layer / support substrate was about 120 μm and the remaining thickness of the groove window layer / support substrate was changed to the thickness shown in Table 1.

(比較例12〜16)
溝の窓層兼支持基板における残り厚さを表1に示す厚さとした以外は、実施例16と同様な方法で発光素子の製造を行った。
(Comparative Examples 12 to 16)
A light emitting device was manufactured in the same manner as in Example 16 except that the remaining thickness of the groove window layer / support substrate was changed to the thickness shown in Table 1.

実施例1〜10、及び比較例1〜6について溝の窓層兼支持基板における残り厚さとスクライブ・ブレーキングによる不良率(%)の関係を表1及び図4に示す。実施例11〜20、及び比較例7〜16について溝の窓層兼支持基板における残り厚さとスクライブ・ブレーキングによる不良率(%)の関係を表1及び図5に示す。   Tables 1 and 4 show the relationship between the remaining thickness of the groove window layer / support substrate and the defect rate (%) due to scribe braking for Examples 1 to 10 and Comparative Examples 1 to 6. Tables 1 and 5 show the relationship between the remaining thickness of the groove window layer / support substrate and the defect rate (%) due to scribe braking for Examples 11 to 20 and Comparative Examples 7 to 16.

Figure 2019036662
Figure 2019036662

表1、図4及び図5から、70μm以下の残り厚さの溝を形成した実施例では、ブレーキング不良率を低減できたことが判った。   From Table 1, FIG. 4 and FIG. 5, it was found that the braking failure rate could be reduced in the example in which the groove having the remaining thickness of 70 μm or less was formed.

なお、本発明は、上記実施形態に限定されるものではない。上記実施形態は例示であり、本発明の特許請求の範囲に記載された技術的思想と実質的に同一な構成を有し、同様な作用効果を奏するものは、いかなるものであっても本発明の技術的範囲に包含される。   The present invention is not limited to the above embodiment. The above-described embodiment is an exemplification, and the present invention has any configuration that has substantially the same configuration as the technical idea described in the claims of the present invention and that exhibits the same effects. Are included in the technical scope.

100,200,300…基板、 101,201,301…第一半導体層、 102,202,302…活性層、 103,203,303…第二半導体層、 104,204,304…中間組成層、 105,205,305…窓層、 106,206,306…窓層兼支持基板、 107,207,307…発光層部、 110,210,310…非除去部 111,211,311…非除去部のうち、第一オーミック電極を有しない領域、 120,220,320…除去部、 121,221,321…除去部のうち、第二オーミック電極以外の領域、 130,230,330…段差部、 140,141,142,240、241,242,340,341,342…誘電体部、 151,251,351…第一オーミック電極、 161,261,361…第二オーミック電極、 170,270…SiOパターン、 290…フォトレジストパターン, 171,271・・・開口部、 180,280…溝、 181,281,381…ブレーキング予備線、 182,282,382…スクライブ痕、 011,021,031…ウェーハ、 A01,A02,A03・・・半導体基板、 01A,02A,03A…半導体基板の発光層部形成面側とは反対側の表面(第一の面)、 01B,02B,03B…半導体基板の発光層部形成面側の表面(第二の面)。 100, 200, 300 ... substrate, 101, 201, 301 ... first semiconductor layer, 102, 202, 302 ... active layer, 103, 203, 303 ... second semiconductor layer, 104, 204, 304 ... intermediate composition layer, 105 , 205, 305 ... window layer, 106, 206, 306 ... window layer and supporting substrate, 107, 207, 307 ... light emitting layer part, 110, 210, 310 ... non-removal part 111, 211, 311 ... non-removal part , A region not having the first ohmic electrode, 120, 220, 320... Removed portion, 121, 221, 321... Removed portion, a region other than the second ohmic electrode, 130, 230, 330. , 142, 240, 241, 242, 340, 341, 342... Dielectric part, 151, 251, 351, first ohmic electrode, 161, 261 361 ... second ohmic electrode, 170, 270 ... SiO 2 pattern, 290 ... photoresist pattern, 171 and 271 ... opening, 180, 280 ... groove, 181,281,381 ... braking spare line, 182,282 , 382 ... Scribe marks, 011,021, 031 ... Wafer, A01, A02, A03 ... Semiconductor substrate, 01A, 02A, 03A ... Surface opposite to the light emitting layer forming surface side of the semiconductor substrate (first Surface), 01B, 02B, 03B... Surface (second surface) on the light emitting layer portion forming surface side of the semiconductor substrate.

Claims (2)

基板上に、該基板と格子整合系の材料で少なくとも第一半導体層、活性層、第二半導体層を順次エピタキシャル成長により成長させて発光層部を形成する工程と、
該発光層部と格子不整合系の材料で窓層兼支持基板を前記発光層部上にエピタキシャル成長させる窓層兼支持基板形成工程と、
前記基板を除去する工程と、
前記第一半導体層表面に第一オーミック電極を形成する工程と、
少なくとも前記第一半導体層と前記活性層を除去して除去部を形成する工程と、
前記除去部の前記第二半導体層または窓層兼支持基板上に第二オーミック電極を形成する工程により、
前記窓層兼支持基板上に、少なくとも、前記除去部以外の発光層部と、前記第一オーミック電極、及び前記第二オーミック電極を有する半導体基板を製造し、その後、該半導体基板から、スクライブ・ブレーキングにより発光素子を分離することにより発光素子を製造する発光素子の製造方法において、
前記発光素子の分離を、前記半導体基板の前記発光層部形成面側とは反対側の表面に、前記窓層兼支持基板における残り厚さが70μm以下となる溝を形成し、その後、前記半導体基板の前記発光層部形成面側から、前記半導体基板の表面に前記溝に沿ってスクライブ痕を付け、前記半導体基板に垂直な力を前記溝の全長または一部に加えることで発光素子を分離することを特徴とする発光素子の製造方法。
Forming a light emitting layer portion on a substrate by sequentially growing at least a first semiconductor layer, an active layer, and a second semiconductor layer by epitaxial growth with a material of lattice matching system with the substrate;
A window layer / support substrate forming step of epitaxially growing a window layer / support substrate on the light emitting layer portion with a material of lattice mismatching with the light emitting layer portion;
Removing the substrate;
Forming a first ohmic electrode on the surface of the first semiconductor layer;
Removing at least the first semiconductor layer and the active layer to form a removal portion;
By forming a second ohmic electrode on the second semiconductor layer or window layer / support substrate of the removal portion,
On the window / support substrate, a semiconductor substrate having at least a light emitting layer portion other than the removal portion, the first ohmic electrode, and the second ohmic electrode is manufactured. In a method for manufacturing a light emitting element, in which the light emitting element is manufactured by separating the light emitting element by braking,
The light emitting element is separated by forming a groove with a remaining thickness of 70 μm or less in the window layer / supporting substrate on the surface of the semiconductor substrate opposite to the light emitting layer portion forming surface side, and then the semiconductor A light-emitting element is separated by making a scribe mark along the groove on the surface of the semiconductor substrate from the light-emitting layer portion forming surface side of the substrate and applying a force perpendicular to the semiconductor substrate to the entire length or a part of the groove. A method for manufacturing a light-emitting element.
前記溝を、湿式エッチングまたはドライエッチングにより形成することを特徴とする請求項1に記載の発光素子の製造方法。   The method for manufacturing a light-emitting element according to claim 1, wherein the groove is formed by wet etching or dry etching.
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Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05285936A (en) * 1992-04-13 1993-11-02 Sumitomo Electric Ind Ltd Dividing method for semiconductor base
JPH11354841A (en) * 1998-06-04 1999-12-24 Rohm Co Ltd Fabrication of semiconductor light emitting element
JP2001168388A (en) * 1999-09-30 2001-06-22 Sharp Corp Gallium nitride compound semiconductor chip, its manufacturing method and gallium nitride compound semiconductor wafer
JP2001267270A (en) * 2000-03-22 2001-09-28 Toyoda Gosei Co Ltd Method and device for dicing semiconductor wafer
JP2001284292A (en) * 2000-03-31 2001-10-12 Toyoda Gosei Co Ltd Chip division method for semiconductor wafer
JP2001284290A (en) * 2000-03-31 2001-10-12 Toyoda Gosei Co Ltd Chip division method for semiconductor wafer
US20040232524A1 (en) * 2003-05-23 2004-11-25 Howard Gregory E. Scribe street width reduction by deep trench and shallow saw cut
JP2005064426A (en) * 2003-08-20 2005-03-10 Mitsubishi Cable Ind Ltd Method for manufacturing nitride-based semiconductor device
JP2015226018A (en) * 2014-05-29 2015-12-14 Tdk株式会社 Individualization method of electronic device
WO2016072050A1 (en) * 2014-11-07 2016-05-12 信越半導体株式会社 Light-emitting element and method for manufacturing light-emitting element

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI238548B (en) * 2002-11-08 2005-08-21 United Epitaxy Co Ltd Light emitting diode and method of making the same

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05285936A (en) * 1992-04-13 1993-11-02 Sumitomo Electric Ind Ltd Dividing method for semiconductor base
JPH11354841A (en) * 1998-06-04 1999-12-24 Rohm Co Ltd Fabrication of semiconductor light emitting element
JP2001168388A (en) * 1999-09-30 2001-06-22 Sharp Corp Gallium nitride compound semiconductor chip, its manufacturing method and gallium nitride compound semiconductor wafer
JP2001267270A (en) * 2000-03-22 2001-09-28 Toyoda Gosei Co Ltd Method and device for dicing semiconductor wafer
JP2001284292A (en) * 2000-03-31 2001-10-12 Toyoda Gosei Co Ltd Chip division method for semiconductor wafer
JP2001284290A (en) * 2000-03-31 2001-10-12 Toyoda Gosei Co Ltd Chip division method for semiconductor wafer
US20040232524A1 (en) * 2003-05-23 2004-11-25 Howard Gregory E. Scribe street width reduction by deep trench and shallow saw cut
JP2005064426A (en) * 2003-08-20 2005-03-10 Mitsubishi Cable Ind Ltd Method for manufacturing nitride-based semiconductor device
JP2015226018A (en) * 2014-05-29 2015-12-14 Tdk株式会社 Individualization method of electronic device
WO2016072050A1 (en) * 2014-11-07 2016-05-12 信越半導体株式会社 Light-emitting element and method for manufacturing light-emitting element

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