TW200417067A - Light emitting diode and method of making the same - Google Patents

Abstract

A light emitting diode (LED) having two electrodes at the same side and altitude is disclosed. The LED includes a high reflective metal layer therein to reflect those lights emitted from the active layer toward it, an electrical connecting plug, and an isolation channel. The electrical connecting plug connects the first ohmic contact electrode which is buried in the LED structure to the outer surface of the lower cladding layer. The isolation channel spaced the LED from two parts. The first part has the electrical connecting plug and the second part has a second ohmic contact electrode formed on the lower cladding layer. The active layer in the second part actives after a voltage is applied.

Description

200417067 V. Description of the invention (l) [Technical field to which the invention belongs] The present invention relates to a light emitting diode (Light Emitting Diode; LED) wafer structure and a method for manufacturing the same, and particularly relates to an aluminum gallium indium phosphide (A1 Gal nP) Structure of light emitting diode and manufacturing method thereof. [Previous technology] The traditional aluminum gallium indium light-emitting diode has a double heterostructure (Double Heterostructure; DH). Its structure is shown in Figure 5. It is a η-type gallium arsenide (GaAs) substrate (Substrate ) 52, a buffer layer 54 is formed first, and then a cladding layer 58 with an aluminum content of 70% to 100% η-type (AlxGaH) 0.5 · η 〇 0.5P, and a (AlxGa χ) 〇 5Ιη () · 5P active layer 60, a 1) type (eight 1 such as 1]) () 51] 1. 5% cladding layer 62 on top of 5? Gap current spreading layer

Layer 64. The material of this layer can be gallium phosphide, gallium phosphide arsenide, indium gallium phosphide, or broken gallium. By changing the composition of the active layer 60, it is possible to change the wavelength of light emitted by the light emitting diode so that it produces a wavelength from 650 nm red to 55 5 nm pure green. However, this conventional light-emitting diode has a disadvantage, that is, the light generated by the active layer enters the Shishenhua gallium substrate 5 2 downwards, because the energy gap of the Shishenhua Su substrate 5 2 is smaller than ⑩, this incident to The light of the gallium arsenide substrate 52 will be absorbed, and a high-efficiency light-emitting diode cannot be generated. In order to avoid the light absorption of the substrate 54, some literatures have been disclosed conventionally.

200417067 V. Description of the invention (2) LED technology, however, these technologies have their shortcomings and limitations. E.g

Published in [Appl. Phys Lett. Vol. 61, 1 775- 1 7 7 7 (1 9 9 2)] by Sugawara et al. Revealed a method of adding a distributed Bragg reflector 54 (Distributed Bragg Reflector; DBR) to arsenic The gallium substrate is used to reflect the light incident on the apocalypse substrate and reduce the absorption of the apocalypse substrate. However, since the DBR reflective layer 54 can effectively reflect only light that is incident on the gallium arsenide substrate perpendicularly, the effect is not significant. Not big.

Kish et al. [Appl · Phys Lett. Vol. 64,

No. 21, 28 39, (1 9 94), entitled "Very high- φ efficiency semiconductor wafer-bonded transparent- (Wa ^ fer bonding) Transparent-Substrate; TS" (AlxGanKsIriuP / GaP Light-emitting diode. This TS AlGalnP LED uses the vapor phase epitaxy (VPE) method to form a P-type gallium phosphide (GaP) window layer with a relatively thick thickness (about 50 // m). The conventional chemical etching method selectively removes N-type gallium arsenide (GaAs) * plates. Then expose this exposed bet (八 1 ^ 1 ^) (). 5111 (). 5? Under the coating, Bonded to η-type gallium phosphide substrate with a thickness of about 8-10 mi 1. Φ Because this wafer bonding (W afer Β ο nding) is directly bonding two III-v group compound semiconductors together Therefore, it can be completed at a higher temperature by heating and pressing for a period of time. In terms of luminous brightness, the TSA 1 G a I η PLED prepared in this way is better than traditional absorption substrates

Page 7 200417067 V. Description of the invention (3) (Absorbing-Substrate; AS) AlGaInP LED has more than twice the brightness. However, the disadvantage of this TS A 1 Gal nP LED is that the manufacturing process is too complicated, and usually has a high resistance characteristic of a non-ohmic contact at the bonding interface. Therefore, it is impossible to obtain a high production yield and it is difficult to reduce the manufacturing cost. Another traditional technique, such as Horng et al. [Appl.

Phys · Lett · ν〇1 · 75, No. 20, 3 0 54 (1 9 9), and the name is "AlGalnP light-emitting diodes with mirror substrates fabricated by wafer bonding"]. Horng et al. Have disclosed a method for forming a mirror substrate (Mirror-Substr ate; Ms) using a wafer fusion technology, and indium aluminum gallium / metal / silicon dioxide / silicon L £ D. It uses AuBe / Au as an adhesive material to bond the silicon substrate and the LED stupid layer. However, 'at an operating current of 20m A, the luminous intensity of this ms A 1 Gal nP LED is only about 90 mcd, which is still at least 40% lower than that of TS A1GaInP LEJ', so its luminous intensity cannot be made satisfaction.

At the same time, the bonding wafers I I I -V group compound semiconductors formed by the above methods cannot have electrodes on the same side, and are not suitable for serial and parallel use of light emitting diodes. 0 This other type of P and N electrodes is located on the same side, and its structure is shown in FIG. 6. A n-type gallium (GaAs) substrate fUbStrate 52 is grown on the buffer layer 54. Sequence: 2 "m ~ 1Q_ 嫂 (Α1 ^) .. Knowing the coating layer 乂 & 14) 0.511 (). 5? Active layer 60, aluminum content of 70%-100%. P (A1 xGaduInQ 5p over cladding layer 62, a p-type high-gap current

200417067 V. Description of the invention (4) Dispersion layer (Current Spreading Layer) 64. The material of this layer can be gallium phosphide, gallium phosphide arsenide, indium gallium phosphide, or aluminum gallium arsenide. A p-type high-gap current dispersing layer 64 has a P-type ohmic contact electrode 70 and a metal pin layer 74. Another N-type ohmic contact electrode 70 and a metal pin layer are formed on the light-emitting diode which has been engraved into a trench to expose the lower cladding layer 5 8. The light emitting diode provided by the present invention can solve the above problems. [Summary of the Invention] In summary, the present invention provides a light-emitting diode structure including a multi-layer epitaxial structure having a light-emitting layer, which is combined with a y high-thermal-conductivity substrate through an adhesive layer. The light emitting layer of the diode may be a homostructure (Singie heterostructure (SH), a double heterostructure (DH) or a multiple quantum well structure (MuUi Quantum we 1 1 s, MQWs)).

The light emitting diode structure also includes a first ohmic contact metal electrode layer and a first ohmic contact metal electrode layer. The first ohmic contact metal electrode layer is connected to the first metal nail line electrode layer through an electrode connection channel, and the second metal nail line electrode layer is above the second ohmic contact metal electrode layer. The first metal nail electrode layer and the second metal nail electrode layer are located on the same side of the substrate with high thermal conductivity and high reflectivity. And because there are electrode connection channels, the first metal nail electrode layer and the second metal nail electrode layer have the same height level.

$ 9 pages 200417067 V. Description of the invention (5) In addition, the present invention further provides a method for manufacturing the above-mentioned light emitting diode. First, a light emitting diode epitaxial stacked layer is sequentially formed on a temporary substrate, and then a first ohmic contact metal electrode layer and a high reflectivity metal layer are formed on the uppermost layer of the epitaxial stacked layer. Next, by using an adhesive layer, such as a metal adhesive layer, such as a metal such as In, Au, or Ag, or a resin such as BCB (B-staged bisbenzocyclobutene; BCB), the high reflectance on the light emitting diode epitaxial layer is high. The metal reflective layer is combined with a non-conductive dielectric layer on a highly thermally conductive substrate, and then the temporary substrate and the etch stop layer of the light emitting diode are removed. Tightly, two-stage etching is performed. In the first stage, an electrode connection channel is formed, and a channel having a width of about 1 to 3 m 1 1 s is etched to the first ohmic contact metal electrode layer for contacting the first ohmic contact. The metal electrode layers are in communication. The second stage is isolated trench or island etching, with an etching width of about 0.2-lniil, and etching or all of the first conductivity type stupid crystal layer. The current of the first ohmic contact metal electrode will flow through the activation layer to the second ohmic contact metal electrode layer. Next, a first metal nail line electrode layer is formed, and the first metal nail line electrode layer and the first ohmic contact are formed. The dot metal electrode layers are in communication. Finally, a second ohmic point metal electrode layer and a second metal nail line electrode layer are formed. An advantage of the present invention is to use an isolated trench or isolated island method, so that the first metal nailed wire electrode layer and the second metal nailed wire electrode layer are on the same side and at the same height. V °

Page 10 200417067

Another advantage of the present invention is that the trench can be isolated or the island can be used. The stud line is sealed and the surface is etched and rough, which makes it difficult to identify the traditional direct-tau deep package. Another advantage of low-rate U is that it is simpler and simpler. Therefore, it is possible to obtain mass production results at the cost of Takahashi Qianxing. # & Another advantage of the present invention + is the first ohmic contact metal electrode layer ^ ′ and then a better and stable photoelectric characteristic can be obtained by channel connection

: Month i ί has the same constant current, has a smaller voltage, better current distribution, and better luminous efficiency. [Embodiment] This invention discloses a light emitting monopole structure and a manufacturing method thereof. In order to make the description of the present invention more detailed and complete ... According to the following: the description of the West is its own: Figures 1 to 4 diagrams. First, please refer to FIG. 1. The epitaxial structure of the light-emitting diode of the present invention includes a sequentially stacked gallium arsenide (GaAs) substrate 24, an etch stop layer 22, and an N-type aluminum gallium indium phosphide. (AlxGaH) 0.5111 (). 5? Under the coating ((: 13 (1 (1 丨 1 ^) layer 2 0 and aluminum gallium indium phosphide (A1 & 1_〇〇.5In (). 5P activity Active layer 18, P-type aluminum gallium indium phosphide (A 1 x Ga Bu X) 〇 · 5Ι η ο. # Cladding layer 16 and P-type ohmic contact epitaxial layer (Ohmic Contact EpitaXial Layer) 14. Next, a P-type ohmic contact metal electrode layer 3 is formed on the p-type ohmic contact epitaxial layer 14.

Page 11 200417067 V. Description of the invention (7) The material of the P-type ohmic contact stupid crystal layer 14 can be GaAs, GaIn, or GaF, as long as its energy gap is greater than the active layer 1 8 It will not absorb light from the active layer, but it must have a high carrier concentration to facilitate the formation of ohmic contacts, and it can be selected as the P-type ohmic contact worm crystal layer 14. The aluminum content of the above active layer 18 is in the range of χ = 0 to 0.45, and the aluminum content of the upper and lower cladding layers is controlled to be about χ = 0.5 to 5 丨. 〇, when the active layer 20 When the aluminum content X = 0, the composition of the active layer is GaG 5inQ 5p, and the wavelength λ d of the light-emitting diode is about 6 3 5nm. The ratio of the above compounds, such as the active layer, is a preferred example, and is not intended to limit the invention. The invention is equally applicable to other ratios. In addition, in the present invention, the structure of the A 1 G a I η P active layer 18 may be a conventional homostructure (Η 〇struct), a single heterostructure (Single Heterostructure), or a double heterostructure (Double Heterostructure; DH). ) Or multiple quantum wells

Quantum Well; MQW) ° In the present invention, the material of the etch stop layer 2 2 may be any compound semiconductor of π I-V group elements, as long as its lattice constant can be matched with the gallium arsenide substrate 24 to avoid the occurrence of differential rows. In addition, the etching rate is much lower than that of the substrate 24 made of a gallium-based material, which can be used as the etching stop layer 22.

Page 12 200417067 V. Description of the invention (8) In the present invention, the preferred material of the etching stop layer 22 may be indium gallium phosphide (InGaP) or aluminum gallium arsenide (AlGaAs). The etching rate of the cladding layer 20 under the N-type aluminum gallium indium phosphide in this embodiment is also much lower than that of the gallium arsenide substrate 24. Therefore, as long as the thickness is thick, another epitaxial layer with a different composition may not be required as the last-cut layer. Next, the structure shown in FIG. 2 is provided. The structure includes an adhesive layer 44, a dielectric layer 42, and a highly thermally conductive substrate 40. The adhesive layer 44 may be a metal adhesive layer, such as a metal or non-metal adhesive layer such as η, Au, or Ag, such as a BCB (B-staged bisbenzocyclobutene; BCB) resin. The highly thermally conductive substrate 40 may be one of a Si wafer, a SiC wafer, a GaP wafer, or an Au, Al, Cu metal, or the like, and a high-reflectivity metal j, then It may be one of Ag, Abu Au, and the like. Next, the light-emitting monopolar wafer on which the P-type ohmic contact metal electrode layer 30 has been formed in FIG. 1 and the south conductive and high reflectivity substrate 4 in FIG. 2 are adhered together by the adhesive layer 44 and adhered well. The epitaxial wafer is then etched with an etching solution (such as 5H3P04: 3H2O2: 3H2O or INZβΗ: 35H2O2) to remove the opaque n-type gallium arsenide substrate 24. If the etching stop layer 22 is made of InGaP or A 1 GaAs, it will still absorb light generated from the active layer 18. Therefore, it is also necessary to completely remove the residual liquid, or to leave only the portion in contact with the N-type ohmic contact metal electrode layer 36. Then, a two-stage lithography and etching technique is performed to form an isolation channel and a p-type ohmic contact metal electrode layer 30 electrode connection channel.

Page 13 200417067 V. Description of the invention (9) First, the N-type aluminum gallium indium phosphide indium cladding layer 20 is filled with lithography and etching technology, the indium gallium indium activation layer 18 is filled, and the P-type bowl is made of gallium The indium upper cladding layer 16 and the P-type ohmic contact stupid crystal layer 14 are sequentially carved from top to bottom to expose an electrode connection channel 3 8 A of the p-type ohmic contact metal electrode layer 30. The width is about 1 ~ 3m i 1. Then, a second etching is performed by using lithography and etching technology, and etching is performed from top to bottom to a portion of the P-type aluminum gallium indium phosphide upper cladding layer 16 (Fig. 3) is left to form an isolation trench or island. 3 8 B, or the bottom surface of the P-type ohmic contact worm crystal layer 14 to form an isolated trench or isolated island 3 8 B (Figure 4), with an etching width of about 0.2 to 1 mi 1. Next, a photoresist pattern (not shown) is formed to define an N-type ohmic contact metal electrode layer 34 on the lower cladding layer 20 of aluminum gallium phosphide. Please note that the photoresist pattern only has openings in the N-type aluminum gallium indium lower cladding layer 20 to define the position of the n-type ohmic contact metal electrode layer 34. The rest are covered by a photoresist pattern, including the isolation trench or island 38B filled with photoresist and the electrode connection channel 38A. Subsequently, an n-type ohmic contact metal electrode layer 34 is formed. Finally, the photoresist and the metal layer formed on the photoresist are removed to define an N-type ohmic contact metal electrode layer 34. Subsequently, it is the same as the method of forming the N-type ohmic contact metal electrode layer 34. The positions of the two metal nailed wire electrode layers 36 are defined with a photoresist pattern (including the opening and the bare N-type ohmic contact metal electrode layer 34 and the bareness). The first connection channel 3 8 A and the electrode connection channel 3 8 A around the n-type aluminum gallium indium phosphide indium cladding layer 20. Then, the electrode connection channel 38A is filled with a metal layer selected from aluminum or gold nail wire. On the exposed n-type aluminum gallium indium phosphide lower cladding layer 20 and on the exposed n-type ohmic contact metal electrode layer 34, two metal nails are formed as shown in the figure.

Page 14 200417067 V. Description of the Invention The light-emitting diode structure of the line electrode layer 36 on the same side and at the same horizontal height with respect to the highly thermally conductive substrate is shown in Figures 3 and 4. Finally, annealing is performed so that the N-type ohmic contact metal electrode layer 34 forms a good ohmic contact with the lower cladding layer 20 and the P ohmic contact electrode 30 and the p-type ohmic contact stupid layer. θ The above sequence of steps is not intended to limit the present invention, and anyone skilled in the relevant arts can adjust the above sequence of steps. For example, the formation step of the isolation trench & or isolation island 3 8 B can be moved to the formation of two metal nailed electrode layers 36 and then performed without changing the diode structure of the present invention. The wavelength of light emitted by the dished aluminum gallium indium light-emitting diode obtained according to the present invention is about 6 3 5 nm, and its light output power is about ImW under an operating current of 20 m Α, which is a traditional absorption substrate The light output power of aluminum gallium indium light emitting diode is more than twice. The present invention is not limited to high-brightness aluminum gallium indium light-emitting diodes. The present invention can also be applied to other light-emitting diode materials, such as aluminum gallium arsenide red and infrared light-emitting diodes. The light-emitting diode of the present invention uses an adhesive layer 44 to join the light-emitting diode and a substrate with high thermal conductivity and high reflectivity 40. Therefore, even if the surface of the light-emitting diode is uneven, it can be used. The adhesive layer 4 4 tightly bonds them together. There will not be the entire silver engraved area. (1) The method of isolating trenches and isolating islands will make the surface rough, making it difficult to identify the package.

Page 15 200417067 V. Description of the invention (11) (2) The voltage can be reduced and the current distribution can be increased under a fixed current, so as to improve the external light emitting efficiency of the light emitting diode. The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of patent application of the present invention. Any other equivalent changes or modifications made without departing from the spirit disclosed by the present invention shall be included in the following Within the scope of patent application.

Page 16 200417067 Schematic illustration of the preferred embodiment of the present invention will be explained in more detail in the following explanatory text with the following figures: Figures 1 to 4 show a preferred embodiment according to the present invention Schematic diagram of the manufacturing process of the light-emitting diode; and Figures 5 and 6 are schematic diagrams showing the structure of a traditional light-emitting diode. Drawing numbers: 5 2: substrate 5 4: buffer layer 56: dispersed Bragg reflector 58: bottom Cladding layer 6 0: ¥ 6 6 2: Upper clad layer 6 4: High-gap current dispersing layer 7 0: P ohm contact metal electrode layer 7 2: N ohm contact metal electrode layer 7 4: Metal nail wire Electrode layer 14: P-type ohmic contact epitaxial layer 16: P-type aluminum gallium indium phosphide upper cladding layer 18: Aluminum gallium indium phosphide active layer 20: N type aluminum gallium indium phosphide cladding layer 2 2: etch stop layer

Page 17 200417067 Brief description of drawings 2 4: N-type gallium arsenide substrate 3 0: P-type ohmic contact metal electrode layer 32: High-reflectivity metal layer 3 4: N-type ohmic contact metal electrode layer 3 6: Metal Nail wire electrode layer 38A: Electrode connection channel 38B: Isolated trench or island 40. Substrate with local thermal conductivity 42: Non-conductive dielectric layer 44: Adhesive layer

Page 18

Claims (1)

200417067 6. Scope of patent application 1. A light-emitting diode at least includes: a light-emitting epitaxial multilayer structure, the light-emitting epitaxial multilayer structure includes at least-ohmic contact worm crystal layer,-upper cladding layer, one = two The layers are stacked in sequence; 乂 & a first ohmic contact metal electrode screen is reported on the Xixing potential layer formed on the ohmic contact epitaxial layer; an ohmic contact metal electrode layer is a high reflectivity metal layer Formed on the first and ohmic contact epitaxial layer; a highly thermally conductive substrate; a dielectric layer formed on the highly thermally conductive substrate; an adhesive layer, the adhesive layer adhering the first ohmic contact metal electrode Layer and the non-conductive dielectric layer; a first pinned metal electrode layer and a second ohmic contact metal electrode layer are formed on the lower cladding layer; and the light-emitting silly multilayer structure has at least one electrode connection channel and An isolation trench is formed therein, wherein the electrode connection channel penetrates the light-emitting stupid multilayer structure to connect the first ohmic contact metal electrode layer and the first pinned metal electrode layer, and the isolation trench emits light The epitaxial multilayer structure isolates and penetrates part of the upper cladding layer, so that the light emitting epitaxial multilayer structure becomes two parts. The two parts are respectively the second ohmic contact metal electrode layer of the light emitting diode and the first Nail wire metal electrode layer connection. 2. The light-emitting diode according to item 1 in the scope of the patent application, wherein the active layer of the light-emitting epitaxial multilayer structure is homogeneous of aluminum gallium indium phosphide (AlGalnP) 200417067 6. Scope of Patent Application One of the structure, single heterostructure, double heterostructure or quantum well structure. 3. The light-emitting diode according to item 1 of the scope of patent application, wherein the ohmic contact epitaxial layer is a P-type semiconductor layer, and the first ohmic contact metal electrode layer is a P-type semiconductor layer; the second The ohmic contact metal electrode layer is an N-type semiconductor layer. 4. According to the light-emitting diode described in item 1 of the scope of the patent application, the isolation trench further includes a penetration through the upper cladding layer so that the bottom of the isolation trench reaches the ohmic contact epitaxial layer. t 5. The light-emitting diode according to item 1 of the scope of patent application, wherein the substrate is selected from the group consisting of a chip (Si), a chip (SiC), and a wafer (G a P). 6. The light-emitting diode according to item 1 of the scope of patent application, wherein the substrate is one of Au, A1, and Cu metal. 7. The light-emitting diode described in item 1 of the scope of patent application, wherein the material of the bonding layer 0 includes BCB (B-stagedbisbe η ζ cycy 1 〇butene; BCB) and resin epoxy resin (E poxy) Any of them. 8. The light-emitting diode according to item 1 of the scope of patent application, wherein the material of the adhesive layer includes any one of metals such as In, Au, A 1 and the like. Page 20 200417067 6. Application for patent scope 9. The light-emitting diode described in item 1 of the scope of patent application, wherein the dielectric layer includes alumina (A 1 20 3), silicon dioxide (S i 0 2) Or silicon nitride (S i NX). 10. The light-emitting diode according to item 1 of the scope of patent application, wherein the high-reflectivity metal layer is selected from one of metals such as Au, Al, and Ag. 1 1. The light-emitting diode according to item 1 of the scope of patent application, further comprising a second metal nail wire electrode layer formed on the second ohmic contact metal electrode layer. 1 2. A method for manufacturing a light emitting diode, at least including: > Providing a light emitting epitaxial multilayer structure, the light emitting epitaxial multilayer structure is sequentially stacked with an ohmic contact stupid layer, an upper cladding layer, a An active layer, a lower cladding layer, an etch stop layer and a temporary substrate; forming a first ohmic contact metal electrode layer on the ohmic contact epitaxial layer; forming a high reflectivity metal layer on the first ohmic contact A metal electrode layer and an ohmic contact stupid crystal layer are provided with a high thermal conductivity substrate; a non-conductive dielectric layer layer is formed on the high thermal conductivity substrate; and an adhesive layer is used to bond the high thermal conductivity substrate conductive dielectric layer Layer and the high-reflectivity metal layer and the ohmic contact epitaxial layer; removing the temporary substrate and the stop etch layer; 200417067 6. The scope of the patent application uses lithography and etching technology to form an electrode connection channel. The electrode connection channel passes from the lower cladding layer of the light-emitting stupid multilayer structure to the P-type ohmic contact metal electrode layer. The lithography and #engraving technology are used to form an isolation channel, and the barrier channel runs through the light-transmitting worm-crystal structure and the island of Baba 'to isolate the above-mentioned material layer that the isolation channel passes through into the first part and the second Part, the part / part includes the electrode connection channel; forming a second ohmic contact metal electrode layer on the lower cladding layer in the second part; and A nail line metal layer is formed to fill the electrode connection channel to connect the first ohmic contact metal electrode layer and extend on the upper surface of the lower cladding layer of the first portion to form a first nail line region, and is also formed at The second ohmic contact metal electrode layer is formed to form a second pin line region. 1 3 · If the contact metal electrode layer of the scope of the patent application is used, then the above-mentioned metal layer is deposited, and finally the photoresist is removed by item 12, wherein the second ohmic photoresist pattern defines the first pin The bit layer of the line area 'is then used to remove the poorly adhered gold 1 4 · If the scope of the patent application is the following: the method of workers, workers, and workers, the life of the person is the same as the method of the U-member, in which the second European contact metal electrode layer formation step 5 6 Zheli A class Include the use of a photoresist pattern to define the position of the first nail line ^, and then deposit μ, +, & 4 to the second ohmic contact layer, and then remove the photoresist macro with tape. Ma press., Occupy the metal layer on the metal ^ pattern, and finally remove the ancestor 0 Page 22 200417067 VI. Application for Patent Scope 1 5 · The method as described in Item 12 of the Patent Application Scope, wherein the step of forming the nailed metal layer includes at least the use of a photoresist pattern to define the position of the second nailed area, and then depositing For the second ohmic contact metal electrode layer, the metal layer on the photoresist pattern is removed by an adhesive tape, and finally the photoresist is removed. 16. The method according to item 12 of the scope of patent application, further comprising performing an annealing step after the formation of the second pin line region and the second pin line region, so that the second ohmic contact metal electrode layer and the The lower cladding layer and the first ohmic contact metal electrode layer and the ohmic contact epitaxial layer form a low resistance ohmic contact. f 1 7. The method according to item 12 of the scope of patent application, wherein the step of forming an isolation channel further includes etching to stop at the ohmic contact epitaxial layer. 1 8. The method according to item 12 of the scope of patent application, wherein the above-mentioned step of forming the isolation channel can be adjusted after the step of forming the nail line metal layer. 19. The method according to item 12 of the scope of patent application, wherein the above-mentioned etching can be dry or wet etching. Page 23