WO2021128810A1 - 一种发光二极管及其制作方法 - Google Patents

一种发光二极管及其制作方法 Download PDF

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WO2021128810A1
WO2021128810A1 PCT/CN2020/101184 CN2020101184W WO2021128810A1 WO 2021128810 A1 WO2021128810 A1 WO 2021128810A1 CN 2020101184 W CN2020101184 W CN 2020101184W WO 2021128810 A1 WO2021128810 A1 WO 2021128810A1
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layer
light
narrow
well
emitting diode
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PCT/CN2020/101184
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English (en)
French (fr)
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卓祥景
程伟
尧刚
万志
蔺宇航
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厦门乾照光电股份有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/025—Physical imperfections, e.g. particular concentration or distribution of impurities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier

Definitions

  • the present invention relates to the technical field of semiconductor devices, and more specifically, to a light emitting diode and a manufacturing method thereof.
  • group III-V nitrides have been widely used in electronics and optics due to their excellent physical and chemical properties (large band gap, high breakdown electric field, high electron saturation mobility, etc.).
  • blue-green light-emitting diodes with GaN-based materials as the main material have made considerable progress in lighting, display, and digital.
  • LED Light Emitting Diode
  • the market has higher and higher requirements for LED performance.
  • Current high-light effect products such as filament lamps, high-end tubes, high-efficiency panel lights, mobile phone backlights, TV backlights, etc. have strict requirements on the luminous efficiency and reliability of LEDs, and high-reliability LEDs have become the current chip manufacturers. Hot spots of technology research and development.
  • the present invention provides a light-emitting diode and a manufacturing method thereof, which effectively solves the technical problems existing in the prior art and improves the reliability of the light-emitting diode.
  • a light emitting diode including:
  • An N-type semiconductor layer located on one side of the substrate;
  • the narrow-well wide-barrier superlattice layer, the first interface modulation layer, the narrow-well narrow-barrier superlattice layer, and the second interface modulation layer are sequentially stacked on the side of the N-type semiconductor layer away from the substrate, wherein The narrow-well wide-barrier superlattice layer and the narrow-well narrow-barrier superlattice layer are combined into a composite shallow quantum well;
  • a multiple quantum well light-emitting layer located on the side of the second interface modulation layer away from the substrate;
  • a P-type semiconductor layer located on the side of the defect covering layer away from the substrate.
  • the defect covering layer includes a first sub defect covering layer on a side close to the substrate and a second sub defect covering layer on a side far from the substrate, wherein the light emitting diode further includes:
  • a tunneling layer located between the first sub-defect covering layer and the second sub-defect covering layer, wherein the impedance of the tunneling layer is less than the impedance of the defect covering layer.
  • the tunnel layer is an AljInkGa1-j-kN layer, where 0 ⁇ j ⁇ 0.5 and 0 ⁇ k ⁇ 0.5.
  • the thickness of the tunneling layer ranges from 1 nm to 10 nm, including the endpoint value.
  • the defect covering layer is an unintentionally doped AlaInbGa1-a-bN layer, where 0 ⁇ a ⁇ 0.5 and 0 ⁇ b ⁇ 0.5.
  • the thickness of the defect covering layer ranges from 10 nm to 50 nm, including endpoint values.
  • the first interface modulation layer and the second interface modulation layer are both AlxInyGa1-x-yN layers, where 0 ⁇ x ⁇ 0.5 and 0 ⁇ y ⁇ 0.5.
  • the light emitting diode further includes:
  • a buffer layer and an unintentional doped layer sequentially superimposed between the substrate and the N-type semiconductor layer;
  • an electron blocking layer located between the multiple quantum well light-emitting layer and the defect covering layer
  • an ohmic contact layer located on the side of the P-type semiconductor layer away from the substrate.
  • the present invention also provides a method for manufacturing a light-emitting diode, including:
  • a narrow-well wide-barrier superlattice layer, a first interface modulation layer, a narrow-well narrow-barrier superlattice layer, and a second interface modulation layer are sequentially stacked on the side of the N-type semiconductor layer away from the substrate.
  • the narrow-well wide-barrier superlattice layer and the narrow-well narrow-barrier superlattice layer are combined into a composite shallow quantum well;
  • a P-type semiconductor layer is formed on the side of the defect covering layer away from the substrate.
  • the manufacturing method of the defect covering layer includes:
  • a reaction source is introduced into the reaction chamber in a pulse mode.
  • the technical solution provided by the present invention has at least the following advantages:
  • the present invention provides a light emitting diode and a manufacturing method thereof, including: a substrate; an N-type semiconductor layer located on one side of the substrate; A well-wide barrier superlattice layer, a first interface modulation layer, a narrow-well narrow-barrier superlattice layer, and a second interface modulation layer, wherein the narrow-well-wide-barrier superlattice layer and the narrow-well-narrow-barrier superlattice layer
  • the lattice layer is combined into a composite shallow quantum well; a multiple quantum well light-emitting layer located on the side of the second interface modulation layer away from the substrate; a defect covering layer located on the side of the multiple quantum well light-emitting layer away from the substrate And, a P-type semiconductor layer located on the side of the defect covering layer away from the substrate.
  • the light-emitting diode provided by the present invention includes a composite shallow quantum well, thereby enabling the light-emitting diode to increase the channel of hole injection into the multi-quantum well light-emitting layer, and improve the hole injection efficiency under high current density.
  • a first interface modulation layer is formed between the narrow-well wide-barrier superlattice layer and the narrow-well narrow-barrier superlattice layer, and a first interface modulation layer is formed between the narrow-well narrow-barrier superlattice layer and the multiple quantum well light-emitting layer.
  • the two-interface modulation layer can further reduce the band bending at the interface between the narrow-well wide-barrier superlattice layer and the narrow-well narrow-barrier superlattice layer through the first interface modulation layer, and reduce the narrow-well narrowness through the second interface modulation layer
  • the energy band at the interface between the barrier superlattice layer and the multi-quantum well light-emitting layer is bent to reduce the height of the heterogeneous barrier introduced thereby, thereby reducing the operating voltage of the light-emitting diode and improving the light-emitting efficiency of the light-emitting diode.
  • the V-shaped defects formed on the multiple quantum well light-emitting layer and the composite shallow quantum well are covered and flattened by the defect covering layer, and the current is effectively blocked from entering the V-shaped defects, thereby effectively reducing the leakage channels formed by the V-shaped defects.
  • FIG. 1 is a schematic structural diagram of a light emitting diode provided by an embodiment of the present invention
  • FIG. 2 is a schematic structural diagram of another light emitting diode provided by an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of yet another light emitting diode provided by an embodiment of the present invention.
  • FIG. 4 is a flowchart of a method for manufacturing a light emitting diode according to an embodiment of the present invention
  • FIG. 5 is a flowchart of a method for manufacturing a defect covering layer according to an embodiment of the present invention.
  • the conventional LED epitaxial structure mainly includes a sapphire substrate, a U-GaN buffer layer, an N-GaN electron supply layer, a multiple quantum well light-emitting layer, an electron blocking layer, a hole supply layer, and an ohmic contact layer.
  • a composite shallow quantum well between the N-GaN electron supply layer and the multiple quantum well light-emitting layer.
  • the composite shallow quantum well includes 3-6 periods of narrow well wide barrier layers and 5-10 periods of narrow well narrow barrier layers, wherein the material of the well layer is InGaN, and the material of the barrier layer is GaN.
  • V-shaped defects By introducing composite shallow quantum wells, some linear dislocations in the bottom layer can form V-shaped defects.
  • the size and density of V-shaped defects can be controlled to a certain extent.
  • the existence of the V-shaped defect also brings more leakage channels, which makes the leakage current of the LED device larger, and affects the reliability of the LED device.
  • the narrow-well wide barrier layer and the narrow-well narrow barrier layer have different In components and different InGaN-GaN width ratios, so that the piezoelectric polarization fields of the two regions are quite different.
  • the interface between the narrow-well wide-barrier superlattice structure and the narrow-well narrow-barrier superlattice structure in the composite shallow quantum well will have a larger band bending, which introduces a higher heterogeneity
  • the barrier layer affects the transmission of electrons, increases the operating voltage of the LED device and reduces the luminous efficiency of the LED device.
  • this problem also exists at the interface of composite shallow quantum well and multi-quantum well superlattice light-emitting structure.
  • the present invention provides a light-emitting diode and a manufacturing method thereof, which effectively solves the technical problems existing in the prior art and improves the reliability of the light-emitting diode.
  • the technical solutions provided by the present invention are as follows, and the technical solutions provided by the embodiments of the present invention will be described in detail with reference to FIGS. 1 to 5.
  • FIG. 1 it is a schematic structural diagram of a light-emitting diode provided by an embodiment of the present invention, where the light-emitting diode provided by the present invention includes:
  • An N-type semiconductor layer 200 located on one side of the substrate;
  • the narrow-well wide-barrier superlattice layer 311, the first interface modulation layer 321, the narrow-well narrow-barrier superlattice layer 312, and the second interface modulation layer are sequentially stacked on the side of the N-type semiconductor layer 200 away from the substrate 100.
  • the multiple quantum well light-emitting layer 400 located on the side of the second interface modulation layer 322 away from the substrate 100;
  • the light-emitting diode provided by the present invention includes a composite shallow quantum well, thereby enabling the light-emitting diode to increase the channel of hole injection into the multi-quantum well light-emitting layer and improve the hole injection efficiency under high current density.
  • a first interface modulation layer is formed between the narrow-well wide-barrier superlattice layer and the narrow-well narrow-barrier superlattice layer, and a first interface modulation layer is formed between the narrow-well narrow-barrier superlattice layer and the multiple quantum well light-emitting layer.
  • the two-interface modulation layer can further reduce the band bending at the interface between the narrow-well wide-barrier superlattice layer and the narrow-well narrow-barrier superlattice layer through the first interface modulation layer, and reduce the narrow-well narrowness through the second interface modulation layer
  • the energy band at the interface between the barrier superlattice layer and the multi-quantum well light-emitting layer is bent to reduce the height of the heterogeneous barrier introduced thereby, thereby reducing the operating voltage of the light-emitting diode and improving the light-emitting efficiency of the light-emitting diode.
  • the V-shaped defects formed on the multiple quantum well light-emitting layer and the composite shallow quantum well are covered and flattened by the defect covering layer, and the current is effectively blocked from entering the V-shaped defects, thereby effectively reducing the leakage channels formed by the V-shaped defects.
  • the defect covering layer provided by the present invention is an unintentionally doped AlaInbGa1-a-bN layer, where 0 ⁇ a ⁇ 0.5 and 0 ⁇ b ⁇ 0.5.
  • the thickness of the defect covering layer provided by the present invention ranges from 10 nm to 50 nm, including the endpoint value.
  • the first interface modulation layer and the second interface modulation layer provided by the present invention are both an N-type AlxInyGa1-x-yN layer, and the doping elements of the N-type AlxInyGa1-x-yN layer It may be Si, where 0 ⁇ x ⁇ 0.5 and 0 ⁇ y ⁇ 0.5.
  • FIG. 2 it is a schematic structural diagram of another light emitting diode provided by an embodiment of the present invention, in which the defect covering layer 500 provided by the embodiment of the present invention includes a first side close to the substrate 100.
  • the tunneling layer 530 located between the first sub-defect covering layer 510 and the second sub-defect covering layer 520, wherein the impedance of the tunneling layer 530 is less than the impedance of the defect covering layer 500.
  • a tunneling layer is inserted into the defect covering layer provided by the embodiment of the present invention, and the impedance of the tunneling layer is less than the impedance of the defect covering layer, so that holes can directly tunnel into the non-V-shaped defect area.
  • the multi-quantum well light-emitting layer can further reduce the operating voltage of the light-emitting diode through the tunneling layer, and improve the reliability of the light-emitting diode.
  • the tunneling layer provided by the present invention is an AljInkGa1-j-kN layer, and the doping element of the AljInkGa1-j-kN layer may be Mg or Si, where 0 ⁇ j ⁇ 0.5 and 0 ⁇ k ⁇ 0.5.
  • the thickness of the tunneling layer provided by the present invention ranges from 1 nm to 10 nm, including the endpoint value.
  • FIG. 3 it is a schematic structural diagram of another light-emitting diode provided by an embodiment of the present invention, wherein the light-emitting diode provided by the embodiment of the present invention further includes:
  • a buffer layer 110 and an unintentional doped layer 120 are sequentially superimposed between the substrate 100 and the N-type semiconductor layer 200;
  • an electron blocking layer 410 located between the multiple quantum well light-emitting layer 400 and the defect covering layer 500;
  • FIG. 4 it is a flowchart of a method for manufacturing a light-emitting diode according to an embodiment of the present invention, wherein the method for manufacturing a light-emitting diode according to the present invention includes:
  • the substrate provided by the present invention may be a substrate made of sapphire and other materials, and the present invention does not specifically limit the parameters such as the thickness of the substrate, and needs to be specifically designed according to actual applications.
  • the growth buffer layer and the unintentional doped layer can also be stacked in sequence.
  • the buffer layer may be a PVD (physical vapor deposition)-AlN buffer layer, and the thickness of the buffer layer may range from 10 nm to 100 nm, including endpoint values; and, the unintentionally doped layer may be a U-GaN layer, and the non-intentional doped layer may be a U-GaN layer.
  • the thickness of the deliberately doped layer can range from 1 ⁇ m to 4 ⁇ m, inclusive.
  • the N-type semiconductor layer provided by the present invention may be an N-type GaN layer, and the thickness of the N-type semiconductor layer may range from 1 ⁇ m to 3 ⁇ m, including endpoints; and the doping concentration of the N-type semiconductor layer may be 1E18-1E20/cm3.
  • a narrow-well wide-barrier superlattice layer, a first interface modulation layer, a narrow-well narrow-barrier superlattice layer, and a second interface modulation layer are sequentially stacked on the side of the N-type semiconductor layer away from the substrate, wherein ,
  • the combination of the narrow-well wide-barrier superlattice layer and the narrow-well narrow-barrier superlattice layer is a composite shallow quantum well;
  • the narrow-well wide-barrier superlattice layer provided by the present invention may be an InGaN/GaN superlattice layer, where the thickness of the InGaN layer may range from 1 nm to 10 nm, including endpoints, and the In group The sub-value range can be 0.01-0.2, including the endpoint value, the thickness of the GaN layer can range from 5nm-100nm, including the endpoint value, and the N-type doping concentration of the narrow well-wide barrier superlattice layer is 0-5E17/cm3 .
  • the first interface modulation layer provided by the embodiment of the present invention may be an N-type AlxInyGa1-x-yN layer, the thickness of the first interface modulation layer may range from 10 nm to 200 nm, including the endpoint value, and the N-type doping of the first interface modulation layer
  • the impurity concentration is 1E17-1E19/cm3.
  • the narrow-well and narrow-barrier superlattice layer provided by the embodiments of the present invention may be an InGaN/GaN superlattice layer, where the thickness of the InGaN layer may range from 1 nm to 5 nm, including endpoints, and the In composition value range may be 0.05-0.1, including the endpoint value, the thickness of the GaN layer can range from 1nm-20nm, including the endpoint value, and the N-type doping concentration of the narrow-well and narrow-barrier superlattice layer is 0-5E17/cm3.
  • the second interface modulation layer provided by the embodiment of the present invention may be an N-type AlxInyGa1-x-yN layer, the thickness of the second interface modulation layer may range from 10 nm to 200 nm, including the endpoint value, and the N type of the second interface modulation layer
  • the type doping concentration is 1E17-1E19/cm3.
  • the LED usually adopts a single quantum well width design, either a wide well or a narrow well.
  • the electron-hole recombination ability of the narrow well is greater than that of the wide well, and the electron-hole wave function overlap of the narrow well is greater than that of the wide well, and the recombination efficiency is high; therefore, the light-emitting diode provided by the embodiment of the present invention can be effective by recombining shallow quantum wells. Improve the recombination efficiency of the device.
  • the multiple quantum well light-emitting layer provided by the present invention may be an InGaN/GaN multiple quantum well light-emitting layer, wherein the thickness of the InGaN layer may be 1nm-5nm, including the endpoint value, and the value of the In composition It can be 0.1-0.25, including the endpoint value, the thickness of the GaN layer can be in the range of 5nm-15nm, including the endpoint value, and the N-type doping concentration of the multiple quantum well light-emitting layer is 0-5E17/cm3.
  • an electron blocking layer may also be formed.
  • the electron blocking layer may be an AlGaN layer, the Al blocking value range is 0.05-0.3, including the endpoint value; the thickness of the electron blocking layer may range from 5nm-50nm, including the endpoint value, and the P-type doping concentration of the electron blocking layer It can be 1E18-1E20/cm3.
  • V-shaped defects are formed on the composite shallow quantum well and the multiple quantum well light-emitting layer. Therefore, a high-impedance defect covering layer is formed on the multiple quantum well light-emitting layer, and then the V-shaped defect is formed by the high-impedance defect covering layer. Defects are covered and filled, effectively blocking current from entering the V-shaped defect area.
  • the defect covering layer provided in the embodiment of the present invention may be an unintentionally doped AlaInbGa1-a-bN layer.
  • a low-impedance tunneling layer can be inserted into the defect covering layer provided by the embodiment of the present invention, so that the holes can directly tunnel into the multi-quantum well light-emitting layer in the non-V-shaped defect region, and then can pass through the tunnel.
  • the layer can further reduce the operating voltage of the light-emitting diode and improve the reliability of the light-emitting diode.
  • the low-resistance tunneling layer provided by the embodiment of the present invention may be an AljInkGa1-j-kN layer, and the doping element of the AljInkGa1-j-kN layer may be Mg or Si.
  • the P-type semiconductor layer provided by the present invention may be a P-type GaN layer, wherein the doping concentration of the P-type semiconductor layer may be 5E18-1E20/cm3, and the thickness of the P-type semiconductor layer may be in the range of 10nm-300nm, including endpoint values.
  • the light emitting diode provided by the present invention can also form an ohmic contact layer on the side of the P-type semiconductor layer away from the substrate, wherein the ohmic contact layer can be a P-type GaN layer, and the doping concentration of the ohmic contact layer can be 1E19- 1E20/cm3.
  • FIG. 5 it is a flowchart of a method for manufacturing a defect covering layer according to an embodiment of the present invention, wherein the method for manufacturing the defect covering layer provided by the present invention includes:
  • reaction source provided by the embodiment of the present invention is introduced into the reaction chamber in a pulse mode, and the growth environment in the reaction chamber is a high temperature and low pressure environment, which can increase the migration time of atoms on the surface of the epitaxial structure, so that the atoms can be fully expanded and promoted. Two-dimensional growth to quickly cover V-shaped defects.
  • the first sub-defect covering layer is fabricated by the above-mentioned method and the tunneling layer is grown, and then the second sub-defect covering layer is still produced by the above-mentioned method.
  • the defect covering layer provided in the embodiment of the present invention may be an unintentionally doped AlaInbGa1-a-bN layer
  • the method of fabricating the unintentionally doped AlaInbGa1-a-bN layer includes:
  • MO reaction source includes a corresponding combination of Al source, Ga source, and In source.
  • the source of the three groups and the source of the five groups are pulsed, and then The migration time of group III atoms on the surface of the epitaxial structure can be increased, so that the atoms can be fully expanded to promote two-dimensional growth, and then quickly cover V-shaped defects.
  • the present invention provides a light emitting diode and a manufacturing method thereof, including: a substrate; an N-type semiconductor layer located on one side of the substrate; A well-wide barrier superlattice layer, a first interface modulation layer, a narrow-well narrow-barrier superlattice layer, and a second interface modulation layer, wherein the narrow-well-wide-barrier superlattice layer and the narrow-well-narrow-barrier superlattice layer
  • the lattice layer is combined into a composite shallow quantum well; a multiple quantum well light-emitting layer located on the side of the second interface modulation layer away from the substrate; a defect covering layer located on the side of the multiple quantum well light-emitting layer away from the substrate And, a P-type semiconductor layer located on the side of the defect covering layer away from the substrate.
  • the light-emitting diode provided by the present invention includes a composite shallow quantum well, thereby enabling the light-emitting diode to increase the channel of hole injection into the multi-quantum well light-emitting layer and improve the hole injection efficiency under high current density.
  • a first interface modulation layer is formed between the narrow-well wide-barrier superlattice layer and the narrow-well narrow-barrier superlattice layer, and a first interface modulation layer is formed between the narrow-well narrow-barrier superlattice layer and the multiple quantum well light-emitting layer.
  • the two-interface modulation layer in turn, can reduce the band bending at the interface between the narrow-well wide-barrier superlattice layer and the narrow-well narrow-barrier superlattice layer through the first interface modulation layer, and reduce the narrow-well narrowness through the second interface modulation layer
  • the energy band at the interface between the barrier superlattice layer and the multi-quantum well light-emitting layer is bent to reduce the height of the heterogeneous barrier introduced thereby, thereby reducing the operating voltage of the light-emitting diode and improving the light-emitting efficiency of the light-emitting diode.
  • the V-shaped defects formed on the multiple quantum well light-emitting layer and composite shallow quantum well are covered and flattened by the defect covering layer, and the current is effectively blocked from entering the V-shaped defects, thereby effectively reducing the leakage channels formed by the V-shaped defects.

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Abstract

一种发光二极管及其制作方法，该发光二极管包括有复合浅量子阱，提高大电流密度下空穴的注入效率。通过第一界面调制层（321）减缓窄阱宽垒超晶格层（311）和窄阱窄垒超晶格层（312）的界面处的能带弯曲，及通过第二界面调制层（322）减缓窄阱窄垒超晶格层（312）和多量子阱发光层（400）的界面处的能带弯曲，降低由此引入的异质势垒高度，进而降低发光二极管的工作电压且提高发光二极管的发光效率。通过缺陷覆盖层（500）来覆盖填平多量子阱发光层（400）和复合浅量子阱上形成的V型缺陷，而有效地阻挡电流进入V型缺陷，从而有效减少V型缺陷所形成的漏电通道，使得空穴从非V型缺陷区域进入多量子阱发光层（400），增大空穴-电子复合几率，最终提高了发光二极管的可靠性和发光效率。

Description

一种发光二极管及其制作方法
本申请要求于2019年12月26日提交中国专利局、申请号为201911366643.7、发明名称为“一种发光二极管及其制作方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及半导体器件技术领域，更为具体地说，涉及一种发光二极管及其制作方法。
背景技术
近来年，III-V族氮化物，由于其优异的物理及化学特性(禁带宽度大、击穿电场高、电子饱和迁移率高等)，从而广泛应用于电子、光学领域。其中，以GaN基为主要材料的蓝绿光发光二极管，更是在照明、显示、数码方面有着长足的发展。随着LED(Light Emitting Diode，发光二极管)应用端的逐渐扩大，市场对LED性能的要求也越来越高。目前的高光效应用产品比如灯丝灯、高阶灯管、高光效面板灯、手机背光、电视背光等对LED的发光效率和可靠性有着严格的要求，高可靠性的LED成为了当前各芯片厂商技术研发的热点。
发明内容
有鉴于此，本发明提供了一种发光二极管及其制作方法，有效解决现有技术中存在的技术问题，提高了发光二极管的可靠性。
为实现上述目的，本发明提供的技术方案如下：
一种发光二极管，包括：
衬底；
位于所述衬底一侧上的N型半导体层；
位于所述N型半导体层背离所述衬底一侧依次叠加的窄阱宽垒超晶格层、第一界面调制层、窄阱窄垒超晶格层及第二界面调制层，其中，所述窄阱宽垒超晶格层和所述窄阱窄垒超晶格层组合为复合浅量子阱；
位于所述第二界面调制层背离所述衬底一侧的多量子阱发光层；
位于所述多量子阱发光层背离所述衬底一侧的缺陷覆盖层；
以及，位于所述缺陷覆盖层背离所述衬底一侧的P型半导体层。
可选的，所述缺陷覆盖层包括靠近所述衬底一侧的第一子缺陷覆盖层及远离所述衬底一侧的第二子缺陷覆盖层，其中，所述发光二极管还包括：
位于所述第一子缺陷覆盖层与所述第二子缺陷覆盖层之间的隧穿层，其中，所述隧穿层的阻抗小于所述缺陷覆盖层的阻抗。
可选的，所述隧穿层为AljInkGa1-j-kN层，其中，0≤j＜0.5且0≤k＜0.5。
可选的，所述隧穿层的厚度范围为1nm-10nm，包括端点值。
可选的，所述缺陷覆盖层为非故意掺杂AlaInbGa1-a-bN层，其中，0≤a＜0.5且0≤b＜0.5。
可选的，所述缺陷覆盖层的厚度范围为10nm-50nm，包括端点值。
可选的，所述第一界面调制层和所述第二界面调制层均为AlxInyGa1-x-yN层，其中，0≤x＜0.5且0≤y＜0.5。
可选的，所述发光二极管还包括：
位于所述衬底与所述N型半导体层之间依次叠加的缓冲层和非故意掺杂层；
和/或，位于所述多量子阱发光层与所述缺陷覆盖层之间的电子阻挡层；
和/或，位于所述P型半导体层背离所述衬底一侧的欧姆接触层。
相应的，本发明还提供了一种发光二极管的制作方法，包括：
提供衬底；
在所述衬底一侧上形成N型半导体层；
在所述N型半导体层背离所述衬底一侧依次叠加形成窄阱宽垒超晶格层、第一界面调制层、窄阱窄垒超晶格层及第二界面调制层，其中，所述窄阱宽垒超晶格层和所述窄阱窄垒超晶格层组合为复合浅量子阱；
在所述第二界面调制层背离所述衬底一侧形成多量子阱发光层；
在所述多量子阱发光层背离所述衬底一侧形成缺陷覆盖层；
在所述缺陷覆盖层背离所述衬底一侧形成P型半导体层。
可选的，所述缺陷覆盖层的制作方法包括：
将反应室的生长压力调整为50Torr-200Torr，包括端点值，同时将所述反应室的生长温度调整为900℃-1100℃，包括端点值；
按脉冲模式在所述反应室内通入反应源。
相较于现有技术，本发明提供的技术方案至少具有以下优点：
本发明提供了一种发光二极管及其制作方法，包括：衬底；位于所述衬底一侧上的N型半导体层；位于所述N型半导体层背离所述衬底一侧依次叠加的窄阱宽垒超晶格层、第一界面调制层、窄阱窄垒超晶格层及第二界面调制层，其中，所述窄阱宽垒超晶格层和所述窄阱窄垒超晶格层组合为复合浅量子阱；位于所述第二界面调制层背离所述衬底一侧的多量子阱发光层；位于所述多量子阱发光层背离所述衬底一侧的缺陷覆盖层；以及，位于所述缺陷覆盖层背离所述衬底一侧的P型半导体层。
由上述内容可知，本发明提供的发光二极管包括有复合浅量子阱，进而能够使得发光二极管增加空穴注入多量子阱发光层的通道，提高大电流密度下空穴的注入效率。同时，在窄阱宽垒超晶格层和窄阱窄垒超晶格层之间形成有第一界面调制层，及在窄阱窄垒超晶格层和多量子阱发光层之间形成第二界面调制层，进而能够通过第一界面调制层减缓窄阱宽垒超晶格层和窄阱窄垒超晶格层的界面处的能带弯曲，及通过第二界面调制层减缓窄阱窄垒超晶格层和多量子阱发光层的界面处的能带弯曲，降低由此引入的异质势垒高度，进而降低发光二极管的工作电压且提高发光二极管的发光效率。此外，通过位于缺陷覆盖层来覆盖填平多量子阱发光层和复合浅量子阱上形成的V型缺陷，而有效的阻挡电流进入V型缺陷，从而有效减少V型缺陷所形成的漏电通道，使得空穴从非V型缺陷区域进入多量子阱发光层，增大空穴-电子复合几率，最终提高了发光二极管的可靠性和发光效率。
附图说明
图1为本发明实施例提供的一种发光二极管的结构示意图；
图2为本发明实施例提供的另一种发光二极管的结构示意图；
图3为本发明实施例提供的又一种发光二极管的结构示意图；
图4为本发明实施例提供的一种发光二极管的制作方法的流程图；
图5为本发明实施例提供的一种缺陷覆盖层的制作方法的流程图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是 全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
正如背景技术所述，常规的LED外延结构主要包括蓝宝石衬底、U-GaN缓冲层、N-GaN电子供给层、多量子阱发光层、电子阻挡层、空穴供给层和欧姆接触层等。为了提高LED的发光效率，研发人员在N-GaN电子供给层和多量子阱发光层之间引入了复合浅量子阱。其中，复合浅量子阱包括3-6个周期的窄阱宽垒层和5-10个周期的窄阱窄垒层，其中阱层的材料为InGaN，垒层的材料为GaN。通过引入复合浅量子阱，可以使得部分底层的线性位错形成V型缺陷，通过控制复合浅量子阱的周期数和厚度，可以一定程度上控制V型缺陷的大小和密度。有研究表明，V型缺陷可以增加空穴注入有源区的通道，即可以使得空穴通过V型缺陷侧壁注入多量子阱发光区，提高大电流密度下空穴的注入效率。但是V型缺陷的存在却也带来了更多的漏电通道，使得LED器件漏电流变大，影响LED器件的可靠性。此外，由于InN与GaN之间的晶格失配，在InGaN/GaN超晶格层中存在较大的压电极化场。复合浅量子阱中窄阱宽垒层和窄阱窄垒层由于不同的In组份和不同的InGaN-GaN宽度比，使得两个区域的压电极化场存在较大的差异。在内建电场的共同作用下，复合浅量子阱中窄阱宽垒层超晶格结构与窄阱窄垒超晶格结构界面将存在较大的能带弯曲，引入了一个较高的异质势垒层，从而影响电子的传输，增加LED器件的工作电压和降低LED器件的发光效率。同样的，在复合浅量子阱和多量子阱超晶格发光结构界面也存在这个问题。
基于此，本发明提供了一种发光二极管及其制作方法，有效解决现有技术中存在的技术问题，提高了发光二极管的可靠性。为实现上述目的，本发明提供的技术方案如下，具体结合图1至图5对本发明实施例提供的技术方案进行详细的描述。
参考图1所示，为本发明实施例提供的一种发光二极管的结构示意图，其中，本发明提供的发光二极管包括：
衬底100；
位于所述衬底一侧上的N型半导体层200；
位于所述N型半导体层200背离所述衬底100一侧依次叠加的窄阱宽垒 超晶格层311、第一界面调制层321、窄阱窄垒超晶格层312及第二界面调制层322，其中，所述窄阱宽垒超晶格层311和所述窄阱窄垒超晶格层312组合为复合浅量子阱；
位于所述第二界面调制层322背离所述衬底100一侧的多量子阱发光层400；
位于所述多量子阱发光层400背离所述衬底100一侧的缺陷覆盖层500；
以及，位于所述缺陷覆盖层500背离所述衬底一侧的P型半导体层600。
可以理解的，本发明提供的发光二极管包括有复合浅量子阱，进而能够使得发光二极管增加空穴注入多量子阱发光层的通道，提高大电流密度下空穴的注入效率。同时，在窄阱宽垒超晶格层和窄阱窄垒超晶格层之间形成有第一界面调制层，及在窄阱窄垒超晶格层和多量子阱发光层之间形成第二界面调制层，进而能够通过第一界面调制层减缓窄阱宽垒超晶格层和窄阱窄垒超晶格层的界面处的能带弯曲，及通过第二界面调制层减缓窄阱窄垒超晶格层和多量子阱发光层的界面处的能带弯曲，降低由此引入的异质势垒高度，进而降低发光二极管的工作电压且提高发光二极管的发光效率。此外，通过位于缺陷覆盖层来覆盖填平多量子阱发光层和复合浅量子阱上形成的V型缺陷，而有效的阻挡电流进入V型缺陷，从而有效减少V型缺陷所形成的漏电通道，使得空穴从非V型缺陷区域进入多量子阱发光层，增大空穴-电子复合几率，最终提高了发光二极管的可靠性和发光效率。
在本发明一实施例中，本发明提供的所述缺陷覆盖层为非故意掺杂AlaInbGa1-a-bN层，其中，0≤a＜0.5且0≤b＜0.5。可选的，本发明提供的所述缺陷覆盖层的厚度范围为10nm-50nm，包括端点值。
在本发明一实施例中，本发明提供的所述第一界面调制层和所述第二界面调制层均为N型AlxInyGa1-x-yN层，N型AlxInyGa1-x-yN层的掺杂元素可以为Si，其中，0≤x＜0.5且0≤y＜0.5。
进一步的，参考图2所示，为本发明实施例提供的另一种发光二极管的结构示意图，其中，本发明实施例提供的所述缺陷覆盖层500包括靠近所述衬底100一侧的第一子缺陷覆盖层510及远离所述衬底100一侧的第二子缺陷覆盖 层520，其中，所述发光二极管还包括：
位于所述第一子缺陷覆盖层510与所述第二子缺陷覆盖层520之间的隧穿层530，其中，所述隧穿层530的阻抗小于所述缺陷覆盖层500的阻抗。
可以理解的，本发明实施例提供的缺陷覆盖层中还插入设置有一隧穿层，且隧穿层的阻抗小于缺陷覆盖层的阻抗，进而可以使得空穴在非V型缺陷区域直接隧穿进入多量子阱发光层，进而能够通过隧穿层能够进一步降低发光二极管的工作电压，提高发光二极管的可靠性。
在本发明一实施例中，本发明提供的所述隧穿层为AljInkGa1-j-kN层，且AljInkGa1-j-kN层的掺杂元素可以为Mg或Si，其中，0≤j＜0.5且0≤k＜0.5。可选的，本发明提供的所述隧穿层的厚度范围为1nm-10nm，包括端点值。
为了进一步提高发光二极管的可靠性和发光效率，本发明还可以对发光二极管的结构进行优化。参考图3所示，为本发明实施例提供的又一种发光二极管的结构示意图，其中，本发明实施例提供的所述发光二极管还包括：
位于所述衬底100与所述N型半导体层200之间依次叠加的缓冲层110和非故意掺杂层120；
和/或，位于所述多量子阱发光层400与所述缺陷覆盖层500之间的电子阻挡层410；
和/或，位于所述P型半导体层600背离所述衬底100一侧的欧姆接触层610。
下面结合制作方法对本发明实施例提供的发光二极管进行更详细的描述。参考图4所示，为本发明实施例提供的一种发光二极管的制作方法流程图，其中，本发明还的发光二极管的制作方法包括：
S1、提供衬底；
在本发明一实施例中，本发明提供的衬底可以为蓝宝石等材质衬底，且本发明对衬底的厚度等参数不做具体限制，需要根据实际应用进行具体设计。
本发明实施例可以在衬底上制作N型半导体层之前，还可以依次叠加生长缓冲层和非故意掺杂层。其中，缓冲层可以为PVD(物理气相沉积法)-AlN 缓冲层，且缓冲层的厚度范围可以为10nm-100nm，包括端点值；以及，非故意掺杂层可以为U-GaN层，且非故意掺杂层的厚度范围可以为1μm-4μm，包括端点值。
S2、在所述衬底一侧上形成N型半导体层；
在本发明一实施例中，本发明提供的N型半导体层可以为N型GaN层，N型半导体层厚度范围可以为1μm-3μm，包括端点值；且N型半导体层的掺杂浓度可以为1E18-1E20/cm3。
S3、在所述N型半导体层背离所述衬底一侧依次叠加形成窄阱宽垒超晶格层、第一界面调制层、窄阱窄垒超晶格层及第二界面调制层，其中，所述窄阱宽垒超晶格层和所述窄阱窄垒超晶格层组合为复合浅量子阱；
在本发明一实施例中，本发明提供的窄阱宽垒超晶格层可以为InGaN/GaN超晶格层，其中，InGaN层的厚度范围可以为1nm-10nm，包括端点值，且In组分取值范围可以为0.01-0.2，包括端点值，GaN层的厚度范围可以为5nm-100nm，包括端点值，且窄阱宽垒超晶格层的N型掺杂浓度为0-5E17/cm3。
本发明实施例提供的第一界面调制层可以为N型AlxInyGa1-x-yN层，第一界面调制层的厚度范围可以为10nm-200nm，包括端点值，且第一界面调制层的N型掺杂浓度为1E17-1E19/cm3。
本发明实施例提供的窄阱窄垒超晶格层可以为InGaN/GaN超晶格层，其中，InGaN层的厚度范围可以为1nm-5nm，包括端点值，且In组分取值范围可以为0.05-0.1，包括端点值，GaN层的厚度范围可以为1nm-20nm，包括端点值，且窄阱窄垒超晶格层的N型掺杂浓度为0-5E17/cm3。
以及，本发明实施例提供的第二界面调制层可以为N型AlxInyGa1-x-yN层，第二界面调制层的厚度范围可以为10nm-200nm，包括端点值，且第二界面调制层的N型掺杂浓度为1E17-1E19/cm3。
可以理解的，LED通常采用单一量子阱宽设计，或者宽阱，或者窄阱。窄阱的电子-空穴复合能力大于宽阱，且窄阱的电子-空穴波函数交叠大于宽阱，复合效率高；故而本发明实施例提供的发光二极管，通过复合浅量子阱能够有效提高器件的复合效率。
S4、在所述第二界面调制层背离所述衬底一侧形成多量子阱发光层；
在本发明一实施例中，本发明提供的多量子阱发光层可以为InGaN/GaN多量子阱发光层，其中，InGaN层的厚度可以为1nm-5nm，包括端点值，In组分的取值可以为0.1-0.25，包括端点值，GaN层的厚度范围可以为5nm-15nm，包括端点值，且多量子阱发光层的N型掺杂浓度为0-5E17/cm3。
在本发明一实施例中，在多量子阱发光层上形成缺陷覆盖层前，还可以形成电子阻挡层。其中，电子阻挡层可以为AlGaN层，Al阻挡取值范围为0.05-0.3，包括端点值；电子阻挡层的厚度范围可以为5nm-50nm，包括端点值，且电子阻挡层的P型掺杂浓度可以为1E18-1E20/cm3。
S5、在所述多量子阱发光层背离所述衬底一侧形成缺陷覆盖层；
可以理解的，复合浅量子阱和多量子阱发光层上形成有V型缺陷，因而，通过在多量子阱发光层上形成高阻抗的缺陷覆盖层，而后通过高阻抗的缺陷覆盖层将V型缺陷覆盖填平，有效阻挡电流进入V型缺陷区。在本发明一实施例中，本发明实施例提供的缺陷覆盖层可以为非故意掺杂AlaInbGa1-a-bN层。
进一步的，本发明实施例提供的缺陷覆盖层中还可以插入一低阻抗的隧穿层，进而可以使得空穴在非V型缺陷区域直接隧穿进入多量子阱发光层，进而能够通过隧穿层能够进一步降低发光二极管的工作电压，提高发光二极管的可靠性。在本发明一实施例中，本发明实施例提供的低阻抗的隧穿层可以为AljInkGa1-j-kN层，且AljInkGa1-j-kN层的掺杂元素可以为Mg或Si。
S6、在所述缺陷覆盖层背离所述衬底一侧形成P型半导体层。
在本发明一实施例中，本发明提供的P型半导体层可以为P型GaN层，其中，P型半导体层的掺杂浓度可以为5E18-1E20/cm3，P型半导体层的厚度范围可以为10nm-300nm，包括端点值。
进一步的，本发明提供的发光二极管还可以在P型半导体层背离衬底一侧形成欧姆接触层，其中，欧姆接触层可以为P型GaN层，且欧姆接触层的掺杂浓度可以为1E19-1E20/cm3。
参考图5所示，为本发明实施例提供的一种缺陷覆盖层的制作方法的流程图，其中，本发明提供的所述缺陷覆盖层的制作方法包括：
S51、将反应室的生长压力调整为50Torr-200Torr，包括端点值，同时将所 述反应室的生长温度调整为900℃-1100℃，包括端点值；
S52、按脉冲模式在所述反应室内通入反应源。
可以理解的，本发明实施例提供的反应源按照脉冲模式通入反应室内，且反应室内生长环境为高温低压环境，进而可以增加原子在外延结构表面的迁移时间，使得原子可以充分的扩展而促进二维生长，进而快速的覆盖V型缺陷。
需要说明的是，本发明提供的缺陷覆盖层中插入有隧穿层时，采用上述方法制作完毕第一子缺陷覆盖层后生长隧穿层，而后依然采用上述方法制作第二子缺陷覆盖层。
在本发明一实施例中，在本发明实施例提供的缺陷覆盖层可以为非故意掺杂AlaInbGa1-a-bN层时，其中，制作非故意掺杂AlaInbGa1-a-bN层的方法包括：
将反应室的生长压力调整为50Torr-200Torr，包括端点值，同时将所述反应室的生长温度调整为900℃-1100℃，包括端点值；
在反应室内持续通入NH3气体；
按脉冲模式在所述反应室内通入MO反应源，即在反应室内通入MO反应源且持续1s-20s(包括端点值)时间后，断开MO反应源且持续1s-10s(包括端点值)时间，而后按照上述的通入MO反应源-断开MO反应源的过程循环10-100次，且最终以通入MO反应源且持续1s-20s(包括端点值)时间结束；其中，MO反应源包括Al源、Ga源、In源中相应组合。
可以理解的，按照本发明实施例提供的上述MO反应源的脉冲模式通入反应室的方法，且控制反应室内生长环境为高温低压环境，脉冲式的通入三族源和五族源，进而可以增加三族原子在外延结构表面的迁移时间，使得原子可以充分的扩展而促进二维生长，进而快速的覆盖V型缺陷。
本发明提供了一种发光二极管及其制作方法，包括：衬底；位于所述衬底一侧上的N型半导体层；位于所述N型半导体层背离所述衬底一侧依次叠加的窄阱宽垒超晶格层、第一界面调制层、窄阱窄垒超晶格层及第二界面调制层，其中，所述窄阱宽垒超晶格层和所述窄阱窄垒超晶格层组合为复合浅量子阱；位于所述第二界面调制层背离所述衬底一侧的多量子阱发光层；位于所述多量子阱发光层背离所述衬底一侧的缺陷覆盖层；以及，位于所述缺陷覆盖层背离 所述衬底一侧的P型半导体层。
由上述内容可知，本发明提供的发光二极管包括有复合浅量子阱，进而能够使得发光二极管增加空穴注入多量子阱发光层的通道，提高大电流密度下空穴的注入效率。同时，在窄阱宽垒超晶格层和窄阱窄垒超晶格层之间形成有第一界面调制层，及在窄阱窄垒超晶格层和多量子阱发光层之间形成第二界面调制层，进而能够通过第一界面调制层减缓窄阱宽垒超晶格层和窄阱窄垒超晶格层的界面处的能带弯曲，及通过第二界面调制层减缓窄阱窄垒超晶格层和多量子阱发光层的界面处的能带弯曲，降低由此引入的异质势垒高度，进而降低发光二极管的工作电压且提高发光二极管的发光效率。此外，通过位于缺陷覆盖层来覆盖填平多量子阱发光层和复合浅量子阱上形成的V型缺陷，而有效的阻挡电流进入V型缺陷，从而有效减少V型缺陷所形成的漏电通道，使得空穴从非V型缺陷区域进入多量子阱发光层，增大空穴-电子复合几率，最终提高了发光二极管的可靠性和发光效率。
对所公开的实施例的上述说明，使本领域专业技术人员能够实现或使用本发明。对这些实施例的多种修改对本领域的专业技术人员来说将是显而易见的，本文中所定义的一般原理可以在不脱离本发明的精神或范围的情况下，在其它实施例中实现。因此，本发明将不会被限制于本文所示的这些实施例，而是要符合与本文所公开的原理和新颖特点相一致的最宽的范围。

Claims (10)

  1. 一种发光二极管，其特征在于，包括：
    衬底；
    位于所述衬底一侧上的N型半导体层；
    位于所述N型半导体层背离所述衬底一侧依次叠加的窄阱宽垒超晶格层、第一界面调制层、窄阱窄垒超晶格层及第二界面调制层，其中，所述窄阱宽垒超晶格层和所述窄阱窄垒超晶格层组合为复合浅量子阱；
    位于所述第二界面调制层背离所述衬底一侧的多量子阱发光层；
    位于所述多量子阱发光层背离所述衬底一侧的缺陷覆盖层；
    以及，位于所述缺陷覆盖层背离所述衬底一侧的P型半导体层。
  2. 根据权利要求1所述的发光二极管，其特征在于，所述缺陷覆盖层包括靠近所述衬底一侧的第一子缺陷覆盖层及远离所述衬底一侧的第二子缺陷覆盖层，其中，所述发光二极管还包括：
    位于所述第一子缺陷覆盖层与所述第二子缺陷覆盖层之间的隧穿层，其中，所述隧穿层的阻抗小于所述缺陷覆盖层的阻抗。
  3. 根据权利要求2所述的发光二极管，其特征在于，所述隧穿层为AljInkGa1-j-kN层，其中，0≤j＜0.5且0≤k＜0.5。
  4. 根据权利要求2所述的发光二极管，其特征在于，所述隧穿层的厚度范围为1nm-10nm，包括端点值。
  5. 根据权利要求1所述的发光二极管，其特征在于，所述缺陷覆盖层为非故意掺杂AlaInbGa1-a-bN层，其中，0≤a＜0.5且0≤b＜0.5。
  6. 根据权利要求1所述的发光二极管，其特征在于，所述缺陷覆盖层的厚度范围为10nm-50nm，包括端点值。
  7. 根据权利要求1所述的发光二极管，其特征在于，所述第一界面调制层和所述第二界面调制层均为AlxInyGa1-x-yN层，其中，0≤x＜0.5且0≤y＜0.5。
  8. 根据权利要求1所述的发光二极管，其特征在于，所述发光二极管还包括：
    位于所述衬底与所述N型半导体层之间依次叠加的缓冲层和非故意掺杂层；
    和/或，位于所述多量子阱发光层与所述缺陷覆盖层之间的电子阻挡层；
    和/或，位于所述P型半导体层背离所述衬底一侧的欧姆接触层。
  9. 一种发光二极管的制作方法，其特征在于，包括：
    提供衬底；
    在所述衬底一侧上形成N型半导体层；
    在所述N型半导体层背离所述衬底一侧依次叠加形成窄阱宽垒超晶格层、第一界面调制层、窄阱窄垒超晶格层及第二界面调制层，其中，所述窄阱宽垒超晶格层和所述窄阱窄垒超晶格层组合为复合浅量子阱；
    在所述第二界面调制层背离所述衬底一侧形成多量子阱发光层；
    在所述多量子阱发光层背离所述衬底一侧形成缺陷覆盖层；
    在所述缺陷覆盖层背离所述衬底一侧形成P型半导体层。
  10. 根据权利要求9所述的发光二极管的制作方法，其特征在于，所述缺陷覆盖层的制作方法包括：
    将反应室的生长压力调整为50Torr-200Torr，包括端点值，同时将所述反应室的生长温度调整为900℃-1100℃，包括端点值；
    按脉冲模式在所述反应室内通入反应源。
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CN110957401B (zh) * 2019-12-26 2021-02-26 厦门乾照光电股份有限公司 一种发光二极管及其制作方法
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103824909A (zh) * 2014-03-12 2014-05-28 合肥彩虹蓝光科技有限公司 一种提高GaN基LED发光亮度的外延方法
CN103972334A (zh) * 2014-05-14 2014-08-06 湘能华磊光电股份有限公司 Led外延层结构、生长方法及具有该结构的led芯片
US20150221826A1 (en) * 2014-02-04 2015-08-06 Jung Seung YANG Nitride semiconductor light emitting device
CN105742423A (zh) * 2015-11-30 2016-07-06 厦门市三安光电科技有限公司 发光二极管及其制作方法
CN108807613A (zh) * 2018-06-27 2018-11-13 聚灿光电科技股份有限公司 Led外延结构及其制备方法
CN110957401A (zh) * 2019-12-26 2020-04-03 厦门乾照光电股份有限公司 一种发光二极管及其制作方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105552186B (zh) * 2014-10-29 2019-03-08 南通同方半导体有限公司 一种具有抑制极化效应垒层蓝光led外延结构

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150221826A1 (en) * 2014-02-04 2015-08-06 Jung Seung YANG Nitride semiconductor light emitting device
CN103824909A (zh) * 2014-03-12 2014-05-28 合肥彩虹蓝光科技有限公司 一种提高GaN基LED发光亮度的外延方法
CN103972334A (zh) * 2014-05-14 2014-08-06 湘能华磊光电股份有限公司 Led外延层结构、生长方法及具有该结构的led芯片
CN105742423A (zh) * 2015-11-30 2016-07-06 厦门市三安光电科技有限公司 发光二极管及其制作方法
CN108807613A (zh) * 2018-06-27 2018-11-13 聚灿光电科技股份有限公司 Led外延结构及其制备方法
CN110957401A (zh) * 2019-12-26 2020-04-03 厦门乾照光电股份有限公司 一种发光二极管及其制作方法

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