WO2021125155A1 - 固体撮像素子 - Google Patents

固体撮像素子 Download PDF

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Publication number
WO2021125155A1
WO2021125155A1 PCT/JP2020/046701 JP2020046701W WO2021125155A1 WO 2021125155 A1 WO2021125155 A1 WO 2021125155A1 JP 2020046701 W JP2020046701 W JP 2020046701W WO 2021125155 A1 WO2021125155 A1 WO 2021125155A1
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Prior art keywords
transistor
light receiving
pixel cell
pixel
solid
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Ceased
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PCT/JP2020/046701
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English (en)
French (fr)
Japanese (ja)
Inventor
祐輔 坂田
田丸　雅規
三佳 森
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Panasonic Intellectual Property Management Co Ltd
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Panasonic Intellectual Property Management Co Ltd
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Priority to CN202080087479.0A priority Critical patent/CN114830338A/zh
Priority to JP2021565584A priority patent/JPWO2021125155A1/ja
Publication of WO2021125155A1 publication Critical patent/WO2021125155A1/ja
Priority to US17/840,139 priority patent/US20220310684A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10—Integrated devices
    • H10F39/12—Image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/802—Geometry or disposition of elements in pixels, e.g. address-lines or gate electrodes
    • H10F39/8023—Disposition of the elements in pixels, e.g. smaller elements in the centre of the imager compared to larger elements at the periphery
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/803—Pixels having integrated switching, control, storage or amplification elements
    • H10F39/8037—Pixels having integrated switching, control, storage or amplification elements the integrated elements comprising a transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/811—Interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/812—Arrangements for transferring the charges in the image sensor perpendicular to the imaging plane, e.g. buried regions used to transfer generated charges to circuitry under the photosensitive region

Definitions

  • the present disclosure relates to a solid-state image sensor including a plurality of pixel cells.
  • Patent Document 1 discloses a solid-state image sensor.
  • This solid-state image sensor is a detection means for detecting information on whether or not there is an incident photon between a light receiving element having a photoelectric conversion function, a reset means for repeatedly resetting the light receiving element, and a reset pulse for resetting the light receiving element. And have.
  • the solid-state image sensor further includes a count value holding means for counting the detection pulse of the detection means for a predetermined period, and a reading means for reading the count value of the count value holding means for each predetermined period.
  • a solid-state image sensor such as the solid-state image sensor described in Patent Document 1
  • the light receiving element is an avalanche photodiode (hereinafter, also referred to as "APD (Avalanche Photodiode)"
  • APD Avalanche Photodiode
  • An object of the present disclosure is to provide a solid-state image sensor suitable for high sensitivity.
  • the solid-state image sensor is formed on the semiconductor substrate and the semiconductor substrate in a two-dimensional array shape along each of the first direction and the second direction intersecting the first direction.
  • Each of the plurality of pixel cells includes a plurality of pixel cells, and each of the plurality of pixel cells receives a light receiving unit that receives incident light to generate a charge, a charge holding unit that holds the charge generated by the light receiving unit, and the first unit. It has a plurality of first transistors arranged in a direction and a pixel circuit including a second transistor that outputs a voltage corresponding to the charge held by the charge holding unit as a light receiving signal, and is included in the plurality of pixel cells.
  • the pixel circuits of the first pixel cell and the light receiving unit of the second pixel cell are the light receiving unit of the first pixel cell.
  • the second pixel which is adjacent to the second light receiving unit in the second direction and has the same function as the first transistor, each of the plurality of first transistors of the first pixel cell.
  • the gate electrode is shared with the first transistor of the cell.
  • FIG. 1 is a diagram for explaining the arrangement of a plurality of pixel cells included in the solid-state image sensor according to the embodiment.
  • FIG. 2 is a diagram showing two pixel cells included in the solid-state image sensor according to the embodiment.
  • FIG. 3 is a diagram showing a circuit configuration of a pixel circuit.
  • FIG. 4 is an enlarged view of the arrangement of a plurality of transistors included in the pixel circuit.
  • FIG. 5 is a cross-sectional view taken along the line VV of FIG.
  • FIG. 6 is a diagram showing two pixel cells included in the solid-state image sensor according to the first modification.
  • FIG. 7 is a diagram showing two pixel cells included in the solid-state image sensor according to the second modification.
  • FIG. 1 is a diagram for explaining the arrangement of a plurality of pixel cells included in the solid-state image sensor according to the embodiment.
  • FIG. 2 is a diagram showing two pixel cells included in the solid-state image sensor according to the embodiment.
  • FIG. 3
  • FIG. 8 is a diagram showing a circuit configuration of the pixel circuit according to the second modification.
  • FIG. 9 is a diagram showing two pixel cells included in the solid-state image sensor according to the third modification.
  • FIG. 10 is a diagram showing a circuit configuration of a pixel circuit according to the third modification.
  • each figure is a schematic diagram and is not necessarily exactly illustrated.
  • the corners may be deformed into a circular shape by ion implantation or heat treatment.
  • the rectangular regions may be expanded to overlap and the impurity concentrations are added to form a region having an impurity concentration not described in the following embodiment.
  • the region where the impurity concentration is low is easily reduced due to the influence of the surroundings, and the concentration may be increased or the conductive type may be partially inverted.
  • substantially the same configuration is designated by the same reference numerals, and duplicate description may be omitted or simplified.
  • the Z-axis direction in the coordinate axes is, for example, the vertical direction, and the Z-axis + side is expressed as the upper side (upper side) or the front side, and the Z-axis-side is expressed as the lower side (lower side) or the back side.
  • the Z-axis direction is a direction perpendicular to the upper surface or the lower surface of the semiconductor substrate, and is a thickness direction of the semiconductor substrate.
  • the Z-axis direction may be expressed as the depth direction.
  • the Z-axis + side is the shallow side in the depth direction
  • the Z-axis-side is the deep side in the depth direction.
  • the X-axis direction and the Y-axis direction are directions orthogonal to each other on a plane (horizontal plane) perpendicular to the Z-axis direction.
  • the X-axis direction is expressed as the horizontal direction, the row direction, or the first direction
  • the Y-axis direction is expressed as the vertical direction, the column direction, or the second direction.
  • plane view means viewing from the Z-axis direction.
  • FIG. 1 is a diagram for explaining the arrangement of a plurality of pixel cells included in the solid-state image sensor according to the embodiment.
  • the solid-state image sensor 1 is used, for example, in a distance measuring system that acquires a distance image of a target space by using a TOF (Time Of Flight) method.
  • the distance measuring system includes, for example, a wave transmitting module that outputs pulsed light, a receiving module that receives pulsed light (reflected light) that is output from the transmitting module and reflected by an object, and a receiving module that receives light. It is provided with a processing unit that obtains the distance to the object based on the reflected light. The processing unit can obtain the distance to the object based on the timing when the transmitting module outputs the pulsed light and the timing when the receiving module receives the reflected light.
  • the pulsed light output from the wave transmitting module is monochromatic light, the pulse width is relatively short, and the peak intensity is relatively high.
  • the wavelength of the pulsed light is in the near-infrared band, which has low human visual sensitivity and is not easily affected by ambient light from sunlight. Is preferable.
  • Such a ranging system can be used, for example, in an object recognition system mounted on an automobile to detect an obstacle, a surveillance camera for detecting an object (person), a security camera, or the like.
  • the solid-state image sensor 1 is used, for example, in the wave receiving module of the above-mentioned ranging system.
  • the solid-state image sensor 1 includes a semiconductor substrate 100 and a plurality of pixel cells 10.
  • the plurality of pixel cells 10 are formed on the semiconductor substrate 100.
  • the plurality of pixel cells 10 are formed in a two-dimensional array on the upper surface side of the semiconductor substrate 100.
  • a group of pixel cells composed of a plurality of pixel cells 10 arranged along the X-axis direction (the left-right direction in FIG. 1; hereinafter, also referred to as the first direction) intersects the X-axis direction.
  • a plurality of them are arranged side by side in the Y-axis direction (vertical direction in FIG. 1; hereinafter, also referred to as a second direction).
  • the wiring 60 connecting the light receiving unit 2 and the pixel circuit 30, the wiring 61 connecting the transistors included in the pixel circuit 30, and the like are omitted.
  • FIG. 2 is a diagram showing two pixel cells 10 out of a plurality of pixel cells 10.
  • the two pixel cells 10 are described as a first pixel cell 10a and a second pixel cell 10b.
  • each of the first pixel cell 10a and the second pixel cell 10b includes a light receiving unit 2 and a pixel circuit 30.
  • the light receiving unit 2 is formed on the semiconductor substrate 100.
  • the light receiving unit 2 is a photoelectric conversion unit that receives incident light and generates an electric charge.
  • the photoelectric conversion unit is, for example, an avalanche photodiode, but it may be a general photodiode.
  • the photoelectric conversion unit is an avalanche photodiode
  • the light receiving unit 2 has a multiplication region in which the electric charge generated by receiving the incident light is multiplied by the avalanche multiplier.
  • the pixel circuit 30 is a circuit for outputting a light receiving signal corresponding to the electric charge generated by the light receiving unit 2.
  • the pixel circuit 30 has a plurality of transistors. Specifically, the plurality of transistors are a transfer transistor 31, a first reset transistor 32, an amplification transistor 33, a selection transistor 35, a second reset transistor 34, and a counting transistor 36. Among these transistors, each of the transfer transistor 31, the first reset transistor 32, the selection transistor 35, the second reset transistor 34, and the counting transistor 36 is also described as the first transistor, and is an amplification transistor. 33 is also described as a second transistor.
  • a plurality of transistors are formed on the semiconductor substrate 100.
  • the gate electrodes of the plurality of transistors are arranged in the first direction (left-right direction in FIG. 2).
  • the arrangement of the plurality of transistors (arrangement order) of the first pixel cell 10a and the arrangement of the plurality of transistors of the second pixel cell 10b are the same from left to right. That is, the first pixel cell 10a and the second pixel cell 10b have a vertically symmetrical structure in a plan view.
  • the light receiving unit 2 of the first pixel cell 10a is adjacent to the light receiving unit 2 of the pixel cell 10 on the opposite side of the second pixel cell 10b, and is not adjacent to the pixel circuit 30 of this pixel cell (see FIG. 1). ..
  • the junction boundary between the pixel circuit 30 and the light receiving unit 2 is reduced as compared with the case where the light receiving unit 2 and the pixel circuit 30 are arranged alternately. Then, since the area of the separated portion between the pixel circuit 30 and the light receiving portion 2 is also reduced, the area ratio of the light receiving portion 2 can be increased without changing the pixel size. That is, the solid-state image sensor 1 can easily be made highly sensitive.
  • the pixel circuit 30 has a charge holding unit 5.
  • the charge holding unit 5 is connected to the light receiving unit 2 by the wiring 60 via the transfer transistor 31.
  • the charge holding unit 5 holds (accumulates) the charge generated by the light receiving unit 2.
  • the charge holding unit 5 is also connected to the gate electrode 330 of the amplification transistor 33 via the wiring 61.
  • the plurality of transistors include a plurality of first transistors and a second transistor.
  • the plurality of first transistors are a transfer transistor 31, a first reset transistor 32, a selection transistor 35, a second reset transistor 34, and a counting transistor 36.
  • the second transistor is an amplification transistor 33.
  • Each of the plurality of first transistors included in the first pixel cell 10a shares a gate electrode with the first transistor included in the second pixel cell 10b, which has the same function as the first transistor.
  • the gate electrodes here are gate electrodes 310, 320, 340, 350, 360, and these gate electrodes are line-shaped (straight) along the second direction and are the first pixel cells. It straddles the boundary 11 of the 10a and the second pixel cell 10b.
  • the solid-state image sensor 1 can suppress the light emitted into the effective pixels from being reflected by the wiring. That is, the solid-state image sensor 1 can easily be made highly sensitive.
  • the gate electrode is used as a mask when forming a diffusion region (diffusion region 50 to 58 in FIG. 2) of the transistor, and the length of the gate electrode in the second direction varies in the manufacturing of the transistor. The length is set so that it can be suppressed.
  • the gate electrode 330 of the amplification transistor 33 is an individual gate electrode to which an independent voltage is applied without being shared by the first pixel cell 10a and the second pixel cell 10b.
  • the protruding dimension A2 of the gate electrode 330 is different. It is shorter than the protruding dimension A1 of the gate electrode of the transistor of.
  • the length of the protruding dimension A1 is set to a length that can sufficiently suppress the manufacturing variation of the transistor, and the length of the protruding dimension A2 cancels the characteristic variation of the amplification transistor 33 by the CDS (Correlated Double Sampling) circuit in the subsequent stage. It is set to a length that allows it. Such lengths are determined empirically or experimentally. As a result, the deterioration of the image quality can be kept within an allowable range.
  • the charge holding portion is separated by a certain distance between the gate electrodes 330 of the amplification transistors 33 of the first pixel cell 10a and the second pixel cell 10b.
  • the arrangement of the diffusion regions 50 to 58 can be brought closer to the boundary 11 while suppressing the parasitic capacitance between the five. Therefore, the width of the pixel circuit 30 can be reduced in the second direction, and the area ratio of the light receiving unit 2 can be increased. That is, the solid-state image sensor 1 can easily be made highly sensitive.
  • FIG. 3 is a diagram showing a circuit configuration of the pixel circuit 30.
  • FIG. 4 is an enlarged view of the arrangement of a plurality of transistors included in the pixel circuit 30.
  • FIG. 5 is a cross-sectional view taken along the line VV of FIG.
  • the pixel circuit 30 includes a transfer transistor 31, a first reset transistor 32, an amplification transistor 33, a selection transistor 35, a second reset transistor 34, and a counting transistor. 36, a charge holding unit 5, and a memory unit 6 are provided. Further, in FIG. 3, in addition to the pixel circuit 30, the light receiving unit 2 is also shown.
  • the light receiving unit 2 is realized by a photodiode formed in the upper surface region in the semiconductor substrate 100.
  • the photodiode is an avalanche photodiode (hereinafter, also referred to as APD) here.
  • APD avalanche photodiode
  • the light receiving unit 2 includes, for example, an n-type diffusion region formed in the p-type semiconductor substrate 100.
  • the light receiving unit 2 realized by the APD has a first mode and a second mode as operation modes.
  • the light receiving unit 2 receives light in a state where a reverse bias voltage smaller than the breakdown voltage is applied, the light receiving unit 2 collects an electric charge of an amount of charge substantially proportional to the number of photons that cause photoelectric conversion to the cathode (first mode). ..
  • the light receiving unit 2 collects a saturated charge amount of charge on the cathode due to photoelectric conversion by one photon (second). mode).
  • the light receiving unit 2 can change the operation mode by changing the potential of the bias electrode 101 connected to the anode.
  • the charge holding unit 5 holds the charge generated by the light receiving unit 2.
  • the diffusion region 50 is a so-called floating diffusion (FD) portion.
  • the transfer transistor 31 has diffusion regions 50 and 52 formed on the semiconductor substrate 100 and a gate electrode 310.
  • the diffusion region 52 of the transfer transistor 31 is connected to the cathode of the light receiving unit 2 via the wiring 60.
  • the wiring 60 is, for example, a metal wiring.
  • the diffusion region 50 is shared with the first reset transistor 32 and also functions as a charge holding unit 5.
  • the first reset transistor 32 has diffusion regions 50 and 53 formed on the semiconductor substrate 100 and a gate electrode 320.
  • the first reset drain electrode 102 is connected to the diffusion region 53 of the first reset transistor 32.
  • the diffusion region 50 is shared with the transfer transistor 31 and also functions as a charge holding unit 5.
  • the first reset transistor 32 is turned on by applying a voltage to the gate electrode 320, so that the electric charge accumulated in the diffusion region 50 is discharged to the first reset drain electrode 102. That is, the first reset transistor 32 resets the electric charge accumulated in the diffusion region 50.
  • the amplification transistor 33 has diffusion regions 54 and 58 formed on the semiconductor substrate 100 and a gate electrode 330.
  • the amplification electrode 103 is connected to the diffusion region 58 of the amplification transistor 33.
  • the diffusion region 54 is shared with the selection transistor 35.
  • the gate electrode 330 of the amplification transistor 33 is connected to the diffusion region 50 and the diffusion region 56 via the wiring 61.
  • the wiring 61 is, for example, a metal wiring.
  • the amplification transistor 33 outputs a voltage corresponding to the amount of electric charge stored in the diffusion region 50.
  • the output voltage from the amplification transistor 33 is a light receiving signal (light receiving signal corresponding to the electric charge generated by the light receiving unit 2) output from the pixel cell 10.
  • the selection transistor 35 has diffusion regions 54 and 55 formed on the semiconductor substrate 100 and a gate electrode 350.
  • the diffusion region 55 of the selection transistor 35 is connected to the signal line 110.
  • the diffusion region 54 is shared with the amplification transistor 33.
  • the selection transistor 35 outputs the voltage (light receiving signal) from the amplification transistor 33 to the signal line 110 only when the voltage is applied to the gate electrode 350 and is turned on.
  • the second reset transistor 34 has diffusion regions 51 and 52 formed on the semiconductor substrate 100 and a gate electrode 340.
  • the second reset drain electrode 104 is connected to the diffusion region 51 of the second reset transistor 34.
  • the diffusion region 52 of the second reset transistor 34 is connected to the cathode of the light receiving unit 2 via the wiring 60.
  • the second reset transistor 34 is turned on by applying a voltage to the gate electrode 340, so that the electric charge accumulated in the cathode of the light receiving unit 2 is discharged to the second reset drain electrode 104. That is, the second reset transistor 34 resets the electric charge accumulated in the cathode of the light receiving unit 2.
  • the memory unit 6 is realized as, for example, a capacitor that stores electric charges.
  • the memory unit 6 has, for example, a laminated structure including a pair of electrodes and an insulating layer sandwiched between them.
  • the memory unit 6 may have a laminated structure of electrodes, a semiconductor layer, and an insulating layer sandwiched between the electrodes.
  • the memory unit 6 is arranged on the semiconductor substrate 100, for example, via an insulating layer. Further, the memory unit 6 may be configured by a laminated structure of two wiring layers and an insulating layer sandwiched between them.
  • the counting transistor 36 has diffusion regions 56 and 57 formed on the semiconductor substrate 100 and a gate electrode 360.
  • the diffusion region 56 of the counting transistor 36 is connected to the diffusion region 50 and the gate electrode 330 via the wiring 61.
  • the diffusion region 57 of the counting transistor 36 is connected to the memory unit 6.
  • the counting transistor 36 prohibits the transfer of electric charge between the diffusion region 50 and the memory unit 6 when a voltage is not applied to the gate electrode 360 and is off. When a voltage is applied to the gate electrode 360 and the counting transistor 36 is turned on, the electric charge is transferred between the diffusion region 50 and the memory unit 6.
  • the circuit configuration of the pixel circuit 30 has been described above.
  • the first reset drain electrode 102 and the second reset drain electrode 104 may be shared. Further, the amplification electrode 103 may be shared with at least one of the second reset drain electrode 104 and the first reset drain electrode 102.
  • the first reset drain electrode 102 and the second reset drain electrode 104 are shared (connected to each other), and a common power source is connected.
  • the solid-state image sensor 1 includes a control unit (control circuit) that controls the operation of the pixel cell 10.
  • the control unit controls the pixel cell 10 by controlling the voltage applied to the bias electrode 101, the voltage applied to each of the gate electrodes of the plurality of first transistors included in the pixel circuit 30, and the like.
  • the control unit of the solid-state image sensor 1 has a first light receiving mode and a second light receiving mode as operation modes.
  • the control unit operates the light receiving unit 2 of the pixel cell 10 in the first mode.
  • the control unit adjusts the voltage applied to the bias electrode 101 so that the light receiving unit 2 operates in the first mode.
  • the control unit operates the light receiving unit 2 of the pixel cell 10 in the second mode. Specifically, the control unit adjusts the voltage applied to the bias electrode 101 so that the light receiving unit 2 operates in the second mode, and the potential difference between the anode and the cathode of the light receiving unit 2 is larger than that in the first mode. Adjust in the direction of The second light receiving mode is a mode more suitable for detecting weak light than the first light receiving mode.
  • the solid-state image sensor 1 operates as follows. First, the control unit of the solid-state image sensor 1 turns on the first reset transistor 32, the second reset transistor 34, and the counting transistor 36, and turns on the cathode of the light receiving unit 2 and the charge holding unit 5 (diffusion region 50). ) And the memory unit 6 are initialized (the accumulated charge is discharged). At this time, the transfer transistor 31 is turned off.
  • the control unit turns off the first reset transistor 32, the second reset transistor 34, and the count transistor 36.
  • This state is the so-called exposure state of the pixel cell 10.
  • the light receiving unit 2 collects an electric charge having an amount of electric charge substantially proportional to the number of photons that cause photoelectric conversion to the cathode.
  • the off-level potential of the second reset transistor 34 is lower than the off-level potential of the transfer transistor 31. Therefore, when the amount of electric charge collected at the cathode of the light receiving unit 2 reaches the saturation level of the cathode, the electric charge exceeding the saturation level exceeds the potential barrier of the second reset transistor 34 and the second reset drain electrode 104. Overflow to.
  • control unit initializes the charge holding unit 5 by turning on the first reset transistor 32. Then, the control unit turns on the transfer transistor 31 to connect the cathode of the light receiving unit 2 and the charge holding unit 5. As a result, the electric charge collected on the cathode of the light receiving unit 2 is transferred to the electric charge holding unit 5 (diffusion region 50) and accumulated.
  • the charge accumulated in the charge holding unit 5 is converted into a light receiving signal according to the amount of electric charge of the accumulated charge by the amplification transistor 33 in which the gate electrode 330 is connected to the charge holding unit 5.
  • the control unit turns on the selection transistor 35 of the desired pixel cell 10 among the plurality of pixel cells 10 to output a light receiving signal from the desired pixel cell 10 to the signal line 110.
  • the solid-state image sensor 1 operates as follows.
  • the control unit divides a predetermined measurement period so as to include a plurality of exposure periods. Then, the control unit counts the number of photons detected by the light receiving unit 2 within the measurement period based on whether or not photoelectric conversion has occurred in the exposure process corresponding to each exposure period.
  • the control unit operates the pixel cell 10 as follows.
  • the control unit turns on the first reset transistor 32, the second reset transistor 34, and the counting transistor 36, and turns on the cathode of the light receiving unit 2 and the charge holding unit 5 (diffuse).
  • the area 50) and the memory unit 6 are initialized (reset). At this time, the transfer transistor 31 is turned off.
  • the control unit turns off the first reset transistor 32, the second reset transistor 34, and the counting transistor 36 at the start of the exposure period of each exposure step, and turns on the transfer transistor 31.
  • This state is the exposure state of the pixel cell 10.
  • the light receiving unit 2 collects electric charges on the cathode at a level (saturated charge amount) at which the charge holding unit 5 is saturated due to photoelectric conversion by one photon.
  • the off-level potential of the second reset transistor 34 is lower than the off-level potential of the transfer transistor 31. Therefore, the electric charge collected beyond the saturation level of the cathode of the light receiving unit 2 exceeds the potential barrier of the second reset transistor 34 and overflows to the second reset drain electrode 104.
  • the amount of electric charge stored in the cathode of the light receiving unit 2 in the second mode (the amount of electric charge stored in the cathode when one photon undergoes photoelectric conversion) is almost the same each time (corresponding to the saturation level of the cathode). The amount of electric charge to be used).
  • control unit turns off the transfer transistor 31.
  • the charge holding unit 5 holds a part of the charges collected on the cathode of the light receiving unit 2 and distributed to the charge holding unit 5.
  • control unit turns on the counting transistor 36 and redistributes the charge accumulated in the charge holding unit 5 to the charge holding unit 5 and the memory unit 6. That is, the control unit transfers (a part of) the electric charge accumulated in the electric charge holding unit 5 to the memory unit 6. As a result, a part of the electric charge generated by the light receiving unit 2 by the photoelectric conversion moves to the memory unit 6, and the amount of electric charge of the memory unit 6 increases.
  • the light receiving unit 2 does not receive light within the exposure period, the light receiving unit 2 does not undergo photoelectric conversion and does not collect electric charges on the cathode. Therefore, even if the control unit turns on the transfer transistor 31, the charge does not move from the cathode of the light receiving unit 2 to the charge holding unit 5, and even if the counting transistor 36 is turned on after that, the memory unit 6 The amount of charge does not increase.
  • the control unit repeats the above operation as many times as the number of exposure steps. As a result, of the plurality of exposure steps included in one measurement period, an amount of electric charge corresponding to the number of exposure steps in which the light receiving unit 2 receives light is accumulated in the memory unit 6.
  • the light receiving unit 2 receives light in the first exposure step
  • the electric charge is already accumulated in the memory unit 6 in the second and subsequent exposure steps. Therefore, the amount of charge of the memory unit 6 that increases in the second and subsequent exposure steps is different from that in the first exposure step. Further, in the second and subsequent exposure steps, it is not always necessary to turn off the first reset transistor 32 at the start of the exposure step. However, since these points are not the purpose of the present disclosure, detailed description thereof will be omitted.
  • the control unit turns on the counting transistor 36 to connect the memory unit 6 and the charge holding unit 5, and the charge accumulated in the memory unit 6 Is distributed to the memory unit 6 and the charge holding unit 5.
  • the charge distributed from the memory unit 6 to the charge holding unit 5 corresponds to the amount of charge by the amplification transistor 33 in which the gate electrode 330 is connected to the charge holding unit 5 (that is, the light receiving unit 2 receives light. It is converted into a received signal (according to the number of exposure steps).
  • the control unit turns on the selection transistor 35 of the desired pixel cell 10 among the plurality of pixel cells 10 to output a light receiving signal from the desired pixel cell 10 to the signal line 110.
  • the received signal output to the signal line 110 is read out by the CDS circuit.
  • the CDS circuit has a potential difference between two arbitrary different timings on the corresponding signal line 110, that is, a potential during signal output operation (potential when the charge holding unit 5 contains a signal charge) and a potential during reset operation (potential during reset operation).
  • a signal corresponding to the difference from the potential after discharging the electric charge of the electric charge holding unit 5 by the first reset transistor 32 is output from the CDS output node.
  • the plurality of pixel cells 10 are formed in a two-dimensional array on the semiconductor substrate 100.
  • the semiconductor substrate 100 is, for example, a p-type silicon substrate.
  • An n-type well region 8 is formed long on the upper surface of the semiconductor substrate 100 in the first direction (left-right direction in FIG. 1).
  • a p-type well region 9 is formed along the longitudinal direction (first direction) of the n-type well region 8.
  • the pixel circuit 30 is formed in the p-type well region 9.
  • the light receiving portion 2 is formed in the p-type region outside the n-type well region 8 in the semiconductor substrate 100.
  • a plurality of (three in FIG. 1) pixel cells 10 (hereinafter, also referred to as a first pixel cell group) are arranged side by side along one side in the longitudinal direction of one p-type well region 9. ing. Further, a plurality of (three in FIG. 1) pixel cells 10 (hereinafter, also referred to as a second pixel cell group) are arranged side by side along the other side of the p-type well region 9 in the longitudinal direction. Has been done. In the p-type well region 9, a pixel circuit 30 of each pixel cell 10 of the first pixel cell group and a pixel circuit 30 of each pixel cell 10 of the second pixel cell group are formed.
  • the pixel circuits 30 of the six pixel cells 10 of the first pixel cell group and the second pixel cell group are formed in one p-type well region 9.
  • the first pixel cell group may include 2 or less pixel cells 10 or 4 or more pixel cells 10.
  • the second pixel cell group may include 2 or less pixel cells 10 or 4 or more pixel cells 10.
  • the number of pixel cells 10 included in the second pixel cell group may be the same as or different from the number of pixel cells 10 included in the first pixel cell group.
  • the plurality of pixel cells 10 included in the first pixel cell group have the same shape and size
  • the plurality of pixel cells 10 included in the second pixel cell group are It has the same shape and size.
  • the pixel cell 10 included in the first pixel cell group and the pixel cell 10 included in the second pixel cell group also have the same shape and size.
  • the shapes of the wirings 60 and 61 connected to the plurality of pixel cells 10 can be made substantially the same. That is, it is possible to make the lengths of the wirings 60 and 61 uniform, and it is possible to make the parasitic resistance and the parasitic capacitance of the wirings 60 and 61 uniform. In other words, it is possible to reduce the variation in characteristics among the plurality of pixel cells 10.
  • the two pixel cells 10 arranged adjacent to each other in the second direction (the lateral direction of the p-type well region 9 and the vertical direction in FIG. 1) among the plurality of pixel cells 10 are light receiving units.
  • the two are adjacent to each other, or the pixel circuits 30 are adjacent to each other.
  • the layout of the components in the pixel circuit 30 will be described. As shown in FIGS. 2, 4, and 5, the components of the pixel circuit 30 are arranged in a long region in the first direction. In this region, the second reset transistor 34, the transfer transistor 31, the first reset transistor 32, the counting transistor 36, the amplification transistor 33, and the selection transistor 35 are arranged in this order from the left side (X-axis-side). They are lined up along the first direction. More specifically, the diffusion regions 50 to 59 are arranged along the first direction, and the plurality of gate electrodes 310 to 360 are arranged along the first direction.
  • Each of the plurality of diffusion regions 50 to 58 is an n-type diffusion region formed in the p-type well region 9. As shown in FIGS. 2, 4, and 5, the diffusion regions 51, 52, 50, 53, 56, 57, 58, 54, and 55 are arranged in this order from the left side in the figure along the first direction. Lined up.
  • the diffusion region 59 is a p-type diffusion region formed in the p-type well region 9.
  • the diffusion region 59 is connected to a power supply (generally a ground power supply) for fixing the voltage of the p-type well region 9 in the pixel cell 10 via the well wiring 62.
  • the diffusion region 59 is, in other words, a well contact.
  • the well wiring 62 is, for example, a metal wiring.
  • the n-type well region 8 is connected to a power source (generally about 1 to 5 V) that has a reverse bias with the p-type well region 9.
  • Each of the plurality of gate electrodes 310 to 360 has a long shape in the second direction.
  • Each of the plurality of gate electrodes 310 to 360 is linear in a plan view, but may have other shapes such as an L shape.
  • the gate electrodes 340, 310, 320, 360, 330, 350 are arranged in this order from the left side in the drawing along the first direction.
  • Each of the plurality of gate electrodes 310 to 360 is formed on the semiconductor substrate 100 via a gate insulating film (not shown) made of silicon oxide or the like. Each of the plurality of gate electrodes 310 to 360 is formed on the semiconductor substrate 100 so as to bridge the ends of two adjacent diffusion regions in the first direction. Each of the plurality of transistors included in the pixel circuit 30 is composed of two adjacent diffusion regions, a gate electrode that bridges the two adjacent diffusion regions, and a gate insulating film.
  • the diffusion regions that should not be electrically connected are separated by, for example, an insulator such as STI (Shallow Trench Isolation) 70. Diffusion regions that should not be electrically connected may be separated by different conductive diffusion regions. Further, for example, a dummy member formed of the same material as the gate electrode may be arranged at a position where the distance between the gate electrodes is large.
  • STI Shallow Trench Isolation
  • the pixel circuits 30 are the first light receiving unit 2 which is the light receiving unit 2 of the first pixel cell 10a and the second light receiving unit 2 of the second pixel cell 10b. Adjacent to the light receiving unit in the second direction.
  • the number of boundaries between the pixel circuit 30 and the light receiving unit 2 is reduced as compared with the configuration in which the pixel circuit 30 and the light receiving unit 2 are alternately arranged in the second direction (hereinafter, also referred to as a comparative example).
  • a comparative example the boundary between the pixel circuit 30 and the light receiving unit 2 is 4 places per 2 lines, but in the solid-state image sensor 1, it is 2 places per 2 lines, and 1 boundary between the light receiving parts 2 is added. Will be done.
  • the number of boundaries that need to be provided with a separation portion can be reduced by one as compared with the comparative example. It is less necessary to provide a separation portion at the boundary between the pixel circuits 30.
  • the area ratio of the light receiving unit 2 can be increased by reducing the area allocated as the separation unit. That is, the solid-state image sensor 1 can easily be made highly sensitive.
  • the arrangement of the plurality of transistors of the first pixel cell 10a in the first direction is the same as the arrangement of the plurality of transistors of the second pixel cell 10b in the first direction.
  • Each of the plurality of first transistors (five transistors other than the amplification transistor 33) included in the one pixel cell 10a has the same function as the first transistor, and the first transistor and the gate electrode of the second pixel cell 10b have the same function.
  • the gate electrode extends to the boundary 11 of the first pixel cell 10a and the second pixel cell 10b, and is formed across the boundary 11. This gate electrode is a gate electrode to which a voltage common to the first pixel cell 10a and the second pixel cell 10b is applied.
  • the pixels in two rows can be driven at the same time by arranging a total of five gate electrode wirings per two rows. Therefore, it is possible to expose and read two lines at the same time while holding the light receiving signals for the upper and lower two pixels for each pixel, and the frame rate is increased. Further, by reducing the number of gate electrode wirings, the degree of freedom in layout is improved, and by arranging the gate electrode wirings at a position close to the boundary 11, the incident light having a large incident angle is reflected by the gate electrode wirings. Can be suppressed. That is, the common use of the gate electrodes also leads to an increase in optical sensitivity.
  • the gate electrodes of the first transistor (five transistors other than the amplification transistor 33) become longer along the second direction, the protruding dimension of the gate electrode in the direction toward the boundary 11 side is automatically manufactured as a transistor. It is sufficiently larger than the protrusion dimension A1 for sufficiently suppressing the variation. That is, by standardizing the gate electrodes, the Vt variation of the first transistor is suppressed.
  • the gate electrode of the amplification transistor 33 is not shared by the first pixel cell 10a and the second pixel cell 10b. That is, the second transistor (that is, the amplification transistor) included in the first pixel cell 10a does not share the gate electrode with the second transistor included in the second pixel cell 10b.
  • a voltage is independently applied to the gate electrode of the amplification transistor 33 of the first pixel cell 10a and the gate electrode of the amplification transistor 33 of the second pixel cell 10b.
  • the protruding dimension A2 of the gate electrode 330 is shorter than the protruding dimension A1 of the gate electrode of another transistor.
  • the length of the protruding dimension A1 is set to a length that can sufficiently suppress the manufacturing variation of the transistor, and the length of the protruding dimension A2 is a length that can cancel the characteristic variation of the amplification transistor 33 in the subsequent CDS circuit. Is set to. Such lengths are determined empirically or experimentally. As a result, the deterioration of the image quality can be kept within an allowable range.
  • the gate electrodes 330 of the first pixel cell 10a and the second pixel cell 10b by separating the gate electrodes 330 of the first pixel cell 10a and the second pixel cell 10b by a certain degree, a parasitic capacitance is generated between the charge holding portions 5 of the first pixel cell 10a and the second pixel cell 10b.
  • the diffusion region can be arranged close to the boundary 11 while suppressing the charge. That is, the width of the region in which the pixel circuit 30 is mounted can be shortened in the first direction. Therefore, in the solid-state image sensor 1, it is easy to increase the area ratio of the light receiving unit 2 to increase the sensitivity.
  • the protruding dimension A1 required to suppress the Vt variation of the first transistor is 0.1 ⁇ m
  • the dimension A3 between the gate electrodes 330 (not shown) required to suppress the parasitic capacitance between the charge holding portions 5 is.
  • the amount of charge when light is detected is about the level (saturated charge amount) at which the light receiving unit 2 and the charge holding unit 5 are saturated. This is because when an electron-hole pair that triggers light detection is generated in the light receiving unit 2, the first generated electron-hole pair creates a new electron-hole pair, and the generated electron-hole pair is further increased.
  • positive feedback that produces electron-hole pairs is generated and a certain amount of charge is accumulated in the light receiving unit 2 and the charge holding unit 5, the potential of the cathode of the light receiving unit 2 drops to the negative side, so that the electron is positive.
  • the amount of decrease in the potential on the cathode side of the light receiving unit 2 is proportional to the amount of generated charge, and is inversely proportional to the total parasitic capacitance of the light receiving unit 2 and the charge holding unit 5. That is, even if the parasitic capacitance of the charge holding unit 5 becomes large, the amount of charge finally accumulated in the charge holding unit 5 increases, and the generation of electron-hole pairs stops at the same voltage value.
  • the wiring length of the wiring 61 connected to the charge holding unit 5 it is not always necessary to design the wiring length of the wiring 61 connected to the charge holding unit 5 to be short in order to reduce the parasitic capacitance. Further, when the parasitic capacitance of the charge holding unit 5 is large, the amount of charge that can be transferred to the memory unit 6 increases when the counting transistor 36 is turned on. As a result, the voltage fluctuation of the memory unit 6 per count becomes large, so that the amount of voltage change per count can be adjusted to be higher than the noise level.
  • the wiring 61 connected to the charge holding unit 5 is also considered to be a part of the charge holding unit 5. That is, it is considered that the charge holding unit 5 includes the wiring 61.
  • the parasitic capacitance may be increased between the wiring 61 and the power supply line to which a constant voltage is applied.
  • the wiring for applying a voltage to the p-type well region 9 or the n-type well region 8 (for example, the well wiring 62 connected to the diffusion region 59) is brought close to the wiring 61 and runs in parallel to charge the electric charge.
  • the parasitic capacitance of the holding portion 5 can be increased.
  • the well wiring 62 and the wiring 61 run in parallel along the first direction, for example, but may run in parallel in other directions.
  • the well wiring 62 and the wiring 61 belong to the same wiring layer and may be arranged at intervals in the second direction, or belong to different wiring layers and belong to the first direction and the second direction. They may be arranged at intervals in the third direction (that is, the Z-axis direction in the drawing) that intersects with each other. An interlayer insulating film is provided between the different wiring layers. Further, the well wiring 62 may be multi-layered, whereby the parasitic capacitance of the charge holding portion 5 can be further increased.
  • the well wiring 62 is a wiring for applying a voltage to the p-type well region 9, but apart from this, a well wiring (not shown) for applying a voltage to the n-type well region 8 is also provided. Exists.
  • the parasitic capacitance of the charge holding portion 5 can also be increased by bringing the well wiring and the wiring 61 close to each other and running them in parallel.
  • FIG. 6 is a diagram showing two pixel cells included in the solid-state image sensor according to the first modification.
  • the solid-state image sensor 1a includes a pixel circuit 30a, and the arrangement of a plurality of transistors in the pixel circuit 30a is different from that of the solid-state image sensor 1.
  • the second reset transistor 34, the transfer transistor 31, the first reset transistor 32, the amplification transistor 33, the selection transistor 35, and the counting transistor 36 are on the left side (X-axis-side). ) In this order, they are lined up along the first direction.
  • the diffusion region 58 of the amplification transistor 33 and the diffusion region 53 of the first reset transistor 32 are shared.
  • the common diffusion region is connected, for example, to the first reset drain electrode 102 (shown in FIG. 3). If the diffusion region 58 of the amplification transistor 33 and the diffusion region 53 of the first reset transistor 32 are shared in this way, it is necessary to arrange a plurality of transistors in the region where the pixel circuit 30a is mounted.
  • the dimension in the first direction is shortened. That is, the size of the pixel cell 10 can be miniaturized.
  • the pixel circuit 30 can be operated by adjusting the Vt of the amplification transistor 33 so that the amplification transistor 33 is turned on by the voltage.
  • the well wiring 62 connected to the diffusion region 59 and the wiring 61 connected to the charge holding portion 5 are mutually connected. They are running side by side in close proximity. According to such an arrangement of wiring, it is possible to increase the amount of charge generated when light is detected in the second light receiving mode by increasing the parasitic capacitance of the charge holding unit 5.
  • the well wiring 62 is multi-layered, or the well wiring 62 is formed in a wiring layer located above the wiring 61 included in the charge holding portion 5, and the well wiring 62 is arranged so as to cover the wiring 61. By doing so, it is possible to further expand the parasitic capacitance. Further, when the well wiring 62 is arranged so as to cover the wiring 61, the well wiring 62 can also be used as a light-shielding member that blocks the light emitted toward the pixel circuit 30a.
  • the well wiring 62 is a wiring for applying a voltage to the p-type well region 9, but separately, a wiring (not shown) for applying a voltage to the n-type well region 8 is arranged. You may.
  • the parasitic capacitance of the charge holding portion 5 can also be increased by bringing the well wiring and the wiring 61 close to each other and running them in parallel.
  • FIG. 7 is a diagram showing two pixel cells included in the solid-state image sensor according to the second modification.
  • FIG. 8 is a diagram showing a circuit configuration of the pixel circuit according to the second modification.
  • the solid-state image sensor 1b according to the second modification includes the pixel circuit 30b, and the pixel circuit 30b does not include the counting transistor 36.
  • the second reset transistor 34, the transfer transistor 31, the first reset transistor 32, the amplification transistor 33, and the selection transistor 35 are on the left side (X-axis-side). They are lined up along the first direction in this order.
  • the counting transistor 36 is omitted in this way, the dimension in the first direction required for arranging the plurality of transistors in the region where the pixel circuit 30b is mounted becomes short. That is, the size of the pixel cell 10 can be miniaturized.
  • the light receiving signal output by the pixel circuit 30b is a binary value indicating whether or not each pixel has detected light. It becomes a signal of.
  • FIG. 9 is a diagram showing two pixel cells included in the solid-state image sensor according to the third modification.
  • FIG. 10 is a diagram showing a circuit configuration of a pixel circuit according to the third modification.
  • the solid-state image sensor 1c according to the third modification includes the pixel circuit 30c, and the pixel circuit 30c does not include the second reset transistor 34.
  • the transfer transistor 31, the first reset transistor 32, the amplification transistor 33, and the selection transistor 35 are arranged in the first direction from the left side (X-axis-side) in this order. Lined up along.
  • the second reset transistor 34 is omitted in this way, the dimension in the first direction required for arranging the plurality of transistors in the region where the pixel circuit 30c is mounted becomes shorter. That is, the size of the pixel cell 10 can be miniaturized.
  • the transfer transistor 31 and the first reset transistor 32 may be turned on at the same time. Further, in the pixel circuit 30c, the electric charge collected on the cathode of the light receiving unit 2 exceeding the saturation level may overflow to the charge holding unit 5.
  • the Vt of the transfer transistor 31 is set high, the voltage when the gate electrode 310 of the transfer transistor is set to off is set low, and the diffusion region 59 (well contact) is set near the diffusion region 52.
  • the solid-state image sensor 1 is formed on the semiconductor substrate 100 and the semiconductor substrate 100 in a two-dimensional array shape along each of the first direction and the second direction intersecting the first direction. It includes a plurality of pixel cells 10.
  • Each of the plurality of pixel cells 10 has a light receiving unit 2 that receives incident light and generates an electric charge, a charge holding unit 5 that holds the electric charge generated by the light receiving unit 2, and a plurality of first units arranged along a first direction. It has one transistor and a pixel circuit 30 including a second transistor that outputs a voltage corresponding to the charge held by the charge holding unit 5 as a light receiving signal.
  • the pixel circuits 30 are the first light receiving unit and the second light receiving unit 2 of the first pixel cell 10a. It is adjacent to the second light receiving part, which is the light receiving part 2 of the two-pixel cell 10b, in the second direction.
  • Each of the plurality of first transistors included in the first pixel cell 10a shares a gate electrode with the first transistor included in the second pixel cell 10b, which has the same function as the first transistor.
  • the second transistor is, for example, an amplification transistor 33.
  • the junction boundary between the pixel circuit 30 and the light receiving portion 2 is reduced, so that the area of the separation portion for relaxing the electric field, which needs to be arranged at such a junction boundary, can be reduced.
  • Higher sensitivity can be achieved by reducing the area of the separating portion and increasing the area of the light receiving portion 2.
  • the gate electrodes of the plurality of first transistors are shared by the adjacent pixel cells, the number and area of wiring for applying a voltage to the gate electrodes can be reduced. Therefore, by increasing the aperture ratio of the wiring region, it is possible to increase the sensitivity to incident light having a large incident angle. Further, the protruding dimension toward the boundary 11 side can be automatically secured for the diffusion region of the plurality of first transistors, and the effect of easily suppressing the variation in the Vt characteristics of the transistors can be obtained.
  • the gate electrode of the first transistor included in the first pixel cell 10a is on the first light receiving portion side by a first length (first protruding dimension A1) with respect to the diffusion region of the first transistor. It protrudes into.
  • the gate electrode of the second transistor of the first pixel cell 10a protrudes toward the second light receiving portion by a second length (second protruding dimension A2) from the diffusion region of the second transistor. ..
  • the second length is shorter than the first length.
  • the parasitic capacitance between the charge holding portions 5 can be reduced by separating the gate electrodes 330 of the amplification transistor 33 (second transistor) between the pixel cells to a certain extent. Further, the arrangement of the diffusion regions 50 to 58 can be brought closer to the boundary 11, and the width of the pixel circuit 30 can be shortened in the second direction. Therefore, it is possible to increase the sensitivity by increasing the area ratio of the light receiving unit 2.
  • the transfer transistor 31 for transferring the charge generated by the light receiving unit 2 to the charge holding unit 5 and the charge accumulated in the charge holding unit 5 in the plurality of first transistors.
  • the first reset transistor 32 and the selection transistor 35 for selecting whether or not to output the light receiving signal output by the second transistor to the signal line are included.
  • the pixel circuit 30 including the transfer transistor 31, the first reset transistor 32, and the amplification transistor 33 can generate a light receiving signal according to the light received by the light receiving unit 2.
  • the plurality of first transistors further include a second reset transistor 34 that resets the electric charge accumulated by the light receiving unit 2.
  • the second reset transistor 34 is turned on by applying a voltage to the gate electrode 340, so that the electric charge accumulated in the cathode of the light receiving unit 2 is discharged to the second reset drain electrode 104 (light receiving unit). It is possible to reset the cathode of 2. Further, the charge exceeding the saturation level accumulated in the cathode of the light receiving unit 2 exceeds the potential barrier of the second reset transistor 34 and overflows to the second reset drain electrode 104, so that the charge holding unit 5 is not charged. It is possible to prevent the signal from leaking during the exposure period.
  • the pixel circuit 30 further includes a memory unit 6, and the plurality of first transistors further include a counting transistor 36 for connecting the charge holding unit 5 and the memory unit 6.
  • the amount of electric charge corresponding to the number of times light is detected in the second light receiving mode can be stored in the memory unit 6, so that the number of photons that can be substantially detected increases. That is, the dynamic range can be expanded.
  • each of the plurality of pixel cells 10 includes a p-type well region 9 and a well wiring 62 for applying a voltage to the p-type well region 9 in the pixel cell 10.
  • the well wiring 62 runs parallel to the wiring 61 connected to the charge holding portion 5.
  • the parasitic capacitance of the charge holding unit 5 increases, so that the amount of charge accumulated up to the saturation level of the charge holding unit 5 when light is detected increases, and the amount of charge that can be transferred to the memory unit 6 increases. To increase. Since the voltage fluctuation of the memory unit 6 increases per count, it is possible to reduce the reading error of the count number.
  • the well wiring 62 and the wiring 61 connected to the charge holding portion 5 are formed in the same wiring layer.
  • the parasitic capacitance of the charge holding portion 5 can be increased by bringing the well wiring 62 and the wiring 61 close to each other in the same wiring layer.
  • the well wiring 62 and the wiring 61 connected to the charge holding portion 5 are formed in different wiring layers.
  • the parasitic capacitance of the charge holding portion 5 can be increased by bringing the well wiring 62 and the wiring 61 close to each other in different wiring layers.
  • the light receiving unit 2 has a multiplication region in which the electric charge generated by receiving the incident light is multiplied by the avalanche multiplication.
  • an avalanche photodiode can be used as the light receiving unit 2.
  • the arrangement of the plurality of first transistors of the first pixel cell in the first direction is the same as the arrangement of the plurality of first transistors of the second pixel cell in the first direction.
  • the gate electrode has a line shape along the second direction.
  • the second transistor included in the first pixel cell does not share the gate electrode with the second transistor included in the second pixel cell.
  • the output of the received light signal can be performed individually for each pixel cell 10.
  • a plurality of first transistors and second transistors are arranged along the first direction.
  • the arrangement of the plurality of transistors can be simplified by arranging the plurality of transistors constituting the pixel circuit 30 on a straight line along the first direction.
  • the second transistor includes two diffusion regions corresponding to the source and the drain, and only one of the two diffusion regions is shared with the plurality of first transistors.
  • the second transistor includes two diffusion regions corresponding to the source and the drain, and both of the two diffusion regions are shared with the plurality of first transistors.
  • the diffusion region 58 of the second transistor and the diffusion region 53 of the first reset transistor 32 among the plurality of first transistors are shared, the region required for arranging the plurality of transistors is shared. The size of is reduced. Therefore, the size of the pixel cell 10 can be miniaturized.
  • the light receiving unit, the plurality of first transistors, and the second transistor are arranged in the first pixel cell 10a, and the light receiving unit 2, the plurality of first transistors in the second pixel cell 10b.
  • the arrangement of the second transistor is line-symmetrical with respect to the boundary 11 of the first pixel cell 10a and the second pixel cell 10b.
  • the arrangement of the plurality of transistors described in the above embodiment is an example, and the arrangement of the plurality of transistors may be changed within the scope of the object of the present disclosure.
  • an arrangement different from other regions may be adopted in a part region of the solid-state image sensor.
  • control unit of the solid-state image sensor operates the pixel cell in two light receiving modes, a first light receiving mode and a second light receiving mode.
  • control unit does not have to operate the pixel cell in the first light receiving mode, and may operate the pixel cell only in the second light receiving mode.
  • the conductive type of the diffusion regions 51 to 58 other than the well contact (diffusion region 59) is made p-type
  • the conductive type of well contact (diffusion region 59) is made n-type
  • the p-type well region 9 is formed. May be an n-type well region. In this case, since the boundary between the p-type well region 9 and the n-type well region 8 disappears, the size of the pixel cell can be miniaturized.
  • the well contacts are arranged one by one in the plurality of pixel cells in order to equalize the voltages in the p-type well regions of the plurality of pixel cells.
  • well contacts need not be arranged in each of the plurality of pixel cells.
  • One well contact may be arranged for each of a plurality of pixel cells, or may be arranged at about one or two places for one row of pixel cells. If the well contact is reduced, the size of the pixel cell can be reduced.
  • the first direction and the second direction are described as being orthogonal to each other, but the angle formed by the first direction and the second direction may be less than 90 degrees.
  • the arrangement of the plurality of transistors in the first pixel cell and the arrangement of the plurality of transistors in the second pixel cell may not be vertically symmetrical, but the arrangement order of the plurality of transistors is the same.
  • the circuit configuration described in the above embodiment is an example, and the present disclosure is not limited to the above circuit configuration. That is, similarly to the above circuit configuration, a circuit capable of realizing the characteristic functions of the present disclosure is also included in the present disclosure.
  • the present disclosure also discloses an element in which elements such as a switching element (transistor), a resistance element, or a capacitive element are connected in series or in parallel to a certain element within a range in which the same function as the above circuit configuration can be realized. included.
  • each layer of the laminated structure of the solid-state image sensor realizes the same function as the laminated structure of the above-described embodiment.
  • Other materials may be included to the extent possible.
  • the corners and sides of each component are shown linearly, but the present disclosure also includes those having rounded corners and sides due to manufacturing reasons and the like.
  • the present disclosure may be realized as a method for manufacturing a solid-state image sensor.
  • the solid-state image sensor of the present disclosure is useful as a solid-state image sensor suitable for increasing sensitivity.

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US20220310684A1 (en) 2022-09-29

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