WO2021120806A1 - 一种批量精确诊断cBit阵列故障的装置和方法 - Google Patents

一种批量精确诊断cBit阵列故障的装置和方法 Download PDF

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Publication number
WO2021120806A1
WO2021120806A1 PCT/CN2020/120803 CN2020120803W WO2021120806A1 WO 2021120806 A1 WO2021120806 A1 WO 2021120806A1 CN 2020120803 W CN2020120803 W CN 2020120803W WO 2021120806 A1 WO2021120806 A1 WO 2021120806A1
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pin
cbit
type
array
channel
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PCT/CN2020/120803
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English (en)
French (fr)
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吕吉强
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上海御渡半导体科技有限公司
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Publication of WO2021120806A1 publication Critical patent/WO2021120806A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2601—Apparatus or methods therefor
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
    • G01R31/2834—Automated test systems [ATE]; using microprocessors or computers

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  • the invention relates to the field of semiconductor automatic test equipment (Automatic Test Equipment, ATE for short), and in particular to a device and method for accurately diagnosing cBit array failures in batches.
  • semiconductor automatic test equipment Auto Test Equipment, ATE for short
  • cBit can be understood as Control Bit.
  • the automatic test equipment ATE
  • Relay delay
  • Mux multiple
  • FIG. 1 is a schematic diagram of a single cBit simple circuit in the prior art.
  • FIG. 2 is a schematic diagram of the function of a single cBit channel in the prior art.
  • the external pins of a single connector except for the core cBit pins, generally need to provide the function definitions of power pin VCC, ground pin GND and floating NC, and the specific location of this part of the pin will also be There is a certain degree of randomness.
  • connection modes are taken as examples for description. Of course, in actual application, these two connection modes are not necessarily required.
  • FIG. 3 is a schematic diagram of the first type of single connector in the prior art
  • FIG. 4 is a schematic diagram of the second type of single connector in the prior art.
  • VCC indicates that the Pin output is power, that is, high level, and the software level can be understood as logic 1
  • GND indicates that the Pin output is power, that is, low level, and the software level can be understood as logic 0
  • NC represents this Pin is Not Connect, which means it is floating.
  • the entire cBit resource board may involve more than 1,000 pin resources, that is, there will be several connectors placed on the same cBit resource board.
  • Short circuit refers to the formation of short circuit between resource channels in the board
  • Open circuit means that the resource channel in the board cannot form a circuit connection with external devices through the connector
  • Constant high means that the resource channel in the board always outputs high level
  • Constant low means that the resource channel in the board always outputs low level.
  • the current conventional cBit diagnosis can usually determine the connectivity of the channels one by one by driving high and low levels. In other words, you can first set channel 1 to a high reading result value of 1, and channel 2 to a high reading result value of 1, and then traverse all channels in turn; then, set channel 1 to a low reading result value of 0 , Channel 2 is set to low and the read result value is 0, and all channels are traversed and judged in turn.
  • the purpose of the present invention is to provide a method for accurately diagnosing cBit array failures in batches of ATE equipment, which can solve the problem of large-scale cBit connectivity in ATE test equipment, that is, it can effectively diagnose connectors during production and equipment maintenance. Connector problems caused by various processes, welding, and human factors that occurred when cBit was extracted.
  • a device for accurately diagnosing cBit array failures in batches includes:
  • the cBit resource board includes a first cBit array on the cBit resource board, the first cBit array is an M*N array, which includes one or more connectors, and the cBit resource board also includes a write register and Output control CPLD; wherein, the M and N are greater than or equal to 3; the write register has M*N storage units, and each storage unit corresponds to a unit in the first cBit array;
  • Diagnostic PB board which includes a second cBit array, M*N read register, and data read control CPLD;
  • the second cBit array is an M*N array, and the M and N are greater than or equal to 3;
  • the read register has M *N storage units, each of the storage units corresponds to a unit in the second cBit array;
  • the first cBit array is connected to the second cBit array through the one or more connectors;
  • CPU processing unit respectively connected to the cBit resource board and the diagnostic PB board;
  • a unit in the first cBit array on the cBit resource board is correspondingly connected to a unit in the second cBit array on the diagnostic PB board; when performing the operation on the first cBit array on the cBit resource board During fault diagnosis, the CPU processing unit includes:
  • the pin attribute classification module is used to classify the attributes of each external pin on the first cBit array, and define the power supply pin VCC as the first type of pin, and the ground pin GND as the second type of pin ,
  • the floating pin NC is defined as the third type of pin, and the cBit channel pin is defined as the fourth type of pin;
  • the setting module sets the content stored in each storage unit in the write register according to the potential islanding effect rule;
  • the potential islanding effect rule is the walking 0 rule and/the walking 1 rule for diagnosing short circuit faults;
  • the control module controls the output control CPLD to drive the output of the first cBit array according to the content stored in each storage unit in the write register; and controls the second cBit array to receive the first cBit array And store the output of the second cBit array into the read register through the read control CPLD;
  • the judgment module compares the value of each storage unit in the write register with the value of each storage unit in the second cBit array corresponding to the read storage unit, and compares the value of each storage unit in the second cBit array according to the comparison result and the
  • the potential islanding effect rule determines the state of the first type of pin, the second type of pin, and the fourth type of pin channel;
  • the first type of pin status includes normal, normally low fault or open circuit fault and short circuit fault;
  • the second type of pin status includes normal, normal high fault or open circuit fault and short circuit fault
  • the fourth type of pin status includes normal, open circuit fault and short circuit fault
  • the third category of pins is not judged.
  • the device for diagnosing cBit array failures in batches further includes a drive unit, the cBit drive unit is an M*N array, and the input terminal of each channel in the cBit drive unit is connected to the first cBit array One unit in the cBit drive unit is connected, and the output terminal of each channel in the cBit drive unit is connected to one unit in the second cBit array.
  • the cBit driving unit is a cBit driving device ULN2003.
  • Step S1 Classify the attributes of each external pin on the first cBit array, and define the power pin VCC as the first type of pin, the ground pin GND as the second type of pin, and the floating pin NC Defined as the third category of pins, and the cBit channel pins are defined as the fourth category of pins;
  • Step S2 Set the content stored in each storage unit in the write register according to the potential islanding effect rule;
  • the potential islanding effect rule is at least the walking 0 rule and/or the walking 1 rule for diagnosing short circuit faults;
  • Step S3 Control the output control CPLD to drive the output of the first cBit array according to the content stored in each storage unit in the write register; and control the second cBit array to receive the first cBit array And store the output of the second cBit array into the read register through the read control CPLD;
  • Step S4 Compare the value of each storage unit in the write register with the value of each storage unit in the second cBit array corresponding to the read storage unit, and compare the value of each storage unit in the second cBit array according to the comparison result and the The potential islanding effect rule determines the state of the first type of pin, the second type of pin, and the fourth type of pin channel; wherein,
  • the first type of pin status includes normal, normally low fault or open circuit fault and short circuit fault;
  • the second type of pin status includes normal, normal high fault or open circuit fault and short circuit fault
  • the fourth type of pin status includes normal, open circuit fault and short circuit fault
  • the third category of pins is not judged.
  • step S2 of the diagnosis method specifically includes step S21, step S22, step S23, and step S24; wherein, step S21 and step S22 are performed in any order, and step S23 and step S24 are performed in any order.
  • step S23 and the step S24 are executed after the step S21 and the step S22 are executed;
  • Step S21 For the first type of pin channel resources, the level of the power pin VCC does not change, and by changing the level of its peripheral channels to output all 0->all 1->all 0, that is, a level pulse matrix is used Method to diagnose the fault of the VCC channel resource of the power pin;
  • Step S22 For the second type of pin channel resources, the level of the ground pin GND does not change, by changing the level of its peripheral channels to output all 0->all 1->all 0, that is, a level pulse matrix is used Method to diagnose the fault of the GND channel resource of the ground pin;
  • Step S23 For the fourth type of pin channel resources, perform the following steps:
  • Step S233 Skip the first-type pin channels, the second-type pin channels, and the third-type pin channels, and sequentially traverse all the fourth-type pin channel resource positions, that is, the method of walking 1 is adopted;
  • Step S24 For the fourth type of pin channel resources, perform the following steps:
  • Step S243 Skip the first-type pin channels, the second-type pin channels, and the third-type pin channels, and traverse all the resource positions of the fourth-type pin channels in turn; that is, the step 0 method is adopted.
  • step S3 of the diagnosis method specifically includes the following steps:
  • Step S31 For the first type of pin channel resources, the read value of the unit in the read memory at the corresponding position of the power pin VCC channel is always 1, indicating that the channel is normal; the corresponding position of the power pin VCC channel is read The value is always 0, which means that the channel is always low or open fault; the read value of the corresponding position of the power pin channel is 0->1->0, which means that the channel is short-circuited;
  • Step S32 For the second type of pin channel resources, the read value of the unit in the read memory at the corresponding position of the ground pin GND channel is always 0, indicating that the channel is normal; the corresponding position of the ground pin GND channel is read The value is always 1, indicating that the channel is always high or open; the read value of the corresponding position of the power pin channel is 1->0->1, which indicates that the channel is short-circuited;
  • Step S33 For the fourth type of pin channel resource, obtain and determine that the corresponding position value is consistent with the set value; if the output value of Row and Col where the inconsistent result value is located after the comparison is 0, determine the corresponding position of the Row and Col.
  • the fourth type of pin channel resource has a short-circuit fault;
  • Step S34 Obtain and determine that the corresponding position value is consistent with the set value; if the output value of Row and Col where the inconsistent result value is located after the comparison is 1, it is determined that the fourth type of pin channel resource corresponding to the Row and Col exists Short circuit fault or open circuit fault.
  • step S31 also includes if the pin channel resource of the first type has a short-circuit fault, a constant low channel fault or an open circuit fault, the fault needs to be eliminated and resolved first; in step S32, it also includes if the pin channel resource of the second type has a short-circuit fault, a constant low channel fault or an open circuit fault. If there is a short-circuit fault, a constant high channel fault, or an open circuit fault, the fault must be eliminated and resolved first.
  • the diagnosis method further includes step S5: for the fourth type of pin channel resource, outputting all 0->all 1->all 0 diagnosis, specifically including the following steps:
  • Step S51 Control all the fourth-type pin channel resources to output all 0s, and read the CPLD from the data to obtain and determine whether they are all 0s; control all the fourth-type pin channel resources to output all 1s, and read from the data Take the CPLD to obtain and judge whether all 1s; control all the fourth-type pin channel resources to output all 0s, and read the CPLD to obtain from the data and judge whether all 0s;
  • Step S52 For the fourth type of pin channel resource, read 0->1->0 in sequence, which means that the fourth type of pin channel resource is normal; the fourth type of pin channel resource is read as all 0s , It means that the fourth type of pin channel resource is a normally low fault; the fourth type of pin channel resource is read as all 1s, and the fourth type of pin channel resource is a normally high fault or an open fault. .
  • the technical solution of the present invention can effectively perform accurate and effective fault diagnosis for the connectivity of a large number of cBit resource connectors, and can accurately diagnose and clarify the fault point and the pin where the cBit resource connector is located. Fault type.
  • Figure 1 shows a schematic diagram of a single cBit simple circuit in the prior art
  • Figure 2 shows a schematic diagram of the function of a single cBit channel in the prior art
  • Fig. 3 is a schematic diagram showing the display values of each unit of the first single connector in the prior art
  • Fig. 4 is a schematic diagram showing the display values of each unit of the second single connector in the prior art
  • Figure 5 shows a schematic diagram of a device for accurately diagnosing cBit array failures in batches in an embodiment of the present invention
  • Figure 6 is a schematic diagram of a method for accurately diagnosing cBit array failures in batches in an embodiment of the present invention
  • the cBit connector in the ATE test equipment is generally composed of several rows and several columns of holes, such as a Go chess board. Each hole can lead out cables, and all cBit cables are connected to the diagnostic board during diagnosis.
  • CPLD Complex Programmable Logic Device
  • the power supply pin can be diagnosed by changing the level 0->1->0 or 1->0->1 of the surrounding channels, that is, the level pulse matrix method VCC and ground pin GND resource failure.
  • the electric potential difference between the holes on the cBit connector can be constructed by driving the output of the high and low electrical signals of each channel on the cBit resource board to effectively judge whether the hole and the cable are in good connection status.
  • Table 1 shows the situation where a high potential surrounds a low potential.
  • Table 2 shows the situation where high potential surrounds low potential
  • FIG. 5 is a schematic diagram of a device for accurately diagnosing cBit array faults in batches in an embodiment of the present invention.
  • the device for diagnosing cBit array failures in batches includes a cBit resource board, a diagnostic PB board, and a CPU processing unit.
  • the cBit resource board includes the first cBit array on the cBit resource board.
  • the first cBit array is an M*N array, which includes one or more connectors.
  • the cBit resource board also includes write registers and output control CPLDs; among them, M And N is greater than or equal to 3; the write register has M*N storage units, and each storage unit corresponds to a unit in the first cBit array.
  • the diagnostic PB board includes a second cBit array, M*N read register and data read control CPLD; the second cBit array is an M*N array, M and N are greater than or equal to 3; the read register has M*N memory cells, each The storage unit corresponds to a unit in a second cBit array; the first cBit array is connected to the second cBit array through the one or more connectors.
  • the CPU processing unit is respectively connected to the cBit resource board and the diagnostic PB board; among them, a unit in the first cBit array on the cBit resource board is connected to a unit in the second cBit array on the diagnostic PB board;
  • the CPU processing unit includes a pin attribute classification module, a setting module, a control module, and a judgment module.
  • the pin attribute classification module is used to classify the attributes of each external pin on the first cBit array, and define the power pin VCC as the first type of pin, and the ground pin GND as the second type of pin.
  • Pin NC is defined as the third type of pin, and the cBit channel pin is defined as the fourth type of pin;
  • the setting module sets the content stored in each memory cell in the write register according to the potential islanding effect rule;
  • the potential islanding effect rule is The walking 0 rule and/the walking 1 rule for diagnosing short-circuit faults;
  • the control module controls the output control CPLD to drive the output of the first cBit array according to the content stored in each storage unit in the write register; and control the second cBit
  • the array receives the output of the first cBit array, and stores the output of the second cBit array in the read register through the read control CPLD;
  • the judgment module the value of each memory cell in the write register and the read memory cell correspond to a second
  • the value of each memory cell in the cBit array is compared, and the status of the first type of pin, the second type of pin, and the fourth type of pin channel are judged according to the comparison result and the potential islanding effect rule;
  • the device for diagnosing cBit array failures in batches may also include a drive unit.
  • the cBit drive unit is an M*N array.
  • the input terminal of each channel in the cBit drive unit is connected to the One unit in the first cBit array is connected, and the output terminal of each channel in the cBit driving unit is connected to one unit in the second cBit array.
  • the cBit driving unit is a cBit driving device ULN2003.
  • the present invention for multiple connectors used on a cBit resource board, it can be considered as a duplication of the same method.
  • the present invention mainly describes the diagnosis of a single connector, and the diagnosis of multiple connectors is Is a copy of the method;
  • Controlling the output 1 of cBit means writing 1 to the "output control CPLD"; outputting 0 means writing 0;
  • the access CPLD of the central processing unit CPU through the local parallel access bus LocalBus takes several tens of ns, and the access through I2C is at the level of 100us; the increase in the number of accesses has little impact on the overall diagnosis time, therefore, in the solution of the present invention Don't worry about the impact of longer diagnosis time;
  • the connector is the pin of NC, the diagnostic PB board has no corresponding data to read the read register controlled by CPLD, all related tests are skipped.
  • FIG. 6 is a schematic diagram of a method for accurately diagnosing cBit array failures in batches in an embodiment of the present invention. As shown in Figure 5, write 1 in the corresponding Bit bit of the write register WriteRegister_n on the cBit resource board to read the result value on the corresponding Bit bit of the read register ReadRegister_n on the diagnostic PB board.
  • the input of the cBit drive device is 0. After the device is driven by cBit, it will be inverted by the inverter 2, and the output will be 1;
  • the power supply pin VCC channel indicates that the resource board provides external power output capability, which can be read as 1 in the corresponding ReadRegister on the diagnostic PB board; affected by the pull-down on the diagnostic PB side, if the channel is open, the ReadRegister reads as 0;
  • the GND channel of the ground pin indicates that the resource board provides external ground, which can be read as 0 in the corresponding ReadRegister on the diagnostic PB board; affected by the pull-up on the diagnostic PB side, if the channel is open, the ReadRegister will read 1.
  • the method for accurately diagnosing cBit array failures in batches in an embodiment of the present invention includes the following steps:
  • Step S1 Classify the attributes of each external pin on the first cBit array, and define the power supply pin VCC as the first type of pin, the ground pin GND as the second type of pin, and the floating pin NC as the The third category of pins, and the cBit channel pins are defined as the fourth category of pins.
  • fault diagnosis is only performed on the pins of the first type, the second type and the fourth type of pins.
  • Step S2 Set the content stored in each storage unit in the write register according to the potential islanding effect rule; the potential islanding effect rule is a walking 0 rule and/or a walking 1 rule for diagnosing at least a short circuit fault.
  • step S2 may specifically include step S21, step S22, step S23, and step S24; wherein, step S21 and step S22 are performed in any order, step S23 and step S24 are performed in any order, and step S23 and Step S24 is executed after the execution of step S21 and step S22 is completed.
  • Step S3 Control the output control CPLD to drive the output of the first cBit array according to the content stored in each memory cell in the write register; and control the second cBit array to receive the output of the first cBit array, and control the CPLD to read The output of the second cBit array is stored in the read register.
  • Step S4 Compare the value of each memory cell in the write register with the value of each memory cell in the second cBit array corresponding to the read memory cell. According to the comparison result and the potential islanding effect rule, determine the first type of pin, The status of the second type of pin and the fourth type of pin channel.
  • step S21 for the diagnosis of a small number of non-adjacent power pin VCC channel resources in the cBit array, step S21 may be performed.
  • Step S21 For the first type of pin channel resources, the level of the power supply pin VCC does not change, by changing the level of its peripheral channels to output all 0->all 1->all 0, that is, using the level pulse matrix method Diagnose the fault of the power supply pin VCC channel resource.
  • step S31 The specific diagnosis result is reflected in step S31, that is, for the first type of pin channel resources, the read value of the unit in the read memory at the corresponding position of the power pin VCC channel is always 1, indicating that the channel is normal; the corresponding position of the power pin VCC channel The read value is always 0, indicating that the channel is always low or open circuit failure; the read value of the corresponding position of the power pin channel is 0->1->0, indicating that the channel is short-circuited.
  • step S22 for the diagnosis of a small number of non-adjacent ground pin GND channel resources in the cBit array, step S22 may be performed.
  • Step S22 For the second type of pin channel resources, the level of the ground pin GND does not change. By changing the level of its peripheral channels to output all 0->all 1->all 0, that is, the level pulse matrix method is adopted. Diagnose the fault of the ground pin GND channel resource.
  • step S32 The specific diagnosis result is reflected in step S32, that is, for the second type of pin channel resource, the reading value of the unit in the read memory corresponding to the ground pin GND channel is always 0, indicating that the channel is normal; the ground pin GND channel corresponds to the position The read value is always 1, indicating that the channel is normally high or open circuit failure; the read value of the corresponding position of the power pin channel is 1->0->1, indicating that the channel is short-circuited.
  • Step S33 For the fourth type of pin channel resource, obtain and determine that the corresponding position value is consistent with the set value; if the output value of Row and Col where the inconsistent result value is located after the comparison is 0, determine the fourth type corresponding to Row and Col There is a short-circuit fault in the pin channel resource;
  • Step S34 Obtain and determine that the corresponding position value is consistent with the set value; if the output value of Row and Col where the inconsistent result value is located after the comparison is 1, it is determined that the fourth type of pin channel resource corresponding to Row and Col has a short circuit fault or open circuit malfunction.
  • outputting all 0->all 1->all 0 diagnosis specifically includes the following steps:
  • Step S51 Control all pin channel resources of the fourth type to output all 0s, and obtain from the data read CPLD and determine whether they are all 0s; control all pin channel resources of the fourth type to output all 1s, and obtain the data from the CPLD read Judge whether it is all 1; control all the fourth-type pin channel resources to output all 0, and read the data from CPLD to obtain and judge whether it is all 0.
  • Table 3 The effect of outputting all 0s is shown in Table 3 below:
  • step S52 The specific diagnosis result is reflected in step S52, that is, for the fourth type of pin channel resource, read 0->1->0, it means that the fourth type of pin channel resource is normal; the fourth type of pin channel resource is read as All 0s means that the fourth type of pin channel resource is a normally low fault; the fourth type of pin channel resource is read as all 1s, and the fourth type of pin channel resource is a normally high fault or open fault.
  • step S23 for the fault diagnosis of the short circuit of the fourth type of pin channel resources, step S23 may be performed, which specifically includes the following steps:
  • Step S233 Skip the first-type pin channels, the second-type pin channels, and the third-type pin channels, and traverse all the fourth-type pin channel resource locations in turn, that is, the step 1 method is adopted.
  • step S33 The specific diagnosis result is reflected in step S33, that is, for the fourth type of pin channel resource, the corresponding position value is obtained and judged to be consistent with the set value; if the inconsistent result value after the comparison is 0, the fourth row and Col corresponding to the row are determined.
  • the pin-like channel resource has a short-circuit fault.
  • step S24 may be executed, which specifically includes the following steps:
  • Step S243 Skip the first-type pin channels, the second-type pin channels, and the third-type pin channels, and traverse all the fourth-type pin channel resource locations in turn; that is, the method of walking 0 is adopted.
  • step S34 The specific diagnosis result is reflected in step S34, that is, for the fourth type of pin channel resource, obtain and determine that the corresponding position value is consistent with the set value; after the comparison, if the output value of Row and Col where the inconsistent result value is located is 0, determine Row and The fourth type of pin channel resource corresponding to Col has a short-circuit fault.
  • Step S34 Obtain and determine that the corresponding position value is consistent with the set value; if the output value of Row and Col where the inconsistent result value is located after the comparison is 1, it is determined that the fourth type of pin channel resource corresponding to Row and Col has a short circuit fault or open circuit malfunction.
  • the present invention is a device and method for accurately diagnosing cBit array failures in batches. It diagnoses whether the pin has a connection failure by constructing a potential island on the output pin (Pin pin) of the cBit resource connector. It can effectively perform accurate and effective fault diagnosis for the connectivity of a large number of cBit resource connectors, and can also accurately diagnose the fault point and fault type of the pin where the cBit resource connector is located.

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Abstract

一种批量精确诊断cBit阵列故障的装置和方法，该装置包括cBit资源板、诊断PB板和CPU处理单元；cBit资源板包括位于cBit资源板上的第一cBit阵列、M*N写寄存器和输出控制CPLD；诊断PB板包括第二cBit阵列、M*N读寄存器和数据读取控制CPLD；CPU处理单元分别与cBit资源板和诊断PB板相连；通过构造cBit资源连接器的输出引脚上的电势孤岛来诊断该引脚是否存在连接故障，不仅可以有效的针对大批量cBit资源连接器的连通性进行精确有效的故障诊断，还可以精确的诊断明确cBit资源连接器所在Pin脚的故障点和故障类型。

Description

一种批量精确诊断cBit阵列故障的装置和方法
交叉引用
本申请要求2019年12月19日提交的申请号为CN201911315329.6的中国专利申请的优先权。上述申请的内容以引用方式被包含于此。
技术领域
本发明涉及半导体自动测试设备(Automatic Test Equipment，简称ATE)领域，尤其涉及一种批量精确诊断cBit阵列故障的装置和方法。
技术背景
cBit可以理解为Control Bit，在测试芯片的过程中，自动测试设备(ATE)通过输出高低电平来为客户提供延迟(Relay)开关功能，和多路(Mux)选路的功能。
在高端ATE设备中，由于需要并行测试的待测器件(Device under test简称DUT)数量多，所需的各类资源数量非常庞大，以cBit的资源来看，完全可能有上千个引脚。
请参阅图1，图1所示为现有技术中单个cBit简易电路示意图。请参阅图2，图2所示为现有技术中单个cBit通道功能示意图。
本领域技术人员清楚，ATE设备的资源通道数量较多，单块cBit资源板上的通道数量往往可以达到1000多个。为了确保客户拿到的cBit单板每一个通道都是功能正常的，因此，在生产环境和客户诊断环境下，均需要快速有效的诊断能力的支持。
并且，单个连接器对外的引脚除核心的cBit引脚外，一般部分引脚需要提供电源引脚VCC、接地引脚GND和悬空NC的功能定义，并且，这部分引脚所在具体位置也会有一定的随机性。
为方便理解，以下列两种连接方式为例进行说明，当然，在实际应用过程中，也并不需要一定按照这两种连接方式。
请参阅图3和图4，图3所示为现有技术中第一种单个连接器的示意图；图4所示为现有技术中第二种单个连接器的示意图。
其中，VCC：表示该Pin输出为电源，即高电平，软件层面可以理解为逻辑1；GND：表示该Pin输出为电源，即低电平，软件层面可以理解为逻辑0；NC：表示该Pin为Not Connect，即表示为悬空。
此外，在硬件走线时，需要避免电源引脚VCC与接地引脚GND设计在相连通道上，以防止电源引脚VCC与接地引脚GND短路的发生。
也就是说，整个cBit资源板有可能涉及到的1000多个引脚(Pin)资源，即会有若干个连接器放置在同一个cBit资源板上。
对于cBit资源板上各连接器之间的连通性故障，常见的有短路、断路、常高和常低等几种情况。上述这连通性故障常见情况的解释如下：
①、短路是指板内资源通道间形成了短接；
②、断路是指板内资源通道通过连接器不能与外部器件形成电路连接；
③、常高是指板内资源通道一直输出高电平；
④、常低是指板内资源通道一直输出低电平。
在现有技术中，目前常规的cBit诊断，通常可以通过驱动高低电平来逐个判断通道的连通性。也就是说，可以首先将通道1设置为高读取结果值为1，通道2设置为高读取结果值1，依次遍历所有的通道；之后，将通道1设置为低读取结果值为0，通道2设置为低读取结果值为0，依次遍历和判断所有通道。
然而，上述的cBit诊断方案对于通道间短路的情况无法有效发现。
发明概要
本发明的目的在于提供一种ATE设备的批量精确诊断cBit阵列故障的方法，其可以解决在ATE测试设备大批量cBit连通性问题，即可以有效诊断连接器在生产制造和设备使用维护时，针对cBit引出时出现的各种工艺制程、焊接和人为因素等造成的连接器问题。
为实现上述目的，本发明的技术方案如下：
一种批量精确诊断cBit阵列故障的装置，包括：
cBit资源板，包括位于所述cBit资源板上的第一cBit阵列，所述第一cBit阵列为M*N阵列，其包括一个或多个连接器，所述cBit资源板上还包括写寄存器和输出控制CPLD；其中，所述M和N大于等于3；所述写寄存器具有M*N个存储单元，每一个所述存储单元对应一个所述第一cBit阵列中的一个单元；
诊断PB板，其包括第二cBit阵列、M*N读寄存器和数据读取控制CPLD；所述第二cBit阵列为M*N阵列，所述M和N大于等于3；所述读寄存器具有M*N个存储单元，每一个所述存储单元对应一个所述第二cBit阵列中的一个单元；所述第一cBit阵列通过所述一个或多个连接器与所述第二cBit阵列相连；
CPU处理单元，分别与所述cBit资源板和所述诊断PB板相连；
其中，所述cBit资源板上的第一cBit阵列中的一个单元和所述诊断PB板上的第二cBit阵列中的一个单元对应相连；当对所述cBit资源板上的第一cBit阵列进行故障诊断时，所述CPU处理单元包括：
引脚属性分类模块，用于分类所述第一cBit阵列上的每一个对外引脚的属性，并将电源引脚VCC定义为第一类引脚，接地引脚GND定义为第二类引脚，悬空引脚NC定义为第三类引脚，以及将cBit通道引脚定义为第四类引脚；
设置模块，根据电势孤岛效应规则设置所述写寄存器中的每一个存储单元所存储的内容；所述电势孤岛效应规则为用于诊断短路故障的走步0规则和/走步1规则；
控制模块，控制所述输出控制CPLD根据所述写寄存器中的每一个存储单元所存储的内容，驱动所述第一cBit阵列的输出；以及控制所述第二cBit阵列接收所述第一cBit阵列的输出，并通过所述读取控制CPLD将所述第二cBit阵列的输出存入到所述读寄存器中；
判断模块，将所述写寄存器中每一个所述存储单元的值与所述读存储单元对应一个所述第二cBit阵列中的每一个所述存储单元的值进行比较，根据比较结果和所述电势孤岛效应规则，判断所述第一类引脚、所述第二类引脚和所述第四类引脚通道的状态；其中，
所述第一类引脚状态包括正常、常低故障或断路故障和短路故障；
所述第二类引脚状态包括正常、常高故障或断路故障和短路故障；
所述第四类引脚状态包括正常、断路故障和短路故障；
所述第三类引脚不做判断。
优选地，所述的批量诊断cBit阵列故障的装置还包括驱动单元，所述cBit驱动单元为M*N阵列，所述cBit驱动单元中的每一个通道的输入端与所述述第一cBit阵列中的一个单元相连，所述cBit驱动单元中的每一个通道的输出端与所述述第二cBit阵列中的一个单元相连。
优选地，所述cBit驱动单元为cBit驱动器件ULN2003。
为实现上述目的，本发明又一技术方案如下：
一种采用所述权利要求1所述的批量诊断cBit阵列故障的装置的诊断方法，包括如下步骤：
步骤S1：分类所述第一cBit阵列上的每一个对外引脚的属性，并将电源引脚VCC定义为第一类引脚，接地引脚GND定义为第二类引脚，悬空引 脚NC定义为第三类引脚，以及将cBit通道引脚定义为第四类引脚；
步骤S2：根据电势孤岛效应规则设置所述写寄存器中的每一个存储单元所存储的内容；所述电势孤岛效应规则为用于至少诊断短路故障的走步0规则和/或走步1规则；
步骤S3：控制所述输出控制CPLD根据所述写寄存器中的每一个存储单元所存储的内容，驱动所述第一cBit阵列的输出；以及控制所述第二cBit阵列接收所述第一cBit阵列的输出，并通过所述读取控制CPLD将所述第二cBit阵列的输出存入到所述读寄存器中；
步骤S4：将所述写寄存器中每一个所述存储单元的值与所述读存储单元对应一个所述第二cBit阵列中的每一个所述存储单元的值进行比较，根据比较结果和所述电势孤岛效应规则，判断所述第一类引脚、所述第二类引脚和所述第四类引脚通道的状态；其中，
所述第一类引脚状态包括正常、常低故障或断路故障和短路故障；
所述第二类引脚状态包括正常、常高故障或断路故障和短路故障；
所述第四类引脚状态包括正常、断路故障和短路故障；
所述第三类引脚不做判断。
优选地，所述的诊断方法的步骤S2具体包括步骤S21、步骤S22、步骤S23和步骤S24；其中，所述步骤S21和步骤S22按任意顺序进行，所述步骤S23和所述步骤S24按任意顺序进行，所述步骤S23和所述步骤S24在所述步骤S21和步骤S22执行完成后执行；
步骤S21：对于第一类引脚通道资源，所述电源引脚VCC的电平不变化，通过改变其周边通道的电平输出全0->全1->全0，即采用电平脉冲矩阵法来诊断所述电源引脚VCC通道资源的故障；
步骤S22：对于第二类引脚通道资源，所述接地引脚GND的电平不变 化，通过改变其周边通道的电平输出全0->全1->全0，即采用电平脉冲矩阵法来诊断所述接地引脚GND通道资源的故障；
步骤S23：对于第四类引脚通道资源，执行如下步骤：
步骤S231：将Row＝1，Col＝1位置置为1，其它位置置为0；
步骤S232：将Row＝1，Col＝2位置置为1，其它位置置为0；
步骤S233：跳过第一类引脚通道、第二类引脚通道和第三类引脚通道，依次遍历所有所述第四类引脚通道资源位置，即采用走步1的方式；
步骤S24：对于第四类引脚通道资源，执行如下步骤：
步骤S241：将Row＝1，Col＝1位置置为0，其它位置置为1；
步骤S242：将Row＝1，Col＝2位置置为0，其它位置置为1；
步骤S243：跳过第一类引脚通道、第二类引脚通道和第三类引脚通道，依次遍历所有所述第四类引脚通道资源位置；即采用走步0的方式。
优选地，所述的诊断方法的步骤S3具体包括如下步骤：
步骤S31：对于第一类引脚通道资源，所述电源引脚VCC通道对应位置所述读存储器中的单元读取值始终为1，表示该通道正常；所述电源引脚VCC通道对应位置读取值始终为0，表示所述通道常低故障或断路故障；所述电源引脚通道对应位置读取值0->1->0，表示所述通道短路故障；
步骤S32：对于第二类引脚通道资源，所述接地引脚GND通道对应位置所述读存储器中的单元读取值始终为0，表示该通道正常；所述接地引脚GND通道对应位置读取值始终为1，表示所述通道常高故障或断路故障；所述电源引脚通道对应位置读取值1->0->1，表示所述通道短路故障；
步骤S33：对于第四类引脚通道资源，获取并判断对应位置值与设置值一致；比较后不一致的结果值所在的Row和Col输出值如果为0，确定所述Row和Col所对应的所述第四类引脚通道资源存在短路故障；
步骤S34：获取并判断对应位置值与设置值一致；比较后不一致的结果 值所在的Row和Col输出值如果为1，确定所述Row和Col所对应的所述第四类引脚通道资源存在短路故障或断路故障。
优选地，在步骤S31还包括如果第一类引脚通道资源中具有短路故障、通道常低故障或断路故障，需先排除并解决故障；在步骤S32还包括如果第二类引脚通道资源中具有短路故障、通道常高故障或断路故障，需先排除并解决故障。
优选地，所述的诊断方法还包括步骤S5：对于第四类引脚通道资源，输出全0->全1->全0诊断，具体包括如下步骤：
步骤S51：控制所有第四类引脚通道资源输出全0，并从所述数据读取CPLD获取并判断是否全0；控制所有第四类引脚通道资源输出全1，并从所述数据读取CPLD获取并判断是否全1；控制所有第四类引脚通道资源输出全0，并从所述数据读取CPLD获取并判断是否全0；
步骤S52：对于第四类引脚通道资源，依次读取0->1->0，则表示所述第四类引脚通道资源正常；所述第四类引脚通道资源读取为全0，则表示所述第四类引脚通道资源为常低故障；所述第四类引脚通道资源读取为全1，所述第四类引脚通道资源为常高故障或断路故障。。
从上述技术方案可以看出，本发明的技术方案可以有效的针对大批量cBit资源连接器的连通性进行精确有效的故障诊断，并可以精确的诊断明确cBit资源连接器所在Pin脚的故障点和故障类型。
附图说明
图1所示为现有技术中单个cBit简易电路示意图
图2所示为现有技术中单个cBit通道功能示意图
图3所示为现有技术中第一种单个连接器各单元显示值的示意图
图4所示为现有技术中第二种单个连接器各单元显示值的示意图
图5所示为本发明实施例中的批量精确诊断cBit阵列故障装置的示意图
图6所示为本发明实施例中的批量精确诊断cBit阵列故障的方法示意图
发明内容
下面结合附图5-6，对本发明的具体实施方式作进一步的详细说明。
ATE测试设备中cBit连接器一般由若干行，若干列孔位组成，如围棋棋盘，每个孔位可以对外引出线缆，诊断时将所有的cBit线缆连接至诊断板上。诊断板上有能够检测所有通道输出高低状态的判断单元CPLD(Complex Programmable Logic Device)复杂可编程逻辑器件。
本发明的解决方案原理之一：
针对单一cBit通道资源，通过连续的电平变化0->1->0或1->0->1诊断，即电平脉冲法来诊断cBit资源的故障。
本发明的解决方案原理之二：
针对VCC，GND通道资源，其电平不能变化，则通过改变其周边通道的电平0->1->0或1->0->1诊断，即电平脉冲矩阵法来诊断电源引脚VCC和接地引脚GND资源的故障。
本发明的解决方案原理之三：
形成完整连接后，即可以通过驱动cBit资源板上各通道的高低电信号的输出，构造出cBit连接器上各孔位间的电势差来有效的判断该孔位及线缆的连接状态是否良好。
基于以上方法，扩展至整个cBit连接器，可以形成一种在所有孔位进行走步0，走步1的机制。
请参阅下表1和表2，表1所示为高电势包围低电势的情况。
1 1 1
1 0 1
1 1 1
表2所示为高电势包围低电势的情况
0 0 0
0 1 0
0 0 0
该原理可以认为是通过形成EII(Electric Isolated Island电势孤岛)来满足对cBit连接器连接故障的诊断。低电势孤岛和高电势孤岛对cBit连接器阵列的诊断本质上并无差别，但针对断路故障会有所差别。
请参阅图5，图5所示为本发明实施例中的批量精确诊断cBit阵列故障的装置结构示意图。如图所示，该批量诊断cBit阵列故障的装置包括cBit资源板、诊断PB板和CPU处理单元。cBit资源板包括位于cBit资源板上的第一cBit阵列，第一cBit阵列为M*N阵列，其包括一个或多个连接器，cBit资源板上还包括写寄存器和输出控制CPLD；其中，M和N大于等于3；写寄存器具有M*N个存储单元，每一个存储单元对应一个第一cBit阵列中的一个单元。
诊断PB板包括第二cBit阵列、M*N读寄存器和数据读取控制CPLD；第二cBit阵列为M*N阵列，M和N大于等于3；读寄存器具有M*N个存储单元，每一个存储单元对应一个第二cBit阵列中的一个单元；所述第一cBit阵列通过所述一个或多个连接器与所述第二cBit阵列相连。
CPU处理单元分别与cBit资源板和诊断PB板相连；其中，cBit资源板上的第一cBit阵列中的一个单元和诊断PB板上的第二cBit阵列中的一个单元对应相连；当对cBit资源板上的第一cBit阵列进行故障诊断时，CPU处理单元包括引脚属性分类模块、设置模块、控制模块和判断模块。引脚属性分类模块用于分类第一cBit阵列上的每一个对外引脚的属性，并将电源引脚VCC定义为第一类引脚，接地引脚GND定义为第二类引脚，悬空引脚NC定义为第三类引脚，以及将cBit通道引脚定义为第四类引脚；设置模块根据电势孤岛效应规则设置写寄存器中的每一个存储单元所存储的内容；电势孤岛效应规则为用于诊断短路故障的走步0规则和/走步1规则；控制模块控制输出控制CPLD根据写寄存器中的每一个存储单元所存储的内容，驱动第一cBit阵列的输出；以及控制第二cBit阵列接收第一cBit阵列的输出，并通过读取控制CPLD将第二cBit阵列的输出存入到读寄存器中；判断模块，将写寄存器中每一个存储单元的值与读存储单元对应一个第二cBit阵列中的每一个存储单元的值进行比较，根据比较结果和电势孤岛效应规则，判断第一类引脚、第二类引脚和第四类引脚通道的状态；其中，在本实施例中，第一类引脚状态可以包括正常、常低故障或断路故障和短路故障；第二类引脚状态 可以包括正常、常高故障或断路故障和短路故障；第四类引脚状态可以包括正常、断路故障和短路故障；第三类引脚不做判断。
在本发明的实施例中，为更真实地模拟测试环境，批量诊断cBit阵列故障的装置还可以包括驱动单元，cBit驱动单元为M*N阵列，cBit驱动单元中的每一个通道的输入端与述第一cBit阵列中的一个单元相连，cBit驱动单元中的每一个通道的输出端与述第二cBit阵列中的一个单元相连。较佳地，cBit驱动单元为cBit驱动器件ULN2003。
需要说明的是：
①.在本发明的实施例中，针对一个cBit资源板上使用的多个连接器，可以认为是相同方法的复制，本发明主要将单个连接器的诊断加以说明，多个连接器的诊断即为该方法的复制；
②.针对指定引脚能够通过调用基础接口实现对指定写寄存器的写入和读寄存器的读取；
③.控制cBit的输出1即表示向“输出控制CPLD”写入1；输出0，即写入0；
④.获取cBit的状态为1即表示从“数据读取CPLD”读取到1；获取0，即读取到0；
⑤.中央处理器CPU通过本地并行访问总线LocalBus的访问CPLD耗时为几十ns，通过I2c访问为100us级别；访问次数的增加对于整体诊断的时间影响较小，因此，在本发明的方案中并不担忧诊断时间变长的影响；
⑥.如果诊断PB板上CPLD输入信号悬空(即断路故障)时，读寄存器中对应位获取值为1。
⑦.连接器为NC的引脚，诊断PB板无对应的数据读取CPLD控制的读寄存器，相关测试全部跳过。
请结合图5参阅图6，图6所示为本发明实施例中的批量精确诊断cBit阵列故障的方法示意图。如图5所示，在cBit资源板上的写寄存器WriteRegister_n对应Bit位上写入1即可在诊断PB板上的读寄存器ReadRegister_n对应Bit位上读取到结果值。
为叙述方便起见，我们将下述一些可能存在的情况示例说明如下：
①.写寄存器WriteRegister_1[Bit0]为1，通过CPLD内部设计的取反 器1，输出0；
②.cBit驱动器件输入为0，通过cBit驱动器件后会被取反器2取反后，输出为1；
③.在读寄存器ReadRegister_1[Bit0]查看读寄存器的值为1；则可以认为数据比较正确；
④.悬空NC通道表示Not Connect，即该通道对外不提供任何功能；
⑤.电源引脚VCC通道表示资源板卡对外提供电源输出能力，可在诊断PB板上对应的ReadRegister读取到1；受诊断PB侧下拉影响，如该通道断路，则ReadRegister读取到0；
⑥.接地引脚GND通道表示资源板卡对外提供地，可在诊断PB板上对应的ReadRegister读取到0；受诊断PB侧上拉影响，如该通道断路，则ReadRegister读取到1。
如图6所示，本发明实施例中的批量精确诊断cBit阵列故障的方法包括如下步骤：
步骤S1：分类第一cBit阵列上的每一个对外引脚的属性，并将电源引脚VCC定义为第一类引脚，接地引脚GND定义为第二类引脚，悬空引脚NC定义为第三类引脚，以及将cBit通道引脚定义为第四类引脚。
在本发明的实施例中，仅针对第一类引脚、第二类引脚和第四类引脚进行故障诊断。
步骤S2：根据电势孤岛效应规则设置写寄存器中的每一个存储单元所存储的内容；电势孤岛效应规则为用于至少诊断短路故障的走步0规则和/或走步1规则。
1 1 1
1 VCC/GND 1
1 1 1
0 0 0
0 VCC/GND 0
0 0 0
在本发明的实施例中，步骤S2可以具体包括步骤S21、步骤S22、步 骤S23和步骤S24；其中，步骤S21和步骤S22按任意顺序进行，步骤S23和步骤S24按任意顺序进行，步骤S23和步骤S24在步骤S21和步骤S22执行完成后执行。
步骤S3：控制输出控制CPLD根据写寄存器中的每一个存储单元所存储的内容，驱动第一cBit阵列的输出；以及控制第二cBit阵列接收第一cBit阵列的输出，并通过读取控制CPLD将第二cBit阵列的输出存入到读寄存器中。
步骤S4：将写寄存器中每一个存储单元的值与读存储单元对应一个第二cBit阵列中的每一个存储单元的值进行比较，根据比较结果和电势孤岛效应规则，判断第一类引脚、第二类引脚和第四类引脚通道的状态。
实施例1
在本发明的实施例中，对于cBit阵列中少量、非相邻的电源引脚VCC通道资源的诊断，可执行步骤S21。
步骤S21：对于第一类引脚通道资源，电源引脚VCC的电平不变化，通过改变其周边通道的电平输出全0->全1->全0，即采用电平脉冲矩阵法来诊断电源引脚VCC通道资源的故障。
具体的诊断结果由步骤S31体现，即对于第一类引脚通道资源，电源引脚VCC通道对应位置读存储器中的单元读取值始终为1，表示该通道正常；电源引脚VCC通道对应位置读取值始终为0，表示通道常低故障或断路故障；电源引脚通道对应位置读取值0->1->0，表示通道短路故障。
在本发明的实施例中，对于cBit阵列中少量、非相邻的接地引脚GND通道资源的诊断，可执行步骤S22。
步骤S22：对于第二类引脚通道资源，接地引脚GND的电平不变化，通过改变其周边通道的电平输出全0->全1->全0，即采用电平脉冲矩阵法来诊断接地引脚GND通道资源的故障。
具体的诊断结果由步骤S32体现，即对于第二类引脚通道资源，接地引脚GND通道对应位置读存储器中的单元读取值始终为0，表示该通道正常；接地引脚GND通道对应位置读取值始终为1，表示通道常高故障或断路故障；电源引脚通道对应位置读取值1->0->1，表示通道短路故障。
需要说明的是，如有出现VCC/GND的各种故障则诊断流程停止，需要优先进行故障排除并解决。
步骤S33：对于第四类引脚通道资源，获取并判断对应位置值与设置值一致；比较后不一致的结果值所在的Row和Col输出值如果为0，确定Row和Col所对应的第四类引脚通道资源存在短路故障；
步骤S34：获取并判断对应位置值与设置值一致；比较后不一致的结果值所在的Row和Col输出值如果为1，确定Row和Col所对应的第四类引脚通道资源存在短路故障或断路故障。
也就是说，通过上述步骤就可以确保电源引脚VCC和接地引脚GND通道不会有短路故障，从而影响周边的cBit通道资源。
实施例2
在本发明的实施例中，对于第四类引脚通道资源，输出全0->全1->全0诊断，具体包括如下步骤：
步骤S51：控制所有第四类引脚通道资源输出全0，并从数据读取CPLD获取并判断是否全0；控制所有第四类引脚通道资源输出全1，并从数据读取CPLD获取并判断是否全1；控制所有第四类引脚通道资源输出全0，并从数据读取CPLD获取并判断是否全0。输出全0效果如下表3所示：
  Col1 Col2 Col3 Col4 Col5 Col6 Col7 Col8 Col9 Col10 Col11 Col12 Col13
ROW1 0 0 0 0 0 0 0 0 0 0 0 0 0
ROW2 0 0 0 0 0 0 0 0 0 0 0 0 0
ROW3 0 0 0 0 0 0 VCC 0 0 0 0 0 0
ROW4 0 0 0 0 0 0 0 0 0 0 0 0 0
ROW5 0 0 0 0 0 0 0 0 0 0 0 0 0
ROW6 0 0 0 GND 0 0 0 0 0 0 0 0 0
ROW7 0 0 0 0 0 0 0 0 NC 0 0 0 0
ROW8 0 0 0 0 0 0 0 0 0 0 0 0 0
ROW9 0 0 0 0 0 0 0 0 0 0 0 0 0
ROW10 0 0 0 0 0 0 0 0 0 0 0 0 0
ROW11 0 0 0 0 0 0 0 0 0 0 0 0 0
ROW12 0 0 0 0 0 0 0 0 0 0 0 0 0
输出全1效果如下表4所示：
  Col1 Col2 Col3 Col4 Col5 Col6 Col7 Col8 Col9 Col10 Col11 Col12 Col13
ROW1 1 1 1 1 1 1 1 1 1 1 1 1 1
ROW2 1 1 1 1 1 1 1 1 1 1 1 1 1
ROW3 1 1 1 1 1 1 VCC 1 1 1 1 1 1
ROW4 1 1 1 1 1 1 1 1 1 1 1 1 1
ROW5 1 1 1 1 1 1 1 1 1 1 1 1 1
ROW6 1 1 1 GND 1 1 1 1 1 1 1 1 1
ROW7 1 1 1 1 1 1 1 1 NC 1 1 1 1
ROW8 1 1 1 1 1 1 1 1 1 1 1 1 1
ROW9 1 1 1 1 1 1 1 1 1 1 1 1 1
ROW10 1 1 1 1 1 1 1 1 1 1 1 1 1
ROW11 1 1 1 1 1 1 1 1 1 1 1 1 1
ROW12 1 1 1 1 1 1 1 1 1 1 1 1 1
具体的诊断结果由步骤S52体现，即对于第四类引脚通道资源，读取0->1->0，则表示第四类引脚通道资源正常；第四类引脚通道资源读取为全0，则表示第四类引脚通道资源为常低故障；第四类引脚通道资源读取为全1，第四类引脚通道资源为常高故障或断路故障。
实施例3
在本发明的实施例中，对于第四类引脚通道资源的短路等故障诊断，可以执行步骤S23，其具体包括如下步骤：
步骤S231：将Row＝1，Col＝1位置置为1，其它位置置为0；结果如下表5所示：
  Col1 Col2 Col3 Col4 Col5 Col6 Col7 Col8 Col9 Col10 Col11 Col12 Col13
ROW1 1 0 0 0 0 0 0 0 0 0 0 0 0
ROW2 0 0 0 0 0 0 0 0 0 0 0 0 0
ROW3 0 0 0 0 0 0 VCC 0 0 0 0 0 0
ROW4 0 0 0 0 0 0 0 0 0 0 0 0 0
ROW5 0 0 0 0 0 0 0 0 0 0 0 0 0
ROW6 0 0 0 GND 0 0 0 0 0 0 0 0 0
ROW7 0 0 0 0 0 0 0 0 NC 0 0 0 0
ROW8 0 0 0 0 0 0 0 0 0 0 0 0 0
ROW9 0 0 0 0 0 0 0 0 0 0 0 0 0
ROW10 0 0 0 0 0 0 0 0 0 0 0 0 0
ROW11 0 0 0 0 0 0 0 0 0 0 0 0 0
ROW12 0 0 0 0 0 0 0 0 0 0 0 0 0
步骤S232：将Row＝1，Col＝2位置置为1，其它位置置为0；结果如下 表6所示：
  Col1 Col2 Col3 Col4 Col5 Col6 Col7 Col8 Col9 Col10 Col11 Col12 Col13
ROW1 0 1 0 0 0 0 0 0 0 0 0 0 0
ROW2 0 0 0 0 0 0 0 0 0 0 0 0 0
ROW3 0 0 0 0 0 0 VCC 0 0 0 0 0 0
ROW4 0 0 0 0 0 0 0 0 0 0 0 0 0
ROW5 0 0 0 0 0 0 0 0 0 0 0 0 0
ROW6 0 0 0 GND 0 0 0 0 0 0 0 0 0
ROW7 0 0 0 0 0 0 0 0 NC 0 0 0 0
ROW8 0 0 0 0 0 0 0 0 0 0 0 0 0
ROW9 0 0 0 0 0 0 0 0 0 0 0 0 0
ROW10 0 0 0 0 0 0 0 0 0 0 0 0 0
ROW11 0 0 0 0 0 0 0 0 0 0 0 0 0
ROW12 0 0 0 0 0 0 0 0 0 0 0 0 0
步骤S233：跳过第一类引脚通道、第二类引脚通道和第三类引脚通道，依次遍历所有第四类引脚通道资源位置，即采用走步1的方式。
具体的诊断结果由步骤S33体现，即对于第四类引脚通道资源，获取并判断对应位置值与设置值一致；比较后不一致的结果值如果为0，确定该Row和Col所对应的第四类引脚通道资源存在短路故障。
实施例4
在本发明的实施例中，对于第四类引脚通道资源的短路等故障诊断，对于第四类引脚通道资源，可以执行步骤S24，其具体包括如下步骤：
步骤S241：将Row＝1，Col＝1位置置为0，其它位置置为1；结果如下表7所示：
  Col1 Col2 Col3 Col4 Col5 Col6 Col7 Col8 Col9 Col10 Col11 Col12 Col13
ROW1 0 1 1 1 1 1 1 1 1 1 1 1 1
ROW2 1 1 1 1 1 1 1 1 1 1 1 1 1
ROW3 1 1 1 1 1 1 VCC 1 1 1 1 1 1
ROW4 1 1 1 1 1 1 1 1 1 1 1 1 1
ROW5 1 1 1 1 1 1 1 1 1 1 1 1 1
ROW6 1 1 1 GND 1 1 1 1 1 1 1 1 1
ROW7 1 1 1 1 1 1 1 1 NC 1 1 1 1
ROW8 1 1 1 1 1 1 1 1 1 1 1 1 1
ROW9 1 1 1 1 1 1 1 1 1 1 1 1 1
ROW10 1 1 1 1 1 1 1 1 1 1 1 1 1
ROW11 1 1 1 1 1 1 1 1 1 1 1 1 1
ROW12 1 1 1 1 1 1 1 1 1 1 1 1 1
步骤S242：将Row＝1，Col＝2位置置为0，其它位置置为1；结果如下表8所示：
  Col1 Col2 Col3 Col4 Col5 Col6 Col7 Col8 Col9 Col10 Col11 Col12 Col13
ROW1 1 0 1 1 1 1 1 1 1 1 1 1 1
ROW2 1 1 1 1 1 1 1 1 1 1 1 1 1
ROW3 1 1 1 1 1 1 VCC 1 1 1 1 1 1
ROW4 1 1 1 1 1 1 1 1 1 1 1 1 1
ROW5 1 1 1 1 1 1 1 1 1 1 1 1 1
ROW6 1 1 1 GND 1 1 1 1 1 1 1 1 1
ROW7 1 1 1 1 1 1 1 1 NC 1 1 1 1
ROW8 1 1 1 1 1 1 1 1 1 1 1 1 1
ROW9 1 1 1 1 1 1 1 1 1 1 1 1 1
ROW10 1 1 1 1 1 1 1 1 1 1 1 1 1
ROW11 1 1 1 1 1 1 1 1 1 1 1 1 1
ROW12 1 1 1 1 1 1 1 1 1 1 1 1 1
步骤S243：跳过第一类引脚通道、第二类引脚通道和第三类引脚通道，依次遍历所有第四类引脚通道资源位置；即采用走步0的方式。
具体的诊断结果由步骤S34体现，即对于第四类引脚通道资源，获取并判断对应位置值与设置值一致；比较后不一致的结果值所在的Row和Col输出值如果为0，确定Row和Col所对应的第四类引脚通道资源存在短路故障。
步骤S34：获取并判断对应位置值与设置值一致；比较后不一致的结果值所在的Row和Col输出值如果为1，确定Row和Col所对应的第四类引脚通道资源存在短路故障或断路故障。
综上所述，本发明一种批量精确诊断cBit阵列故障的装置和方法，其通过构造cBit资源连接器的输出引脚(Pin脚)上的电势孤岛来诊断该引脚是否存在连接故障，不仅可以有效的针对大批量cBit资源连接器的连通性进行精确有效的故障诊断，还可以精确的诊断明确cBit资源连接器所在Pin脚的故障点和故障类型。
需要说明的是，上述实施例可以根据需要任意搭配使用。
以上所述的仅为本发明的优选实施例，所述实施例并非用以限制本发明的专利保护范围，因此凡是运用本发明的说明书及附图内容所作的等同结构变化，同理均应包含在本发明的保护范围内。

Claims (8)

  1. 一种批量诊断cBit阵列故障的装置，其特征在于，包括：
    cBit资源板，包括位于所述cBit资源板上的第一cBit阵列，所述第一cBit阵列为M*N阵列，其包括一个或多个连接器，所述cBit资源板上还包括写寄存器和输出控制CPLD；其中，所述M和N大于等于3；所述写寄存器具有M*N个存储单元，每一个所述存储单元对应一个所述第一cBit阵列中的一个单元；
    诊断PB板，其包括第二cBit阵列、M*N读寄存器和数据读取控制CPLD；所述第二cBit阵列为M*N阵列，所述M和N大于等于3；所述读寄存器具有M*N个存储单元，每一个所述存储单元对应一个所述第二cBit阵列中的一个单元；所述第一cBit阵列通过所述一个或多个连接器与所述第二cBit阵列相连；
    CPU处理单元，分别与所述cBit资源板和所述诊断PB板相连；
    其中，所述cBit资源板上的第一cBit阵列中的一个单元和所述诊断PB板上的第二cBit阵列中的一个单元对应相连；当对所述cBit资源板上的第一cBit阵列进行故障诊断时，所述CPU处理单元包括：
    引脚属性分类模块，用于分类所述第一cBit阵列上的每一个对外引脚的属性，并将电源引脚VCC定义为第一类引脚，接地引脚GND定义为第二类引脚，悬空引脚NC定义为第三类引脚，以及将cBit通道引脚定义为第四类引脚；
    设置模块，根据电势孤岛效应规则设置所述写寄存器中的每一个存储单元所存储的内容；所述电势孤岛效应规则为用于诊断短路故障的走步0规则和/走步1规则；
    控制模块，控制所述输出控制CPLD根据所述写寄存器中的每一个存储单元所存储的内容，驱动所述第一cBit阵列的输出；以及控制所述第二cBit阵列接收所述第一cBit阵列的输出，并通过所述读取控制CPLD将所述第二cBit阵列的输出存入到所述读寄存器中；
    判断模块，将所述写寄存器中每一个所述存储单元的值与所述读存储单元对应一个所述第二cBit阵列中的每一个所述存储单元的值进行比较，根据比较结果和所述电势孤岛效应规则，判断所述第一类引脚、所述第二类引脚 和所述第四类引脚通道的状态；其中，
    所述第一类引脚状态包括正常、常低故障或断路故障和短路故障；
    所述第二类引脚状态包括正常、常高故障或断路故障和短路故障；
    所述第四类引脚状态包括正常、断路故障和短路故障；
    所述第三类引脚不做判断。
  2. 根据权利要求1所述的批量诊断cBit阵列故障的装置，其特征在于，还包括驱动单元，所述cBit驱动单元为M*N阵列，所述cBit驱动单元中的每一个通道的输入端与所述述第一cBit阵列中的一个单元相连，所述cBit驱动单元中的每一个通道的输出端与所述第二cBit阵列中的一个单元相连。
  3. 根据权利要求2所述的批量诊断cBit阵列故障的装置，其特征在于，所述cBit驱动单元为cBit驱动器件ULN2003。
  4. 一种采用所述权利要求1所述的批量诊断cBit阵列故障的装置的诊断方法，其特征在于，包括如下步骤：
    步骤S1：分类所述第一cBit阵列上的每一个对外引脚的属性，并将电源引脚VCC定义为第一类引脚，接地引脚GND定义为第二类引脚，悬空引脚NC定义为第三类引脚，以及将cBit通道引脚定义为第四类引脚；
    步骤S2：根据电势孤岛效应规则设置所述写寄存器中的每一个存储单元所存储的内容；所述电势孤岛效应规则为用于至少诊断短路故障的走步0规则和/或走步1规则；
    步骤S3：控制所述输出控制CPLD根据所述写寄存器中的每一个存储单元所存储的内容，驱动所述第一cBit阵列的输出；以及控制所述第二cBit阵列接收所述第一cBit阵列的输出，并通过所述读取控制CPLD将所述第二cBit阵列的输出存入到所述读寄存器中；
    步骤S4：将所述写寄存器中每一个所述存储单元的值与所述读存储单元对应一个所述第二cBit阵列中的每一个所述存储单元的值进行比较，根据比较结果和所述电势孤岛效应规则，判断所述第一类引脚、所述第二类引脚和所述第四类引脚通道的状态；其中，
    所述第一类引脚状态包括正常、常低故障或断路故障和短路故障；
    所述第二类引脚状态包括正常、常高故障或断路故障和短路故障；
    所述第四类引脚状态包括正常、断路故障和短路故障；
    所述第三类引脚不做判断。
  5. 根据权利要求4所述的诊断方法，其特征在于，所述步骤S2具体包括步骤S21、步骤S22、步骤S23和步骤S24；其中，所述步骤S21和步骤S22按任意顺序进行，所述步骤S23和所述步骤S24按任意顺序进行，所述步骤S23和所述步骤S24在所述步骤S21和步骤S22执行完成后执行；
    步骤S21：对于第一类引脚通道资源，所述电源引脚VCC的电平不变化，通过改变其周边通道的电平输出全0->全1->全0，即采用电平脉冲矩阵法来诊断所述电源引脚VCC通道资源的故障；
    步骤S22：对于第二类引脚通道资源，所述接地引脚GND的电平不变化，通过改变其周边通道的电平输出全0->全1->全0，即采用电平脉冲矩阵法来诊断所述接地引脚GND通道资源的故障；
    步骤S23：对于第四类引脚通道资源，执行如下步骤：
    步骤S231：将Row＝1，Col＝1位置置为1，其它位置置为0；
    步骤S232：将Row＝1，Col＝2位置置为1，其它位置置为0；
    步骤S233：跳过第一类引脚通道、第二类引脚通道和第三类引脚通道，依次遍历所有所述第四类引脚通道资源位置，即采用走步1的方式；
    步骤S24：对于第四类引脚通道资源，执行如下步骤：
    步骤S241：将Row＝1，Col＝1位置置为0，其它位置置为1；
    步骤S242：将Row＝1，Col＝2位置置为0，其它位置置为1；
    步骤S243：跳过第一类引脚通道、第二类引脚通道和第三类引脚通道，依次遍历所有所述第四类引脚通道资源位置；即采用走步0的方式。
  6. 根据权利要求5所述的诊断方法，其特征在于，所述步骤S3具体包括如下步骤：
    步骤S31：对于第一类引脚通道资源，所述电源引脚VCC通道对应位置所述读存储器中的单元读取值始终为1，表示该通道正常；所述电源引脚VCC通道对应位置读取值始终为0，表示所述通道常低故障或断路故障；所述电源引脚通道对应位置读取值0->1->0，表示所述通道短路故障；
    步骤S32：对于第二类引脚通道资源，所述接地引脚GND通道对应位 置所述读存储器中的单元读取值始终为0，表示该通道正常；所述接地引脚GND通道对应位置读取值始终为1，表示所述通道常高故障或断路故障；所述电源引脚通道对应位置读取值1->0->1，表示所述通道短路故障；
    步骤S33：对于第四类引脚通道资源，获取并判断对应位置值与设置值一致；比较后不一致的结果值所在的Row和Col输出值如果为0，确定所述Row和Col所对应的所述第四类引脚通道资源存在短路故障；
    步骤S34：获取并判断对应位置值与设置值一致；比较后不一致的结果值所在的Row和Col输出值如果为1，确定所述Row和Col所对应的所述第四类引脚通道资源存在短路故障或断路故障。
  7. 根据权利要求6所述的诊断方法，其特征在于，还包括：在步骤S31还包括如果第一类引脚通道资源中具有短路故障、通道常低故障或断路故障，需先排除并解决故障；在步骤S32还包括如果第二类引脚通道资源中具有短路故障、通道常高故障或断路故障，需先排除并解决故障。
  8. 根据权利要求4所述的诊断方法，其特征在于，还包括步骤S5：对于第四类引脚通道资源，输出全0->全1->全0诊断，具体包括如下步骤：
    步骤S51：控制所有第四类引脚通道资源输出全0，并从所述数据读取CPLD获取并判断是否全0；控制所有第四类引脚通道资源输出全1，并从所述数据读取CPLD获取并判断是否全1；控制所有第四类引脚通道资源输出全0，并从所述数据读取CPLD获取并判断是否全0；
    步骤S52：对于第四类引脚通道资源，依次读取0->1->0，则表示所述第四类引脚通道资源正常；所述第四类引脚通道资源读取为全0，则表示所述第四类引脚通道资源为常低故障；所述第四类引脚通道资源读取为全1，所述第四类引脚通道资源为常高故障或断路故障。
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