WO2021120223A1 - 数据发送单元、数据接收单元、数据发送方法及接收方法 - Google Patents

数据发送单元、数据接收单元、数据发送方法及接收方法 Download PDF

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Publication number
WO2021120223A1
WO2021120223A1 PCT/CN2019/127199 CN2019127199W WO2021120223A1 WO 2021120223 A1 WO2021120223 A1 WO 2021120223A1 CN 2019127199 W CN2019127199 W CN 2019127199W WO 2021120223 A1 WO2021120223 A1 WO 2021120223A1
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Prior art keywords
data
unit
packet header
module
data unit
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PCT/CN2019/127199
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English (en)
French (fr)
Inventor
罗林
张广宇
左文明
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华为技术有限公司
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Priority to PCT/CN2019/127199 priority Critical patent/WO2021120223A1/zh
Priority to CN201980102236.7A priority patent/CN114730297A/zh
Publication of WO2021120223A1 publication Critical patent/WO2021120223A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction

Definitions

  • This application relates to the field of communication technology, and in particular to a data sending unit, a data receiving unit, a data transmission system, an electronic device, a data sending method, and a data receiving method.
  • the MIPI physical layer MPHY (MIPI Physical Layer, MPHY) in the MIPI UFS protocol uses 8B/10B encoding.
  • This encoding method encodes 8bit effective data into 10bit data blocks, and the effective data in the encoded 10bit data blocks is only 8/10, that is, 80%, so the encoding efficiency of 8B/10B encoding is low.
  • the encoding method in the prior art has 64B/66B encoding, and the encoding efficiency of this encoding method is 96.97%, which can better solve the encoding efficiency problem.
  • the effective data of a data unit of this encoding method is 64 bits
  • the data bit width of a protocol data unit (Protocol Data Unit, PDU) of MPHY in the current MIPI UFS 3.0 protocol is 16 bits
  • the data bit width of RMMI is 40bit. If this encoding method is adopted, the package circuit needs to be modified on the basis of the existing MIPI UFS protocol.
  • the clock generation circuit of the transmitter needs to be modified, and the clock data recovery circuit (Clock data recovery circuit) of the receiver needs to be modified. Data Recovery, CDR) etc. Therefore, the 64B/66B encoding scheme has a relatively large amount of modification compared to the existing 8B/10B encoding scheme, so the encoding method cannot be better compatible with the existing protocol specifications.
  • the encoding method in the prior art also has 128B/130B encoding, and the encoding efficiency of this encoding method is 98.46%.
  • this coding method is adopted, the existing design also needs to be greatly modified, so the coding method cannot be better compatible with the existing protocol specifications.
  • This application provides a data sending unit, a data receiving unit, a data transmission system, an electronic device, a data sending method, and a data receiving method, which not only can effectively improve the coding efficiency, but also can be better compatible with existing protocol standards.
  • the first aspect of the embodiments of the present application provides a data sending unit, including an encoding module and a sending module, the encoding module is connected to the sending module, and the data sending unit transmits data based on the MIPI UFS protocol; the encoding The module is used to convert the data unit to be sent into a data block; wherein the size of the data unit is 16 bits, and the size of the data block is 17 bits or 18 bits or 19 bits; the sending module is used to send the data blocks.
  • the data bit width of a protocol data unit PDU of the MPHY in the MIPI UFS 3.0 protocol is 16 bits
  • the data bit width of the interface RMMI specified in the existing protocol is 40 bits.
  • the coding efficiency of the 16B/17B coding method is 94.12%.
  • the coding efficiency of the 16B/18B coding method is 88.89%.
  • the coding efficiency of the 16B/19B coding method is 84.21%.
  • the coding efficiency of each of the above coding methods is higher than that of 8B/10B coding.
  • the effective data of a data unit in each of the above encoding methods is 16 bits, which conforms to the data bit width of a protocol data unit PDU of MPHY in the current MIPI UFS 3.0 protocol, and conforms to the data bit width of the interface RMMI specified in the existing protocol. Therefore, the new coding method provided by this solution can effectively improve coding efficiency while being compatible with the existing MIPI UFS 3.0 protocol.
  • the data block includes the data unit and a packet header, and the packet header is used to indicate the type of the data unit.
  • the packet header is used to indicate the type of the data unit.
  • One of them is PA_PDU with only valid data data symbol. In other words, only valid data is included in the PA_PDU.
  • the other is the CTRL_PDU containing the control data symbol.
  • CTRL_PDU is the control Symbol specified by the protocol.
  • the packet header may be located at the highest bit of the data block; or, the packet header may be located at the lowest bit of the data block.
  • the size of the header is 1 bit; when the size of the data block is 18 bits, the size of the header is 2 bits; when the size of the data block is 19 bits, the size of the header is 2 bits; The size of the header is 3 bits.
  • the packet header When the size of the packet header is 1 bit, if the value of the packet header is the first value, the packet header is used to indicate that the type of the data unit is PA-PDU; if the value of the packet header is the second value Value, the packet header is used to indicate that the type of the data unit is CTRL-PDU.
  • the aforementioned first value may be 0 or 1.
  • the above-mentioned second value may also be 0 or 1. Among them, the first value and the second value are different.
  • the value of the packet header can be 00, 01, 10, 11, etc.
  • the value of the packet header is 01 or 10.
  • different values of the packet header respectively indicate different types of data units. If the value of the packet header is 01, the packet header is used to indicate that the type of the data unit is CTRL-PDU. When the value of the packet header is 10, the packet header is used to indicate that the type of the data unit is PA-PDU. Alternatively, when the value of the packet header is 01, the packet header is used to indicate that the type of the data unit is PA-PDU. When the value of the packet header is 10, the packet header is used to indicate that the type of the data unit is CTRL-PDU.
  • the value of the packet header may be 000, 001, 010, 011, 100, 101, 110, 111, etc.
  • the value of the packet header is 010,101.
  • different values of the packet header respectively indicate different types of data units.
  • the data sending unit also includes a data serialization module, and the output end of the data serialization module is connected to the input end of the encoding module; wherein, the data serialization module is used to transmit the
  • the data unit is converted into a serialized data unit; the encoding module is specifically configured to convert the serialized data unit into the data block.
  • the data sending unit further includes a scrambling module, the input terminal of the scrambling module is connected to the output terminal of the data serialization module, and the output terminal of the scrambling module is connected to the input terminal of the encoding module. Connection; wherein the scrambling module is used to scramble the serialized data unit to obtain a scrambled data unit; the encoding module is specifically used to transform the scrambled data unit Is the data block.
  • a second aspect of the embodiments of the present application provides a data receiving unit, including a receiving module and a decoding module, the receiving module is connected to the decoding module, and the data receiving unit receives data based on the MIPI UFS protocol; the decoding The module is used to convert the data block received by the receiving module into a data unit; wherein the size of the data unit is 16 bits, and the size of the data block is 17 bits or 18 bits or 19 bits.
  • the data block includes the data unit and a packet header, and the packet header is used to indicate the type of the data unit.
  • the packet header is used to indicate the type of the data unit.
  • One of them is PA_PDU with only valid data data symbol. In other words, only valid data is included in the PA_PDU.
  • the other is the CTRL_PDU containing the control data symbol.
  • CTRL_PDU is the control Symbol specified by the protocol.
  • the packet header is located at the highest bit of the data block; or, the packet header is located at the lowest bit of the data block.
  • the size of the header is 1 bit; when the size of the data block is 18 bits, the size of the header is 2 bits; when the size of the data block is 19 bits, the size of the header is 2 bits; The size of the header is 3 bits.
  • the packet header When the size of the packet header is 1 bit, if the value of the packet header is the first value, the packet header is used to indicate that the type of the data unit is PA-PDU; if the value of the packet header is the second value Value, the packet header is used to indicate that the type of the data unit is CTRL-PDU.
  • the aforementioned first value may be 0 or 1.
  • the above-mentioned second value may also be 0 or 1. Among them, the first value and the second value are different.
  • the value of the packet header can be 00, 01, 10, 11, etc.
  • the value of the packet header is 01 or 10.
  • different values of the packet header respectively indicate different types of data units. If the value of the packet header is 01, the packet header is used to indicate that the type of the data unit is CTRL-PDU. When the value of the packet header is 10, the packet header is used to indicate that the type of the data unit is PA-PDU. Alternatively, when the value of the packet header is 01, the packet header is used to indicate that the type of the data unit is PA-PDU. When the value of the packet header is 10, the packet header is used to indicate that the type of the data unit is CTRL-PDU.
  • the value of the packet header may be 000, 001, 010, 011, 100, 101, 110, 111, etc.
  • the value of the packet header is 010,101.
  • different values of the packet header respectively indicate different types of data units.
  • the data receiving unit further includes a data parallelization module, and the output terminal of the decoding module is connected to the input terminal of the data parallelization module; wherein, the data parallelization module is used to transform the data unit It is a parallelized data unit.
  • the data receiving unit further includes a descrambling module, the input of the descrambling module is connected to the output of the decoding module, and the output of the descrambling module is connected to the input of the data parallelization module Connection; wherein, the descrambling module is used to descramble the data unit to obtain a descrambled data unit; the data parallelization module is specifically used to convert the descrambled data unit into parallel Data unit.
  • a third aspect of the embodiments of the present application provides a data transmission system, including the data sending unit and/or the data receiving unit.
  • the fourth aspect of the embodiments of the present application provides an electronic device, including the data transmission system described above.
  • the fifth aspect of the embodiments of the present application provides a data sending method, including:
  • the data unit Convert the data unit to be sent into a data block; wherein the size of the data unit is 16bit, the size of the data block is 17bit or 18bit or 19bit, and the data unit is the MIPI physical layer MPHY protocol in the MIPI UFS protocol Data unit PDU;
  • the above-mentioned sending of the data block is based on the MIPI UFS protocol for data sending.
  • a sixth aspect of the embodiments of the present application provides a data receiving method, including:
  • the received data block into a data unit; wherein the size of the data unit is 16bit, the size of the data block is 17bit or 18bit or 19bit, and the data unit is the MIPI physical layer MPHY in the MIPI UFS protocol Protocol data unit PDU.
  • Fig. 1 is a schematic diagram of a data transmission system applied in the MIPI UFS protocol provided by an embodiment of the present application;
  • FIG. 2 is a schematic diagram of a data sending unit provided by an embodiment of the present application.
  • 3 to 6 are respectively schematic diagrams of the packet header located at the highest bit of the data block provided by the embodiments of the present application.
  • FIGS 7-10 are schematic diagrams of the packet header located at the lowest bit of the data block provided by the embodiments of the present application.
  • FIG. 11 is a schematic diagram of another data sending unit provided by an embodiment of the present application.
  • FIG. 12 is a schematic diagram of another data sending unit provided by an embodiment of the present application.
  • FIG. 13 is a schematic diagram of a data receiving unit provided by an embodiment of the present application.
  • FIG. 14 is a schematic diagram of another data receiving unit provided by an embodiment of the present application.
  • FIG. 15 is a schematic diagram of another data receiving unit provided by an embodiment of the present application.
  • MIPI UFS protocol MIPI alliance, that is, the Mobile Industry Processor Interface (MIPI) alliance.
  • MIPI UFS protocol is one of the open standard protocols for mobile universal storage initiated by the MIPI Alliance.
  • the data bit width of a protocol data unit PDU (Protocol Data Unit) of the MPHY in the MIPI UFS 3.0 protocol is 16 bits
  • the data bit width of the interface RMMI specified in the existing protocol is 40 bits.
  • UFS Universal Flash Storage Universal flash storage.
  • Protocol Data Unit Protocol data unit.
  • the data unit mentioned in the embodiment of the present application may be a protocol data unit PDU.
  • PA_PDU PHY Adapter Protocol Data Unit The protocol data unit of the physical adaptation layer.
  • CTRL_PDU Control Protocol Data Unit Control attribute protocol data unit.
  • the MIPI physical layer MPHY in the MIPI UFS protocol uses 8B/10B encoding.
  • the coding efficiency of the 8B/10B coding method is low.
  • 64B/66B encoding and 128B/130B encoding in the prior art.
  • the coding efficiency of these two coding methods is higher than that of 8B/10B coding.
  • 64B/66B encoding and 128B/130B encoding are applied in MIPI UFS protocol, both of them exceed the data bit width (16bit) of one PDU of MPHY by the protocol, and exceed the interface RMMI specified in the existing protocol. Data bit width (40bit).
  • this solution proposes a 16B/17B coding scheme to replace the existing 8B/10B coding scheme of MIPI UFS 3.0.
  • the coding efficiency of this 16B/17B coding method is 94.12%.
  • the coding efficiency is higher than that of 8B/10B coding.
  • the effective data of a data unit of this encoding method is 16 bits, which conforms to the data bit width of a protocol data unit PDU of MPHY in the current MIPI UFS 3.0 protocol, and conforms to the data bit width of the interface RMMI specified in the existing protocol. Therefore, this solution can effectively improve coding efficiency while being compatible with the existing MIPI UFS 3.0 protocol.
  • this solution also provides a 16B/18B coding solution that can replace the existing 8B/10B coding solution of MIPI UFS 3.0.
  • the coding efficiency of this 16B/18B coding method is 88.89%.
  • the coding efficiency is higher than that of 8B/10B coding.
  • the effective data of a data unit of this encoding method is 16 bits, which conforms to the data bit width of a protocol data unit PDU of MPHY in the current MIPI UFS 3.0 protocol, and conforms to the data bit width of the interface RMMI specified in the existing protocol. Therefore, this solution can effectively improve coding efficiency while being compatible with the existing MIPI UFS 3.0 protocol.
  • the embodiment of the present application also provides a 16B/19B coding scheme to replace the existing 8B/10B coding scheme of MIPI UFS 3.0.
  • the coding efficiency of this 16B/19B coding method is 84.21%.
  • the coding efficiency is higher than that of 8B/10B coding.
  • the effective data of a data unit of this encoding method is 16 bits, which conforms to the data bit width of a protocol data unit PDU of MPHY in the current MIPI UFS 3.0 protocol, and conforms to the data bit width of the interface RMMI specified in the existing protocol. Therefore, this solution can effectively improve coding efficiency while being compatible with the existing MIPI UFS 3.0 protocol.
  • FIG. 1 it is a schematic diagram of a data transmission system applied in the MIPI UFS protocol provided by an embodiment of the present application.
  • the system includes a system-on-a chip (SOC), a controller UFS host, and a device UFS device.
  • the controller UFS host is interconnected with the system-on-chip SOC through a high-speed bus interface.
  • the controller UFS Host and the device UFS Device are interconnected through a high-speed SerDes (serializer/deserializer) interface.
  • SerDes serializer/deserializer
  • the system-on-chip SOC may be a terminal chip.
  • the controller UFS host can be integrated on the application processor (AP) side of the terminal.
  • the device UFS device contains flash memory particles.
  • the flash memory particles are the final storage medium for data, such as Flash.
  • the UFS device can be a memory card or an embedded large-capacity device. Among them, the UFS device includes multiple logical units, logical units and device management units.
  • the device management unit manages the power supply and other aspects of the device, while the logic unit is related to control data reading and writing.
  • the device UFS device is usually used in the terminal device as a storage device.
  • terminal devices such as smart phones, bracelets, and smart watches.
  • the controller UFS host and the device UFS device both adopt the MIPI UFS protocol.
  • the controller UFS host is used to group and unpack the data transmitted from the system-on-chip SOC or the data to be sent to the system-on-chip SOC.
  • the data is transmitted from the SOC to the controller UFS host through the high-speed bus interface.
  • the controller UFS Host performs packet processing on the data.
  • the data packet processing may include encoding processing and the like.
  • the controller UFS host sends the processed data to the UFS device via the high-speed SerDes interface.
  • UFS device decodes the received data, etc.
  • the UFS device stores the processed data in the flash memory particles of the UFS device. For example, UFS device stores the processed data in Flash.
  • the UFS device When the SOC needs to read data, the UFS device performs packet processing on the data. For example, UFS device encodes data and so on. Then the UFS device transmits the processed data to the controller UFS host through the high-speed SerDes interface. The controller UFS Host performs packet processing on the data. Such as decoding processing and so on. Then the controller UFS Host sends the processed data to the SOC via the high-speed bus interface.
  • the above-mentioned controller UFS host can be used as the sending end to send data, and the device UFS device can be used as the receiving end to receive data.
  • the above-mentioned device UFS device can also be used as a sending end to send data, and the controller UFS host can also be used as a receiving end to receive data.
  • the data sending unit includes an encoding module and a sending module, and the encoding module is connected to the sending module.
  • the encoding module is used to convert the data unit to be sent into a data block.
  • the sending module is used to send the data block.
  • the above-mentioned data sending unit realizes data sending based on the MIPI UFS protocol.
  • the size of the data unit is 16 bits.
  • the size of the data block is 17 bits. That is to say, the coding module provided by the embodiment of the present application adopts the 16B/17B coding mode.
  • the encoding module converts a 16-bit data unit into a 17-bit data block.
  • the data block includes the data unit and also includes a packet header.
  • the size of the packet header is 1 bit. As shown in FIG. 3 to FIG. 6, the packet header may be located at the highest bit of the data block. Optionally, as shown in FIG. 7 to FIG. 10, the packet header may also be located at the lowest bit of the data block. This solution does not specifically limit the location of Baotou.
  • the packet header is used to indicate the type of the data unit.
  • the other is the CTRL_PDU containing the control data symbol.
  • CTRL_PDU is the control Symbol specified by the protocol.
  • the control data Symbol may include Marker0 (MK0), Marker1 (MK1), Marker2 (MK2), Marker3 (MK3), Marker4 (MK4), FILLER (FLR), etc.
  • CTRL_PDU composed of these control symbols can include ⁇ MK0,PA_PDU[7:0]>, ⁇ MK0,MK1>, ⁇ MK0,FLR>, ⁇ MK2,MK2>, ⁇ FLR,FLR>, etc.
  • the value of the header can be 0.
  • the value of the packet header may also be 1.
  • the packet header is used to indicate that the type of the data unit is PA-PDU.
  • the packet header is used to indicate that the type of the data unit is CTRL-PDU, as shown in FIGS. 4 and 8.
  • the packet header is used to indicate that the type of the data unit is CTRL-PDU.
  • the packet header is used to indicate that the type of the data unit is PA-PDU, as shown in FIG. 5 and FIG. 9.
  • the data sending unit provided in the embodiment of the present application may be located in the controller UFS host as shown in FIG. 1.
  • the controller UFS host may include the data sending unit.
  • the data sending unit provided in this application may also be located in the UFS device shown in FIG. 1.
  • the UFS device can include the data sending unit.
  • the data sending unit that adopts the MIPI UFS protocol provided in the embodiment of the present application transmits data by adopting a 16B/17B encoding method. Its coding efficiency is 94.12%. The coding efficiency is higher than that of 8B/10B coding in the prior art.
  • the effective data of a data unit of this encoding method is 16 bits, which conforms to the data bit width of a protocol data unit PDU of MPHY in the current MIPI UFS 3.0 protocol, and conforms to the data bit width of the interface RMMI specified in the existing protocol. Therefore, this solution can effectively improve coding efficiency while being compatible with the existing MIPI UFS 3.0 protocol.
  • this solution uses a 16-bit data unit plus a 1-bit packet header to encode a 17-bit data block.
  • the packet header can be used to indicate the type of the data unit, which is very intuitive.
  • FIG. 11 is a schematic diagram of another data sending unit provided in an embodiment of the present application.
  • the data sending unit includes an encoding module and a sending module.
  • the data sending unit also includes a data serialization module.
  • the output terminal of the data serialization module is connected with the input terminal of the encoding module.
  • the encoding module is connected to the sending module.
  • the data serialization module is used to convert the data unit to be sent into a serialized data unit.
  • the hardware interface is simple and the interface ports are few.
  • the encoding module is used to convert the serialized data unit into the data block.
  • the sending module is used to send the data block.
  • the data sending unit adopts the MIPI UFS protocol.
  • the size of the data unit is 16 bits.
  • the size of the data block is 17 bits.
  • the data block includes the data unit and also includes a packet header.
  • the size of the packet header is 1 bit. As shown in FIG. 3 to FIG. 6, the packet header may be located at the highest bit of the data block. Optionally, as shown in FIG. 7 to FIG. 10, the packet header may also be located at the lowest bit of the data block. This solution does not specifically limit the location of Baotou.
  • the data serialization module can serialize the parallel data to be sent.
  • the data serialization module converts multi-bit data into single-bit serial data for transmission and sends to the encoding module.
  • the encoding module encodes the received serial data according to 16 bits as the data unit to obtain a 17-bit data block.
  • the encoding module sends the data block to the sending module for data sending.
  • the data sending unit provided in this embodiment may be located in the controller UFS host as shown in FIG. 1.
  • the controller UFS host may include the data sending unit.
  • the data sending unit provided in this application may also be located in the UFS device shown in FIG. 1.
  • the device UFS device may include the data sending unit.
  • the data sending unit provided in the embodiment of the present application sends data by adopting a 16B/17B encoding method. Its coding efficiency is 94.12%. The coding efficiency is higher than that of 8B/10B coding in the prior art.
  • the effective data of a data unit of this encoding method is 16 bits, which conforms to the data bit width of a protocol data unit PDU of MPHY in the current MIPI UFS 3.0 protocol, and conforms to the data bit width of the interface RMMI specified in the existing protocol. Therefore, this solution can effectively improve coding efficiency while being compatible with the existing MIPI UFS 3.0 protocol.
  • transition density TD Transition Density
  • the DC balance means that the number of 0 and 1 in the encoded data block are as equal as possible. DC balance can effectively avoid problems caused by unstable voltages at both ends of the transceiver.
  • the transition density TD represents the density of 0 to 1 or 1 to 0 transition edges in the serial data sent. The higher the value of TD, the more conducive to the clock data recovery at the receiving end.
  • FIG. 12 is a schematic diagram of another data sending unit provided in an embodiment of the present application.
  • the data sending unit includes a data serialization module, an encoding module, and a sending module.
  • the data sending unit also includes a scrambling module.
  • the input terminal of the scrambling module is connected with the output terminal of the data serialization module, and the output terminal of the scrambling module is connected with the input terminal of the encoding module.
  • the encoding module is connected to the sending module.
  • the data serialization module is used to convert the data unit to be sent into a serialized data unit.
  • the scrambling module is used for scrambling the serialized data unit to obtain a scrambled data unit.
  • the encoding module is used to convert the scrambled data unit into a data block.
  • the sending module is used to send the data block.
  • the data sending unit adopts the MIPI UFS protocol.
  • the size of the data unit is 16 bits.
  • the size of the data block is 17 bits.
  • the data block includes the data unit and also includes a packet header.
  • the size of the packet header is 1 bit. As shown in FIG. 3 to FIG. 6, the packet header may be located at the highest bit of the data block. Optionally, as shown in FIG. 7 to FIG. 10, the packet header may also be located at the lowest bit of the data block. This solution does not specifically limit the location of Baotou.
  • the data serialization module can serialize the parallel data to be sent.
  • the data serialization module converts multi-bit parallel data into single-bit serial data for transmission and sends to the scrambling module.
  • the scrambling module scrambles the received serial data.
  • the scrambling module sends the scrambled data to the encoding module.
  • the encoding module converts the scrambled data into 17-bit data blocks.
  • the data sending unit provided in this embodiment may be located in the controller UFS host as shown in FIG. 1.
  • the controller UFS host may include the data sending unit.
  • the data sending unit provided in this application may also be located in the UFS device shown in FIG. 1.
  • the device UFS device may include the data sending unit.
  • the scrambling module may include 16 D trigger registers such as D0, D1, ... D15.
  • the scrambling module also includes 16 XOR gates. Wherein, the first input terminal of each XOR gate is respectively connected with the corresponding input data stream. The first output terminal of each D trigger register is respectively connected to the second input terminal of each XOR gate. In other words, a D trigger register is connected to an XOR gate. The second input terminal of each XOR gate is respectively connected to the first output terminal of the corresponding D trigger register.
  • the above-mentioned 16 D trigger registers plus XOR gates form a linear feedback shift register (LFSR).
  • the linear feedback shift register is the scrambling code stream generating circuit.
  • G(X) represents the scrambling code stream generated by LFSR. Seed represents the initial value of the scrambled code stream.
  • the input data stream (16bit PDU) sent to the scrambling module after serial conversion by the data serialization module is XORed with the scrambling code stream (in 16bit units) to complete the input data unit Scrambled.
  • the current MIPI UFS agreement stipulates that the UFS high-speed data transmission channel supports 4 lanes. Therefore, one lane, two lanes, three lanes, or four lanes can be used in practical applications. If all 4 lanes are used, the data of the 4 lanes need to be scrambled separately. Therefore, 4 identical LFSR circuits are required to generate the scrambled code stream. Among them, in order to prevent the signal interference between the 4 lanes, the initial value Seed of the scrambling code stream of the 4 LFSRs needs to be different.
  • the Seed value corresponding to each lane can be expressed as: Seed of the first lane is 0x0040. The Seed of the second lane is 0x0080. The Seed of the third lane is 0x00C0. The Seed of the fourth lane is 0x0100.
  • the above-mentioned scrambling module performs 16B/17B encoding by performing a scrambling process on the data and then sending the data to the encoding module.
  • the data sending unit that adopts the MIPI UFS protocol provided in the embodiment of the present application transmits data by adopting a 16B/17B encoding method. Its coding efficiency is 94.12%. The coding efficiency is higher than that of 8B/10B coding in the prior art.
  • the effective data of a data unit of this encoding method is 16 bits, which conforms to the data bit width of a protocol data unit PDU of MPHY in the current MIPI UFS 3.0 protocol, and conforms to the data bit width of the interface RMMI specified in the existing protocol. Therefore, this solution can effectively improve coding efficiency while being compatible with the existing MIPI UFS 3.0 protocol.
  • this application also provides a 16B/18B coding scheme.
  • This coding scheme can replace the aforementioned 16B/17B coding scheme.
  • the data sending unit in each of the foregoing embodiments may adopt the 16B/18B encoding mode.
  • the encoding module is used to convert the data unit to be sent into a data block.
  • the size of the data unit is 16 bits.
  • the size of the data block is 18 bits.
  • the data block includes the data unit and also includes a packet header.
  • the packet header is used to indicate the type of the data unit.
  • the size of the packet header may be 2 bits.
  • the packet header may be located at the highest bit of the data block.
  • the packet header may also be located at the lowest bit of the data block.
  • the value of the header may be 00, 01, 10, 11, etc.
  • the value of the packet header is 01 or 10.
  • different values of the packet header respectively indicate different types of data units. If the value of the packet header is 01, the packet header is used to indicate that the type of the data unit is CTRL-PDU. When the value of the packet header is 10, the packet header is used to indicate that the type of the data unit is PA-PDU. Alternatively, when the value of the packet header is 01, the packet header is used to indicate that the type of the data unit is PA-PDU. When the value of the packet header is 10, the packet header is used to indicate that the type of the data unit is CTRL-PDU.
  • the packet header is used to indicate that the type of the data unit is CTRL-PDU.
  • the data sending unit provided in this embodiment may be located in the controller UFS host as shown in FIG. 1.
  • the controller UFS host may include the data sending unit.
  • the data sending unit provided in this application may also be located in the UFS device shown in FIG. 1.
  • the device UFS device may include the data sending unit.
  • the coding efficiency of the 16B/18B coding method provided in the embodiment of the present application is 88.89%.
  • the coding efficiency is higher than that of 8B/10B coding.
  • the effective data of a data unit of this encoding method is 16 bits, which conforms to the data bit width of a protocol data unit PDU of MPHY in the current MIPI UFS 3.0 protocol, and conforms to the data bit width of the interface RMMI specified in the existing protocol. Therefore, this solution can effectively improve coding efficiency while being compatible with the existing MIPI UFS 3.0 protocol.
  • the embodiment of the present application also provides a 16B/19B coding scheme.
  • This coding scheme can replace the aforementioned 16B/17B coding scheme.
  • the data sending unit in each of the foregoing embodiments can adopt the 16B/19B encoding method.
  • the encoding module is used to convert the data unit to be sent into a data block.
  • the size of the data unit is 16 bits.
  • the size of the data block is 19 bits.
  • the data block includes the data unit and also includes a packet header.
  • the packet header is used to indicate the type of the data unit.
  • the size of the packet header may be 3 bits.
  • the packet header may be located at the highest bit of the data block.
  • the packet header may also be located at the lowest bit of the data block.
  • the value of the header may be 000, 001, 010, 011, 100, 101, 110, 111, etc.
  • the value of the packet header is 010,101.
  • different packet header values indicate different types of data units. The details can be described with reference to Figs. 3 to 10, which will not be repeated here.
  • the data sending unit provided in this embodiment may be located in the controller UFS host as shown in FIG. 1.
  • the controller UFS host may include the data sending unit.
  • the data sending unit provided in this application may also be located in the UFS device shown in FIG. 1.
  • the device UFS device may include the data sending unit.
  • the coding efficiency of the 16B/19B coding method provided in the embodiment of the present application is 84.21%.
  • the coding efficiency is higher than that of 8B/10B coding.
  • the effective data of a data unit of this encoding method is 16 bits, which conforms to the data bit width of a protocol data unit PDU of MPHY in the current MIPI UFS 3.0 protocol, and conforms to the data bit width of the interface RMMI specified in the existing protocol. Therefore, this solution can effectively improve coding efficiency while being compatible with the existing MIPI UFS 3.0 protocol.
  • the data receiving unit includes a receiving module and a decoding module.
  • the receiving module is connected to the decoding module.
  • the decoding module is used to convert the data block received by the receiving module into a data unit.
  • the above-mentioned data receiving unit adopts the MIPI UFS protocol.
  • the size of the aforementioned data unit is 16 bits.
  • the size of the data block is 17 bits.
  • the decoding module provided in the embodiment of the present application converts a 17-bit data block into a 16-bit data unit.
  • the data block includes the data unit and also includes a packet header.
  • the size of the packet header is 1 bit. As shown in FIG. 3 to FIG. 6, the packet header may be located at the highest bit of the data block. Optionally, as shown in FIG. 7 to FIG. 10, the packet header may also be located at the lowest bit of the data block. This solution does not specifically limit the location of Baotou.
  • the packet header is used to indicate the type of the data unit.
  • the other is the CTRL_PDU containing the control data symbol.
  • CTRL_PDU is the control Symbol specified by the protocol.
  • the control data Symbol may include Marker0 (MK0), Marker1 (MK1), Marker2 (MK2), Marker3 (MK3), Marker4 (MK4), FILLER (FLR), etc.
  • CTRL_PDU composed of these control symbols can include ⁇ MK0,PA_PDU[7:0]>, ⁇ MK0,MK1>, ⁇ MK0,FLR>, ⁇ MK2,MK2>, ⁇ FLR,FLR>, etc.
  • the value of the header can be 0.
  • the value of the packet header may also be 1.
  • the packet header is used to indicate that the type of the data unit is PA-PDU.
  • the packet header is used to indicate that the type of the data unit is CTRL-PDU, as shown in FIGS. 4 and 8.
  • the packet header is used to indicate that the type of the data unit is CTRL-PDU.
  • the packet header is used to indicate that the type of the data unit is PA-PDU, as shown in FIG. 5 and FIG. 9.
  • the data receiving unit provided in this embodiment may be located in the controller UFS host as shown in FIG. 1.
  • the controller UFS host may include the data receiving unit.
  • the data receiving unit provided in this application may also be located in the UFS device shown in FIG. 1.
  • the device UFS device may include the data receiving unit.
  • FIG. 14 is a schematic diagram of another data receiving unit provided in an embodiment of the present application.
  • the data receiving unit includes a receiving module and a decoding module.
  • the data receiving unit also includes a data parallelization module. Wherein, the receiving module is connected to the decoding module.
  • the output terminal of the decoding module is connected to the input terminal of the data parallelization module.
  • the decoding module is used to convert the data block received by the receiving module into a data unit.
  • the data parallelization module is used to convert the data unit into a parallelized data unit. By transforming the data unit into a parallelized data unit, it can improve the efficiency of data processing.
  • the decoding module converts the received data block with a data size of 17 bits into a 16-bit data unit.
  • the decoding module sends the decoded data unit to the data parallelization module.
  • the data parallelization module can parallelize the received data unit and convert it into parallel data.
  • the data parallelization module sends the parallel data to the UFS internal circuit module for use.
  • the data receiving unit provided in this embodiment may be located in the controller UFS host as shown in FIG. 1.
  • the controller UFS host may include the data receiving unit.
  • the data receiving unit provided in this application may also be located in the UFS device shown in FIG. 1.
  • the device UFS device may include the data receiving unit.
  • FIG. 15 is a schematic diagram of another data receiving unit provided in an embodiment of the present application.
  • the data receiving unit includes a receiving module, a decoding module, and a data parallelization module.
  • the data receiving unit also includes a descrambling module. Among them, the receiving module is connected with the decoding module.
  • the output terminal of the decoding module is connected with the input terminal of the descrambling module.
  • the output terminal of the descrambling module is connected with the input terminal of the data parallelization module.
  • the decoding module is used to convert the received data block into a data unit.
  • the descrambling module is used to descramble the data unit to obtain a descrambled data unit.
  • the data parallelization module is used to convert the descrambled data unit into a parallelized data unit.
  • the data receiving unit adopts the MIPI UFS protocol.
  • the size of the data unit is 16 bits.
  • the size of the data block is 17 bits.
  • the data block includes the data unit and also includes a packet header.
  • the size of the packet header is 1 bit.
  • the decoding module of the data receiving unit can convert the received data block with a data size of 17 bits into a 16-bit data unit.
  • the decoding module sends the decoded data unit to the descrambling module.
  • the descrambling module descrambles the received data unit.
  • the descrambling module sends the descrambled data unit to the data parallelization module, so that the data parallelization module converts the descrambled data unit into parallel data.
  • the converted parallel data can be sent to the UFS internal circuit module for use.
  • the data receiving unit provided in this embodiment may be located in the controller UFS host as shown in FIG. 1.
  • the controller UFS host may include the data receiving unit.
  • the data receiving unit provided in this application may also be located in the UFS device shown in FIG. 1.
  • the device UFS device may include the data receiving unit.
  • the above-mentioned embodiment only introduces the decoding method corresponding to the 16B/17B encoding method.
  • the embodiment of the present application also provides a decoding method corresponding to the 16B/18B encoding method.
  • the decoding method corresponding to the 16B/18B encoding method can replace the decoding method corresponding to the aforementioned 16B/17B encoding method.
  • the above-mentioned data receiving unit can adopt the decoding method corresponding to the 16B/18B encoding method.
  • the decoding module using the decoding method corresponding to the 16B/18B encoding method is used to convert the received data block into a data unit.
  • the size of the data unit is 16 bits.
  • the size of the data block is 18 bits.
  • the data block includes the data unit and also includes a packet header.
  • the packet header is used to indicate the type of the data unit.
  • the size of the packet header may be 2 bits.
  • the packet header may be located at the highest bit of the data block.
  • the packet header may also be located at the lowest bit of the data block.
  • the value of the header may be 00, 01, 10, 11, etc.
  • the value of the packet header is 01 or 10.
  • different values of the packet header respectively indicate different types of data units. If the value of the packet header is 01, the packet header is used to indicate that the type of the data unit is CTRL-PDU. When the value of the packet header is 10, the packet header is used to indicate that the type of the data unit is PA-PDU. Alternatively, when the value of the packet header is 01, the packet header is used to indicate that the type of the data unit is PA-PDU. When the value of the packet header is 10, the packet header is used to indicate that the type of the data unit is CTRL-PDU.
  • the packet header is used to indicate that the type of the data unit is CTRL-PDU.
  • the data receiving unit provided in this embodiment may be located in the controller UFS host as shown in FIG. 1.
  • the controller UFS host may include the data receiving unit.
  • the data receiving unit provided in this application may also be located in the UFS device shown in FIG. 1.
  • the device UFS device may include the data receiving unit.
  • the embodiment of the present application also provides a decoding method corresponding to the 16B/19B encoding method.
  • the decoding method corresponding to the 16B/19B encoding method can replace the decoding method corresponding to the aforementioned 16B/17B encoding method.
  • the above-mentioned data receiving unit can adopt the decoding method corresponding to the 16B/19B encoding method.
  • the decoding module using the decoding method corresponding to the 16B/19B encoding method is used to convert the received data block into a data unit.
  • the size of the data unit is 16 bits.
  • the size of the data block is 19 bits.
  • the data block includes the data unit and also includes a packet header.
  • the packet header is used to indicate the type of the data unit.
  • the size of the packet header may be 3 bits.
  • the packet header may be located at the highest bit of the data block.
  • the packet header may also be located at the lowest bit of the data block.
  • the value of the header may be 000, 001, 010, 011, 100, 101, 110, 111, etc.
  • the value of the packet header is 010,101.
  • different packet header values indicate different types of data units. The details can be described with reference to Figs. 3 to 10, which will not be repeated here.
  • the data receiving unit provided in this embodiment may be located in the controller UFS host as shown in FIG. 1.
  • the controller UFS host may include the data receiving unit.
  • the data receiving unit provided in this application may also be located in the UFS device shown in FIG. 1.
  • the device UFS device may include the data receiving unit.
  • An embodiment of the present application also provides a data transmission system, including the data sending unit and the data receiving unit.
  • An embodiment of the present application also provides an electronic device, including the data transmission system described above.
  • the electronic device can be a terminal device such as a mobile phone or a computer.
  • An embodiment of the present application also provides a data sending method, including:
  • the data unit Convert the data unit to be sent into a data block; wherein the size of the data unit is 16bit, the size of the data block is 17bit or 18bit or 19bit, and the data unit is the MIPI physical layer MPHY protocol in the MIPI UFS protocol Data unit PDU;
  • the above-mentioned sending of the data block is based on the MIPI UFS protocol for data sending.
  • the data block includes the data unit and a packet header, and the packet header is used to indicate the type of the data unit.
  • the packet header is used to indicate the type of the data unit.
  • One of them is PA_PDU with only valid data data symbol. In other words, only valid data is included in the PA_PDU.
  • the other is the CTRL_PDU containing the control data symbol.
  • CTRL_PDU is the control Symbol specified by the protocol.
  • the packet header is located at the highest bit of the data block; or, the packet header is located at the lowest bit of the data block.
  • the size of the header is 1 bit; when the size of the data block is 18 bits, the size of the header is 2 bits; when the size of the data block is 19 bits, the size of the header is 2 bits; The size of the header is 3 bits.
  • the packet header When the size of the packet header is 1 bit, if the value of the packet header is the first value, the packet header is used to indicate that the type of the data unit is PA-PDU; if the value of the packet header is the second value Value, the packet header is used to indicate that the type of the data unit is CTRL-PDU.
  • the aforementioned first value may be 0 or 1.
  • the above-mentioned second value may also be 0 or 1. Among them, the first value and the second value are different.
  • the value of the packet header can be 00, 01, 10, 11, etc.
  • the value of the packet header is 01 or 10.
  • different values of the packet header respectively indicate different types of data units. If the value of the packet header is 01, the packet header is used to indicate that the type of the data unit is CTRL-PDU. When the value of the packet header is 10, the packet header is used to indicate that the type of the data unit is PA-PDU. Alternatively, when the value of the packet header is 01, the packet header is used to indicate that the type of the data unit is PA-PDU. When the value of the packet header is 10, the packet header is used to indicate that the type of the data unit is CTRL-PDU.
  • the value of the packet header may be 000, 001, 010, 011, 100, 101, 110, 111, etc.
  • the value of the packet header is 010,101.
  • the different values of the packet header respectively indicate different types of data units.
  • said converting the data unit to be sent into a data block includes:
  • the serialized data unit is converted into the data block.
  • said converting the data unit to be sent into a data block includes:
  • the scrambled data unit is converted into the data block.
  • the coding efficiency of the 16B/17B coding method provided by the embodiment of the present application is 94.12%; the coding efficiency of the 16B/18B coding method is 88.89%; the coding efficiency of the 16B/19B coding method is 84.21%.
  • the coding efficiency of each of the above coding methods is higher than that of 8B/10B coding.
  • the effective data of a data unit in each of the above encoding methods is 16 bits, which conforms to the data bit width of a protocol data unit PDU of MPHY in the current MIPI UFS 3.0 protocol, and conforms to the data bit width of the interface RMMI specified in the existing protocol. Therefore, the new coding method provided by this solution can effectively improve coding efficiency while being compatible with the existing MIPI UFS 3.0 protocol.
  • the embodiment of the present application also provides a data receiving method, including:
  • the received data block into a data unit; wherein the size of the data unit is 16bit, the size of the data block is 17bit or 18bit or 19bit, and the data unit is the MIPI physical layer MPHY in the MIPI UFS protocol Protocol data unit PDU.
  • the data block includes the data unit and a packet header, and the packet header is used to indicate the type of the data unit.
  • the packet header is used to indicate the type of the data unit.
  • One of them is PA_PDU with only valid data data symbol. In other words, only valid data is included in the PA_PDU.
  • the other is the CTRL_PDU containing the control data symbol.
  • CTRL_PDU is the control Symbol specified by the protocol.
  • the packet header is located at the highest bit of the data block; or, the packet header is located at the lowest bit of the data block.
  • the size of the header is 1 bit; when the size of the data block is 18 bits, the size of the header is 2 bits; when the size of the data block is 19 bits, the size of the header is 2 bits; The size of the header is 3 bits.
  • the packet header When the size of the packet header is 1 bit, if the value of the packet header is the first value, the packet header is used to indicate that the type of the data unit is PA-PDU; if the value of the packet header is the second value Value, the packet header is used to indicate that the type of the data unit is CTRL-PDU.
  • the aforementioned first value may be 0 or 1.
  • the above-mentioned second value may also be 0 or 1. Among them, the first value and the second value are different.
  • the value of the packet header can be 00, 01, 10, 11, etc.
  • the value of the packet header is 01 or 10.
  • different values of the packet header respectively indicate different types of data units. If the value of the packet header is 01, the packet header is used to indicate that the type of the data unit is CTRL-PDU. When the value of the packet header is 10, the packet header is used to indicate that the type of the data unit is PA-PDU. Alternatively, when the value of the packet header is 01, the packet header is used to indicate that the type of the data unit is PA-PDU. When the value of the packet header is 10, the packet header is used to indicate that the type of the data unit is CTRL-PDU.
  • the value of the packet header may be 000, 001, 010, 011, 100, 101, 110, 111, etc.
  • the value of the packet header is 010,101.
  • different values of the packet header respectively indicate different types of data units.
  • the method further includes:
  • the data unit is transformed into a parallelized data unit.
  • said converting the data unit into a parallelized data unit includes:
  • the descrambled data unit is converted into a parallelized data unit.
  • the computer program product includes one or more computer instructions.
  • the computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices.
  • the computer instructions may be stored in a computer-readable storage medium or transmitted through the computer-readable storage medium.
  • the computer instructions can be sent from one website site, computer, server, or data center to another website site, computer, or data center via wired (e.g.
  • the computer-readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server or a data center integrated with one or more available media.
  • the usable medium may be a magnetic medium (for example, a floppy disk, a hard disk, and a magnetic tape), an optical medium (for example, a DVD), or a semiconductor medium (for example, a solid state disk (SSD)).
  • the process can be completed by a computer program instructing relevant hardware.
  • the program can be stored in a computer readable storage medium. , May include the processes of the above-mentioned method embodiments.
  • the aforementioned storage media include: ROM or random storage RAM, magnetic disks or optical disks and other media that can store program codes.

Abstract

本申请实施例公开了一种数据发送单元、数据接收单元、数据传输系统及电子设备，所述数据发送单元包括：包括编码模块和发送模块，所述编码模块与所述发送模块连接，其特征在于，所述数据发送单元基于MIPI UFS协议进行数据发送；所述编码模块用于将待发送的数据单元转化为数据块；其中，所述数据单元的大小为16bit，所述数据块的大小为17bit或18bit或19bit；所述发送模块用于发送所述数据块。采用上述实施例，不仅能够有效提升编码效率，而且也能较好的兼容现有协议标准。

Description

数据发送单元、数据接收单元、数据发送方法及接收方法 技术领域
本申请涉及通信技术领域，尤其涉及一种数据发送单元、数据接收单元、数据传输系统、电子设备、数据发送方法及数据接收方法。
背景技术
目前MIPI UFS协议中MIPI物理层MPHY(MIPI Physical Layer，MPHY)采用的是8B/10B编码。该编码方式将8bit的有效数据编码成10bit的数据块，而编码后的10bit数据块中有效数据只有8/10，也即80％，所以8B/10B编码的编码效率较低。
现有技术中的编码方式有64B/66B编码，该编码方式编码效率为96.97％，能比较好的解决编码效率问题。然而，该编码方式的一个数据单元的有效数据是64bit，而目前MIPI UFS 3.0协议中MPHY的一个协议数据单元(Protocol Data Unit，PDU)的数据位宽是16bit，并且现有协议中规定的接口RMMI的数据位宽是40bit，如果采用该编码方式，则在现有MIPI UFS协议的基础上需要修改组包电路，同时需要修改发送端时钟产生电路，以及需要修改接收端的时钟数据恢复电路(Clock Data Recovery，CDR)等。所以采用64B/66B编码方案相对于现有的8B/10B编码方案修改量比较大，因此该编码方式不能比较好的兼容现有的协议规范。
现有技术中的编码方式还有128B/130B编码，该编码方式编码效率为98.46％。同样的，如果采用该编码方式，也需要对现有的设计进行较大修改，所以该编码方式也不能比较好的兼容现有的协议规范。
发明内容
本申请提供了一种数据发送单元、数据接收单元、数据传输系统、电子设备、数据发送方法及数据接收方法，不仅能够有效提升编码效率，而且也能较好的兼容现有协议标准。
本申请实施例的第一方面提供了一种数据发送单元，包括编码模块和发送模块，所述编码模块与所述发送模块连接，所述数据发送单元基于MIPI UFS协议进行数据发送；所述编码模块用于将待发送的数据单元转化为数据块；其中，所述数据单元的大小为16bit，所述数据块的大小为17bit或18bit或19bit；所述发送模块用于发送所述数据块。
目前MIPI UFS 3.0协议中MPHY的一个协议数据单元PDU的数据位宽是16bit，并且现有协议中规定的接口RMMI的数据位宽是40bit。采用16B/17B的编码方式的编码效率为94.12％。采用16B/18B的编码方式的编码效率为88.89％。采用16B/19B的编码方式的编码效率为84.21％。上述各编码方式的编码效率均高于8B/10B编码的编码效率。上述各编码方式的一个数据单元的有效数据为16bit，符合目前MIPI UFS 3.0协议中MPHY的一个协议数据单元PDU的数据位宽16bit，且符合现有协议中规定的接口RMMI的数据位宽。因此，本方案提供的新的编码方式能够在兼容现有MIPI UFS 3.0协议基础上同时有效提升编码效率。
其中，所述数据块包括所述数据单元和包头，所述包头用于指示所述数据单元的类型。 其中，数据单元的类型包含两种。其中一种是只有有效数据data symbol的PA_PDU。也就是说，PA_PDU中仅包含有效数据。另一种是含有控制数据symbol的CTRL_PDU。其中，CTRL_PDU是协议规定的控制Symbol。
所述包头可位于所述数据块的最高位；或者，所述包头位于所述数据块的最低位。
其中，当所述数据块的大小为17bit时，所述包头的大小为1bit；当数据块的大小为18bit时，所述包头的大小为2bit；当所述数据块的大小为19bit时，所述包头的大小为3bit。
当所述包头的大小为1bit时，若所述包头的取值为第一值时，所述包头用于指示所述数据单元的类型为PA-PDU；若所述包头的取值为第二值，所述包头用于指示所述数据单元的类型为CTRL-PDU。上述第一值可以为0或者1。上述第二值也可以为0或者1。其中，第一值和第二值不同。
当包头的大小可为2bit时，包头的取值可以为00,01,10,11等。优选的，所述包头的取值为01，或者10。其中，包头的不同取值分别指示不同的数据单元的类型。如所述包头的取值为01时，所述包头用于指示所述数据单元的类型为CTRL-PDU。当所述包头的取值为10时，所述包头用于指示所述数据单元的类型为PA-PDU。可替代的，当所述包头的取值为01时，所述包头用于指示所述数据单元的类型为PA-PDU。当所述包头的取值为10时，所述包头用于指示所述数据单元的类型为CTRL-PDU。
当包头的大小为3bit时，所述包头的取值可以为000,001,010,011,100,101,110,111等。优选的，所述包头的取值为010,101。其中，包头的不同取值分别指示不同的数据单元的类型。
所述数据发送单元还包括数据串行化模块，所述数据串行化模块的输出端与所述编码模块的输入端连接；其中，所述数据串行化模块用于将所述待发送的数据单元转化为串行化的数据单元；所述编码模块具体用于将所述串行化的数据单元转化为所述数据块。
进一步，所述数据发送单元还包括加扰模块，所述加扰模块的输入端与所述数据串行化模块的输出端连接，所述加扰模块的输出端与所述编码模块的输入端连接；其中，所述加扰模块用于对所述串行化的数据单元进行加扰，以得到加扰后的数据单元；所述编码模块具体用于将所述加扰后的数据单元转化为所述数据块。
本申请实施例的第二方面提供了一种数据接收单元，包括接收模块和解码模块，所述接收模块与所述解码模块连接，所述数据接收单元基于MIPI UFS协议进行数据接收；所述解码模块用于将所述接收模块接收的数据块转化为数据单元；其中，所述数据单元的大小为16bit，所述数据块的大小为17bit或18bit或19bit。
所述数据块包括所述数据单元和包头，所述包头用于指示所述数据单元的类型。其中，数据单元的类型包含两种。其中一种是只有有效数据data symbol的PA_PDU。也就是说，PA_PDU中仅包含有效数据。另一种是含有控制数据symbol的CTRL_PDU。其中，CTRL_PDU是协议规定的控制Symbol。
其中，所述包头位于所述数据块的最高位；或者，所述包头位于所述数据块的最低位。
其中，当所述数据块的大小为17bit时，所述包头的大小为1bit；当数据块的大小为18bit 时，所述包头的大小为2bit；当所述数据块的大小为19bit时，所述包头的大小为3bit。
当所述包头的大小为1bit时，若所述包头的取值为第一值时，所述包头用于指示所述数据单元的类型为PA-PDU；若所述包头的取值为第二值，所述包头用于指示所述数据单元的类型为CTRL-PDU。上述第一值可以为0或者1。上述第二值也可以为0或者1。其中，第一值和第二值不同。
当包头的大小可为2bit时，包头的取值可以为00,01,10,11等。优选的，所述包头的取值为01，或者10。其中，包头的不同取值分别指示不同的数据单元的类型。如所述包头的取值为01时，所述包头用于指示所述数据单元的类型为CTRL-PDU。当所述包头的取值为10时，所述包头用于指示所述数据单元的类型为PA-PDU。可替代的，当所述包头的取值为01时，所述包头用于指示所述数据单元的类型为PA-PDU。当所述包头的取值为10时，所述包头用于指示所述数据单元的类型为CTRL-PDU。
当包头的大小为3bit时，所述包头的取值可以为000,001,010,011,100,101,110,111等。优选的，所述包头的取值为010,101。其中，包头的不同取值分别指示不同的数据单元的类型。
进一步地，所述数据接收单元还包括数据并行化模块，所述解码模块的输出端与所述数据并行化模块的输入端连接；其中，所述数据并行化模块用于将所述数据单元转化为并行化的数据单元。
进一步地，所述数据接收单元还包括解扰模块，所述解扰模块的输入端与所述解码模块的输出端连接，所述解扰模块的输出端与所述数据并行化模块的输入端连接；其中，所述解扰模块用于对所述数据单元进行解扰，以得到解扰后的数据单元；所述数据并行化模块具体用于将所述解扰后的数据单元转化为并行化的数据单元。
本申请实施例的第三方面提供了一种数据传输系统，包括所述的数据发送单元和/或所述的数据接收单元。
本申请实施例的第四方面提供了一种电子设备，包括所述的数据传输系统。
本申请实施例的第五方面提供了一种数据发送方法，包括：
将待发送的数据单元转化为数据块；其中，所述数据单元的大小为16bit，所述数据块的大小为17bit或18bit或19bit，所述数据单元为MIPI UFS协议中MIPI物理层MPHY的协议数据单元PDU；
发送所述数据块。
其中，上述发送所述数据块是基于MIPI UFS协议进行数据发送的。
本申请实施例的第六方面提供了一种数据接收方法，包括：
基于MIPI UFS协议进行数据接收；
将接收的数据块转化为数据单元；其中，所述数据单元的大小为16bit，所述数据块的大小为17bit或18bit或19bit，所述数据单元为所述MIPI UFS协议中MIPI物理层MPHY的协议数据单元PDU。
附图说明
图1是本申请实施例提供的应用在MIPI UFS协议中的数据传输系统示意图；
图2是本申请实施例提供的一种数据发送单元的示意图；
图3-图6分别是本申请实施例提供的包头位于数据块的最高位的示意图；
图7-图10分别是本申请实施例提供的的包头位于数据块的最低位的示意图；
图11是本申请实施例提供的另一种数据发送单元的示意图；
图12是本申请实施例提供的又一种数据发送单元的示意图；
图13是本申请实施例提供的一种数据接收单元的示意图；
图14是本申请实施例提供的另一种数据接收单元的示意图；
图15是本申请实施例提供的又一种数据接收单元的示意图。
具体实施方式
为了使本技术领域的人员更好地理解本申请方案，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分的实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都应当属于本申请保护的范围。
首先介绍本申请实施例涉及的概念：
MIPI UFS协议：MIPI联盟，即移动产业处理器接口(Mobile Industry Processor Interface简称MIPI)联盟。MIPI UFS协议是MIPI联盟发起的为移动通用存储制定的开放标准协议之一。
目前MIPI UFS 3.0协议中MPHY的一个协议数据单元PDU(Protocol Data Unit)的数据位宽是16bit，并且现有协议中规定的接口RMMI的数据位宽是40bit。
UFS：Universal Flash Storage通用闪存存储。
PDU：Protocol Data Units协议数据单元。其中，本申请实施例中所提到的数据单元，可以是协议数据单元PDU。
PA_PDU：PHY Adapter Protocol Data Unit物理适配层的协议数据单元。
CTRL_PDU：Control Protocol Data Unit控制属性协议数据单元。
目前MIPI UFS协议中MIPI物理层MPHY采用的是8B/10B编码。该8B/10B编码方式的编码效率较低。现有技术中有64B/66B编码以及128B/130B编码。这两种编码方式的编码效率均高于8B/10B编码。然而，将64B/66B编码以及128B/130B编码应用在MIPI UFS协议中时，由于两者均超出协议对于MPHY的一个PDU的数据位宽(16bit)，并且超出现有协议中规定的接口RMMI的数据位宽(40bit)。在现有UFS协议的基础上需要修改组包电路、发送端时钟产生电路以及接收端的时钟数据恢复电路等。其修改量较大。因此，现有的编码方式并不能比较好的兼容现有的协议规范。
为此，本方案提出一种16B/17B的编码方案替换MIPI UFS 3.0现有的8B/10B编码方 案。该16B/17B的编码方式的编码效率为94.12％。该编码效率高于8B/10B编码的编码效率。同时，该编码方式的一个数据单元的有效数据是16bit，符合目前MIPI UFS 3.0协议中MPHY的一个协议数据单元PDU的数据位宽16bit，且符合现有协议中规定的接口RMMI的数据位宽。因此，该方案能够在兼容现有MIPI UFS 3.0协议基础上同时有效提升编码效率。
可选的，本方案还提供一种16B/18B的编码方案可替换MIPI UFS 3.0现有的8B/10B编码方案。该16B/18B的编码方式的编码效率为88.89％。该编码效率高于8B/10B编码的编码效率。同时，该编码方式的一个数据单元的有效数据是16bit，符合目前MIPI UFS 3.0协议中MPHY的一个协议数据单元PDU的数据位宽16bit，且符合现有协议中规定的接口RMMI的数据位宽。因此，该方案能够在兼容现有MIPI UFS 3.0协议基础上同时有效提升编码效率。
可替代的，本申请实施例还提供一种16B/19B的编码方案替换MIPI UFS 3.0现有的8B/10B编码方案。该16B/19B的编码方式的编码效率为84.21％。该编码效率高于8B/10B编码的编码效率。同时，该编码方式的一个数据单元的有效数据是16bit，符合目前MIPI UFS 3.0协议中MPHY的一个协议数据单元PDU的数据位宽16bit，且符合现有协议中规定的接口RMMI的数据位宽。因此，该方案能够在兼容现有MIPI UFS 3.0协议基础上同时有效提升编码效率。
下面介绍本申请提供的新的编码方式应用于MIPI UFS协议中的系统示意图。
参照图1，是本申请实施例提供的一种应用在MIPI UFS协议中的数据传输系统的示意图。如图1所示，该系统包括系统级芯片(System on a Chip，SOC)，控制器UFS host和设备UFS device。该控制器UFS host与所述系统级芯片SOC通过高速总线接口互联。控制器UFS Host和设备UFS Device间通过高速SerDes(串行器/解串器)接口互联。
其中，该系统级芯片SOC可以是终端芯片。该控制器UFS host可集成在终端的应用处理器(application processor，AP)侧。该设备UFS device包含闪存颗粒。该闪存颗粒即数据的最终存放介质，如Flash。该设备UFS device可以是存储卡，也可以是嵌入式大容量器件等。其中，设备UFS device包含多个逻辑单元logical units和器件管理单元等。器件管理单元管理器件的电源等方面，而逻辑单元与控制数据读写相关。
具体地，当上述系统级芯片SOC为终端芯片时，设备UFS device通常应用在终端设备中作为存储器件。比如应用在智能手机、手环、智能手表等终端设备。
其中，控制器UFS host和设备UFS device均采用MIPI UFS协议。控制器UFS host用于对从系统级芯片SOC传输来的数据或者即将发送到系统级芯片SOC的数据进行组包和拆包处理。
当SOC需要存储数据时，数据通过高速总线接口从SOC传输到控制器UFS host。控制器UFS Host对该数据进行数据包处理。该数据包处理可包括编码处理等。然后控制器UFS host将处理后的数据经过高速SerDes接口发送到UFS device。UFS device对接收到的数据进行解码处理等。最终UFS device将处理后的数据存放到UFS device的闪存颗粒中。 如UFS device将处理后的数据存放到Flash中。
当SOC需要读取数据时，则UFS device对数据进行数据包处理。如UFS device对数据进行编码处理等。然后UFS device将处理后的数据通过高速SerDes接口传输到控制器UFS host。控制器UFS Host对该数据进行数据包处理。如解码处理等。然后控制器UFS Host将处理后的数据经过高速总线接口发送至SOC。
其中，上述控制器UFS host可以作为发送端进行数据的发送，设备UFS device可以作为接收端进行数据的接收。同时，上述设备UFS device也可以作为发送端进行数据的发送，控制器UFS host也可以作为接收端进行数据的接收。
下面实施例将介绍本方案提供的采用16B/17B的编码方式的数据发送单元的具体实现方式。
参照图2，是本申请实施例提供的一种数据发送单元的示意图。其中，该数据发送单元包括编码模块和发送模块，所述编码模块与所述发送模块连接。所述编码模块用于将待发送的数据单元转化为数据块。所述发送模块用于发送所述数据块。其中，上述数据发送单元基于MIPI UFS协议实现数据发送。
其中，所述数据单元的大小为16bit。所述数据块的大小为17bit。也就是说，本申请实施例提供的编码模块采用16B/17B的编码方式。该编码模块将16bit的数据单元转化为17bit的数据块。其中，所述数据块包括所述数据单元，还包括包头。所述包头的大小为1bit。如图3至图6所示，所述包头可以位于所述数据块的最高位。可选的，如图7至图10所示，所述包头也可以位于所述数据块的最低位。本方案对于包头所处位置并不做具体限定。
其中，所述包头用于指示所述数据单元的类型。所述数据单元的类型包含两种。其中一种是只有有效数据data symbol的PA_PDU。也就是说，PA_PDU中仅包含有效数据。另一种是含有控制数据symbol的CTRL_PDU。其中，CTRL_PDU是协议规定的控制Symbol。所述控制数据Symbol可包含Marker0(MK0)，Marker1(MK1)，Marker2(MK2)，Marker3(MK3)，Marker4(MK4)，FILLER(FLR)等。这些控制symbol组成的CTRL_PDU的类型可包含<MK0,PA_PDU[7:0]>，<MK0,MK1>，<MK0,FLR>，<MK2,MK2>，<FLR,FLR>等。
其中，包头的取值可以为0。或者，所述包头的取值也可以为1。
在一种可选的实现方式中，如图3、图7所示。所述包头的取值为0时，所述包头用于指示所述数据单元的类型为PA-PDU。当所述包头的取值为1时，所述包头用于指示所述数据单元的类型为CTRL-PDU，如图4、图8所示。
在另一种可选的实现方式中，如图6、图10所示。所述包头的取值为0时，所述包头用于指示所述数据单元的类型为CTRL-PDU。当所述包头的取值为1时，所述包头用于指示所述数据单元的类型为PA-PDU，如图5、图9所示。
其中，本申请实施例所提供的数据发送单元可位于如图1所示的控制器UFS host内。也就是说，控制器UFS host可包含该数据发送单元。进一步地，本申请所提供的数据发送单元也可位于如图1所示的设备UFS device中。也就是说，设备UFS device可包含该数据 发送单元。
本申请实施例提供的采用MIPI UFS协议的数据发送单元，通过采用16B/17B的编码方式进行数据发送。其编码效率为94.12％。该编码效率高于现有技术中8B/10B编码的编码效率。同时，该编码方式的一个数据单元的有效数据是16bit，符合目前MIPI UFS 3.0协议中MPHY的一个协议数据单元PDU的数据位宽16bit，且符合现有协议中规定的接口RMMI的数据位宽。因此，该方案能够在兼容现有MIPI UFS 3.0协议基础上同时有效提升编码效率。
另一方面，本方案采用将16bit的数据单元加上1bit的包头编码成17bit的数据块。其中，该包头可用于指示数据单元的类型，十分直观。
作为上述实施例的进一步改进，参照图11，是本申请实施例提供的另一种数据发送单元的示意图。该数据发送单元除了包括编码模块和发送模块。所述数据发送单元还包括数据串行化模块。所述数据串行化模块的输出端与所述编码模块的输入端连接。所述编码模块与所述发送模块连接。
其中，所述数据串行化模块用于将所述待发送的数据单元转化为串行化的数据单元。这样可以实现硬件接口简单，接口端口少。所述编码模块用于将所述串行化的数据单元转化为所述数据块。所述发送模块用于发送所述数据块。
其中，所述数据发送单元采用MIPI UFS协议。所述数据单元的大小为16bit。所述数据块的大小为17bit。所述数据块包括所述数据单元，还包括包头。所述包头的大小为1bit。可参照如图3至图6所示，所述包头可以位于所述数据块的最高位。可选的，如图7至图10所示，所述包头也可以位于所述数据块的最低位。本方案对于包头所处位置并不做具体限定。
具体地，其中，数据串行化模块可将待发送的并行数据进行串行化处理。数据串行化模块将多bit的数据转换成单bit的串行数据进行传输并发送至编码模块。编码模块将接收到的串行数据按照16bit为数据单元进行编码得到17bit的数据块。编码模块将所述数据块发送给发送模块进行数据的发送。
其中，本实施例所提供的数据发送单元可位于如图1所示的控制器UFS host内。也就是说，控制器UFS host可包含该数据发送单元。进一步地，本申请所提供的数据发送单元也可位于如图1所示的设备UFS device中。也就是说，设备UFS device可包含该数据发送单元。
本申请实施例提供的数据发送单元，通过采用16B/17B的编码方式进行数据发送。其编码效率为94.12％。该编码效率高于现有技术中8B/10B编码的编码效率。同时，该编码方式的一个数据单元的有效数据是16bit，符合目前MIPI UFS 3.0协议中MPHY的一个协议数据单元PDU的数据位宽16bit，且符合现有协议中规定的接口RMMI的数据位宽。因此，该方案能够在兼容现有MIPI UFS 3.0协议基础上同时有效提升编码效率。
为了提升直流DC(Direct Current)平衡和跳变密度TD(Transition Density)，在对 待发送数据进行编码前需要对PDU进行加扰(Scrambling)。其中直流平衡表示编码后的数据块中的0和1的个数尽可能的相等。直流DC平衡可以有效避免由于收发两端电压不稳引起的问题。跳变密度TD表示发送的串行数据中的0到1或者1到0的跳变沿的密度。TD的值越高越有利于接收端的时钟数据恢复。作为上述各实施例的进一步改进，参照图12，是本申请实施例提供的又一种数据发送单元的示意图。该数据发送单元除了包括数据串行化模块、编码模块和发送模块。所述数据发送单元还包括加扰模块。所述加扰模块的输入端与所述数据串行化模块的输出端连接，所述加扰模块的输出端与所述编码模块的输入端连接。所述编码模块与所述发送模块连接。
其中，所述数据串行化模块用于将所述待发送的数据单元转化为串行化的数据单元。所述加扰模块用于对所述串行化的数据单元进行加扰以得到加扰后的数据单元。所述编码模块用于将所述加扰后的数据单元转化为数据块。所述发送模块用于发送所述数据块。其中，所述数据发送单元采用MIPI UFS协议。所述数据单元的大小为16bit。所述数据块的大小为17bit。所述数据块包括所述数据单元，还包括包头。所述包头的大小为1bit。可参照如图3至图6所示，所述包头可以位于所述数据块的最高位。可选的，如图7至图10所示，所述包头也可以位于所述数据块的最低位。本方案对于包头所处位置并不做具体限定。
具体地，其中，所述数据串行化模块可将待发送的并行数据进行串行化处理。数据串行化模块将多bit的并行数据转换成单bit的串行数据进行传输并发送至加扰模块。加扰模块将接收到的串行数据进行加扰。加扰模块将加扰后的数据发送给编码模块。编码模块将加扰后的的数据转化为17bit的数据块。
其中，本实施例所提供的数据发送单元可位于如图1所示的控制器UFS host内。也就是说，控制器UFS host可包含该数据发送单元。进一步地，本申请所提供的数据发送单元也可位于如图1所示的设备UFS device中。也就是说，设备UFS device可包含该数据发送单元。
作为一种可选的实现方式，该加扰模块可包括D0，D1，…D15等16个D触发寄存器。该加扰模块还包括16个异或门。其中，各个异或门的第一输入端分别与对应的输入数据流连接。每个D触发寄存器的第一输出端分别与每个异或门的第二输入端连接。也就是说，一个D触发寄存器连接一个异或门。各个异或门的第二输入端分别与对应的D触发寄存器的第一输出端连接。
上述16个D触发寄存器加上异或门构成线性反馈移位寄存器(LFSR)。该线性反馈移位寄存器即是加扰码流产生电路。其中G(X)表示LFSR产生的加扰码流。Seed表示加扰码流初始值。作为一种可选的实现方式，G(X)可表示为G(X)＝X 16+X 5+X 4+X 3+1。
其中，经过数据串行化模块进行串行转化后发送到加扰模块的输入数据流(16bit PDU)与加扰码流(以16bit为单位)做异或运算，从而完成对输入的数据单元的加扰。
目前现有的MIPI UFS协议中规定UFS的高速数据传输通道支持4条lane。因此，在实际应用中可使用1条lane，也可以使用2条lane、3条lane或者4条lane等。如果4条lane都要使用，则需要对4条lane的数据分别加扰。因此，需要4个相同的LFSR电路来产生加扰码流。其中，为了防止4条lane之间信号的互相干扰，4个LFSR的加扰码流初 始值Seed需要不同。可选的，每条lane对应的Seed值可表示为：第一条lane的Seed为0x0040。第二条lane的Seed为0x0080。第三条lane的Seed为0x00C0。第四条lane的Seed为0x0100。
上述加扰模块通过对数据进行加扰处理后将数据发送至编码模块以实现16B/17B编码。
本申请实施例提供的采用MIPI UFS协议的数据发送单元，通过采用16B/17B的编码方式进行数据发送。其编码效率为94.12％。该编码效率高于现有技术中8B/10B编码的编码效率。同时，该编码方式的一个数据单元的有效数据是16bit，符合目前MIPI UFS 3.0协议中MPHY的一个协议数据单元PDU的数据位宽16bit，且符合现有协议中规定的接口RMMI的数据位宽。因此，该方案能够在兼容现有MIPI UFS 3.0协议基础上同时有效提升编码效率。
作为本申请的另一种可选的实现方式，本申请还提供一种16B/18B的编码方案。该编码方案可替换上述16B/17B的编码方案。其中，上述各实施例中的数据发送单元可采用该16B/18B的编码方式。
具体地，编码模块用于将待发送的数据单元转化为数据块。所述数据单元的大小为16bit。所述数据块的大小为18bit。所述数据块包括所述数据单元，还包括包头。
所述包头用于指示所述数据单元的类型。所述包头的大小可为2bit。所述包头可以位于所述数据块的最高位。所述包头也可以位于所述数据块的最低位。
其中，所述包头的取值可以为00,01,10,11等。优选的，所述包头的取值为01，或者10。其中，包头的不同取值分别指示不同的数据单元的类型。如所述包头的取值为01时，所述包头用于指示所述数据单元的类型为CTRL-PDU。当所述包头的取值为10时，所述包头用于指示所述数据单元的类型为PA-PDU。可替代的，当所述包头的取值为01时，所述包头用于指示所述数据单元的类型为PA-PDU。当所述包头的取值为10时，所述包头用于指示所述数据单元的类型为CTRL-PDU。上述仅作为一种具体实现方式，对于包头的取值为00或11时同样适用。
其中，本实施例所提供的数据发送单元可位于如图1所示的控制器UFS host内。也就是说，控制器UFS host可包含该数据发送单元。进一步地，本申请所提供的数据发送单元也可位于如图1所示的设备UFS device中。也就是说，设备UFS device可包含该数据发送单元。
本申请实施例提供的16B/18B的编码方式的编码效率为88.89％。该编码效率高于8B/10B编码的编码效率。同时，该编码方式的一个数据单元的有效数据是16bit，符合目前MIPI UFS 3.0协议中MPHY的一个协议数据单元PDU的数据位宽16bit，且符合现有协议中规定的接口RMMI的数据位宽。因此，该方案能够在兼容现有MIPI UFS 3.0协议基础上同时有效提升编码效率。
作为本申请实施例的再一种可选的实现方式，本申请实施例还提供一种16B/19B的编码方案。该编码方案可替换上述16B/17B的编码方案。上述各实施例中的数据发送单元可 采用该16B/19B的编码方式。
具体地，编码模块用于将待发送的数据单元转化为数据块。其中，所述数据单元的大小为16bit。所述数据块的大小为19bit。所述数据块包括所述数据单元，还包括包头。所述包头用于指示所述数据单元的类型。
所述包头的大小可为3bit。所述包头可以位于所述数据块的最高位。所述包头也可以位于所述数据块的最低位。其中，所述包头的取值可以为000,001,010,011,100,101,110,111等。优选的，所述包头的取值为010,101。其中，不同的包头取值指示不同的数据单元的类型。具体可参照图3至图10所述，在此不再赘述。
其中，本实施例所提供的数据发送单元可位于如图1所示的控制器UFS host内。也就是说，控制器UFS host可包含该数据发送单元。进一步地，本申请所提供的数据发送单元也可位于如图1所示的设备UFS device中。也就是说，设备UFS device可包含该数据发送单元。
本申请实施例提供的16B/19B的编码方式的编码效率为84.21％。该编码效率高于8B/10B编码的编码效率。同时，该编码方式的一个数据单元的有效数据是16bit，符合目前MIPI UFS 3.0协议中MPHY的一个协议数据单元PDU的数据位宽16bit，且符合现有协议中规定的接口RMMI的数据位宽。因此，该方案能够在兼容现有MIPI UFS 3.0协议基础上同时有效提升编码效率。
下面将介绍本方案采用16B/17B的编码方式所对应的解码方式的数据接收单元的具体实现方式。
参照图13，是本申请实施例提供的一种数据接收单元的示意图。其中，该数据接收单元包括接收模块和解码模块。所述接收模块与所述解码模块连接。所述解码模块用于将所述接收模块接收的数据块转化为数据单元。其中，上述数据接收单元采用MIPI UFS协议。
上述数据单元的大小为16bit。所述数据块的大小为17bit。也就是说，本申请实施例提供的解码模块将17bit的数据块转化为16bit的数据单元。其中，所述数据块包括所述数据单元，还包括包头。所述包头的大小为1bit。如图3至图6所示，所述包头可以位于所述数据块的最高位。可选的，如图7至图10所示，所述包头也可以位于所述数据块的最低位。本方案对于包头所处位置并不做具体限定。
其中，所述包头用于指示所述数据单元的类型。所述数据单元的类型包含两种。其中一种是只有有效数据data symbol的PA_PDU。也就是说，PA_PDU中仅包含有效数据。另一种是含有控制数据symbol的CTRL_PDU。其中，CTRL_PDU是协议规定的控制Symbol。所述控制数据Symbol可包含Marker0(MK0)，Marker1(MK1)，Marker2(MK2)，Marker3(MK3)，Marker4(MK4)，FILLER(FLR)等。这些控制symbol组成的CTRL_PDU的类型可包含<MK0,PA_PDU[7:0]>，<MK0,MK1>，<MK0,FLR>，<MK2,MK2>，<FLR,FLR>等。
其中，包头的取值可以为0。或者，所述包头的取值也可以为1。
在一种可选的实现方式中，如图3、图7所示。所述包头的取值为0时，所述包头用 于指示所述数据单元的类型为PA-PDU。当所述包头的取值为1时，所述包头用于指示所述数据单元的类型为CTRL-PDU，如图4、图8所示。
在另一种可选的实现方式中，如图6、图10所示。所述包头的取值为0时，所述包头用于指示所述数据单元的类型为CTRL-PDU。当所述包头的取值为1时，所述包头用于指示所述数据单元的类型为PA-PDU，如图5、图9所示。
其中，本实施例所提供的数据接收单元可位于如图1所示的控制器UFS host内。也就是说，控制器UFS host可包含该数据接收单元。进一步地，本申请所提供的数据接收单元也可位于如图1所示的设备UFS device中。也就是说，设备UFS device可包含该数据接收单元。
作为上述实施例的进一步改进，参照图14，是本申请实施例提供的另一种数据接收单元的示意图。该数据接收单元除了包括接收模块和解码模块。该数据接收单元还包括数据并行化模块。其中，所述接收模块与所述解码模块连接。所述解码模块的输出端与所述数据并行化模块的输入端连接。
其中，所述解码模块用于将所述接收模块接收的数据块转化为数据单元。所述数据并行化模块用于将所述数据单元转化为并行化的数据单元。通过将数据单元转化为并行化的数据单元，其可提高数据处理的效率。
具体地，其中，解码模块将接收的数据大小为17bit的数据块转化为16bit的数据单元。解码模块将解码后的数据单元发送至数据并行化模块。数据并行化模块可将接收到的数据单元进行并行化处理并转化为并行数据。数据并行化模块将该并行数据发送到UFS内部电路模块中以进行使用。
其中，本实施例所提供的数据接收单元可位于如图1所示的控制器UFS host内。也就是说，控制器UFS host可包含该数据接收单元。进一步地，本申请所提供的数据接收单元也可位于如图1所示的设备UFS device中。也就是说，设备UFS device可包含该数据接收单元。
作为上述各实施例的进一步改进，参照图15，是本申请实施例提供的另一种数据接收单元的示意图。该数据接收单元除了包括接收模块、解码模块和数据并行化模块。该数据接收单元还包括解扰模块。其中，接收模块与解码模块连接。解码模块的输出端与解扰模块的输入端连接。解扰模块的输出端与数据并行化模块的输入端连接。
其中，所述解码模块用于将接收的数据块转化为数据单元。所述解扰模块用于对所述数据单元进行解扰，以得到解扰后的数据单元。所述数据并行化模块用于将所述解扰后的数据单元转化为并行化的数据单元。其中，所述数据接收单元采用MIPI UFS协议。所述数据单元的大小为16bit。所述数据块的大小为17bit。所述数据块包括所述数据单元，还包括包头。所述包头的大小为1bit。
具体地，数据接收单元的解码模块可将接收到的数据大小为17bit的数据块转化为16bit的数据单元。解码模块将解码后的数据单元发送至解扰模块。解扰模块对接收到的数 据单元进行解扰。然后解扰模块将解扰后的数据单元发送至数据并行化模块，以便所述数据并行化模块将所述解扰后的数据单元转化为并行数据。该转化后的并行数据可发送到UFS内部电路模块中使用。
其中，本实施例所提供的数据接收单元可位于如图1所示的控制器UFS host内。也就是说，控制器UFS host可包含该数据接收单元。进一步地，本申请所提供的数据接收单元也可位于如图1所示的设备UFS device中。也就是说，设备UFS device可包含该数据接收单元。
上述实施例仅以16B/17B的编码方式所对应的解码方式进行介绍。本申请实施例还提供一种16B/18B的编码方式所对应的解码方式。该16B/18B的编码方式所对应的解码方式可替换上述16B/17B的编码方式所对应的解码方式。也就是说，上述数据接收单元可采用该16B/18B的编码方式所对应的解码方式。
与上述采用16B/17B的编码方式所对应的解码方式的数据接收单元不同的是，采用16B/18B的编码方式所对应的解码方式的解码模块用于将接收的数据块转化为数据单元。其中，所述数据单元的大小为16bit。所述数据块的大小为18bit。所述数据块包括所述数据单元，还包括包头。所述包头用于指示所述数据单元的类型。所述包头的大小可为2bit。所述包头可以位于所述数据块的最高位。所述包头也可以位于所述数据块的最低位。
其中，所述包头的取值可以为00,01,10,11等。优选的，所述包头的取值为01，或者10。其中，包头的不同取值分别指示不同的数据单元的类型。如所述包头的取值为01时，所述包头用于指示所述数据单元的类型为CTRL-PDU。当所述包头的取值为10时，所述包头用于指示所述数据单元的类型为PA-PDU。可替代的，当所述包头的取值为01时，所述包头用于指示所述数据单元的类型为PA-PDU。当所述包头的取值为10时，所述包头用于指示所述数据单元的类型为CTRL-PDU。上述仅作为一种具体实现方式，对于包头的取值为00或11时同样适用。
其中，本实施例所提供的数据接收单元可位于如图1所示的控制器UFS host内。也就是说，控制器UFS host可包含该数据接收单元。进一步地，本申请所提供的数据接收单元也可位于如图1所示的设备UFS device中。也就是说，设备UFS device可包含该数据接收单元。
可替代的，本申请实施例还提供一种16B/19B的编码方式所对应的解码方式。该16B/19B的编码方式所对应的解码方式可替换上述16B/17B的编码方式所对应的解码方式。也就是说，上述数据接收单元可采用该16B/19B的编码方式所对应的解码方式。
与上述采用16B/17B的编码方式所对应的解码方式的数据接收单元不同的是，采用16B/19B的编码方式所对应的解码方式的解码模块用于将接收的数据块转化为数据单元。其中，所述数据单元的大小为16bit。所述数据块的大小为19bit。所述数据块包括所述数据单元，还包括包头。所述包头用于指示所述数据单元的类型。所述包头的大小可为3bit。所述包头可以位于所述数据块的最高位。所述包头也可以位于所述数据块的最低位。
其中，所述包头的取值可以为000,001,010,011,100,101,110,111等。优选的，所述包头的取值为010,101。其中，不同的包头取值指示不同的数据单元的类型。具体可参照图3至图10所述，在此不再赘述。
本实施例所提供的数据接收单元可位于如图1所示的控制器UFS host内。也就是说，控制器UFS host可包含该数据接收单元。进一步地，本申请所提供的数据接收单元也可位于如图1所示的设备UFS device中。也就是说，设备UFS device可包含该数据接收单元。
本申请实施例还提供一种数据传输系统，包括所述的数据发送单元和所述数据接收单元。
本申请实施例还提供一种电子设备，包括所述的数据传输系统。该电子设备可以是手机、电脑等终端设备。
本申请实施例还提供一种数据发送方法，包括：
将待发送的数据单元转化为数据块；其中，所述数据单元的大小为16bit，所述数据块的大小为17bit或18bit或19bit，所述数据单元为MIPI UFS协议中MIPI物理层MPHY的协议数据单元PDU；
发送所述数据块。
其中，上述发送所述数据块是基于MIPI UFS协议进行数据发送的。
所述数据块包括所述数据单元和包头，所述包头用于指示所述数据单元的类型。其中，数据单元的类型包含两种。其中一种是只有有效数据data symbol的PA_PDU。也就是说，PA_PDU中仅包含有效数据。另一种是含有控制数据symbol的CTRL_PDU。其中，CTRL_PDU是协议规定的控制Symbol。
其中，所述包头位于所述数据块的最高位；或者，所述包头位于所述数据块的最低位。
其中，当所述数据块的大小为17bit时，所述包头的大小为1bit；当数据块的大小为18bit时，所述包头的大小为2bit；当所述数据块的大小为19bit时，所述包头的大小为3bit。
当所述包头的大小为1bit时，若所述包头的取值为第一值时，所述包头用于指示所述数据单元的类型为PA-PDU；若所述包头的取值为第二值，所述包头用于指示所述数据单元的类型为CTRL-PDU。上述第一值可以为0或者1。上述第二值也可以为0或者1。其中，第一值和第二值不同。
当包头的大小可为2bit时，包头的取值可以为00,01,10,11等。优选的，所述包头的取值为01，或者10。其中，包头的不同取值分别指示不同的数据单元的类型。如所述包头的取值为01时，所述包头用于指示所述数据单元的类型为CTRL-PDU。当所述包头的取值为10时，所述包头用于指示所述数据单元的类型为PA-PDU。可替代的，当所述包头的取值为01时，所述包头用于指示所述数据单元的类型为PA-PDU。当所述包头的取值为10时，所述包头用于指示所述数据单元的类型为CTRL-PDU。
当包头的大小为3bit时，所述包头的取值可以为000,001,010,011,100,101,110,111等。优选的，所述包头的取值为010,101。其中，包头的不同取值分别指示不同的数据单元的类 型。
其中，所述将待发送的数据单元转化为数据块，包括：
将所述待发送的数据单元转化为串行化的数据单元；
将所述串行化的数据单元转化为所述数据块。
进一步地，所述将待发送的数据单元转化为数据块，包括：
将所述待发送的数据单元转化为串行化的数据单元；
对所述串行化的数据单元进行加扰以得到加扰后的数据单元；
将所述加扰后的数据单元转化为所述数据块。
本申请实施例提供的16B/17B的编码方式的编码效率为94.12％；16B/18B的编码方式的编码效率为88.89％；16B/19B的编码方式的编码效率为84.21％。上述各编码方式的编码效率均高于8B/10B编码的编码效率。上述各编码方式的一个数据单元的有效数据为16bit，符合目前MIPI UFS 3.0协议中MPHY的一个协议数据单元PDU的数据位宽16bit，且符合现有协议中规定的接口RMMI的数据位宽。因此，本方案提供的新的编码方式能够在兼容现有MIPI UFS 3.0协议基础上同时有效提升编码效率。
本申请实施例还提供一种数据接收方法，包括：
基于MIPI UFS协议进行数据接收；
将接收的数据块转化为数据单元；其中，所述数据单元的大小为16bit，所述数据块的大小为17bit或18bit或19bit，所述数据单元为所述MIPI UFS协议中MIPI物理层MPHY的协议数据单元PDU。
其中，所述数据块包括所述数据单元和包头，所述包头用于指示所述数据单元的类型。其中，数据单元的类型包含两种。其中一种是只有有效数据data symbol的PA_PDU。也就是说，PA_PDU中仅包含有效数据。另一种是含有控制数据symbol的CTRL_PDU。其中，CTRL_PDU是协议规定的控制Symbol。
其中，所述包头位于所述数据块的最高位；或者，所述包头位于所述数据块的最低位。
其中，当所述数据块的大小为17bit时，所述包头的大小为1bit；当数据块的大小为18bit时，所述包头的大小为2bit；当所述数据块的大小为19bit时，所述包头的大小为3bit。
当所述包头的大小为1bit时，若所述包头的取值为第一值时，所述包头用于指示所述数据单元的类型为PA-PDU；若所述包头的取值为第二值，所述包头用于指示所述数据单元的类型为CTRL-PDU。上述第一值可以为0或者1。上述第二值也可以为0或者1。其中，第一值和第二值不同。
当包头的大小可为2bit时，包头的取值可以为00,01,10,11等。优选的，所述包头的取值为01，或者10。其中，包头的不同取值分别指示不同的数据单元的类型。如所述包头的取值为01时，所述包头用于指示所述数据单元的类型为CTRL-PDU。当所述包头的取值为10时，所述包头用于指示所述数据单元的类型为PA-PDU。可替代的，当所述包头的取值为01时，所述包头用于指示所述数据单元的类型为PA-PDU。当所述包头的取值为10时，所述包头用于指示所述数据单元的类型为CTRL-PDU。
当包头的大小为3bit时，所述包头的取值可以为000,001,010,011,100,101,110,111等。优选的，所述包头的取值为010,101。其中，包头的不同取值分别指示不同的数据单元的类型。
其中，所述方法还包括：
将所述数据单元转化为并行化的数据单元。
进一步地，所述将所述数据单元转化为并行化的数据单元包括：
对所述数据单元进行解扰，以得到解扰后的数据单元；
将所述解扰后的数据单元转化为并行化的数据单元。
在上述实施例中，可以全部或部分地通过软件、硬件、固件或者其任意组合来实现。当使用软件实现时，可以全部或部分地以计算机程序产品的形式实现。所述计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行所述计算机程序指令时，全部或部分地产生按照本申请实施例所述的流程或功能。所述计算机可以是通用计算机、专用计算机、计算机网络、或者其他可编程装置。所述计算机指令可以存储在计算机可读存储介质中，或者通过所述计算机可读存储介质进行传输。所述计算机指令可以从一个网站站点、计算机、服务器或数据中心通过有线(例如同轴电缆、光纤、数字用户线)或无线(例如红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。所述计算机可读存储介质可以是计算机能够存取的任何可用介质或者是包含一个或多个可用介质集成的服务器、数据中心等数据存储设备。所述可用介质可以是磁性介质，(例如，软盘、硬盘、磁带)、光介质(例如，DVD)、或者半导体介质(例如，固态硬盘(solid state disk，SSD))等。
本领域普通技术人员可以理解实现上述实施例方法中的全部或部分流程，该流程可以由计算机程序来指令相关的硬件完成，该程序可存储于计算机可读取存储介质中，该程序在执行时，可包括如上述各方法实施例的流程。而前述的存储介质包括：ROM或随机存储记忆体RAM、磁碟或者光盘等各种可存储程序代码的介质。
以上所述，仅为本申请实施例的具体实施方式，但本申请实施例的保护范围并不局限于此，任何在本申请实施例揭露的技术范围内的变化或替换，都应涵盖在本申请实施例的保护范围之内。因此，本申请实施例的保护范围应以所述权利要求的保护范围为准。

Claims (24)

  1. 一种数据发送单元，包括编码模块和发送模块，所述编码模块与所述发送模块连接，其特征在于，所述数据发送单元基于MIPI UFS协议进行数据发送；
    所述编码模块用于将待发送的数据单元转化为数据块；其中，所述数据单元的大小为16bit，所述数据块的大小为17bit或18bit或19bit，所述数据单元为所述MIPI UFS协议中MIPI物理层MPHY的协议数据单元PDU；
    所述发送模块用于发送所述数据块。
  2. 根据权利要求1所述的数据发送单元，其特征在于，所述数据块包括所述数据单元和包头，所述包头用于指示所述数据单元的类型。
  3. 根据权利要求2所述的数据发送单元，其特征在于，所述包头位于所述数据块的最高位；或者，所述包头位于所述数据块的最低位。
  4. 根据权利要求1至3任一项所述的数据发送单元，其特征在于，所述包头的大小为1bit、2bit或3bit。
  5. 根据权利要求4所述的数据发送单元，其特征在于，当所述包头的大小为1bit时，若所述包头的取值为第一值时，所述包头用于指示所述数据单元的类型为PA-PDU；
    若所述包头的取值为第二值，所述包头用于指示所述数据单元的类型为CTRL-PDU。
  6. 根据权利要求1至5任一项所述的数据发送单元，其特征在于，所述数据发送单元还包括数据串行化模块，所述数据串行化模块的输出端与所述编码模块的输入端连接；
    其中，所述数据串行化模块用于将所述待发送的数据单元转化为串行化的数据单元；
    所述编码模块具体用于将所述串行化的数据单元转化为所述数据块。
  7. 根据权利要求6所述的数据发送单元，其特征在于，所述数据发送单元还包括加扰模块，所述加扰模块的输入端与所述数据串行化模块的输出端连接，所述加扰模块的输出端与所述编码模块的输入端连接；
    其中，所述加扰模块用于对所述串行化的数据单元进行加扰，以得到加扰后的数据单元；
    所述编码模块具体用于将所述加扰后的数据单元转化为所述数据块。
  8. 一种数据接收单元，包括接收模块和解码模块，所述接收模块与所述解码模块连接，其特征在于，所述数据接收单元基于MIPI UFS协议进行数据接收；所述解码模块用于将所述接收模块接收的数据块转化为数据单元；其中，所述数据单元的大小为16bit，所述数据 块的大小为17bit或18bit或19bit，所述数据单元为所述MIPI UFS协议中MIPI物理层MPHY的协议数据单元PDU。
  9. 根据权利要求8所述的数据接收单元，其特征在于，所述数据块包括所述数据单元和包头，所述包头用于指示所述数据单元的类型。
  10. 根据权利要求9所述的数据接收单元，其特征在于，所述包头位于所述数据块的最高位；或者，所述包头位于所述数据块的最低位。
  11. 根据权利要求8至10任一项所述的数据接收单元，其特征在于，所述包头的大小为1bit、2bit或3bit。
  12. 根据权利要求11所述的数据接收单元，其特征在于，当所述包头的大小为1bit时，若所述包头的取值为第一值时，所述包头用于指示所述数据单元的类型为PA-PDU；
    若所述包头的取值为第二值，所述包头用于指示所述数据单元的类型为CTRL-PDU。
  13. 根据权利要求8至12任一项所述的数据接收单元，其特征在于，所述数据接收单元还包括数据并行化模块，所述解码模块的输出端与所述数据并行化模块的输入端连接；
    其中，所述数据并行化模块用于将所述数据单元转化为并行化的数据单元。
  14. 根据权利要求13所述的数据接收单元，其特征在于，所述数据接收单元还包括解扰模块，所述解扰模块的输入端与所述解码模块的输出端连接，所述解扰模块的输出端与所述数据并行化模块的输入端连接；
    其中，所述解扰模块用于对所述数据单元进行解扰，以得到解扰后的数据单元；
    所述数据并行化模块具体用于将所述解扰后的数据单元转化为并行化的数据单元。
  15. 一种数据传输系统，其特征在于，包括权利要求1至7任一项所述的数据发送单元和/或权利要求8至14任一项所述的数据接收单元。
  16. 一种电子设备，其特征在于，包括权利要求15所述的数据传输系统。
  17. 一种数据发送方法，其特征在于，包括：
    将待发送的数据单元转化为数据块；其中，所述数据单元的大小为16bit，所述数据块的大小为17bit或18bit或19bit，所述数据单元为MIPI UFS协议中MIPI物理层MPHY的协议数据单元PDU；
    发送所述数据块。
  18. 根据权利要求17所述的方法，其特征在于，所述数据块包括所述数据单元和包头，所述包头用于指示所述数据单元的类型。
  19. 根据权利要求18所述的方法，其特征在于，所述包头位于所述数据块的最高位；或者，所述包头位于所述数据块的最低位。
  20. 根据权利要求17至19任一项所述的方法，其特征在于，所述将待发送的数据单元转化为数据块，包括：
    将所述待发送的数据单元转化为串行化的数据单元；
    将所述串行化的数据单元转化为所述数据块。
  21. 一种数据接收方法，其特征在于，包括：
    基于MIPI UFS协议进行数据接收；
    将接收的数据块转化为数据单元；其中，所述数据单元的大小为16bit，所述数据块的大小为17bit或18bit或19bit，所述数据单元为所述MIPI UFS协议中MIPI物理层MPHY的协议数据单元PDU。
  22. 根据权利要求21所述的方法，其特征在于，所述数据块包括所述数据单元和包头，所述包头用于指示所述数据单元的类型。
  23. 根据权利要求22所述的方法，其特征在于，所述包头位于所述数据块的最高位；或者，所述包头位于所述数据块的最低位。
  24. 根据权利要求21至23任一项所述的方法，其特征在于，还包括：
    将所述数据单元转化为并行化的数据单元。
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