WO2019237625A1 - 解扰方法、设备及可读存储介质 - Google Patents

解扰方法、设备及可读存储介质 Download PDF

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Publication number
WO2019237625A1
WO2019237625A1 PCT/CN2018/111423 CN2018111423W WO2019237625A1 WO 2019237625 A1 WO2019237625 A1 WO 2019237625A1 CN 2018111423 W CN2018111423 W CN 2018111423W WO 2019237625 A1 WO2019237625 A1 WO 2019237625A1
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Prior art keywords
current
bit set
descrambling
sequence
bits
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PCT/CN2018/111423
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English (en)
French (fr)
Inventor
王拂依
张裕桦
曹丹
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深圳市华星光电技术有限公司
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Publication of WO2019237625A1 publication Critical patent/WO2019237625A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03828—Arrangements for spectral shaping; Arrangements for providing signals with specified spectral properties
    • H04L25/03866—Arrangements for spectral shaping; Arrangements for providing signals with specified spectral properties using scrambling

Definitions

  • the present application relates to the field of data transmission, and in particular, to a descrambling method, device, and readable storage medium.
  • the transmitted data can be encoded into a code stream containing a clock frequency component, so that the receiver can extract clock synchronization information from the code stream.
  • the clock synchronization information can ensure that the receiver receives The original data is reproduced from the signal.
  • the transmitted code stream In the actual transmission process, the transmitted code stream often has a long continuous same logic value. Such a low code stream quality will affect the clock synchronization information extracted by the receiving end, and decoding errors (ie, bit errors) may occur. In addition, the frequency distribution of the code stream with strong regularity is uneven, and the power of one or some frequency components is too large, which may cause strong electromagnetic interference during the transmission process.
  • the technical problem mainly solved by this application is to provide a descrambling method, a device, and a readable storage medium, which can solve the decoding errors caused by the low-quality code stream in the prior art, and the strong regular code stream causes strong transmission during transmission. Problems with electromagnetic interference.
  • the present application provides a readable storage medium that stores instructions.
  • the following method is implemented: using a previous descrambling sequence to obtain a current descrambling sequence, wherein the first The bit set is obtained by shifting and assigning the second bit set of the previous descrambling sequence, and the third bit set of the current descrambling sequence is the logic of the feature bit set in the previous descrambling sequence
  • the third bit set is composed of all other bits in the current descrambling sequence except the first bit set, and the characteristic bit set includes multiple characteristic bits, at least two of which The interval between the characteristic bits is greater than or equal to half the sequence length;
  • the current scrambled data is descrambled by using a predetermined bit set in the current descrambling sequence to obtain the current original data; at least two adjacent ones of the The spacing between the characteristic bits is greater than or equal to half of the sequence length, and the predetermined bit set has no intersection with the third bit set.
  • the present application provides a descrambling method, which includes: obtaining a current descrambling sequence by using a previous descrambling sequence, wherein a first bit set of the current descrambling sequence is determined by the previous descrambling sequence.
  • the second bit set is directly assigned.
  • the third bit set of the current descrambling sequence is assigned by the logical operation result of the characteristic bit set in the previous descrambling sequence.
  • the third bit set is divided by the first descramble sequence.
  • the characteristic bit set includes multiple characteristic bits, where the distance between at least two characteristic bits is greater than or equal to half of the sequence length; using a predetermined bit set in the current descrambling sequence to compare the current The scrambled data is descrambled to obtain the current original data.
  • the present application provides a descrambling apparatus.
  • the apparatus includes a processor, and the processor is configured to execute instructions to implement the foregoing method.
  • the beneficial effect of the present application is: using the previous descrambling sequence to obtain the current descrambling sequence, wherein the first bit set of the current descrambling sequence is obtained by shifting and assigning the second bit set of the previous descrambling sequence, and the current descrambling sequence
  • the third bit set of the sequence is obtained from the logical operation result of the characteristic bit set in the previous descrambling sequence.
  • the third bit set consists of all other bits in the current descrambling sequence except the first bit set.
  • the bit set includes a plurality of characteristic bits, wherein a distance between at least two characteristic bits is greater than or equal to half of a sequence length; and then a predetermined bit set in the current descrambling sequence is used to descramble the current scrambled data to obtain the current original data.
  • the above steps are performed cyclically.
  • the descrambling sequence has a certain balance, that is, the numbers of "0" and "1" are relatively balanced. Since the descrambling sequence and the scrambling sequence are exactly the same, the scrambling sequence also has the same The characteristics make the probability of low quality of the scrambled data after scrambling greatly reduced, and it is close to the statistical characteristics of the white noise signal, which reduces the bit error rate and the electromagnetic interference during transmission.
  • FIG. 1 is a schematic flowchart of an embodiment of a descrambling method according to the present application
  • FIG. 2 is a schematic diagram of a specific embodiment of a descrambling method according to the present application.
  • FIG. 3 is a schematic diagram of another specific embodiment of a descrambling method according to the present application.
  • FIG. 4 is a schematic flowchart of another embodiment of a descrambling method according to the present application.
  • FIG. 5 is a schematic structural diagram of an embodiment of a descrambling device according to the present application.
  • FIG. 6 is a schematic structural diagram of an embodiment of a readable storage medium of the present application.
  • an embodiment of the descrambling method of this application includes:
  • the original data at the sending end is divided into multiple groups with the same number of bits, and each group is called a codeword.
  • the sender can use the scrambler to generate the current scrambling code sequence to scramble the current original data, that is, the current codeword.
  • the descrambling is generally performed at the receiving end. After the receiving end extracts the current scrambling code data, it can use a descrambler to generate a current descrambling sequence to descramble the current scrambling code data.
  • the scrambler and descrambler may be linear feedback shift registers (LFSR), which may be implemented by software or hardware.
  • the first bit set of the current descrambling sequence is obtained by shifting and assigning the second bit set of the previous descrambling sequence.
  • the third bit set of the current descrambling sequence is obtained from the logical operation result of the characteristic bit set in the previous descrambling sequence.
  • the logical operation is generally XOR.
  • the third bit set consists of all other bits in the current descrambling sequence except the first bit set, that is, all bits of the current descrambling sequence are the complete set, and the first and third bit sets are complements of each other. .
  • the previous descrambling sequence is the same length as the current descrambling sequence.
  • the feature bit set includes a plurality of feature bits, and a distance between at least two feature bits is greater than or equal to half a sequence length.
  • the sequence length refers to a length of a previous descrambling sequence and a current descrambling sequence. This means that at least one signature is in the first half of the previous descrambling sequence, and at least one signature is in the second half of the previous descrambling sequence.
  • the distance between at least two adjacent feature bits is greater than or equal to half the sequence length, for example, the sequence length is 8 bits
  • the feature bit set includes the first, second, and seventh bits, where the second and seventh bits
  • the spacing between the bits is 5 bits, which is more than half the sequence length.
  • the signature bits may be located at the first 1/4 and the last 1/4 of the previous descrambling sequence.
  • the descrambling sequence is set with an initial value for generating a subsequent descrambling sequence.
  • the initial value of the descrambling sequence is determined by the generator polynomial of the LFSR. All the bits in the polynomial whose coefficients are not 0 (hereinafter referred to as the initial bits) have the same logical value, and all other bits have the same logical value and the logical values of the two are opposite. .
  • the feature bit set may be exactly the same as the set of initial bits, or it may be partially the same.
  • the bits other than the corresponding bits of the third bit set being reversely shifted are all characteristic bits.
  • the descrambling sequences obtained are connected in sequence, which can form a long-period sequence.
  • the number of bits of a single descrambling sequence is n, and the corresponding long period is 2 n -1.
  • S2 Descramble the current scrambling code data by using a predetermined bit set in the current descrambling sequence to obtain the current original data.
  • the predetermined set of bits in the current descrambling sequence and the current scrambling code data are XORed logically bit by bit to obtain the current original data.
  • the bits in the predetermined bit set may be continuous or discontinuous, and the order of exclusive ORing with the current original data is not limited.
  • the predetermined bit set is fixed for different descrambling sequences.
  • the predetermined bit set is a subset of the first bit set, so that the predetermined bit set used for each actual descrambling is obtained by shift assignment, which further guarantees its Balance.
  • the configuration parameters of the descrambler and the scrambler are completely the same, and they work synchronously, so that for each codeword, the sequence for scrambling and the sequence for descrambling are exactly the same, and the predetermined bit set is also completely the same. Since the exclusive OR operation satisfies Therefore, the current scrambled code data can be obtained by performing an exclusive-OR logical operation on a predetermined bit set in the current descrambling sequence and the current original data bit by bit.
  • the previous descrambling sequence is used to obtain the current descrambling sequence.
  • the first bit set of the current descrambling sequence is obtained by shifting and assigning the second bit set of the previous descrambling sequence.
  • the third bit set of the sequence is obtained from the logical operation result of the characteristic bit set in the previous descrambling sequence.
  • the third bit set consists of all other bits in the current descrambling sequence except the first bit set.
  • the bit set includes a plurality of characteristic bits, wherein a distance between at least two characteristic bits is greater than or equal to half of a sequence length; and then a predetermined bit set in the current descrambling sequence is used to descramble the current scrambled data to obtain the current original data.
  • the descrambling sequence has a certain balance, that is, the numbers of "0" and "1" are relatively balanced. Since the descrambling sequence and the scrambling sequence are exactly the same, the scrambling sequence also has the same Characteristics, so that the probability of low quality scrambled data after scrambling (that is, the number of consecutive identical logical values is greater than a preset threshold) is greatly reduced, and it is close to the statistical characteristics of white noise signals, reducing the bit error rate and reducing the Electromagnetic interference.
  • the number of bits of the current descrambling sequence and the previous descrambling sequence are both 16, the first bit set is 1-15th bit, and the second bit set is It is the 0th to 14th bits, the third bit set is the 0th bit, and the characteristic bit set includes the 3rd, 12th, 14th, and 15th bits, and the characteristic bits belong to the first 1/4 or the last 1/4 of the sequence.
  • the generator polynomial G (x) of LFSR is X 16 + X 14 + X 12 + X 3 +1.
  • the first term X 16 in the formula indicates that the number of bits of a single descrambling sequence is 16.
  • the current descrambling sequence tt [i] is the i-th descrambling sequence
  • the previous descrambling sequence tt [i-1] is the i-1 descrambling sequence.
  • the predetermined bit set is the 6th to 13th bits, the current original data is Din [i], the current scrambled data is Dout [i], and the number of bits of the current scrambled data and the current original data are both 8.
  • the number of bits of the current descrambling sequence and the previous descrambling sequence are both 16, and the first bit set is 0-14th, and the second bit is The set is the 1st to 15th bits, the third set is the 15th bit, and the feature bit set includes the 0, 1, 3, and 12 bits, and the feature bits belong to the first 1/4 or the last 1/4 of the sequence.
  • the generator polynomial G (x) of LFSR is X 16 4X 12 4X 3 4X41.
  • the first term X 16 in the formula indicates that the number of bits of a single descrambling sequence is 16.
  • the current descrambling sequence tt [i] is the i-th descrambling sequence
  • the previous descrambling sequence tt [i-1] is the i-1 descrambling sequence
  • the initial value of the descrambling sequence tt [0] is 1101000000001000.
  • the predetermined bit set is the 6th to 13th bits, the current original data is Din [i], the current scrambled data is Dout [i], and the number of bits of the current scrambled data and the current original data are both 8.
  • the sending end after scrambling, the probability of low quality scrambled data is greatly reduced, and it can be directly used for transmission. However, low-quality scrambling data is still possible.
  • the sending end may further encode the scrambled data after scrambling, and correspondingly, the receiving end may perform descrambling after decoding. The process of decoding before descrambling is described below with reference to the drawings, and the same parts as those in the foregoing embodiment are not described again.
  • another embodiment of the descrambling method of this application includes:
  • S12 Perform an exclusive-OR operation on a specific bit and an identification bit in the received data to determine whether the received data has undergone quality adjustment.
  • the received data can be data received by the receiving end, which is undecoded and descrambled data, and the number of bits can be determined according to the actual transmission requirements, such as 9 bits, 17 bits, and so on.
  • the number of bits in the received data is greater than the number of bits in the current scrambled data.
  • This quality criterion may be related to consecutive bits having the same logical value in the current scrambling code data.
  • the size of the threshold can be related to the number of digits in the current scrambling code Half plus a positive integer.
  • the received data includes an identification bit and a specific bit, which is used to distinguish whether the current scrambled data has undergone quality adjustment.
  • An exclusive OR operation can be performed on a specific bit and an identification bit in the received data to obtain an operation result, and then according to the operation result, it is determined whether the current scrambling code data has undergone quality adjustment.
  • the operation result is not equal to 1 (that is, equal to 0), which means that the specific bit and the identification bit are the same, then it is determined that the current scrambling code data has undergone quality adjustment. It is determined that the current scrambling code data has not undergone quality adjustment.
  • the correspondence between which operation result is selected and the result of the quality adjustment judgment can be determined by the assignment method of the identification bit selected by the transmitting end in the encoding process.
  • the conversion process corresponds to the quality adjustment process in the encoding process at the transmitting end, so that some bits in the quality-adjusted received data are restored to the current scrambling code data to obtain the adjusted data. Then jump to S15.
  • S15 Ignore the identification bits in the output received data or adjustment data to form the current scrambling code data.
  • the received data directly output is the combination of the current scrambled data and the flag bit; if the current scrambled data has undergone quality adjustment, the adjusted data output after the received data is converted is the current scrambled data.
  • S16 Descramble the current scrambling code data by using a predetermined bit set in the current descrambling sequence to obtain the current original data.
  • the receiving end decodes the received data first and then descrambles. Since the probability of the data quality after the scrambling of the transmitting end does not meet the standard is greatly reduced, the probability of the need for quality adjustment is greatly reduced. The probability of converting received data is also greatly reduced, thereby improving the real-time nature of the decoding process.
  • an embodiment of the descrambling device of the present application includes a processor 110.
  • the descrambling device may further include a memory (not shown).
  • the processor 110 controls the operation of the descrambling device.
  • the processor 110 may also be referred to as a CPU (Central Processing Unit).
  • the processor 110 may be an integrated circuit chip and has a processing capability of a signal sequence.
  • the processor 110 may also be a general-purpose processor, a digital signal sequence processor (DSP), an application specific integrated circuit (ASIC), an off-the-shelf programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, and discrete hardware. Components.
  • a general-purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
  • the processor 110 is configured to execute instructions to implement the method provided by any embodiment and possible combination of the descrambling method of the present application.
  • an embodiment of the readable storage medium of the present application includes a memory 210 that stores instructions that, when executed, implement the method provided by any embodiment and possible combination of the descrambling method of the present application.
  • the memory 210 may include a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a flash memory (Flash), a hard disk, an optical disk, and the like.
  • ROM read-only memory
  • RAM random access memory
  • flash flash memory
  • the disclosed methods and devices may be implemented in other ways.
  • the device implementation described above is only schematic.
  • the division of the modules or units is only a logical function division.
  • multiple units or components may The combination can either be integrated into another system, or some features can be ignored or not implemented.
  • the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, which may be electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, which may be located in one place, or may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the objective of the solution of this embodiment.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may be separately physically included, or two or more units may be integrated into one unit.
  • the above integrated unit may be implemented in the form of hardware or in the form of software functional unit.
  • the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it may be stored in a computer-readable storage medium.
  • the technical solution of the present application is essentially a part that contributes to the existing technology or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium , Including a number of instructions for causing a computer device (which may be a personal computer, a server, or a network device) or a processor to perform all or part of the steps of the method described in each embodiment of the present application.
  • the foregoing storage media include: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disks or optical disks and other media that can store program codes .

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Abstract

本申请公开了一种解扰方法，该方法包括：利用前一解扰序列获取当前解扰序列，其中当前解扰序列的第一位集是由前一解扰序列的第二位集直接赋值得到的，当前解扰序列的第三位集是由前一解扰序列中的特征位集的逻辑运算结果赋值得到的，第三位集由当前解扰序列中除第一位集之外的所有其他位组成，特征位集包括多个特征位，其中至少两个特征位之间的间距大于或等于序列长度的一半；利用当前解扰序列中的预定位集对当前扰码数据进行解扰得到当前原始数据。本申请还公开了一种解扰装置和可读存储介质。

Description

解扰方法、设备及可读存储介质 【技术领域】
本申请涉及数据传输领域，特别是涉及一种解扰方法、设备及可读存储介质。
【背景技术】
在串行数据传输中，传输的数据可以被编码成包含有时钟频率分量的码流，使得接收端可以从码流中提取时钟同步信息，时钟同步信息可以保证接收端按照正确的时序从接收到的信号中再生出原始数据。
实际传输过程中，传输的码流中往往会出现较长的连续相同的逻辑值，这样的码流质量低，会影响接收端提取时钟同步信息，可能出现解码错误(即误码)。此外，规律性较强的码流频谱分布不均匀，某个或者某些频率分量的功率过大，在传输过程中可能造成强电磁干扰。
【发明内容】
本申请主要解决的技术问题是提供一种解扰方法、设备及可读存储介质，能够解决现有技术中的低质量码流带来的解码错误以及规律性强的码流在传输中造成强电磁干扰的问题。
为了解决上述技术问题，本申请提供了一种可读存储介质，存储有指令，指令被执行时实现以下方法：利用前一解扰序列获取当前解扰序列，其中所述当前解扰序列的第一位集是由所述前一解扰序列的第二位集移位赋值得到的，所述当前解扰序列的第三位集是由所述前一解扰序列中的特征位集的逻辑运算结果赋值得到的，所述第三位集由所述当前解扰序列中除所述第一位集之外的所有其他位组成，所述特征位集包括多个特征位，其中至少两个所述特征位之间的间距大于或等于序列长度的一半；利用所述当前解扰序列中的预定位集对当前扰码数据进行解扰得到当前原始数据；其中至少两个相邻的所述特征位之间的间距大于或等于所述序列长度的一半，所述预定位集与所述第三位集没有交集。
为了解决上述技术问题，本申请提供了一种解扰方法，该方法包括：利用前一解扰序列获取当前解扰序列，其中当前解扰序列的第一位集是由前一解扰序列的第二位集直接赋值得到的，当前解扰序列的第三位集是由前一解扰序列中的特征位集的逻辑运算结果赋值得到的，第三位集由当前解扰序列中除第一位集之外的所有其他位组成，特征位集包括多个特征位，其中至少两个特征位之间的间距大于或等于序列长度的一半；利用当前解扰序列中的预定位集对当前扰码数据进行解扰得到当前原始数据。
为了解决上述技术问题，本申请提供了一种解扰装置，该装置包括处理器，处理器用于执行指令以实现前述的方法。
本申请的有益效果是：利用前一解扰序列获取当前解扰序列，其中当前解扰序列的第一位集是由前一解扰序列的第二位集移位赋值得到的，当前解扰序列的第三位集是由前一解扰序列中的特征位集的逻辑运算结果赋值得到的，第三位集由当前解扰序列中除第一位集之外的所有其他位组成，特征位集包括多个特征位，其中至少两个特征位之间的间距大于或等于序列长度的一半；再利用当前解扰序列中的预定位集对当前扰码数据进行解扰得到当前原始数据。上述步骤循环执行，总体而言，解扰序列具有一定的均衡性，即其中的“0”和“1”数量相对均衡，由于解扰序列和加扰序列完全相同，加扰序列也具有同样的特性，使得加扰之后的扰码数据低质量的概率大大降低，并且接近白噪声信号的统计特性，降低误码率并减少传输过程中的电磁干扰。
【附图说明】
图1是本申请解扰方法一实施例的流程示意图；
图2是本申请解扰方法一具体实施例的示意图；
图3是本申请解扰方法另一具体实施例的示意图；
图4是本申请解扰方法另一实施例的流程示意图；
图5是本申请解扰设备一实施例的结构示意图；
图6是本申请可读存储介质一实施例的结构示意图。
【具体实施方式】
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清 楚、完整地描述，以下各实施例中不冲突的可以相互结合。显然，所描述的实施例仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
如图1所示，本申请解扰方法一实施例包括：
S1：利用前一解扰序列获取当前解扰序列。
发送端的原始数据被分为多个位数相同的组，每组被称为一个码字。在传输前，发送端可以利用扰码器生成当前扰码序列以对当前原始数据，即当前码字进行加扰。
解扰一般在接收端进行。接收端在提取出当前扰码数据后，可以利用解扰器生成当前解扰序列以对当前扰码数据进行解扰。扰码器和解扰器可以为线性反馈移位寄存器(Linear feedback shift register，LFSR)，可以由软件或者硬件实现。
当前解扰序列的第一位集是由前一解扰序列的第二位集移位赋值得到的。当前解扰序列的第三位集是由前一解扰序列中的特征位集的逻辑运算结果赋值得到的，逻辑运算一般为异或。第三位集由当前解扰序列中除第一位集之外的所有其他位组成，即以当前解扰序列的所有位为全集，第一位集和第三位集互为对方的补集。前一解扰序列和当前解扰序列长度相同。
特征位集包括多个特征位，其中至少两个特征位之间的间距大于或等于序列长度的一半，序列长度是指前一解扰序列和当前解扰序列的长度。这意味着，至少一个特征位在前一解扰序列的前半部分，至少一个特征位在前一解扰序列的后半部分。可选的，至少两个相邻的特征位之间的间距大于或等于序列长度的一半，例如序列长度为8位，特征位集包括第1、2、7位，其中第2位和第7位之间的间距为5位，大于序列长度的一半。进一步的，特征位可以位于前一解扰序列的前1/4和后1/4。
得到当前解扰序列后，可以采用同样的方法利用当前解扰序列得到下一解扰序列，下一解扰序列可以用于对下一码字的解扰。解扰序列设置有初始值，以用于生成后续的解扰序列。解扰序列的初始值由LFSR的生成多项式决定，多项式中所有系数不为0的项对应的位(以下简称初始位)的逻辑值相同，其余所有位逻辑值相同，且两者的逻辑值相反。特征位集可以与初始位组成的集合完全相同，也可以部分相同。一般而言，初始位中除第三位集反向移位的对应 位之外的其他位均为特征位。从初始值开始，得到的解扰序列依次连接起来，可以形成长周期的序列。一般而言，单个解扰序列的位数为n，对应的长周期为2 n-1。
S2：利用当前解扰序列中的预定位集对当前扰码数据进行解扰得到当前原始数据。
具体的，将当前解扰序列中的预定位集与当前扰码数据逐位进行异或逻辑运算得到当前原始数据。预定位集中位可以是连续的，也可以是不连续的，与当前原始数据进行异或的顺序也并无限制。为保障解扰效果，对于不同的解扰序列，预定位集是固定的。
可选的，预定位集与第三位集没有交集，即预定位集是第一位集的子集，使得每次实际解扰所用的预定位集都是移位赋值得到的，进一步保障其均衡性。
解扰器和加扰器的配置参数完全相同，且二者同步工作，使得对于每一个码字，对其进行加扰的序列和进行解扰的序列都完全相同，预定位集也完全相同。由于异或逻辑运算满足
Figure PCTCN2018111423-appb-000001
因此，将当前解扰序列中的预定位集与当前原始数据逐位进行异或逻辑运算即可得到当前扰码数据。
通过本实施例的实施，利用前一解扰序列获取当前解扰序列，其中当前解扰序列的第一位集是由前一解扰序列的第二位集移位赋值得到的，当前解扰序列的第三位集是由前一解扰序列中的特征位集的逻辑运算结果赋值得到的，第三位集由当前解扰序列中除第一位集之外的所有其他位组成，特征位集包括多个特征位，其中至少两个特征位之间的间距大于或等于序列长度的一半；再利用当前解扰序列中的预定位集对当前扰码数据进行解扰得到当前原始数据。上述步骤循环执行，总体而言，解扰序列具有一定的均衡性，即其中的“0”和“1”数量相对均衡，由于解扰序列和加扰序列完全相同，加扰序列也具有同样的特性，使得加扰之后的扰码数据低质量(即连续相同的逻辑值的数量大于预设阈值)的概率大大降低，并且接近白噪声信号的统计特性，降低误码率并减少传输过程中的电磁干扰。
下面结合附图举例说明具体的解扰过程。
如图2所示，在本申请解扰方法一具体实施例中，当前解扰序列和前一解扰序列的位数均为16，第一位集为第1-15位，第二位集为第0-14位，第三位集为第0位，特征位集包括第3、12、14和15位，特征位均属于序列的前1/4或后1/4。LFSR的生成多项式G(x)为X 16+X 14+X 12+X 3+1，式中的第一个项X 16表 示单个解扰序列的位数为16。
使用逻辑表达式来表达当前解扰序列的获取方式，当前解扰序列tt[i]为第i个解扰序列，前一解扰序列tt[i-1]为第i-1个解扰序列。
tt[i，j]＝tt[i-1，j-1]，j＝1，2，...，15
Figure PCTCN2018111423-appb-000002
其中，
Figure PCTCN2018111423-appb-000003
表示异或逻辑运算。解扰序列的初始值tt[0]为1001000000001010。
预定位集为第6-13位，当前原始数据为Din[i]，当前扰码数据为Dout[i]，当前扰码数据和当前原始数据的位数均为8。
Figure PCTCN2018111423-appb-000004
如图3所示，在本申请解扰方法另一具体实施例中，当前解扰序列和前一解扰序列的位数均为16，第一位集为第0-14位，第二位集为第1-15位，第三位集为第15位，特征位集包括第0、1、3和12位，特征位均属于序列的前1/4或后1/4。LFSR的生成多项式G(x)为X 164X 124X 34X41，式中的第一个项X 16表示单个解扰序列的位数为16。
使用逻辑表达式来表达当前解扰序列的获取方式，当前解扰序列tt[i]为第i个解扰序列，前一解扰序列tt[i-1]为第i-1个解扰序列。
tt[i，j-1]＝tt[i-1，j]，j＝1，2，...，15
Figure PCTCN2018111423-appb-000005
其中，
Figure PCTCN2018111423-appb-000006
表示异或逻辑运算。解扰序列的初始值tt[0]为1101000000001000。
预定位集为第6-13位，当前原始数据为Din[i]，当前扰码数据为Dout[i]，当前扰码数据和当前原始数据的位数均为8。
Figure PCTCN2018111423-appb-000007
在发送端，经过加扰之后，扰码数据低质量的概率大大降低，可以直接用于传输。但仍有可能出现低质量的扰码数据。为了进一步降低误码率，发送端可以在加扰之后进一步对扰码数据进行编码，对应的，接收端解码之后再进行解扰。下面结合附图描述解扰之前先解码的过程，其中与前述实施例相同的部分不再赘述。
如图4所示，本申请解扰方法另一实施例包括：
S11：利用前一解扰序列获取当前解扰序列。
S11与S12-15之间的执行顺序仅为示意而非限制。
S12：对接收数据中的特定位和标识位进行异或逻辑运算以判断接收数据是 否经过了质量调整。
接收数据可以是接收端接收到的数据，为未经解码和解扰的数据，其位数可以根据实际传输需求而定，例如9位、17位等。接收数据的位数大于当前扰码数据的位数。在编码过程中，需要判断当前扰码数据的质量是否满足质量标准，如果不满足则需要对当前扰码数据进行质量调整。该质量标准可以与当前扰码数据中逻辑值相同的连续位有关。一般来说，满足质量标准的当前扰码数据中的逻辑值相同的连续位数不超过一阈值，该阈值的大小可以与当前扰码数据的位数相关，例如当前扰码数据的位数的一半加上一个正整数。
接收数据包括标识位和特定位，用于区分当前扰码数据是否经过了质量调整。标识位和特定位的位数以及在接收数据中的位置并无限制。例如，接收数据的位数为9，特定位可以为第1位，标识位可以为第0位。可以对接收数据中的特定位和标识位进行异或逻辑运算得到运算结果，然后根据运算结果来判断当前扰码数据是否经过了质量调整。
具体的，若运算结果不等于1(即等于0)，意味着特定位和标识位相同，则判定当前扰码数据经过了质量调整，若运算结果等于1，意味着特定位和标识位不同，则判定当前扰码数据未经过质量调整。
当然也可以反过来，即若运算结果等于1，则判定当前扰码数据经过了质量调整，若运算结果不等于1，则判定当前扰码数据未经过质量调整。
实际应用中，选择哪种运算结果和是否经过质量调整的判断结果之间的对应关系可以由发送端在编码过程中选择的标识位的赋值方式决定。
若运算结果表示接收数据经过了质量调整，则跳转到S13；否则跳转到S14。
S13：将当前接收数据转换成调整数据。
一般而言，转换过程与发送端编码过程中的质量调整过程相对应，从而将质量调整后的接收数据中的部分位恢复为当前扰码数据得到调整数据。然后跳转到S15。
S14：直接输出接收数据。
跳转到S15。
S15：将输出的接收数据或调整数据中的标识位忽略以形成当前扰码数据。
若当前扰码数据未经质量调整，直接输出的接收数据为当前扰码数据和标识位的组合；若当前扰码数据经过了质量调整，对接收数据进行了转换之后输出的调整数据为当前扰码数据和标识位的组合。将输出的接收数据或调整数据 中的标识位忽略可以形成当前扰码数据，从而完成解码。
S16：利用当前解扰序列中的预定位集对当前扰码数据进行解扰得到当前原始数据。
在上述实施例中，接收端先对接收数据进行解码再进行解扰，由于发送端加扰之后的数据质量不满足标准的概率大大降低，需要进行质量调整的概率大大降低，相应的接收端需要对接收数据进行转换的概率也大大降低，从而提高解码过程的实时性。
如图5所示，本申请解扰设备一实施例包括：处理器110。除此之外，解扰设备还可以包括存储器(图中未画出)。
处理器110控制解扰设备的操作，处理器110还可以称为CPU(Central Processing Unit，中央处理单元)。处理器110可能是一种集成电路芯片，具有信号序列的处理能力。处理器110还可以是通用处理器、数字信号序列处理器(DSP)、专用集成电路(ASIC)、现成可编程门阵列(FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。
处理器110用于执行指令以实现本申请解扰方法任一实施例及可能的组合所提供的方法。
如图6所示，本申请可读存储介质一实施例包括存储器210，存储器210存储有指令，该指令被执行时实现本申请解扰方法任一实施例及可能的组合所提供的方法。
存储器210可以包括只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、闪存(Flash Memory)、硬盘、光盘等。
在本申请所提供的几个实施例中，应该理解到，所揭露的方法和装置，可以通过其它的方式实现。例如，以上所描述的装置实施方式仅仅是示意性的，例如，所述模块或单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者 也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施方式方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理包括，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
所述集成的单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的全部或部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)或处理器(processor)执行本申请各个实施方式所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述仅为本申请的实施方式，并非因此限制本申请的专利范围，凡是利用本申请说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本申请的专利保护范围内。

Claims (19)

  1. 一种可读存储介质，存储有指令，其中，所述指令被执行时实现以下方法：利用前一解扰序列获取当前解扰序列，其中所述当前解扰序列的第一位集是由所述前一解扰序列的第二位集移位赋值得到的，所述当前解扰序列的第三位集是由所述前一解扰序列中的特征位集的逻辑运算结果赋值得到的，所述第三位集由所述当前解扰序列中除所述第一位集之外的所有其他位组成，所述特征位集包括多个特征位，其中至少两个所述特征位之间的间距大于或等于序列长度的一半；
    利用所述当前解扰序列中的预定位集对当前扰码数据进行解扰得到当前原始数据；
    其中至少两个相邻的所述特征位之间的间距大于或等于所述序列长度的一半，所述预定位集与所述第三位集没有交集。
  2. 一种解扰方法，其中，所述方法包括：
    利用前一解扰序列获取当前解扰序列，其中所述当前解扰序列的第一位集是由所述前一解扰序列的第二位集移位赋值得到的，所述当前解扰序列的第三位集是由所述前一解扰序列中的特征位集的逻辑运算结果赋值得到的，所述第三位集由所述当前解扰序列中除所述第一位集之外的所有其他位组成，所述特征位集包括多个特征位，其中至少两个所述特征位之间的间距大于或等于序列长度的一半；
    利用所述当前解扰序列中的预定位集对当前扰码数据进行解扰得到当前原始数据。
  3. 根据权利要求2所述的方法，其中，至少两个相邻的所述特征位之间的间距大于或等于所述序列长度的一半。
  4. 根据权利要求3所述的方法，其中，所述特征位位于所述前一解扰序列的前1/4和后1/4。
  5. 根据权利要求2所述的方法，其中，所述预定位集与所述第三位集没有交集。
  6. 根据权利要求2所述的方法，其中，所述当前解扰序列和所述前一解扰序列的位数均为16，所述第一位集为第1-15位，所述第二位集为第0-14位，所述第三位集为第0位，所述特征位集包括第3、12、14和15位。
  7. 根据权利要求6所述的方法，其中，
    所述预定位集为第6-13位。
  8. 根据权利要求2所述的方法，其中，所述当前解扰序列和所述前一解扰序列的位数均为16，所述第一位集为第0-14位，所述第二位集为第1-15位，所述第三位集为第15位，所述特征位集包括第0、1、3和12位。
  9. 根据权利要求8所述的方法，其中，
    所述预定位集为第6-13位。
  10. 根据权利要求2所述的方法，其中，所述利用所述当前解扰序列中的预定位集对当前扰码数据进行解扰得到当前原始数据包括：
    将所述当前解扰序列中的预定位集与所述当前扰码数据逐位进行异或逻辑运算得到所述当前原始数据。
  11. 根据权利要求2所述的方法，其中，所述利用所述当前解扰序列中的预定位集对当前扰码数据进行解扰得到当前原始数据之前进一步包括：
    对所述接收数据中的特定位和标识位进行异或逻辑运算以判断所述接收数据是否经过了质量调整；
    若运算结果表示所述接收数据经过了所述质量调整，则将所述当前接收数据转换成调整数据，若所述运算结果表示所述接收数据未经过所述质量调整，则直接输出所述接收数据；
    将输出的所述接收数据或所述调整数据中的所述标识位忽略以形成所述当前扰码数据。
  12. 一种解扰设备，其中，包括处理器，所述处理器用于执行指令以利用前一解扰序列获取当前解扰序列，其中所述当前解扰序列的第一位集是由所述前一解扰序列的第二位集移位赋值得到的，所述当前解扰序列的第三位集是由所述前一解扰序列中的特征位集的逻辑运算结果赋值得到的，所述第三位集由所述当前解扰序列中除所述第一位集之外的所有其他位组成，所述特征位集包括多个特征位，其中至少两个所述特征位之间的间距大于或等于序列长度的一半；利用所述当前解扰序列中的预定位集对当前扰码数据进行解扰得到当前原始数据。
  13. 根据权利要求12所述的解扰设备，其中，至少两个相邻的所述特征位之间的间距大于或等于所述序列长度的一半。
  14. 根据权利要求13所述的解扰设备，其中，所述特征位位于所述前一解 扰序列的前1/4和后1/4。
  15. 根据权利要求12所述的解扰设备，其中，所述预定位集与所述第三位集没有交集。
  16. 根据权利要求12所述的解扰设备，其中，所述当前扰码序列和所述前一扰码序列的位数均为16；
    所述第一位集为第1-15位，所述第二位集为第0-14位，所述第三位集为第0位，所述特征位集包括第3、12、14和15位；
    或所述第一位集为第0-14位，所述第二位集为第1-15位，所述第三位集为第15位，所述特征位集包括第0、1、3和12位。
  17. 根据权利要求16所述的解扰设备，其中，所述预定位集为第6-13位。
  18. 根据权利要求12所述的解扰设备，其中，所述处理器具体用于执行指令以将所述当前解扰序列中的预定位集与所述当前扰码数据逐位进行异或逻辑运算得到所述当前原始数据。
  19. 根据权利要求12所述的解扰设备，其中，所述处理器进一步用于执行指令以在所述利用所述当前解扰序列中的预定位集对当前扰码数据进行解扰得到当前原始数据之前对所述接收数据中的特定位和标识位进行异或逻辑运算以判断所述接收数据是否经过了质量调整；若运算结果表示所述接收数据经过了所述质量调整，则将所述当前接收数据转换成调整数据，若所述运算结果表示所述接收数据未经过所述质量调整，则直接输出所述接收数据；将输出的所述接收数据或所述调整数据中的所述标识位忽略以形成所述当前扰码数据。
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