WO2019237624A1 - 加扰方法、设备及可读存储介质 - Google Patents

加扰方法、设备及可读存储介质 Download PDF

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Publication number
WO2019237624A1
WO2019237624A1 PCT/CN2018/111419 CN2018111419W WO2019237624A1 WO 2019237624 A1 WO2019237624 A1 WO 2019237624A1 CN 2018111419 W CN2018111419 W CN 2018111419W WO 2019237624 A1 WO2019237624 A1 WO 2019237624A1
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Prior art keywords
current
bit set
scrambling code
bits
sequence
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PCT/CN2018/111419
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English (en)
French (fr)
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王拂依
张裕桦
曹丹
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深圳市华星光电技术有限公司
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Publication of WO2019237624A1 publication Critical patent/WO2019237624A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03828—Arrangements for spectral shaping; Arrangements for providing signals with specified spectral properties
    • H04L25/03866—Arrangements for spectral shaping; Arrangements for providing signals with specified spectral properties using scrambling

Definitions

  • the present application relates to the field of data transmission, and in particular, to a scrambling method, a device, and a readable storage medium.
  • the transmitted data can be encoded into a code stream containing a clock frequency component, so that the receiver can extract clock synchronization information from the code stream.
  • the clock synchronization information can ensure that the receiver receives The original data is reproduced from the signal.
  • the transmitted code stream In the actual transmission process, the transmitted code stream often has a long continuous same logic value. Such a low code stream quality will affect the clock synchronization information extracted by the receiving end, and decoding errors (ie, bit errors) may occur. In addition, the frequency distribution of the code stream with strong regularity is uneven, and the power of one or some frequency components is too large, which may cause strong electromagnetic interference during the transmission process.
  • the technical problem mainly solved by this application is to provide a scrambling method, device and readable storage medium, which can solve the decoding errors caused by the low quality code stream in the prior art and the strong regular code stream causes strong transmission during transmission. Problems with electromagnetic interference.
  • this application provides a readable storage medium that stores instructions.
  • the following method is implemented: using a previous scrambling sequence to obtain a current scrambling sequence, wherein the first A bit set is obtained by shifting and assigning a second bit set of the previous scrambling code sequence, and a third bit set of the current scrambling code sequence is a logic of a characteristic bit set in the previous scrambling code sequence Resulting from the operation result assignment, the third bit set is composed of all other bits in the current scrambling code sequence except the first bit set, and the characteristic bit set includes multiple characteristic bits, of which at least two The distance between the characteristic bits is greater than or equal to half the sequence length; the current original data is scrambled by using a predetermined bit set in the current scrambling code sequence to obtain the current scrambling code data; at least two adjacent ones of the The spacing between the characteristic bits is greater than or equal to half of the sequence length, and the predetermined bit set has no intersection with the third bit set.
  • the present application provides a scrambling method, which includes: obtaining a current scrambling sequence by using a previous scrambling sequence, wherein a first bit set of the current scrambling sequence is determined by the previous scrambling sequence.
  • the second bit set is directly assigned.
  • the third bit set of the current scrambling sequence is assigned by the logical operation result of the characteristic bit set in the previous scrambling sequence.
  • the third bit set is divided by the current scrambling sequence. All other bits except bit set, the characteristic bit set includes multiple characteristic bits, where the distance between at least two characteristic bits is greater than or equal to half of the sequence length; using a predetermined bit set in the current scrambling code
  • the original data is scrambled to obtain the current scrambled code data.
  • the present application provides a scrambling device, which includes a processor, and the processor is configured to execute instructions to implement the foregoing method.
  • the beneficial effect of the present application is that the current scrambling code sequence is obtained by using the previous scrambling code sequence, where the first bit set of the current scrambling code sequence is obtained by shifting and assigning the second bit set of the previous scrambling code sequence,
  • the third bit set of the sequence is obtained from the logical operation result of the characteristic bit set in the previous scrambling code sequence.
  • the third bit set is composed of all other bits in the current scrambling code sequence except the first bit set.
  • the bit set includes a plurality of characteristic bits, wherein a distance between at least two characteristic bits is greater than or equal to half of a sequence length; and the current original data is scrambled by using a predetermined bit set in the current scrambling code sequence to obtain the current scrambling code data.
  • the scrambling code sequence has a certain balance, that is, the number of "0" and "1" is relatively balanced, the probability of low quality of the scrambled data after scrambling is greatly reduced, and it is close to white noise.
  • the statistical characteristics of the signal reduce the bit error rate and reduce electromagnetic interference during transmission.
  • FIG. 1 is a schematic flowchart of an embodiment of a scrambling method according to the present application
  • FIG. 2 is a schematic diagram of a specific embodiment of a scrambling method according to the present application.
  • FIG. 3 is a schematic diagram of another specific embodiment of a scrambling method according to the present application.
  • FIG. 4 is a schematic flowchart of another embodiment of a scrambling method according to the present application.
  • FIG. 5 is a schematic flowchart of another embodiment of a scrambling method according to the present application.
  • FIG. 6 is a schematic structural diagram of an embodiment of a scrambling device according to the present application.
  • FIG. 7 is a schematic structural diagram of an embodiment of a readable storage medium of the present application.
  • an embodiment of the scrambling method of this application includes:
  • Scrambling is generally performed at the transmitting end.
  • the original data to be transmitted is divided into multiple groups with the same number of bits, and each group is called a codeword.
  • a scrambler can be used to generate the current scrambling code sequence to scramble the current original data, that is, the current codeword.
  • the scrambler can be a linear feedback shift register (LFSR), which can be implemented by software or hardware.
  • LFSR linear feedback shift register
  • the first bit set of the current scrambling code sequence is obtained by shifting and assigning the second bit set of the previous scrambling code sequence.
  • the third bit set of the current scrambling code sequence is obtained from the logical operation result of the characteristic bit set in the previous scrambling code sequence.
  • the logical operation is generally XOR.
  • the third bit set consists of all other bits in the current scrambling sequence except the first bit set, that is, all bits of the current scrambling sequence are the complete set, and the first bit set and the third bit set are complements of each other. .
  • the previous scrambling sequence is the same length as the current scrambling sequence.
  • the feature bit set includes a plurality of feature bits, wherein a distance between at least two feature bits is greater than or equal to half a sequence length.
  • the sequence length refers to a length of a previous scrambling sequence and a current scrambling sequence. This means that at least one signature is in the first half of the previous scrambling sequence, and at least one signature is in the second half of the previous scrambling sequence.
  • the distance between at least two adjacent feature bits is greater than or equal to half the sequence length, for example, the sequence length is 8 bits
  • the feature bit set includes the first, second, and seventh bits, where the second and seventh bits
  • the spacing between the bits is 5 bits, which is more than half the sequence length.
  • the characteristic bits may be located at the first 1/4 and the last 1/4 of the previous scrambling code sequence.
  • the next scrambling code sequence can be used to scramble the next codeword.
  • the scrambling code sequence is provided with an initial value for generating a subsequent scrambling code sequence.
  • the initial value of the scrambling sequence is determined by the LFSR generator polynomial.
  • the bits in the polynomial whose coefficients are not 0 (hereinafter referred to as the initial bits) have the same logical value, and all other bits have the same logical value, and the logical values of the two are opposite .
  • the feature bit set may be exactly the same as the set of initial bits, or it may be partially the same.
  • the bits other than the corresponding bits of the third bit set being reversely shifted are all characteristic bits.
  • the obtained scrambling code sequences are connected in order to form a long-period sequence.
  • the number of bits of a single scrambling code sequence is n, and the corresponding long period is 2 n - 1.
  • S2 Use the predetermined bit set in the current scrambling code sequence to scramble the current original data to obtain the current scrambling code data.
  • the predetermined set of bits in the current scrambling code sequence is bitwise XORed with the current original data to obtain the current scrambling code data.
  • the bits in the predetermined bit set may be continuous or discontinuous, and the order of exclusive ORing with the current original data is not limited. To ensure the scrambling effect, the predetermined bit set is fixed for different scrambling code sequences.
  • the predetermined bit set is a subset of the first bit set, so that the predetermined bit set used for each actual scrambling is obtained by shift assignment, further ensuring its Balance.
  • the receiving end may use a descrambler to generate a current descrambling sequence for descrambling.
  • the configuration parameters of the descrambler and the scrambler are completely the same, and the two work in synchronization, so that for each codeword, the sequence for scrambling and the sequence for descrambling are completely the same. Since the exclusive OR operation satisfies Therefore, the current original data can be obtained by performing an exclusive-OR logical operation on the predetermined set of bits in the current descrambling sequence and the current scrambling code data bit by bit.
  • the previous scrambling code sequence is used to obtain the current scrambling code sequence.
  • the first bit set of the current scrambling code sequence is obtained by shifting and assigning the second bit set of the previous scrambling code sequence.
  • the third bit set of the sequence is obtained from the logical operation result of the characteristic bit set in the previous scrambling code sequence.
  • the third bit set is composed of all other bits in the current scrambling code sequence except the first bit set.
  • the bit set includes a plurality of characteristic bits, wherein a distance between at least two characteristic bits is greater than or equal to half of a sequence length; and then the current original data is scrambled by using a predetermined bit set in the current scrambling code sequence to obtain the current scrambled data.
  • the scrambling code sequence has a certain balance, that is, the number of "0" and "1" is relatively balanced, and the scrambled data after scrambling is of low quality (that is, the number of consecutive same logical values (Larger than the preset threshold), greatly reduced, and close to the statistical characteristics of white noise signals, reducing the bit error rate and reducing electromagnetic interference during transmission.
  • the number of bits of the current scrambling code sequence and the previous scrambling code sequence are both 16, the first bit set is 1-15th bit, and the second bit set is It is the 0th to 14th bits, the third bit set is the 0th bit, and the characteristic bit set includes the 3rd, 12th, 14th, and 15th bits, and the characteristic bits belong to the first 1/4 or the last 1/4 of the sequence.
  • the generator polynomial G (x) of LFSR is X 16 + X 14 + X 12 + X 3 +1.
  • the first term X 16 in the formula indicates that the number of bits of a single scrambling code sequence is 16.
  • a logical expression is used to express the current scrambling sequence acquisition method.
  • the current scrambling sequence tt [i] is the i-th scrambling sequence
  • the previous scrambling sequence tt [i-1] is the i-1 scrambling sequence. .
  • the predetermined bit set is the 6th to 13th bits, the current original data is Din [i], the current scrambled data is Dout [i], and the number of bits of the current original data and the current scrambled data is 8.
  • the number of bits of the current scrambling code sequence and the previous scrambling code sequence are both 16, the first bit set is the 0-14th bit, and the second bit The set is the 1st to 15th bits, the third set is the 15th bit, and the feature bit set includes the 0, 1, 3, and 12 bits, and the feature bits belong to the first 1/4 or the last 1/4 of the sequence.
  • the generator polynomial G (x) of LFSR is X 16 + X 12 + X 3 + X + 1.
  • the first term X 16 in the formula indicates that the number of bits of a single scrambling code sequence is 16.
  • a logical expression is used to express the current scrambling sequence acquisition method.
  • the current scrambling sequence tt [i] is the i-th scrambling sequence
  • the previous scrambling sequence tt [i-1] is the i-1 scrambling sequence. .
  • the predetermined bit set is the 6th to 13th bits, the current original data is Din [i], the current scrambled data is Dout [i], and the number of bits of the current original data and the current scrambled data is 8.
  • the sending end may further encode the scrambled data after scrambling, and correspondingly, the receiving end may perform descrambling after decoding.
  • another embodiment of the scrambling method of this application includes:
  • S12 Use a predetermined bit set in the current scrambling code sequence to scramble the current original data to obtain the current scrambling code data.
  • the quality judgment may be to judge whether the quality of the current scrambling code data meets a preset quality standard.
  • This quality criterion may be related to consecutive bits having the same logical value in the current scrambling code data.
  • the size of the threshold can be related to the number of digits in the current scrambling code. Half plus a positive integer. Specific quality standards are based on actual needs and are not limited here.
  • the quality of the current scrambling code data does not need to be improved, and can be directly output.
  • the purpose of the conversion is to improve the quality of the current scrambled data.
  • the adjustment data obtained after conversion can meet preset quality standards. After outputting the adjustment data, jump to S16.
  • S16 Combine the output current scrambling code data or adjustment data with an identification bit to form output data.
  • the number of flag bits can be 1 or more.
  • the identification bit can be directly inserted into the current scrambling code data / adjustment data before / medium / backward to form output data, or at least a part of the current scrambling code data / adjustment data can be logically inserted into the identification bit, or Other combinations are used, which are not limited here.
  • the combination of the identification bit and the current scrambling data / adjustment data should not affect the encoding quality, that is, the output data still meets the preset quality standard.
  • the value of the identification bit may be related to whether the current scrambling code data or adjustment data is combined with it, so that the receiving end can determine whether the quality adjustment has been performed during the decoding process.
  • another embodiment of the scrambling method of this application includes:
  • the quality judgment may be to judge whether the quality of the current scrambling code data meets a preset quality standard.
  • This quality criterion may be related to consecutive bits having the same logical value in the current scrambling code data.
  • the size of the threshold can be related to the number of digits in the current scrambling code Half plus a positive integer. Specific quality standards are based on actual needs and are not limited here.
  • the number of flag bits can be 1 or more.
  • the identification bits may be directly inserted before, during, or after the current scrambled data to form the first encoded data, or at least part of the bits of the current scrambled data may be logically inserted into the identification bits, or other combinations may be used. There are no restrictions here. Generally speaking, the combination of the identification bit and the current scrambling code data should not affect the scrambling quality, that is, the first encoded data still meets a preset quality standard.
  • S25 Perform a logical operation on the current scrambling code data to output the second encoded data.
  • the number of bits of the second encoded data is greater than the current scrambled data. Logical operations can improve the quality of the current scrambled data. Generally, the second encoded data obtained after the logical operation can satisfy a preset quality standard.
  • the original data is scrambled first and then encoded. Since the probability that the quality of the data after the scrambling does not meet the standard is greatly reduced, the probability of the need for quality adjustment is greatly reduced, thereby improving the real-time nature of the encoding process. .
  • an embodiment of the scrambling device of the present application includes: a processor 110.
  • the scrambling device may further include a memory (not shown).
  • the processor 110 controls the operation of the scrambling device.
  • the processor 110 may also be referred to as a CPU (Central Processing Unit).
  • the processor 110 may be an integrated circuit chip and has a processing capability of a signal sequence.
  • the processor 110 may also be a general-purpose processor, a digital signal sequence processor (DSP), an application specific integrated circuit (ASIC), an off-the-shelf programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, and discrete hardware. Components.
  • a general-purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
  • the processor 110 is configured to execute instructions to implement the method provided by any embodiment and possible combination of the scrambling method of the present application.
  • an embodiment of the readable storage medium of the present application includes a memory 210 that stores instructions that, when executed, implement the method provided by any embodiment and possible combination of the scrambling method of the present application.
  • the memory 210 may include a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a flash memory (Flash), a hard disk, an optical disk, and the like.
  • ROM read-only memory
  • RAM random access memory
  • flash flash memory
  • the disclosed methods and devices may be implemented in other ways.
  • the device implementation described above is only schematic.
  • the division of the modules or units is only a logical function division.
  • multiple units or components may The combination can either be integrated into another system, or some features can be ignored or not implemented.
  • the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, which may be electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the objective of the solution of this embodiment.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may be separately physically included, or two or more units may be integrated into one unit.
  • the above integrated unit may be implemented in the form of hardware or in the form of software functional unit.
  • the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it may be stored in a computer-readable storage medium.
  • the technical solution of the present application is essentially a part that contributes to the existing technology or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium , Including a number of instructions for causing a computer device (which may be a personal computer, a server, or a network device) or a processor to perform all or part of the steps of the method described in each embodiment of the present application.
  • the foregoing storage media include: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disks or optical disks and other media that can store program codes .

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Abstract

本申请公开了一种加扰方法，该方法包括：利用前一扰码序列获取当前扰码序列，其中当前扰码序列的第一位集是由前一扰码序列的第二位集直接赋值得到的，当前扰码序列的第三位集是由前一扰码序列中的特征位集的逻辑运算结果赋值得到的，第三位集由当前扰码序列中除第一位集之外的所有其他位组成，特征位集包括多个特征位，其中至少两个特征位之间的间距大于或等于序列长度的一半；利用当前扰码序列中的预定位集对当前原始数据进行加扰得到当前扰码数据。本申请还公开了一种加扰装置和可读存储介质。

Description

加扰方法、设备及可读存储介质 【技术领域】
本申请涉及数据传输领域，特别是涉及一种加扰方法、设备及可读存储介质。
【背景技术】
在串行数据传输中，传输的数据可以被编码成包含有时钟频率分量的码流，使得接收端可以从码流中提取时钟同步信息，时钟同步信息可以保证接收端按照正确的时序从接收到的信号中再生出原始数据。
实际传输过程中，传输的码流中往往会出现较长的连续相同的逻辑值，这样的码流质量低，会影响接收端提取时钟同步信息，可能出现解码错误(即误码)。此外，规律性较强的码流频谱分布不均匀，某个或者某些频率分量的功率过大，在传输过程中可能造成强电磁干扰。
【发明内容】
本申请主要解决的技术问题是提供一种加扰方法、设备及可读存储介质，能够解决现有技术中的低质量码流带来的解码错误以及规律性强的码流在传输中造成强电磁干扰的问题。
为了解决上述技术问题，本申请提供了一种可读存储介质，存储有指令，指令被执行时实现以下方法：利用前一扰码序列获取当前扰码序列，其中所述当前扰码序列的第一位集是由所述前一扰码序列的第二位集移位赋值得到的，所述当前扰码序列的第三位集是由所述前一扰码序列中的特征位集的逻辑运算结果赋值得到的，所述第三位集由所述当前扰码序列中除所述第一位集之外的所有其他位组成，所述特征位集包括多个特征位，其中至少两个所述特征位之间的间距大于或等于序列长度的一半；利用所述当前扰码序列中的预定位集对当前原始数据进行加扰得到当前扰码数据；其中至少两个相邻的所述特征位之间的间距大于或等于所述序列长度的一半，所述预定位集与所述第三位集没有交集。
为了解决上述技术问题，本申请提供了一种加扰方法，该方法包括：利用前一扰码序列获取当前扰码序列，其中当前扰码序列的第一位集是由前一扰码序列的第二位集直接赋值得到的，当前扰码序列的第三位集是由前一扰码序列中的特征位集的逻辑运算结果赋值得到的，第三位集由当前扰码序列中除第一位集之外的所有其他位组成，特征位集包括多个特征位，其中至少两个特征位之间的间距大于或等于序列长度的一半；利用当前扰码序列中的预定位集对当前原始数据进行加扰得到当前扰码数据。
为了解决上述技术问题，本申请提供了一种加扰装置，该装置包括处理器，处理器用于执行指令以实现前述的方法。
本申请的有益效果是：利用前一扰码序列获取当前扰码序列，其中当前扰码序列的第一位集是由前一扰码序列的第二位集移位赋值得到的，当前扰码序列的第三位集是由前一扰码序列中的特征位集的逻辑运算结果赋值得到的，第三位集由当前扰码序列中除第一位集之外的所有其他位组成，特征位集包括多个特征位，其中至少两个特征位之间的间距大于或等于序列长度的一半；再利用当前扰码序列中的预定位集对当前原始数据进行加扰得到当前扰码数据。上述步骤循环执行，总体而言，扰码序列具有一定的均衡性，即其中的“0”和“1”数量相对均衡，加扰之后的扰码数据低质量的概率大大降低，并且接近白噪声信号的统计特性，降低误码率并减少传输过程中的电磁干扰。
【附图说明】
图1是本申请加扰方法一实施例的流程示意图；
图2是本申请加扰方法一具体实施例的示意图；
图3是本申请加扰方法另一具体实施例的示意图；
图4是本申请加扰方法另一实施例的流程示意图；
图5是本申请加扰方法又一实施例的流程示意图；
图6是本申请加扰设备一实施例的结构示意图；
图7是本申请可读存储介质一实施例的结构示意图。
【具体实施方式】
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清 楚、完整地描述，以下各实施例中不冲突的可以相互结合。显然，所描述的实施例仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
如图1所示，本申请加扰方法一实施例包括：
S1：利用前一扰码序列获取当前扰码序列。
加扰一般在发送端进行。待发送的原始数据被分为多个位数相同的组，每组被称为一个码字。在传输前，可以利用扰码器生成当前扰码序列以对当前原始数据，即当前码字进行加扰。扰码器可以为线性反馈移位寄存器(Linear feedback shift register，LFSR)，可以由软件或者硬件实现。
当前扰码序列的第一位集是由前一扰码序列的第二位集移位赋值得到的。当前扰码序列的第三位集是由前一扰码序列中的特征位集的逻辑运算结果赋值得到的，逻辑运算一般为异或。第三位集由当前扰码序列中除第一位集之外的所有其他位组成，即以当前扰码序列的所有位为全集，第一位集和第三位集互为对方的补集。前一扰码序列和当前扰码序列长度相同。
特征位集包括多个特征位，其中至少两个特征位之间的间距大于或等于序列长度的一半，序列长度是指前一扰码序列和当前扰码序列的长度。这意味着，至少一个特征位在前一扰码序列的前半部分，至少一个特征位在前一扰码序列的后半部分。可选的，至少两个相邻的特征位之间的间距大于或等于序列长度的一半，例如序列长度为8位，特征位集包括第1、2、7位，其中第2位和第7位之间的间距为5位，大于序列长度的一半。进一步的，特征位可以位于前一扰码序列的前1/4和后1/4。
得到当前扰码序列后，可以采用同样的方法利用当前扰码序列得到下一扰码序列，下一扰码序列可以用于对下一码字的加扰。扰码序列设置有初始值，以用于生成后续的扰码序列。扰码序列的初始值由LFSR的生成多项式决定，多项式中所有系数不为0的项对应的位(以下简称初始位)的逻辑值相同，其余所有位逻辑值相同，且两者的逻辑值相反。特征位集可以与初始位组成的集合完全相同，也可以部分相同。一般而言，初始位中除第三位集反向移位的对应位之外的其他位均为特征位。从初始值开始，得到的扰码序列依次连接起来，可以形成长周期的序列。一般而言，单个扰码序列的位数为n，对应的长周期为2 n -1。
S2：利用当前扰码序列中的预定位集对当前原始数据进行加扰得到当前扰码数据。
具体的，将当前扰码序列中的预定位集与当前原始数据逐位进行异或逻辑运算得到当前扰码数据。预定位集中的位可以是连续的，也可以是不连续的，与当前原始数据进行异或的顺序也并无限制。为保障加扰效果，对于不同的扰码序列，预定位集是固定的。
可选的，预定位集与第三位集没有交集，即预定位集是第一位集的子集，使得每次实际加扰所用的预定位集都是移位赋值得到的，进一步保障其均衡性。
对应的，接收端在提取到当前扰码数据后，可以利用解扰器生成当前解扰序列进行解扰。解扰器和加扰器的配置参数完全相同，且二者同步工作，使得对于每一个码字，对其进行加扰的序列和进行解扰的序列都完全相同。由于异或逻辑运算满足
Figure PCTCN2018111419-appb-000001
因此，将当前解扰序列中的预定位集与当前扰码数据逐位进行异或逻辑运算即可得到当前原始数据。
通过本实施例的实施，利用前一扰码序列获取当前扰码序列，其中当前扰码序列的第一位集是由前一扰码序列的第二位集移位赋值得到的，当前扰码序列的第三位集是由前一扰码序列中的特征位集的逻辑运算结果赋值得到的，第三位集由当前扰码序列中除第一位集之外的所有其他位组成，特征位集包括多个特征位，其中至少两个特征位之间的间距大于或等于序列长度的一半；再利用当前扰码序列中的预定位集对当前原始数据进行加扰得到当前扰码数据。上述步骤循环执行，总体而言，扰码序列具有一定的均衡性，即其中的“0”和“1”数量相对均衡，加扰之后的扰码数据低质量(即连续相同的逻辑值的数量大于预设阈值)的概率大大降低，并且接近白噪声信号的统计特性，降低误码率并减少传输过程中的电磁干扰。
下面结合附图举例说明具体的加扰过程。
如图2所示，在本申请加扰方法一具体实施例中，当前扰码序列和前一扰码序列的位数均为16，第一位集为第1-15位，第二位集为第0-14位，第三位集为第0位，特征位集包括第3、12、14和15位，特征位均属于序列的前1/4或后1/4。LFSR的生成多项式G(x)为X 16+X 14+X 12+X 3+1，式中的第一个项X 16表示单个扰码序列的位数为16。
使用逻辑表达式来表达当前扰码序列的获取方式，当前扰码序列tt[i]为第i个扰码序列，前一扰码序列tt[i-1]为第i-1个扰码序列。
tt[i，j]＝tt[i-1，j-1]，j＝1，2，...，15
Figure PCTCN2018111419-appb-000002
其中，
Figure PCTCN2018111419-appb-000003
表示异或逻辑运算。扰码序列的初始值tt[0]为1001000000001010。
预定位集为第6-13位，当前原始数据为Din[i]，当前扰码数据为Dout[i]，当前原始数据和当前扰码数据的位数均为8。
Figure PCTCN2018111419-appb-000004
如图3所示，在本申请加扰方法另一具体实施例中，当前扰码序列和前一扰码序列的位数均为16，第一位集为第0-14位，第二位集为第1-15位，第三位集为第15位，特征位集包括第0、1、3和12位，特征位均属于序列的前1/4或后1/4。LFSR的生成多项式G(x)为X 16+X 12+X 3+X+1，式中的第一个项X 16表示单个扰码序列的位数为16。
使用逻辑表达式来表达当前扰码序列的获取方式，当前扰码序列tt[i]为第i个扰码序列，前一扰码序列tt[i-1]为第i-1个扰码序列。
tt[i，j-1]＝tt[i-1，j]，j＝1，2，...，15
Figure PCTCN2018111419-appb-000005
其中，
Figure PCTCN2018111419-appb-000006
表示异或逻辑运算。扰码序列的初始值tt[0]为1101000000001000。
预定位集为第6-13位，当前原始数据为Din[i]，当前扰码数据为Dout[i]，当前原始数据和当前扰码数据的位数均为8。
Figure PCTCN2018111419-appb-000007
经过加扰之后，扰码数据低质量的概率大大降低，可以直接用于传输。但仍有可能出现低质量的扰码数据。为了进一步降低误码率，发送端可以在加扰之后进一步对扰码数据进行编码，对应的，接收端解码之后再进行解扰。下面结合附图描述加扰之后编码的过程，其中与前述实施例相同的部分不再赘述。
如图4所示，本申请加扰方法另一实施例包括：
S 11：利用前一扰码序列获取当前扰码序列。
S12：利用当前扰码序列中的预定位集对当前原始数据进行加扰得到当前扰码数据。
S13：对当前扰码数据进行质量判断。
质量判断可以为判断当前扰码数据的质量是否满足预设的质量标准。该质量标准可以与当前扰码数据中逻辑值相同的连续位有关。一般来说，满足质量标准的当前扰码数据中的逻辑值相同的连续位数不超过一阈值，该阈值的大小 可以与当前扰码数据的位数相关，例如当前扰码数据的位数的一半加上一个正整数。具体的质量标准根据实际需要而定，在此不做限制。
经过质量判断后，若当前扰码数据满足质量标准，则跳转到S14；若当前扰码数据不满足质量标准，则跳转到S15。
S14：输出当前扰码数据。
当前扰码数据满足预设的质量标准的情况下，不需要提高当前扰码数据的质量，可以直接输出。
跳转到S16。
S15：对当前扰码数据进行转换，并输出调整数据。
转换的目的是为了提高当前扰码数据的质量。一般而言，转换之后得到的调整数据可以满足预设的质量标准。输出调整数据后跳转到S16。
S16：将输出的当前扰码数据或调整数据与标识位进行组合，以形成输出数据。
标识位的位数可以为1，也可以为更多。具体的，可以将标识位直接插入当前扰码数据/调整数据前/中/后以形成输出数据，也可以将当前扰码数据/调整数据的至少部分位进行逻辑运算后插入标识位，也可以采用其他组合方式，在此不做限制。一般而言，标识位与当前扰码数据/调整数据的组合不应影响编码质量，即输出数据仍满足预设的质量标准。标识位的取值可以与与其组合的是当前扰码数据还是调整数据相关，以便接收端在解码过程中判断是否经过了质量调整。
如图5所示，本申请加扰方法又一实施例包括：
S21：利用前一扰码序列获取当前扰码序列。
S22：利用当前扰码序列中的预定位集对当前原始数据进行加扰得到当前扰码数据。
S23：对当前扰码数据进行质量判断。
质量判断可以为判断当前扰码数据的质量是否满足预设的质量标准。该质量标准可以与当前扰码数据中逻辑值相同的连续位有关。一般来说，满足质量标准的当前扰码数据中的逻辑值相同的连续位数不超过一阈值，该阈值的大小可以与当前扰码数据的位数相关，例如当前扰码数据的位数的一半加上一个正整数。具体的质量标准根据实际需要而定，在此不做限制。
经过质量判断后，若当前扰码数据满足质量标准，则跳转到S24；若当前扰 码数据不满足质量标准，则跳转到S25。
S24：将当前扰码数据与标识位进行组合以输出第一编码数据。
当前扰码数据满足预设的质量标准的情况下，不需要提高当前扰码数据的质量，可以与标识位组合之后直接输出。
标识位的位数可以为1，也可以为更多。具体的，可以将标识位直接插入当前扰码数据前/中/后以形成第一编码数据，也可以将当前扰码数据的至少部分位进行逻辑运算后插入标识位，也可以采用其他组合方式，在此不做限制。一般而言，标识位与当前扰码数据的组合不应影响加扰质量，即第一编码数据仍满足预设的质量标准。
S25：对当前扰码数据进行逻辑运算以输出第二编码数据。
第二编码数据的位数大于当前扰码数据。逻辑运算可以提高当前扰码数据的质量。一般而言，逻辑运算之后得到的第二编码数据可以满足预设的质量标准。
在上述两个实施例中，先对原始数据进行加扰再进行编码，由于加扰之后的数据质量不满足标准的概率大大降低，需要进行质量调整的概率大大降低，从而提高编码过程的实时性。
如图6所示，本申请加扰设备一实施例包括：处理器110。除此之外，加扰设备还可以包括存储器(图中未画出)。
处理器110控制加扰设备的操作，处理器110还可以称为CPU(Central Processing Unit，中央处理单元)。处理器110可能是一种集成电路芯片，具有信号序列的处理能力。处理器110还可以是通用处理器、数字信号序列处理器(DSP)、专用集成电路(ASIC)、现成可编程门阵列(FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。
处理器110用于执行指令以实现本申请加扰方法任一实施例及可能的组合所提供的方法。
如图7所示，本申请可读存储介质一实施例包括存储器210，存储器210存储有指令，该指令被执行时实现本申请加扰方法任一实施例及可能的组合所提供的方法。
存储器210可以包括只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、闪存(Flash Memory)、硬盘、光盘等。
在本申请所提供的几个实施例中，应该理解到，所揭露的方法和装置，可以通过其它的方式实现。例如，以上所描述的装置实施方式仅仅是示意性的，例如，所述模块或单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施方式方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理包括，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
所述集成的单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的全部或部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)或处理器(processor)执行本申请各个实施方式所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述仅为本申请的实施方式，并非因此限制本申请的专利范围，凡是利用本申请说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本申请的专利保护范围内。

Claims (20)

  1. 一种可读存储介质，存储有指令，其中，所述指令被执行时实现以下方法：
    利用前一扰码序列获取当前扰码序列，其中所述当前扰码序列的第一位集是由所述前一扰码序列的第二位集移位赋值得到的，所述当前扰码序列的第三位集是由所述前一扰码序列中的特征位集的逻辑运算结果赋值得到的，所述第三位集由所述当前扰码序列中除所述第一位集之外的所有其他位组成，所述特征位集包括多个特征位，其中至少两个所述特征位之间的间距大于或等于序列长度的一半；
    利用所述当前扰码序列中的预定位集对当前原始数据进行加扰得到当前扰码数据；
    其中至少两个相邻的所述特征位之间的间距大于或等于所述序列长度的一半，所述预定位集与所述第三位集没有交集。
  2. 一种加扰方法，其中，所述方法包括：
    利用前一扰码序列获取当前扰码序列，其中所述当前扰码序列的第一位集是由所述前一扰码序列的第二位集移位赋值得到的，所述当前扰码序列的第三位集是由所述前一扰码序列中的特征位集的逻辑运算结果赋值得到的，所述第三位集由所述当前扰码序列中除所述第一位集之外的所有其他位组成，所述特征位集包括多个特征位，其中至少两个所述特征位之间的间距大于或等于序列长度的一半；
    利用所述当前扰码序列中的预定位集对当前原始数据进行加扰得到当前扰码数据。
  3. 根据权利要求2所述的方法，其中，至少两个相邻的所述特征位之间的间距大于或等于所述序列长度的一半。
  4. 根据权利要求3所述的方法，其中，所述特征位位于所述前一扰码序列的前1/4和后1/4。
  5. 根据权利要求2所述的方法，其中，所述预定位集与所述第三位集没有交集。
  6. 根据权利要求2所述的方法，其中，所述当前扰码序列和所述前一扰码序列的位数均为16，所述第一位集为第1-15位，所述第二位集为第0-14位，所 述第三位集为第0位，所述特征位集包括第3、12、14和15位。
  7. 根据权利要求6所述的方法，其中，
    所述预定位集为第6-13位。
  8. 根据权利要求2所述的方法，其中，所述当前扰码序列和所述前一扰码序列的位数均为16，所述第一位集为第0-14位，所述第二位集为第1-15位，所述第三位集为第15位，所述特征位集包括第0、1、3和12位。
  9. 根据权利要求8所述的方法，其中，
    所述预定位集为第6-13位。
  10. 根据权利要求2所述的方法，其中，所述利用所述当前扰码序列中的预定位集对当前原始数据进行加扰得到当前扰码数据包括：
    将所述当前扰码序列中的预定位集与所述当前原始数据逐位进行异或逻辑运算得到所述当前扰码数据。
  11. 根据权利要求2所述的方法，其中，所述方法进一步包括：
    对所述当前扰码数据进行质量判断；
    若所述当前扰码数据满足预设的质量标准，则输出所述当前扰码数据；
    若所述当前扰码数据不满足预设的质量标准，则对所述当前扰码数据进行转换，并输出调整数据；
    将输出的所述当前扰码数据或所述调整数据与标识位进行组合，以形成编码数据。
  12. 根据权利要求2所述的方法，其中，所述方法进一步包括：
    对所述当前扰码数据进行质量判断；
    若所述当前扰码数据满足预设的质量标准，则将所述当前扰码数据与标识位进行组合以输出第一编码数据；
    若所述当前扰码数据不满足预设的质量标准，则对所述当前扰码数据进行逻辑运算以输出第二编码数据，所述第二编码数据的位数大于所述当前扰码数据。
  13. 一种加扰设备，其中，包括处理器，所述处理器用于执行指令以利用前一扰码序列获取当前扰码序列，其中所述当前扰码序列的第一位集是由所述前一扰码序列的第二位集移位赋值得到的，所述当前扰码序列的第三位集是由所述前一扰码序列中的特征位集的逻辑运算结果赋值得到的，所述第三位集由所述当前扰码序列中除所述第一位集之外的所有其他位组成，所述特征位集包括 多个特征位，其中至少两个所述特征位之间的间距大于或等于序列长度的一半；利用所述当前扰码序列中的预定位集对当前原始数据进行加扰得到当前扰码数据。
  14. 根据权利要求13所述的加扰设备，其中，至少两个相邻的所述特征位之间的间距大于或等于所述序列长度的一半。
  15. 根据权利要求14所述的加扰设备，其中，所述特征位位于所述前一扰码序列的前1/4和后1/4。
  16. 根据权利要求13所述的加扰设备，其中，所述预定位集与所述第三位集没有交集。
  17. 根据权利要求13所述的加扰设备，其中，所述当前扰码序列和所述前一扰码序列的位数均为16；
    所述第一位集为第1-15位，所述第二位集为第0-14位，所述第三位集为第0位，所述特征位集包括第3、12、14和15位；
    或所述第一位集为第0-14位，所述第二位集为第1-15位，所述第三位集为第15位，所述特征位集包括第0、1、3和12位。
  18. 根据权利要求17所述的加扰设备，其中，所述预定位集为第6-13位。
  19. 根据权利要求13所述的加扰设备，其中，所述处理器具体用于执行指令以将所述当前扰码序列中的预定位集与所述当前原始数据逐位进行异或逻辑运算得到所述当前扰码数据。
  20. 根据权利要求13所述的加扰设备，其中，所述处理器进一步用于执行指令以对所述当前扰码数据进行质量判断；若所述当前扰码数据满足预设的质量标准，则输出所述当前扰码数据；若所述当前扰码数据不满足预设的质量标准，则对所述当前扰码数据进行转换，并输出调整数据；将输出的所述当前扰码数据或所述调整数据与标识位进行组合，以形成编码数据。
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