WO2021115454A1 - 光电信号转换器、光驱动处理和接收模组及网络交互设备 - Google Patents

光电信号转换器、光驱动处理和接收模组及网络交互设备 Download PDF

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Publication number
WO2021115454A1
WO2021115454A1 PCT/CN2020/135925 CN2020135925W WO2021115454A1 WO 2021115454 A1 WO2021115454 A1 WO 2021115454A1 CN 2020135925 W CN2020135925 W CN 2020135925W WO 2021115454 A1 WO2021115454 A1 WO 2021115454A1
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Prior art keywords
optical
clock
data transmission
data
mode
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PCT/CN2020/135925
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English (en)
French (fr)
Inventor
胡如龙
帅家龙
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华为技术有限公司
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Publication of WO2021115454A1 publication Critical patent/WO2021115454A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
    • H04B10/40—Transceivers
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements
    • G02B6/4201—Packages, e.g. shape, construction, internal or external details
    • G02B6/4246—Bidirectionally operating package structures

Definitions

  • the embodiments of the present application relate to the technical field of photoelectric signal conversion, and in particular, to a photoelectric signal converter and a network interactive device.
  • optical transmission systems have put forward higher requirements for optical modules.
  • Optical modules are gradually developing in the direction of large-capacity and high-speed data.
  • the optical module can be backward compatible with a smaller transmission rate at the current data transmission rate, but cannot be upward compatible with a data transmission rate greater than the current transmission rate.
  • the gradual increase in the speed of optical fiber communication speed changes, which leads to the fact that the optical module is completely unable to adapt to the current rapid increase in the current optical fiber communication speed in terms of packaging and data transmission rates.
  • embodiments of the present application provide a photoelectric signal converter and network interaction device with a wide range of data transmission rate and flexible adjustment.
  • an embodiment of the present application provides an opto-electronic signal converter, including a main control unit, a light drive processing module, a light emitting module, and a light receiving module.
  • the main control unit is electrically connected to the The light driving processing module and the light receiving module
  • the light emitting module is electrically connected to the light driving processing module.
  • the optical receiving module is used for receiving optical signals from the receiving optical fiber and converting the optical signals into electrical signals, and the optical receiving module includes a linear operating mode and a limiting operating mode.
  • the light emitting module is used for receiving electrical signals from the light driving processing module and converting them into optical signals.
  • the main control unit is configured to receive a data transmission rate instruction, and output a control signal to the light driving processing module and the light receiving module according to the data transmission rate instruction.
  • the optical drive processing module is used for receiving the converted electrical signal provided by the light receiving module and converting it into a data signal for output, and converting the received data signal into an electrical signal and transmitting it to the light emitting module,
  • the optical drive processing module performs a first data transmission rate or a second data transmission rate, and the optical drive processing module operates at the first data transmission rate or the second data transmission rate according to the control signal ,
  • the first data transmission rate is less than or equal to 25 Gb/s
  • the second data transmission rate is greater than or equal to 50 Gb/s.
  • the optical transmitting module converts the received electrical signal into an optical signal and outputs it to the transmitting optical fiber.
  • the main control unit outputs corresponding control signals to the light drive processing module and light receiving module according to the received data transmission instruction, and can flexibly adjust the data by controlling the working status and working mode of the light drive processing module and the light receiving module Transmission rate.
  • a wide range of data transmission rates can be upwardly and downwardly compatible between 25Gb/s and 50Gb/s.
  • the optical drive processing module includes a limiting amplifier, a first clock and data recovery circuit, a second clock and data recovery circuit, and a drive circuit electrically connected to the main control unit, respectively.
  • the limiting amplifier is electrically connected to the light receiving module and the first clock and data recovery circuit.
  • the second clock and data recovery circuit is also electrically connected to the driving circuit.
  • the first clock and data recovery circuit is used for decoding and converting electrical signals into data signals for output.
  • the second clock and data recovery circuit is used to encode and convert the received data signal into an electrical signal.
  • the first clock and data recovery circuit and the second clock and data recovery circuit include an NZR mode and a PAM4 mode, the NZR mode corresponds to the first data transmission rate, and the PAM4 mode corresponds to the second data transmission rate.
  • the driving circuit includes a limiting mode and a linear mode. When the control signal controls the first clock and data recovery circuit and the second clock and data recovery circuit to operate in the NZR mode, the driving circuit and the limiting amplifier are simultaneously controlled to operate in the limiting mode, and the optical The drive processing module transmits data according to the first data rate.
  • the light receiving module further includes a transimpedance amplifier, and the transimpedance amplifier includes a linear mode and a limiting mode.
  • the control signal controls the first clock and data recovery circuit and the second clock and data recovery circuit to work in the PAM mode, and at the same time controls the drive circuit or the transimpedance amplifier to work in the linear mode
  • the The optical drive processing module transmits data according to the second data rate.
  • the control signal controls the limiting amplifier to bypass and stop working.
  • Controlling the first clock and data recovery circuit and the second clock and data recovery circuit by control signals includes switching between NZR mode and PAM4 mode, and cooperates with the operating limit of the driving circuit, the limiting amplifier, and the transimpedance amplifier. In amplitude mode or linear mode, the data transmission rate of the photoelectric signal converter can be adjusted accurately and flexibly.
  • the light receiving module includes a plurality of connection terminals, and the plurality of connection terminals are electrically connected to the main control unit and the connection port, wherein among the plurality of connection terminals Two connection terminals connected to the transimpedance amplifier are connected to the main control unit through an I2C bus connection end, the two connection ends are used to receive the control signal from the main control unit, and the two connections The level signal at the terminal is used to characterize the control signal.
  • connection ends of the eight coaxial structures of the optical receiving module wherein, among the eight connection ends, the SCL control end and the SDA data end of the I2C bus port are connected to all the ports.
  • the connecting terminal of the transimpedance amplifier is connected to all the ports.
  • the main control unit is electrically connected to the limiting amplifier, the first clock and data recovery circuit, and the first control terminal and the second control terminal included in the I2C bus connection terminal, respectively.
  • the second clock and data recovery circuit and the drive circuit, the level signals transmitted by the first control terminal and the second control terminal represent the control signal, wherein the two in the light receiving module
  • the connection terminals connected to the transimpedance amplifier are electrically connected to the first control terminal and the second control terminal, respectively.
  • the control signal including the data transmission rate is characterized by the level signal of the control terminal SCL and the control terminal SCA in the I2C bus port, so that the wireless additional components can be set to accurately and easily control the drive processing module and the light receiving module.
  • the working state of the group enables the optical signal converter to flexibly adjust the data transmission rate, while ensuring that the optical signal converter contains fewer components and has a smaller overall volume.
  • the transimpedance amplifier works in the limiting mode
  • the first clock and data recovery circuit and the second clock and data recovery circuit are in bypass mode
  • the limiting amplifier is in a working state
  • the optical processing drive module performs data transmission according to a third data transmission rate
  • the third data transmission rate is less than the first data transmission rate.
  • the transimpedance amplifier works in the limiting mode
  • the first clock and data recovery circuit is in the NRZ mode
  • the limiting amplifier is correspondingly in working state
  • the optical processing drive module is in accordance with the first data transmission rate Perform data transfer.
  • the transimpedance amplifier When the transimpedance amplifier is operating in the linear mode, the first clock and data recovery circuit and the second clock and data recovery circuit are in PAM4 mode, the limiting amplifier is in a bypass state, and the optical processing drive mode The group performs data transmission according to the second data transmission rate.
  • the photoelectric signal converter further includes a gold finger connection terminal, and the gold finger connection terminal includes a plurality of pins, and the pins are connected to the main control unit and the light through conductive lines.
  • the driving processing module, the golden finger connection terminal is used to connect to a service board that needs to perform data interaction, and at least two of the plurality of pins are electrically connected to the main control unit to receive the service
  • the data transmission rate command including the data transmission rate is transmitted, which saves pins and ensures the accurate transmission of the data transmission rate command.
  • the photoelectric signal converter includes a plurality of light emitting modules and a plurality of light receiving modules, and the plurality of light emitting modules and the plurality of light receiving modules simultaneously receive or emit Optical signal, which can further improve the data transmission rate of the optical signal converter.
  • an embodiment of the present application provides a network interactive device including the aforementioned photoelectric signal converter.
  • an embodiment of the present application provides an optical drive processing module, which is applied to a photoelectric signal converter.
  • the optical drive processing module is used to receive the converted electrical signal provided by a light receiving module and convert it into a data signal for output, and convert the received data signal into an electrical signal and transmit it to the light emitting module, according to the control signal Working at a first data transmission rate or a second data transmission rate, the first data transmission rate is less than or equal to 25Gb/s, and the second data transmission rate is greater than or equal to 50Gb/s, wherein the control signal is based on The data transmission rate command output that characterizes the data transmission rate.
  • the data transmission rate can be flexibly adjusted by controlling the working state and working mode of the optical drive processing module. As a result, without the need to adjust the hardware structure of the photoelectric signal converter, it can be used at 25Gb/s and The 50Gb/s transfer rate is upward and downward compatible with a wide range of data transfer rates.
  • the optical drive processing module includes a limiting amplifier, a first clock and data recovery circuit, a second clock and data recovery circuit, and a drive circuit electrically connected to the main control unit, respectively.
  • the limiting amplifier is electrically connected to the light receiving module and the first clock and data recovery circuit;
  • the second clock and data recovery circuit is also electrically connected to the driving circuit;
  • the first clock and data recovery circuit is used To decode and convert the electrical signal into a data signal for output;
  • the second clock and data recovery circuit is used to encode and convert the received data signal into an electrical signal;
  • the recovery circuit includes an NZR mode and a PAM4 mode, the NZR mode corresponds to the first data transmission rate, and the PAM4 mode corresponds to the second data transmission rate;
  • the driving circuit includes a limiting mode and a linear mode.
  • the control signal controls the first clock and data recovery circuit and the second clock and data recovery circuit to operate in the NZR mode
  • the driving circuit and the limiting amplifier are simultaneously controlled to operate in the limiting mode
  • the optical The drive processing module transmits data according to the first data rate.
  • the main control unit is configured to receive a data transmission rate instruction, and output the control signal to the optical drive processing module according to the data transmission rate instruction.
  • the driving circuit or the transimpedance amplifier when the control signal controls the first clock and data recovery circuit and the second clock and data recovery circuit to work in the PAM mode, the driving circuit or the transimpedance amplifier is simultaneously controlled to work in the PAM mode.
  • the optical drive processing module transmits data according to the second data rate, wherein the transimpedance amplifier is arranged in a light receiving module that receives optical signals from a receiving optical fiber and converts the optical signals into electrical signals in.
  • the transimpedance amplifier includes a linear mode and a limiting mode.
  • the driver is controlled at the same time.
  • the circuit and the transimpedance amplifier work in a linear mode, and the control signal controls the limiting amplifier to bypass and stop working.
  • the limit The amplitude amplifier when the transimpedance amplifier works in the limit mode, and the first clock and data recovery circuit and the second clock and data recovery circuit are in bypass mode, the limit The amplitude amplifier is in the working state, the optical processing drive module performs data transmission according to a third data transmission rate, and the third data transmission rate is less than the first data transmission rate; when the transimpedance amplifier is working in the limiting mode , The first clock and data recovery circuit and the second clock and data recovery circuit are in NRZ mode, the limiting amplifier is correspondingly in working state, and the optical processing drive module performs data transmission according to the first data transmission rate ; When the transimpedance amplifier is working in the linear mode, the first clock and data recovery circuit and the second clock and data recovery circuit are in PAM4 mode, the limiting amplifier is in a bypass state, and the optical The processing driving module executes data transmission according to the second data transmission rate.
  • an embodiment of the present application provides a light receiving module, which is applied to a photoelectric signal converter.
  • the optical receiving module is used for receiving optical signals from the receiving optical fiber and converting the optical signals into electrical signals, and the optical receiving module includes a linear operating mode and a limiting operating mode.
  • the light receiving module further includes a transimpedance amplifier, and the transimpedance amplifier includes a linear mode and a limiting mode.
  • the light receiving module includes a plurality of connection terminals which are electrically connected to the connection ports of the main control unit and the connector, wherein two of the plurality of connection terminals are connected to the The connection terminal of the transimpedance amplifier is connected to the main control unit through the I2C bus connection end, the two connection terminals are used to receive control signals from the main control unit, and the level signals of the two connection terminals are used to characterize The control signal is output according to a data transmission rate instruction that characterizes the data transmission rate and controls the rate at which data is received by light.
  • connection ends of the eight coaxial structures of the optical receiving module wherein, among the eight connection ends, the SCL control end and the SDA data end of the I2C bus port are connected to all the ports.
  • the connecting terminal of the transimpedance amplifier is connected to all the ports.
  • FIG. 1 is a schematic diagram of a three-dimensional structure of a photoelectric signal converter in an embodiment of the application
  • Fig. 2 is a schematic diagram of an exploded structure of the photoelectric signal converter shown in Fig. 1;
  • FIG. 3 is a functional block diagram showing the photoelectric signal converter along the first direction of the circuit board 2 shown in FIG. 2;
  • FIG. 4 is a functional block diagram showing the photoelectric signal converter along the second direction of the circuit board 2 shown in FIG. 2;
  • Fig. 5 is a circuit block diagram of the photoelectric signal converter shown in Fig. 3 or Fig. 4;
  • FIG. 6 is a schematic diagram of a specific circuit structure of the photoelectric signal converter shown in FIG. 5;
  • FIG. 7 is a schematic diagram of the three-dimensional structure of the connecting end of the light receiving module shown in FIG. 5 or FIG. 6;
  • FIG. 8 is a schematic diagram of the circuit structure of the light receiving module shown in FIG. 7 and the connection of the connection end.
  • FIG. 1 is a schematic diagram of the three-dimensional structure of the photoelectric signal converter 10 in an embodiment of the application.
  • the photoelectric signal converter 10 is a photoelectric signal converter of a small pluggable optical module.
  • the photoelectric signal converter 10 may be SFP (Small Form-factor Pluggable, SFP).
  • SFP Small Form-factor Pluggable
  • the photoelectric signal converter 10 may also be other types of optical modules, and it is not limited thereto.
  • FIG. 2 is a schematic diagram of an exploded structure of the photoelectric signal converter 10 shown in FIG. 1.
  • the photoelectric signal converter 10 includes a housing 1, a circuit board assembly 2, an optical transmitting assembly (Transmitter Optical Sub-Assembly, TOSA) 3, an optical receiving assembly (Receiver Optical Sub-Assembly, ROSA) 4, a gold finger Connector 6 and subminiature socket 7.
  • the circuit board assembly 2, the light emitting module 3 and the light receiving module 4 are assembled in an accommodating cavity formed by the housing 1.
  • the light emitting module 3 and the light receiving module 4 are electrically connected to the circuit board assembly 2, and the connection method can be connected by welding or connected by a flexible circuit board.
  • the light receiving module 4 and the circuit board assembly 2 are respectively provided with at least one optical fiber adapter, and the light receiving module 4 and the circuit board assembly 2 are respectively connected to the optical fiber (FIG. 5) through the optical fiber adapter and perform optical and electrical signal interactive transmission.
  • the circuit board assembly 2 includes a gold finger connector 6.
  • the gold finger connector 6 as a connector includes a plurality of pins for performing data signal, control signal and power transmission, and can be inserted in the super Used in small socket 7.
  • the multiple pins include at least two customizable pins.
  • the customizable pins are pins used for data signal, control signal, and power transmission, and users can follow their needs. Set the pin of the signal to be transmitted by yourself.
  • the number of pins included in the gold finger connector 6 can be set according to requirements. For example, the gold finger connector 6 in this embodiment includes 20 pins, while in other embodiments of the present application, the gold finger connector 6 includes 20 pins. 6 contains other numbers of pins and is not limited to this.
  • the golden finger connector 6 is used for electrical connection with an external service board (not shown in the figure).
  • the service single board may be a single data processing circuit module in a network interactive device, and the network interactive device may be a switch.
  • Figures 3 and 4 are functional block diagrams of the photoelectric signal converter 10 shown in Figure 2 along two opposite directions, that is, Figure 3 is along the circuit board shown in Figure 2 2 is a functional block diagram shown in the first direction.
  • FIG. 4 is a functional block diagram shown along the second direction of the circuit board 2.
  • the first direction is opposite to the second direction.
  • the first side surface 2a of the circuit board 2 includes the main control unit 101.
  • the second side surface 2b of the circuit board 2 is provided with a light driving processing module 102.
  • the optical drive processing module 102 is arranged on the circuit board assembly 2 in the form of a chip package.
  • the light emitting module 3 and the light receiving module 4 are electrically connected to the main control unit 101 and the light drive processing module 102 through conductive lines (not shown) on the circuit board 2, and the main control unit 101 and the light drive processing module 102 cooperates to control the data transmission rate between the light emitting module 3, the light receiving module 4 and the function module 20.
  • the light emitting module 3 is used to convert electrical signals into optical fibers and transmit them to the first optical fiber OF1 (not shown) connected to it, and the light receiving module 4 is used to transfer the electrical signals from the second optical fiber OF2 (not shown). ) Receive the optical signal, convert the optical signal into an electrical signal and transmit it to the optical drive processing module 102.
  • the main control unit 101 and the optical drive processing module 102 are both electrically connected to the golden finger connector 6 through a signal transmission wire.
  • the main control unit 101 obtains from the business single board BV the instruction of the current data transmission rate required, and the main control unit 101 outputs the corresponding control signal to the optical drive processing module 102, the optical emission module 3, and the optical receiving module according to the instruction. 4.
  • control the drive processing module 102 to cooperate with the optical transmitter module 3 to output data to the optical fiber according to the required transmission rate according to the instruction, or control the processing module 102 to cooperate with the optical receiving module 4 to output the required transmission rate from the optical fiber according to the instruction.
  • the received data is transmitted to the business single board BV.
  • the optical drive processing module 102 performs data exchange after the codec conversion of the data between the external service single board BV and the optical fiber.
  • the photoelectric signal converter 10 when the photoelectric signal converter 10 is connected to the business single board BV, it can be understood that the photoelectric signal converter 10 is fixedly connected to the network interactive device (not labeled), so that the network interactive device can communicate with the outside through the photoelectric signal converter 10 Optical fiber for interactive data transmission.
  • FIG. 5 is a circuit block diagram of the photoelectric signal converter 10 shown in FIG. 3 or FIG. 4, and FIG. 6 is a specific circuit structure of the photoelectric signal converter 10 shown in FIG. Schematic.
  • the optical receiving module 4 includes an optical receiver 41 and a trans-impedance amplifier (Trans-Impedance Amplifier, TIA) 42 that are electrically connected to each other.
  • the optical receiver 41 is used to receive light from the second optical fiber OF2.
  • the transimpedance amplifier 42 is used to receive the current signal from the optical receiver 41 and convert the current signal into a voltage signal, and convert the optical signal into a current signal, and the gain of the converted voltage signal can be adjusted as required proportion.
  • the optical receiver 41 and the transimpedance amplifier 42 in the optical receiving module 4 are in the form of a packaged chip structure.
  • the light emitting module 3 converts the current signal corresponding to the data signal into an optical signal and transmits it to the first optical fiber OF1.
  • the light emitting module 3 includes a light emitter 31 composed of photoelectric conversion diodes, where the photoelectric conversion diode as the light emitter 31 may be a laser diode.
  • the optical drive processing module 102 includes a limiting amplifier (LA) 1021 corresponding to the optical receiving module 4, a first clock and data recovery circuit (Lock And Data Recovery, CDR) 102a, and a corresponding optical transmitting module 3 The second clock and data recovery circuit 102b and the driving circuit 1023.
  • LA limiting amplifier
  • CDR Lock And Data Recovery
  • the limiting amplifier 1021 is used for limiting and amplifying the voltage signal converted and amplified by the transimpedance amplifier 42 to eliminate amplitude interference in the voltage signal.
  • the first clock and data recovery circuit 102a is used to extract the clock signal from the signal that has been limited and amplified by the limiting amplifier 1021, find the correct phase relationship between the data and the clock, and accurately transmit the data signal to the It is used in the functional module connected through the golden finger connector 6.
  • the second clock and data recovery circuit 102b is electrically connected to the connection port and the drive circuit 1023 to identify and encode the data signal provided by the functional module according to the clock and then is converted into a current signal by the drive circuit 1023 and output to the light emitting module 3.
  • the light emitting module 3 outputs a corresponding light signal to the first optical fiber OF1 according to the current signal, and the first light OF1 correspondingly transmits the light signal to the outside.
  • the first clock and data recovery circuit 102a and the second clock and data recovery circuit 102b include a non-return-to-zero code (Non-Return-Zero, NRZ) mode and a four-level pulse amplitude modulation mode after starting to work. (Pulse Amplitude Modulate 4-Level, PAM4).
  • NRZ mode is used to support 24.33024Gbit/s, 25Gbit/s, 25.78125Gbit/s, 28.05Gbit/s and other data transmission rates;
  • the PAM4 mode supports data transmission rates such as 24.33024Gbit/s, 25.78125Gbit/s, 28.05Gbit/s, 53.125Gbit/s, and 106Gbit/s.
  • the signal transmission and interaction of the network equipment mainly adopt the non-return-to-zero code NRZ mode and the PAM mode for modulation.
  • the non-return-to-zero code NRZ mode uses two signal levels to represent the 0 and 1 information of the digital logic signal, and each symbol period can transmit 1 bit of logic information.
  • Pulse amplitude modulation PAM signals can use more signal levels, so that more bits of information can be transmitted per symbol period.
  • PAM-4 signal uses 4 different signal levels for signal transmission, and each symbol period can represent 2 bits of logic information (0, 1, 2, 3). Therefore, to achieve the same signal transmission capability, the symbol rate of the PAM-4 signal only needs to reach half of the NRZ signal.
  • the driving circuit 1023 is a laser diode driver (LDD), which includes a linear mode and a limiting mode.
  • LDD laser diode driver
  • the linear mode supports high-profile signals, such as PAM4, PAMn and DMT and other modes.
  • the limiting mode the data signal transmitted in the NRZ modulation mode is supported.
  • the main control unit 101 is electrically connected to the functional circuit of the optical drive processing module 102 and the optical receiving module 4, thereby controlling the limiting amplifier 1021, the first clock and data recovery circuit 102a, the second clock and data recovery circuit 102b, and the driver The working state and working mode of the circuit 1023.
  • the main control unit 101 communicates with the limiting amplifier 1021 through the I2C bus interface, the first clock and data recovery circuit 102a, the second clock and data recovery circuit 102b, and the working state and working mode of the driving circuit 1023, that is, It is said that by controlling the driving circuit 1023 to work in linear mode or limiting mode, the first clock and data recovery circuit 102a, the second clock and data recovery circuit 102b work in NRZ mode or PAM mode, whether the limiting amplifier 1021 is in working state
  • the data transmission rate of the optical drive processing module 102 can be flexibly adjusted.
  • the golden finger connector 6 includes a plurality of pins, which are electrically connected to the main control unit 101 and the optical drive processing module 102, respectively. In this embodiment, there are 20 pins.
  • An example of a connection port with pins as an example illustrates its connection method as shown in Table 1 below:
  • VccR Receiver power 16 VccT Transmitter power supply 17 VeeT Transmitter ground 18 TD+ Originating data input 19 TD- Originating data input 20 VeeT Transmitter ground
  • the business single board BV outputs a data transmission rate command to the main control unit 101 through the seventh pin RS0 and the ninth pin RS1 in the golden finger connector 6, wherein the data transmission rate command can be
  • the levels of the 7-pin RS0 and the 9th pin RS1 are characterized, for example, the 7th pin RS0 and the 9th pin RS1 are respectively characterized by a combination of high level or low level to represent the current optical drive processing module 102 and the light
  • the receiving module 4 needs to perform the data transmission rate.
  • the seventh pin RS0 and the ninth pin RS1 are user-defined pins among the multiple pins in the golden finger connector 6.
  • the correspondence between the level information of the 7th pin RS0 and the 9th pin RS1 and the data transmission rate included in the data transmission rate command may be as shown in Table 2 below.
  • RS0 RS1 Data transfer rate 0 0 1.25Gbit/s, 2.5Gbit/s, 4.9Gbit/s, 6.9Gbit/s, 9.8Gbit/s 0 1 24.3Gbit/s, 25.7Gbit/s, 28Gbit/s 1 0 56.5Gbit/s 1 1 113.1Gbit/s
  • the correspondence between the level information of the 7th pin RS0 and the 9th pin RS1 and the data transmission rate command can also be adjusted, and it is not limited to this.
  • the main control unit 101 reads the level from the 7th pin RS0 and 9th pin RS1 to obtain the data transmission rate contained in the data transmission rate command, and writes the corresponding data in the internal register location according to the data transmission rate command. Numerical value.
  • the internal register position in the main control unit can be 8-bit storage bits, as shown in Table 3, where the second and third positions are written from the 7th pin RS0 and the 9th pin RS1 to read ⁇ level information.
  • the main control unit 101 obtains the drive processing module 102 and the light receiving module 4 through the I2C bus port to be electrically connected to and transmits the control signal corresponding to the data transmission rate command.
  • the I2C bus port includes a first control terminal SCL and a second control terminal SCA, and the main control unit 101 communicates with the drive processing module 102 and the light receiving module through the first control terminal SCL and the second control terminal SCA, respectively.
  • 4 is electrically connected, and the control signal is formed by the level signal transmitted by the first control terminal SCL and the second control terminal SCA, so as to control the working state of the light drive processing module 102 and the light receiving module 4 and Operating mode.
  • the level signals transmitted by the first control terminal SCL and the second control terminal SCA may be TTL level.
  • Table 6 is the corresponding relationship between the control signal represented by the level signal in the first control terminal SCL and the second control terminal SCA, the working status of the driving processing module 102, the light receiving module 4, and the data transmission rate.
  • Table 6 by adjusting the level signals in the first control terminal SCL and the second control terminal SCA to control the working status of the drive processing module 102 and the light receiving module 4, the photoelectric signal converter 10 can be flexibly adjusted.
  • Data transmission rate so that it is not necessary to adjust the hardware structure of the photoelectric signal converter 10 at all, and the data transmission rate is adapted to the 25Gb/s data transmission rate required for 5G network transmission, and it can also be upwardly compatible with 50Gb/s at the same time The data transmission rate, even 100Gb/s data transmission rate.
  • the optical drive processing module 102 and the optical receiving module 4 may also write the signal received from the I2C bus interface into a preset storage location, for example, into a control location in an internal register. Later, you can directly perform data transmission at the corresponding rate by reading the information of the preset storage location.
  • the preset location may be an 8-bit storage location
  • the storage location setting diagram of the light drive processing module 102 and the light receiving module 4 is schematic.
  • the storage location setting diagram of the optical driving processing module 102 and the optical receiving module 4 may be as shown in Table 7:
  • FIG. 7 is a schematic diagram of the three-dimensional structure of the connecting end of the light receiving module 4 shown in FIG. 5 or FIG. 6, and FIG. 8 is the circuit structure of the light receiving module 4 shown in FIG. 7 and the connection of the connecting end Schematic.
  • the optical receiving module 4 includes 8 connection terminals, and the 8 connection terminals are: 1 VPD, 2 VCC, 3 OUTN, 4 OUTP, 5 SCL, 6 SDA, 7 GND, 8 GND.
  • the connection terminal 2 VCC cooperates with the connection terminal 7 GND and the connection terminal 8 GND to provide driving power for the light receiving module 4.
  • the connection terminals 3 OUTN and 4 OUTP cooperate to perform data output.
  • connection terminal 5 SCL and the connection terminal 6 SDA are electrically connected to the I2C terminal, and the autonomous control unit 101 receives a signal that characterizes its required working mode.
  • the correspondence between the level signals received by the connection terminal 5 SCL and the connection terminal 6 SDA and the working mode of the transimpedance amplifier 42 in the optical receiving module 4 can be seen in Table 4.
  • the transimpedance amplifier 42 in the optical receiving module 4 judges that it is currently in the limiting mode or the linear mode according to the level signals received by the connection terminal 5 SCL and the connection terminal 6 SDA, so as to compare with the first clock and data
  • the working mode of the recovery circuit cooperates to perform data reception according to the corresponding data transmission rate.
  • the business single board BV outputs two low levels (00) from the 7th pin RS0 and the 9th pin RS1 respectively, which is to control the The level of the 7 pin RS0 and the 9th pin RS1 is low, then the main control unit 101 outputs a control signal of 00 to the light processing driving module 102 and the transimpedance amplifier 4.
  • the transimpedance amplifier 42 works in the limit mode, and the limit amplifier 1021 is in the working state.
  • the corresponding connection terminal 5 SCL and the connection terminal 6 When the level signal received by SDA is 00, when the first clock and data recovery circuit 102a and the second clock and data recovery circuit 102b are in bypass mode and not working, the optical processing drive module 102 transmits data at 10Gb/s and below Perform data transmission at a rate to meet the needs of small broadband data transmission.
  • the business single board BV outputs a low level and a high level (01) from the 7th pin RS0 and the 9th pin RS1, respectively, which is to control the 7th pin RS0 and the 9th pin.
  • the level of the pin RS1 is low and high respectively, then the main control unit 101 outputs the control signal of 01 to the light processing drive module 102 and the transimpedance amplifier 42, then the main control unit 101 outputs the control of 01
  • the signal is sent to the light processing driving module 102 and the transimpedance amplifier 42.
  • the first clock and data recovery circuit 102a and the second clock and data recovery circuit 102b are in the NRZ mode, and the transimpedance amplifier 42 works in the limiting mode ,
  • the limiting amplifier 1021 is correspondingly in the working state, and the optical processing drive module 102 performs data transmission at a data transmission rate of about 25 Gb/s to meet medium-band data transmission.
  • the business single board BV outputs a high level and a low level (01) or two high levels (11) from the 7th pin RS0 and the 9th pin RS1 respectively, that is, Control the level of the 7th pin RS0 and the 9th pin RS1 to be high level and low level or two high levels respectively, then the main control unit 101 outputs the control signal of 10 or 11 to the light processing drive module 102 and the transimpedance amplifier 42, then the main control unit 101 outputs a control signal of 10 or 11 to the optical processing driving module 102 and the transimpedance amplifier 42.
  • the transimpedance amplifier 42 works in linear mode.
  • the first clock and data recovery circuit 102a and the second clock and data recovery circuit 102b are in the PAM4 mode of 50Gb/s
  • the transimpedance amplifier 42 is working in linear mode
  • the limiting amplifier 1021 is correspondingly in the bypass state.
  • the optical processing driving module 102 performs data transmission at a data transmission rate of about 50 Gb/s.
  • the first clock and data recovery circuit 102a and the second clock and data recovery circuit 102b are in 100Gb/s PAM4 mode, and the transimpedance amplifier 42 works In the linear mode, the limiting amplifier 1021 is correspondingly in the bypass state and the optical processing drive module 102 performs data transmission at a data transmission rate of about 100 Gb/s to meet the needs of large broadband data transmission.
  • the data transmission of the photoelectric signal converter 10 can be flexibly adjusted.
  • the data transmission rate can be adapted to the 25Gb/s data transmission rate required for 5G network transmission without the need to adjust the hardware structure of the photoelectric signal converter 10 at all, and it can also be upwardly compatible with 50Gb/s data at the same time. The transmission rate, even the 100Gb/s data transmission rate is improved.
  • the photoelectric signal converter 10 may further include multiple light emitting modules and multiple light receiving modules, so as to further increase the data transmission rate.
  • it includes 2 light emitting modules and 2 light receiving modules to form a two-channel DSFP package; or, including 4 light emitting modules and 4 light receiving modules to form a four-channel QSFP package; 8 The light transmitting module and 8 light receiving modules form an eight-channel DSFP-DD package.
  • the plurality of light emitting modules and the plurality of light receiving modules simultaneously receive or emit photoelectric signals.
  • the two-channel DSFP package can support data transmission rates of 200Gb/s, 100Gb/s, 50Gb/s, 25Gb/s, 10Gb/s and below;
  • the four-channel QSFP package can support 400Gb/s, 200Gb/s , 100Gb/s, 50Gb/s, 20Gb/s, and the following data transmission rate;
  • the eight-channel DSFP-DD package can support 800Gb/s, 200Gb/s, 100Gb/s, 50Gb/s, 20Gb/s and its The following data transfer rate.

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Abstract

本申请提供一种数据传输速率调整范围较宽且灵活的光电信号转换器。光电信号转换器包括相互电性连接的主控单元、光驱动处理模组。光接收模组用于自接收光纤接收光信号并且将所述光信号转换为电信号并传输至光驱动处理模组，光发射模组用于自所述光驱动处理模组接收电信号并转换为光信号。主控单元用于接收数据传输速率指令并据此输出控制信号至光驱动处理模组以及光接收模组，以控制光驱动处理模组、光发射模组以及光接收模组工作于所述第一数据传输速率或者所述第二数据传输速率，第一、第二数据传输速率涵盖25Gb/s以下及50Gb/s以上的数据传输速率。本申请还提供一种包括前述光电信号转换器的网络交互设备。

Description

光电信号转换器、光驱动处理和接收模组及网络交互设备
本申请要求于2019年12月13日提交中国专利局、申请号为201911285580.2、申请名称为“光电信号转换器及网络交互设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及光电信号转换技术领域，尤其涉及一种光电信号转换器以及网络交互设备。
背景技术
随着光纤通信的发展，光传输系统对光模块提出了更高的要求。光模块逐渐向大容量、数据高速率方向发展。目前而言，光模块能够在当前的数据传输速率下向下兼容更小传输速率，却无法向上兼容比当前传输速率更大的数据传输速率。然而，光纤通信速率更迭提速的逐渐增快，这就导致光模块在封装和数据传输速率上完全无法适应当前光纤通信速率的快速提升。
发明内容
为解决前述技术问题，本申请实施例提供一种数据传输速率范围较宽且调整灵活的光电信号转换器与网络交互设备。
第一方面，本申请一实施例中提供一种光电信号转换器，包括主控单元、光驱动处理模组、光发射模组与光接收模组，所述主控单元电性连接于所述光驱动处理模组以及所述光接收模组，所述光发射模组电性连接于所述光驱动处理模组。所述光接收模组用于自接收光纤接收光信号并且将所述光信号转换为电信号，所述光接收模组包括线性工作模式与限幅工作模式。所述光发射模组用于自所述光驱动处理模组接收电信号并转换为光信号。所述主控单元用于接收数据传输速率指令，并且依据所述数据传输速率指令输出控制信号至所述光驱动处理模组以及所述光接收模组。所述光驱动处理模组用于接收光接收模组提供的经转换后的电信号并转换为数据信号输出，以及将接收到的数据信号转换为电信号并传输至所述光发射模组，所述光驱动处理模组执行第一数据传输速率或者第二数据传输速率，所述光驱动处理模组依据控制所述控制信号工作于所述第一数据传输速率或者所述第二数据传输速率，所述第一数据传输速率小于或者等于25Gb/s，所述第二数据传输速率大于或者等于50Gb/s。所述光发射模组将接收到的所述电信号转换为光信号并输出至发送光纤。
主控单元依据接收到的数据传输指令输出对应的控制信号至光驱动处理模组与光接收模组，通过控制光驱动处理模组与光接收模组工作状态与工作模式即可灵活的调整数据传输速率。由此，在并不需要针对光电信号转换器的硬件结构进行调整的情况下，即可在25Gb/s与50Gb/s传输速率之间向上、向下兼容较宽范围的数据传输速率。
本申请一实施例中，所述光驱动处理模组包括分别电性连接于所述主控单元的限幅放大器、第一时钟和数据恢复电路、第二时钟和数据恢复电路以及驱动电路。所述限幅放大器电性连接于所述光接收模组与第一时钟和数据恢复电路。第二时钟和数据恢复电路还电性连接所述驱动电路。所述第一时钟和数据恢复电路用于将电信号解码并转换为数据信号输出。所述第二时钟和数据恢复电路用于将接收的数据信号编码并转换为电信号。所述第一时钟和数据恢复电路、第二时钟和数据恢复电路包括NZR模式与PAM4模式，所述NZR模式对应所述第一数据传输速率，所述PAM4模式对应所述第二数据传输速率。所述驱动电路包括限幅模式与线性模式。当所述控制信号控制所述第一时钟和数据恢复电路与第二时钟和数据恢复电路工作在所述NZR模式时，同时控制所述驱动电路与限幅放大器工作于限幅模式，所述光驱动处理模组按照第一数据传速率数据。
本申请一实施例中，所述光接收模组还包括跨阻放大器，所述跨阻放大器包括线性模式与限幅模式。当所述控制信号控制所述第一时钟和数据恢复电路与第二时钟和数据恢复电路工作在所述PAM模式时，同时控制所述驱动电路或者所述跨阻放大器工作于线性模式，所述光驱动处理模组按照所述第二数据传速率数据。
本申请一实施例中，当所述第一时钟和数据恢复电路与第二时钟和数据恢复电路工作在所述PAM4模式，同时控制所述驱动电路与所述跨阻放大器工作于线性模式，所述控制信号控制所述限幅放大器旁路并停止工作。
通过控制信号来控制所述第一时钟和数据恢复电路、第二时钟和数据恢复电路包括NZR模式与PAM4模式之间切换，并且配合所述驱动电路、所述限幅放大器、跨阻放大器工作限幅模式或者线性模式下，从而准确而灵活的调整光电信号转换器的数据传输速率。
本申请一实施例中，所述光接收模组包括多个连接端子，所述多个连接端电性连接于所述主控单元与所述连接端口，其中，所述多个连接端子中的两个连接于所述跨阻放大器的连接端子通过I2C总线连接端连接于所述主控单元，所述两个连接端用于自所述主控单元接收所述控制信号，所述两个连接端的电平信号用于表征所述控制信号。
本申请一实施例中，所述光接收模组八个同轴结构的所述连接端，其中，所述八个连接端中的表征I2C总线端口中SCL控制端与SDA数据端作为连接于所述跨阻放大器的连接端子。
本申请一实施例中，所述主控单元通过I2C总线连接端包括的第一控制端与第二控制端分别电性连接所述限幅放大器、所述第一时钟和数据恢复电路、所述第二时钟和数据恢复电路以及所述驱动电路，所述第一控制端与所述第二控制端传输的电平信号表征所述控制信号，其中，所述光接收模组中所述两个连接于所述跨阻放大器的连接端分别电性连接于所述第一控制端与所述第二控制端。
通过I2C总线端口中的控制端SCL与控制端SCA中电平信号来表征包含有数据传输速率的控制信号，从而无线额外设置其他元部件即可准确、简便的控制驱动处理模组、光接收模组的工作状态，从而使得光信号转换器能够灵活的调整数据传输速率，同时保证光信号转换器包含的元部件较少且整体体积较小。
本申请一种可能的实现方式中，当所述跨阻放大器工作在所述限幅模式，所述第一时钟和数据恢复电路和所述第二时钟和数据恢复电路处于旁路未工作时，所述限幅放大器处 于工作状态，所述光处理驱动模组按照第三数据传输速率执行数据传输，所述第三数据传输速率小于第一数据传输速率。当所述跨阻放大器工作在所述限幅模式，所述第一时钟和数据恢复电路处于NRZ模式，所述限幅放大器对应处于工作状态，所述光处理驱动模组按照第一数据传输速率执行数据传输。当跨阻放大器工作在所述线性模式，所述第一时钟和数据恢复电路和所述第二时钟和数据恢复电路处于PAM4模式，限幅放大器处于旁路未工作状态，所述光处理驱动模组按照所述第二数据传输速率执行数据传输。
本申请一实施例中，所述光电信号转换器还包括金手指连接端，所述金手指连接端的包括多个引脚，所述引脚通过导电线路连接于所述主控单元与所述光驱动处理模组，所述金手指连接端用于连接于需要执行数据交互的业务单板，所述多个引脚中至少两个引脚电性连接所述主控单元以接收自所述业务单板输出的数据传输速率指令，所述数据传输速率指令包括所述光驱动处理模组需要执行数据传输的数据传输速率。通过金手指连接端本身具有的引脚传输包含有数据传输速率的数据传输速率指令，节省了引脚的同时还保证数据传输速率指令的准确传输。
本申请一实施例中，所述光电信号转换器包括多个光发射模组与多个光接收模组，所述多个光发射模组与所述多个光接收模组分时接收或者发射光电信号，从而能够进一步提高光电信号转换器的数据传输速率。
第二方面，本申请一实施例提供一种网络交互设备，包括有前述的光电信号转换器。
第三方面，本申请一实施例提供一种光驱动处理模组，应用于光电信号转换器。光驱动处理模组用于接收一光接收模组提供的经转换后的电信号并转换为数据信号输出，以及将接收到的数据信号转换为电信号并传输至光发射模组，依据控制信号工作于第一数据传输速率或者第二数据传输速率，所述第一数据传输速率小于或者等于25Gb/s，所述第二数据传输速率大于或者等于50Gb/s，其中，所述控制信号为依据表征数据传输速率的数据传输速率指令输出。通过控制光驱动处理模组的工作状态与工作模式即可灵活的调整数据传输速率，由此，在并不需要针对光电信号转换器的硬件结构进行调整的情况下，即可在25Gb/s与50Gb/s传输速率之间向上、向下兼容较宽范围的数据传输速率。
本申请一实施例中，所述光驱动处理模组包括分别电性连接于主控单元的限幅放大器、第一时钟和数据恢复电路、第二时钟和数据恢复电路以及驱动电路。所述限幅放大器电性连接于所述光接收模组与第一时钟和数据恢复电路；第二时钟和数据恢复电路还电性连接所述驱动电路；所述第一时钟和数据恢复电路用于将电信号解码并转换为数据信号输出；所述第二时钟和数据恢复电路用于将接收的数据信号编码并转换为电信号；所述第一时钟和数据恢复电路、第二时钟和数据恢复电路包括NZR模式与PAM4模式，所述NZR模式对应所述第一数据传输速率，所述PAM4模式对应所述第二数据传输速率；所述驱动电路包括限幅模式与线性模式。当所述控制信号控制所述第一时钟和数据恢复电路与第二时钟和数据恢复电路工作在所述NZR模式时，同时控制所述驱动电路与限幅放大器工作于限幅模式，所述光驱动处理模组按照第一数据传速率数据。其中，主控单元用于接收数据传输速率指令，并且依据所述数据传输速率指令输出所述控制信号至所述光驱动处理模组。
本申请一实施例中，当所述控制信号控制所述第一时钟和数据恢复电路与第二时钟和数据恢复电路工作在所述PAM模式时，同时控制所述驱动电路或者跨阻放大器工作于线性 模式，所述光驱动处理模组按照所述第二数据传速率数据，其中，所述跨阻放大器设置于自接收光纤接收光信号并且将所述光信号转换为电信号的光接收模组中。
本申请一实施例中，所述跨阻放大器包括线性模式与限幅模式，当所述第一时钟和数据恢复电路与第二时钟和数据恢复电路工作在所述PAM4模式，同时控制所述驱动电路与所述跨阻放大器工作于线性模式，所述控制信号控制所述限幅放大器旁路并停止工作。
本申请一实施例中，当所述跨阻放大器工作在所述限幅模式，所述第一时钟和数据恢复电路和所述第二时钟和数据恢复电路处于旁路未工作时，所述限幅放大器处于工作状态，所述光处理驱动模组按照第三数据传输速率执行数据传输，所述第三数据传输速率小于第一数据传输速率；当所述跨阻放大器工作在所述限幅模式，所述第一时钟和数据恢复电路和所述第二时钟和数据恢复电路处于NRZ模式，所述限幅放大器对应处于工作状态，所述光处理驱动模组按照第一数据传输速率执行数据传输；当跨阻放大器工作在所述线性模式，所述第一时钟和数据恢复电路和所述第二时钟和数据恢复电路处于PAM4模式，所述限幅放大器处于旁路未工作状态，所述光处理驱动模组按照所述第二数据传输速率执行数据传输。
第四方面，本申请一实施例提供一种光接收模组，应用于光电信号转换器。所述光接收模组用于自接收光纤接收光信号并且将所述光信号转换为电信号，所述光接收模组包括线性工作模式与限幅工作模式。所述光接收模组还包括跨阻放大器，所述跨阻放大器包括线性模式与限幅模式。所述光接收模组包括多个连接端子，所述多个连接端子电性连接于所述主控单元与连接器的连接端口，其中，所述多个连接端子中的两个连接于所述跨阻放大器的连接端子通过I2C总线连接端连接于所述主控单元，所述两个连接端子用于自所述主控单元接收控制信号，所述两个连接端子的电平信号用于表征所述控制信号，所述控制信号为依据表征数据传输速率的数据传输速率指令输出并控制光接收数据时的速率。
本申请一实施例中，所述光接收模组八个同轴结构的所述连接端，其中，所述八个连接端中的表征I2C总线端口中SCL控制端与SDA数据端作为连接于所述跨阻放大器的连接端子。
附图说明
图1为本申请一实施例中光电信号转换器的立体结构示意图；
图2为图1所示光电信号转换器的分解结构示意图；
图3为光电信号转换器沿着图2所示电路板2的第一方向所展示的功能方框图；
图4为光电信号转换器沿着图2所示电路板2的第二方向所展示的功能方框图；
图5为如图3或者图4所示光电信号转换器的电路框图；
图6为如图5所示光电信号转换器的具体电路结构示意图；
图7为如图5或者如图6所示光接收模组连接端的立体结构示意图；
图8为如图7所示光接收模组的电路结构与连接端的连接示意图。
具体实施方式
下面以具体的实施例对本申请进行说明。
请参阅图1，其为本申请一实施例中光电信号转换器10的立体结构示意图。本实施中，如图1所示，光电信号转换器10为小型可插拔光模块的光电信号转换器。举例来说，光电信号转换器10为可以为SFP(Small Form-factor Pluggable,SFP)，当然，光电信号转换器10也可以为其他类型的光模块，并不以此为限。
请结合图1一并参阅图2，图2为如图1所示光电信号转换器10的分解结构示意图。如图2所示，光电信号转换器10包括外壳1、电路板组件2、光发射组件(Transmitter Optical Sub-Assembly,TOSA)3，光接收组件(Receiver Optical Sub-Assembly,ROSA)4，金手指连接器6和超小型插座7。
其中，电路板组件2，光发射模组3和光接收模组4装配在外壳1构成的容置腔内。光发射模组3、光接收模组4与电路板组件2电性连接，其连接方式可以通过焊接进行连接，或者通过柔性电路板进行连接。同时，光接收模组4与电路板组件2分别设置有至少一个光纤适配器，光接收模组4与电路板组件2通过光纤适配器分别与光纤(图5)进行连接且进行光电信号交互传输。
电路板组件2包含金手指连接器6，该金手指连接器6作为连接器包含有多个引脚，该多个引脚用于执行数据信号、控制信号以及电源的传输，并可插在超小型插座7中使用。本实施例中，该多个引脚至少包含2个可以自定义的引脚，所述自定义的引脚为除数据信号、控制信号以及电源的传输用的引脚之外，用户可以依据需求自行进行设定其传输的信号的引脚。其中，金手指连接器6包含的引脚数量可以依据需求进行设定，例如，本实施例中金手指连接器6包含有20个引脚，而在本申请其他实施例中，金手指连接器6包含有其他数量的引脚，并不以此为限。
本实施例中，金手指连接器6用于与外部业务单板(图未示)电性连接。其中，所述业务单板可以为网络交互设备中的单个数据处理电路模组，所述网络交互设备可以为交换机。
请参阅图3-图4，图3与图4分别为如图2所示光电信号转换器10沿着两个相反方向展示的功能方框图，也即是图3为沿着图2所示电路板2的第一方向所展示的功能方框图，图4为沿着电路板2的第二方向所展示的功能方框图，第一方向与第二方向相反。如图3所示，在电路板2的第一侧面2a，包括主控单元101，如图4所示，电路板2的第二侧面2b设置有光驱动处理模组102。本实施例中，光驱动处理模组102采用芯片封装的形式设置于电路板组件2上。
光发射模组3与光接收模组4通过电路板2上的导电线路(图未示)与主控单元101与光驱动处理模组102电性连接，主控单元101与光驱动处理模组102配合控制光发射模组3、光接收模组4与功能模组20之间进行数据传输的速率。
本实施例中，光发射模组3用于将电信号转换为光纤并传输至与其连接的第一光纤OF1(图未示)，光接收模组4用于自第二光纤OF2(图未示)接收光信号，并将光信号转换为电信号传输至光驱动处理模组102。
主控单元101与光驱动处理模组102均通过信号传输导线与金手指连接器6电性连接， 当光电信号转换器10通过金手指连接器6与外部业务单板BV(Business veneer)时，主控单元101自业务单板BV获取当前需要实行数据传输的速率的指令，主控单元101依据该指令输出对应的控制信号至光驱动处理模组102、光发射模组3、光接收模组4，进而控制驱动处理模组102配合光发射模组3按照指令进行需求的传输速率将数据输出至光纤，或者控制处理模组102配合光接收模组4按照指令进行需求的传输速率将自光纤接收的数据传输至业务单板BV。本实施例中，光驱动处理模组102在外部业务单板BV与光纤之间数据的编解码转换后进行数据交互。
需要说明的是，光电信号转换器10与业务单板BV连接时可以理解为光电信号转换器10固定连接于网络交互设备(未标示)中，以便于网络交互设备通过光电信号转换器10与外部光纤进行数据交互传输。
更为具体地，请参阅图5-图6，图5为如图3或者图4所示光电信号转换器10的电路框图，图6为如图5所示光电信号转换器10的具体电路结构示意图。
如图5所示，光接收模组4包括相互电性连接的光接收器41与跨阻放大器(Trans-Impedance Amplifier,TIA)42，其中，光接收器41用于自第二光纤OF2接收光信号，并且将光信号转换为电流信号，跨阻放大器42用于自光接收器41接收所述电流信号，并且将所述电流信号转化为电压信号，并且可以依据需要调整转换为电压信号的增益比例。本实施例中，光接收模组4中光接收器41与跨阻放大器42为封装的芯片结构形式。
光发射模组3则将对应数据信号的电流信号转换为光信号并传输至第一光纤OF1。本实施例中，光发射模组3包括由光电转换二极管构成的光发射器31，其中，作为光发射器31的光电转换二极管可以是激光二极管。
光驱动处理模组102包括对应光接收模组4的限幅放大器(Limiting Amplifier,LA)1021与第一时钟和数据恢复电路(Lock And Data Recovery，CDR)102a，以及对应光发送模组3的第二时钟和数据恢复电路102b与驱动电路1023。
具体地，限幅放大器1021用于针对经过跨阻放大器42转换放大后的电压信号进行限幅放大，消除电压信号中的振幅干扰。
第一时钟和数据恢复电路102a用于针对经过限幅放大器1021经过限幅放大后的信号中提取时钟信号并找出数据和时钟正确的相位关系，并且将依据时钟信号将数据信号准确地传输至通过金手指连接器6连接的功能模组中进行使用。
第二时钟和数据恢复电路102b电性连接于连接端口与驱动电路1023，以针对功能模组提供的数据信号按照时钟进行识别编码然后经过驱动电路1023转换为电流信号输出至光发射模组3，光发射模组3将依据电流信号输出对应的光信号至第一光纤OF1，第一光线OF1对应将光信号向外部传送。
本实施例中，第一时钟和数据恢复电路102a、第二时钟和数据恢复电路102b在启动工作后，包括非归零码(Non-Return-Zero,NRZ)模式和四电平脉冲幅度调制模式(Pulse Amplitude Modulate 4-Level,PAM4)。
其中，NRZ模式用于支持24.33024Gbit/s、25Gbit/s、25.78125Gbit/s、28.05Gbit/s等数据传输速率；
PAM4模式支持24.33024Gbit/s、25.78125Gbit/s、28.05Gbit/s、53.125Gbit/s以及106Gbit/s等数据传输速率。
其中，网络设备进行信号传输及交互主要采用非归零码NRZ模式与PAM模式进行调制。其中，非归零码NRZ模式为使用两种信号电平来表示数字逻辑信号的0、1信息，每个符号周期可传输1个bit的逻辑信息。
脉冲幅度调制PAM信号则可以采用更多信号电平，从而每个符号周期可传输更多bit信息。以PAM-4信号为例，其采用4个不同的信号电平来进行信号传输，每个符号周期可以表示2个bit的逻辑信息(0、1、2、3)。因此，要实现同样的信号传输能力，PAM-4信号的符号速率只需要达到NRZ信号的一半即可。
本实施例中，当光发射器31为激光二极管，驱动电路1023为激光启动放大器(Laser Diode Driver,LDD)，其包括线性模式与限幅模式，其中，在线性模式下支持高调信号，例如支持PAM4、PAMn以及DMT等模式。而在限幅模式下，支持NRZ调制模式下传输的数据信号。
主控单元101电性连接于光驱动处理模组102的功能电路以及光接收模组4，从而控制限幅放大器1021、第一时钟和数据恢复电路102a、第二时钟和数据恢复电路102b、驱动电路1023的工作状态与工作模式。
本实施例中，主控单元101通过I2C总线接口与限幅放大器1021、第一时钟和数据恢复电路102a、第二时钟和数据恢复电路102b、驱动电路1023的工作状态与工作模式，也即是说通过控制驱动电路1023是工作在线性模式或者限幅模式，第一时钟和数据恢复电路102a、第二时钟和数据恢复电路102b工作在NRZ模式或者PAM模式，限幅放大器1021是否处于工作状态来灵活调整光驱动处理模组102进行数据传输的速率。
本实施例中，金手指连接器6包括多个引脚，该些多个引脚分别与主控单元101、光驱动处理模组102电性连接，本实施例中，以含有个20个引脚为例的连接端口举例说明其连接方式如下表1所示：
表1
1 VeeT 发射端地
2 TX_FAULT 发射端检测
3 TX_DISABLE 发射端使能
4 SDA 可选
5 SCL 可选
6 MOD-ABS I2C总线时钟接口
7 RS0 速率指令端
8 RX-LOS 接收逻辑指示
9 RS1 速率指令端
10 VeeR 接收端地
11 VeeR 接收端地
12 RD+ 发端数据输入
13 RD- 发端数据输入
14 VeeR 接收端地
15 VccR 接收端电源
16 VccT 发射端电源
17 VeeT 发射端地
18 TD+ 发端数据输入
19 TD- 发端数据输入
20 VeeT 发射端地
本实施例中，业务单板BV通过金手指连接器6中的通过第7引脚RS0与第9引脚RS1输出数据传输速率指令至主控单元101，其中，所述数据传输速率指令可由第7引脚RS0与第9引脚RS1的电平进行表征，例如第7引脚RS0与第9引脚RS1分别通过高电平或者低电平的组合来表征当前光驱动处理模组102以及光接收模组4需要执行数据传输的速率。本实施例中，第7引脚RS0与第9引脚RS1即为金手指连接器6中多个引脚中用户可以自定义的引脚。
举例而言，第7引脚RS0与第9引脚RS1的电平信息与数据传输速率指令中包含的数据传输速率的对应关系可以为如下表2所示。
表2
RS0 RS1 数据传输速率
0 0 1.25Gbit/s、2.5Gbit/s、4.9Gbit/s、6.9Gbit/s、9.8Gbit/s
0 1 24.3Gbit/s、25.7Gbit/s、28Gbit/s
1 0 56.5Gbit/s
1 1 113.1Gbit/s
当然，在本申请其他实施例中，第7引脚RS0与第9引脚RS1的电平信息与数据传输速率指令的对应关系也可以执行调整，并不以此为限。
主控单元101自第7引脚RS0与第9引脚RS1读取其电平而获得数据传输速率指令中包含的数据传输速率后，并依据数据传输速率指令在内部的寄存位置写入对应的数值。
具体的，主控单元中内部的寄存位置可以为8位存储位，如表3所示，其中，在第2位置和第3位置写入自第7引脚RS0与第9引脚RS1读取的电平信息。
表3
7 RS1
6 RS0
5 保留
4 保留
3 RS0管脚电平
2 RS1管脚电平
1 保留
0 保留
请继续参阅图6，如图6所示，主控单元101通过I2C总线端口获得驱动处理模组102以及光接收模组4电性连接并传输对应所述数据传输速率指令的控制信号。本实施例中，I2C总线端口包括第一控制端SCL与第二控制端SCA，主控单元101则通过第一控制端SCL与第二控制端SCA分别与驱动处理模组102以及光接收模组4电性连接，并且通过第一控制端SCL与第二控制端SCA所传输的电平信号来构成所述控制信号，从而控制过光驱动处理模组102以及光接收模组4的工作状态与工作模式。本实施例中，第一控制端SCL与第二控制端SCA所传输的电平信号可以为TTL电平。
请参阅表4与表5，分别为驱动处理模组102以及光接收模组4的工作状态与第一控制端SCL与第二控制端SCA中电平信号的对应关系。
表4
第一控制端SCL电平 第二控制端SCA电平 跨阻放大器工作模式
0 0 限幅模式
0 1 限幅模式
1 0 线性模式
1 1 线性模式
表5
Figure PCTCN2020135925-appb-000001
请参阅表6，其为分别第一控制端SCL与第二控制端SCA中电平信号表征的控制信号与驱动处理模组102、光接收模组4的工作状态以及数据传输速率的对应关系。如表6所示，通过调整第一控制端SCL与第二控制端SCA中电平信号控制驱动处理模组102、光接收模组4的工作状态，即可灵活地调整光电信号转换器10的数据传输速率，从而能够完全不需要针对光电信号转换器10的硬件结构进行调整的情况下，适应数据传输速率在适应5G网络传输需要的25Gb/s数据传输速率，还能够同时向上兼容50Gb/s的数据传输速率、甚至100Gb/s数据传输速率的提升。
表6
Figure PCTCN2020135925-appb-000002
Figure PCTCN2020135925-appb-000003
在本申请其他实施例中，光驱动处理模组102以及光接收模组4也可以将自I2C总线接口接收到的信号写入预设的存储位置，例如写入内部寄存器中控制的位置。后续则可以直接通过读取预设的存储位置的信息即可直接执行对应速率的数据传输。
本实施例中，预设位置可以为8位存储位，光驱动处理模组102以及光接收模组4存储位置设置示意图。举例而言，光驱动处理模组102以及光接收模组4存储位置设置示意图可以为如表7所示：
表7
Figure PCTCN2020135925-appb-000004
请参阅图7-图8，图7为如图5或者如图6所示光接收模组4连接端的立体结构示意图，图8为图7所示光接收模组4的电路结构与连接端的连接示意图。
如图7与图8所示，光接收模组4包括8个连接端子，所述8个连接端子分别为：1 VPD、2 VCC、3 OUTN、4 OUTP、5 SCL、6 SDA、7 GND、8 GND。其中，连接端子2 VCC配合连接端子7 GND、连接端子8 GND为光接收模组4提供驱动电源。连接端子3 OUTN与4 OUTP配合执行数据输出。
连接端子5 SCL与连接端子6 SDA电性连接I2C端子，以自主控单元101接收表征其需要工作模式的信号。具体地，连接端子5 SCL与连接端子6 SDA所接收的电平信号与光接收模组4中跨阻放大器42的工作模式对应关系可参见表4。
如图8所示，光接收模组4中跨阻放大器42依据连接端子5 SCL与连接端子6 SDA接收到的电平信号来判断当前处于限幅模式或者线性模式，从而与第一时钟和数据恢复电路的工作模式配合按照对应的数据传输速率执行数据接收。
举例来说，结合表4-表7，对于小带宽数据传输时，业务单板BV从第7引脚RS0与第9引脚RS1分别输出两个低电平(00)，也即是控制第7引脚RS0与第9引脚RS1的 电平为低电平，那么主控单元101则输出00的控制信号至光处理驱动模组102与跨阻放大器4。
当连接端子5 SCL与连接端子6 SDA接收到的电平信号为00时，跨阻放大器42工作在限幅模式，限幅放大器1021处于工作状态，此时，对应连接端子5 SCL与连接端子6 SDA接收到的电平信号为00时，第一时钟和数据恢复电路102a和第二时钟和数据恢复电路102b处于旁路未工作时，光处理驱动模组102按照10Gb/s及其以下数据传输速率执行数据传输，以满足小宽带数据传输。
对于中带宽数据传输时，业务单板BV从第7引脚RS0与第9引脚RS1分别输出一个低电平与一个高电平(01)，也即是控制第7引脚RS0与第9引脚RS1的电平分别为低电平与高电平，那么主控单元101则输出01的控制信号至光处理驱动模组102与跨阻放大器42，那么主控单元101则输出01的控制信号至光处理驱动模组102与跨阻放大器42。
对应连接端子5 SCL与连接端子6 SDA接收到的电平信号为01时，第一时钟和数据恢复电路102a和第二时钟和数据恢复电路102b处于NRZ模式，跨阻放大器42工作在限幅模式，限幅放大器1021对应处于工作状态，光处理驱动模组102按照25Gb/s左右数据传输速率执行数据传输，以满足中宽带数据传输。
对于大带宽数据传输时，业务单板BV从第7引脚RS0与第9引脚RS1分别输出一个高电平与一个低电平(01)或者两个高电平(11)，也即是控制第7引脚RS0与第9引脚RS1的电平分别为高电平与低电平或者两个高电平，那么主控单元101则输出10或者11的控制信号至光处理驱动模组102与跨阻放大器42，那么主控单元101则输出10或者11的控制信号至光处理驱动模组102与跨阻放大器42。
当连接端子5 SCL与连接端子6 SDA接收到的电平信号为10或者11时，跨阻放大器42工作在线性模式，此时，对应连接端子5 SCL与连接端子6 SDA接收到的电平信号为10时，第一时钟和数据恢复电路102a和第二时钟和数据恢复电路102b处于50Gb/s的PAM4模式，跨阻放大器42工作在线性模式，限幅放大器1021对应处于旁路未工作状态，光处理驱动模组102按照50Gb/s左右的数据传输速率执行数据传输。对应连接端子5 SCL与连接端子6 SDA接收到的电平信号为11时，第一时钟和数据恢复电路102a和第二时钟和数据恢复电路102b处于100Gb/s的PAM4模式，跨阻放大器42工作在线性模式，限幅放大器1021对应处于旁路未工作状态，光处理驱动模组102按照100Gb/s左右的数据传输速率执行数据传输，以满足大宽带数据传输。
可见，通过调整第一控制端SCL与第二控制端SCA中电平信号，控制驱动处理模组102、与光接收模组4的工作状态，即可灵活地调整光电信号转换器10的数据传输速率，从而能够完全不需要针对光电信号转换器10的硬件结构进行调整的情况下，适应数据传输速率在适应5G网络传输需要的25Gb/s数据传输速率，还能够同时向上兼容50Gb/s的数据传输速率、甚至100Gb/s数据传输速率的提升。
在本申请其他实施例中，光电信号转换器10还可以包括多个光发射模组与多个光接收模组，从而能够进一步提高数据传输速率。例如，包括2个光发射模组与2个光接收模组，构成二通道的DSFP封装；或者，包括4个光发射模组与4个光接收模组，构成四通道的QSFP封装；8个光发射模组与8个光接收模组，构成八通道的DSFP-DD封装。其中，所 述多个光发射模组与所述多个光接收模组分时接收或者发射光电信号。
由此，二通道的DSFP封装能够支持200Gb/s、100Gb/s、50Gb/s、25Gb/s、10Gb/s及其以下数据传输速率；四通道的QSFP封装能够支持400Gb/s、200Gb/s、100Gb/s、50Gb/s、20Gb/s、及其以下数据传输速率；八通道的DSFP-DD封装能够支持800Gb/s、200Gb/s、100Gb/s、50Gb/s、20Gb/s及其以下数据传输速率。
以上所述是本申请的优选实施例，应当指出，对于本技术领域的普通技术人员来说，在不脱离本申请原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也视为本申请的保护范围。

Claims (18)

  1. 一种光电信号转换器，其特征在于，包括，主控单元、光驱动处理模组、光发射模组与光接收模组，所述主控单元电性连接于所述光驱动处理模组以及所述光接收模组，所述光发射模组电性连接于所述光驱动处理模组，其中，
    所述光接收模组用于自接收光纤接收光信号并且将所述光信号转换为电信号，所述光接收模组包括线性工作模式与限幅工作模式；
    所述光发射模组用于自所述光驱动处理模组接收电信号并转换为光信号；
    所述主控单元用于接收数据传输速率指令，并且依据所述数据传输速率指令输出控制信号至所述光驱动处理模组以及所述光接收模组；
    所述光驱动处理模组用于接收光接收模组提供的经转换后的电信号并转换为数据信号输出，以及将接收到的数据信号转换为电信号并传输至所述光发射模组，所述光驱动处理模组执行第一数据传输速率或者第二数据传输速率，所述光驱动处理模组依据所述控制信号工作于所述第一数据传输速率或者所述第二数据传输速率，所述第一数据传输速率小于或者等于25Gb/s，所述第二数据传输速率大于或者等于50Gb/s；
    所述光发射模组将接收到的所述电信号转换为光信号并输出至发送光纤。
  2. 根据权利要求1所述的光电信号转换器，其特征在于，所述光驱动处理模组包括分别电性连接于所述主控单元的限幅放大器、第一时钟和数据恢复电路、第二时钟和数据恢复电路以及驱动电路，
    所述限幅放大器电性连接于所述光接收模组与第一时钟和数据恢复电路；
    第二时钟和数据恢复电路还电性连接所述驱动电路；
    所述第一时钟和数据恢复电路用于将电信号解码并转换为数据信号输出；
    所述第二时钟和数据恢复电路用于将接收的数据信号编码并转换为电信号；
    所述第一时钟和数据恢复电路、第二时钟和数据恢复电路包括NZR模式与PAM4模式，所述NZR模式对应所述第一数据传输速率，所述PAM4模式对应所述第二数据传输速率；
    所述驱动电路包括限幅模式与线性模式；
    当所述控制信号控制所述第一时钟和数据恢复电路与第二时钟和数据恢复电路工作在所述NZR模式时，同时控制所述驱动电路与限幅放大器工作于限幅模式，所述光驱动处理模组按照第一数据传速率数据。
  3. 根据权利要求2所述的光电信号转换器，其特征在于，所述光接收模组还包括跨阻放大器，所述跨阻放大器包括线性模式与限幅模式；
    当所述控制信号控制所述第一时钟和数据恢复电路与第二时钟和数据恢复电路工作在所述PAM模式时，同时控制所述驱动电路或者所述跨阻放大器工作于线性模式，所述光驱动处理模组按照所述第二数据传速率数据。
  4. 根据权利要求2-3任意一项所述的光电信号转换器，其特征在于，当所述第一时钟和数据恢复电路与第二时钟和数据恢复电路工作在所述PAM4模式，同时控制所述驱动电 路与所述跨阻放大器工作于线性模式，所述控制信号控制所述限幅放大器旁路并停止工作。
  5. 根据权利要求4所述的光电信号转换器，其特征在于，
    所述光接收模组包括多个连接端子，所述多个连接端子电性连接于所述主控单元与连接器的连接端口，其中，所述多个连接端子中的两个连接于所述跨阻放大器的连接端子通过I2C总线连接端连接于所述主控单元，所述两个连接端子用于自所述主控单元接收所述控制信号，所述两个连接端子的电平信号用于表征所述控制信号。
  6. 根据权利要求5所述的光电信号转换器，其特征在于，所述光接收模组八个同轴结构的所述连接端，其中，所述八个连接端中的表征I2C总线端口中SCL控制端与SDA数据端作为连接于所述跨阻放大器的连接端子。
  7. 根据权利要求6所述的光电信号转换器，其特征在于，所述主控单元通过I2C总线连接端包括的第一控制端与第二控制端分别电性连接所述限幅放大器、所述第一时钟和数据恢复电路、所述第二时钟和数据恢复电路以及所述驱动电路，所述第一控制端与所述第二控制端传输的电平信号表征所述控制信号，其中，所述光接收模组中所述两个连接于所述跨阻放大器的连接端分别电性连接于所述第一控制端与所述第二控制端。
  8. 根据权利要求1-7任意一项所述的光电信号转换器，其特征在于，
    当所述跨阻放大器工作在所述限幅模式，所述第一时钟和数据恢复电路和所述第二时钟和数据恢复电路处于旁路未工作时，所述限幅放大器处于工作状态，所述光处理驱动模组按照第三数据传输速率执行数据传输，所述第三数据传输速率小于第一数据传输速率；
    当所述跨阻放大器工作在所述限幅模式，所述第一时钟和数据恢复电路和所述第二时钟和数据恢复电路处于NRZ模式，所述限幅放大器对应处于工作状态，所述光处理驱动模组按照第一数据传输速率执行数据传输；
    当跨阻放大器工作在所述线性模式，所述第一时钟和数据恢复电路和所述第二时钟和数据恢复电路处于PAM4模式，所述限幅放大器处于旁路未工作状态，所述光处理驱动模组按照所述第二数据传输速率执行数据传输。
  9. 根据权利要求8所述的光电信号转换器，其特征在于，所述光电信号转换器还包括金手指连接端，所述金手指连接端的包括多个引脚，所述引脚通过导电线路连接于所述主控单元与所述光驱动处理模组，所述金手指连接端用于连接于需要执行数据交互的业务单板，所述多个引脚中至少两个引脚电性连接所述主控单元以接收自所述业务单板输出的数据传输速率指令，所述数据传输速率指令包括所述光驱动处理模组需要执行数据传输的数据传输速率。
  10. 根据权利要求9所述的光电信号转换器，其特征在于，所述光电信号转换器包括多个光发射模组与多个光接收模组，所述多个光发射模组与所述多个光接收模组分时接收或 者发射光电信号。
  11. 一种光驱动处理模组，应用于光电信号转换器，其特征在于，
    接收一光接收模组提供的经转换后的电信号并转换为数据信号输出，以及将接收到的数据信号转换为电信号并传输至光发射模组；
    依据控制信号工作于第一数据传输速率或者第二数据传输速率，所述第一数据传输速率小于或者等于25Gb/s，所述第二数据传输速率大于或者等于50Gb/s，其中，所述控制信号为依据表征数据传输速率的数据传输速率指令输出。
  12. 根据权利要求11所述的光驱动处理模组，其特征在于，所述光驱动处理模组包括分别电性连接于主控单元的限幅放大器、第一时钟和数据恢复电路、第二时钟和数据恢复电路以及驱动电路，
    所述限幅放大器电性连接于所述光接收模组与第一时钟和数据恢复电路；
    第二时钟和数据恢复电路还电性连接所述驱动电路；
    所述第一时钟和数据恢复电路用于将电信号解码并转换为数据信号输出；
    所述第二时钟和数据恢复电路用于将接收的数据信号编码并转换为电信号；
    所述第一时钟和数据恢复电路、第二时钟和数据恢复电路包括NZR模式与PAM4模式，所述NZR模式对应所述第一数据传输速率，所述PAM4模式对应所述第二数据传输速率；
    所述驱动电路包括限幅模式与线性模式；
    当所述控制信号控制所述第一时钟和数据恢复电路与第二时钟和数据恢复电路工作在所述NZR模式时，同时控制所述驱动电路与限幅放大器工作于限幅模式，所述光驱动处理模组按照第一数据传速率数据；
    其中，主控单元用于接收数据传输速率指令，并且依据所述数据传输速率指令输出所述控制信号至所述光驱动处理模组。
  13. 根据权利要求12所述的光驱动处理模组，其特征在于，
    当所述控制信号控制所述第一时钟和数据恢复电路与第二时钟和数据恢复电路工作在所述PAM模式时，同时控制所述驱动电路或者跨阻放大器工作于线性模式，所述光驱动处理模组按照所述第二数据传速率数据，其中，所述跨阻放大器设置于自接收光纤接收光信号并且将所述光信号转换为电信号的光接收模组中。
  14. 根据权利要求13所述的光接收模组，其特征在于，
    所述跨阻放大器包括线性模式与限幅模式，
    当所述第一时钟和数据恢复电路与第二时钟和数据恢复电路工作在所述PAM4模式，同时控制所述驱动电路与所述跨阻放大器工作于线性模式，所述控制信号控制所述限幅放大器旁路并停止工作。
  15. 根据权利要求13或者14所述的光接收模组，其特征在于，
    当所述跨阻放大器工作在所述限幅模式，所述第一时钟和数据恢复电路和所述第二时钟和数据恢复电路处于旁路未工作时，所述限幅放大器处于工作状态，所述光处理驱动模组按照第三数据传输速率执行数据传输，所述第三数据传输速率小于第一数据传输速率；
    当所述跨阻放大器工作在所述限幅模式，所述第一时钟和数据恢复电路和所述第二时钟和数据恢复电路处于NRZ模式，所述限幅放大器对应处于工作状态，所述光处理驱动模组按照第一数据传输速率执行数据传输；
    当跨阻放大器工作在所述线性模式，所述第一时钟和数据恢复电路和所述第二时钟和数据恢复电路处于PAM4模式，所述限幅放大器处于旁路未工作状态，所述光处理驱动模组按照所述第二数据传输速率执行数据传输。
  16. 一种光接收模组，应用于光电信号转换器，其特征在于，
    所述光接收模组用于自接收光纤接收光信号并且将所述光信号转换为电信号，所述光接收模组包括线性工作模式与限幅工作模式；
    所述光接收模组还包括跨阻放大器，所述跨阻放大器包括线性模式与限幅模式；
    所述光接收模组包括多个连接端子，所述多个连接端子电性连接于所述主控单元与连接器的连接端口，其中，所述多个连接端子中的两个连接于所述跨阻放大器的连接端子通过I2C总线连接端连接于所述主控单元，所述两个连接端子用于自所述主控单元接收控制信号，所述两个连接端子的电平信号用于表征所述控制信号，所述控制信号为依据表征数据传输速率的数据传输速率指令输出并控制光接收数据时的速率。
  17. 根据权利要求16所述的光接收模组，其特征在于，所述光接收模组八个同轴结构的所述连接端，其中，所述八个连接端中的表征I2C总线端口中SCL控制端与SDA数据端作为连接于所述跨阻放大器的连接端子。
  18. 一种网络交互设备，其特征在于，包括权利要求1-10任一项所述的光电信号转换器。
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