WO2021115377A1 - 封装方法、封装结构及封装模块 - Google Patents

封装方法、封装结构及封装模块 Download PDF

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Publication number
WO2021115377A1
WO2021115377A1 PCT/CN2020/135264 CN2020135264W WO2021115377A1 WO 2021115377 A1 WO2021115377 A1 WO 2021115377A1 CN 2020135264 W CN2020135264 W CN 2020135264W WO 2021115377 A1 WO2021115377 A1 WO 2021115377A1
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WIPO (PCT)
Prior art keywords
package
interconnection structure
components
pads
package body
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PCT/CN2020/135264
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English (en)
French (fr)
Inventor
李衡军
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中兴通讯股份有限公司
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Publication of WO2021115377A1 publication Critical patent/WO2021115377A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/13—Moulding and encapsulation; Deposition techniques; Protective layers
    • H05K2203/1305—Moulding and encapsulation
    • H05K2203/1316—Moulded encapsulation of mounted components

Definitions

  • the present disclosure relates to the technical field of electronic packaging, and in particular, to a packaging method, a packaging structure and a packaging module.
  • PCBs printed circuit boards
  • a package on package (Package on Package, PoP for short) packaging form.
  • a base substrate is plastic-encapsulated to form a package, and then the package is laser-drilled.
  • the holes are filled with conductive media such as solder paste, silver paste, etc., and then pads are made on the outer surface of the package.
  • the stacked components on the package are electrically interconnected with the circuit in the base substrate through the pad, the conductive medium, and the copper pillar in sequence.
  • the above-mentioned interconnection path is long, the package structure is complicated, and the connection between the conductive medium and the copper pillar in the package is located inside the package, and the connection reliability is poor.
  • the present disclosure proposes a packaging method, a packaging structure, and a packaging module, which can reduce interconnection paths, simplify the packaging structure, and improve connection reliability.
  • the present disclosure provides an encapsulation method, the encapsulation method includes:
  • Two mountings in which the base body package on which the components and the interconnection structure are mounted is formed into a package, and each of the pads located on the opposite side of the interconnection structure are separated from each other from the package body The surface is exposed so as to be able to be interconnected with the stacked body and the printed circuit board respectively.
  • the present disclosure also provides a packaging structure, including:
  • the package body is used to package the components, the interconnection structure, and the base body as a whole, and the package body is arranged such that each of the pads located on the opposite side of the interconnection structure are separated from each other.
  • the two mounting surfaces facing away from each other of the package body are exposed so as to be able to be interconnected with the stacked body and the printed circuit board respectively.
  • the present disclosure also provides a package module, including:
  • the stacked body is stacked on the packaging structure and interconnected with one of the pads of the packaging structure.
  • FIG. 1 is a flowchart of a packaging method provided by an embodiment of the disclosure
  • FIG. 2 is a process diagram of the packaging method provided by an embodiment of the disclosure.
  • FIG. 3 is another process diagram of the packaging method provided by an embodiment of the present disclosure.
  • FIG. 4 is a cross-sectional view of a package structure provided by an embodiment of the disclosure.
  • FIG. 5 is another cross-sectional view of the package structure provided by the embodiment of the disclosure.
  • the packaging method provided by the embodiment of the present disclosure includes:
  • Step 101 Provide a substrate 1.
  • the base 1 is a laminated substrate.
  • the base 1 may also adopt any other structure, such as a lead frame.
  • the base 1 includes a component mounting surface 11. Before the component 2 is installed, the component mounting surface 11 may be subjected to necessary surface treatment to facilitate the interconnection process of the component 2 such as welding and wire bonding.
  • Step 102 Mount the components 2 and the interconnection structure 3 on the substrate 1.
  • the component 2 includes a chip, a capacitor, a resistor, an inductor, and so on.
  • the welding of the component 2 can be realized by means of wire bonding, flip-chip welding, SMT surface mount, etc.
  • the component 2 can be connected to the interconnection structure 3 by bonding, soldering, wire bonding, etc., or can be directly soldered on the pads of the interconnection structure 3.
  • step 102 specifically includes:
  • Step 1021 as shown in the diagram (a) in FIG. 2, a through hole 12 penetrating the substrate 1 is formed in the substrate 1.
  • an adhesive film (not shown in the figure) is provided on the surface of the substrate 1 that is away from the plane where the components 2 are located. After the adhesive film is irradiated by UV light or baked at a high temperature, it loses its viscosity and can be peeled off.
  • Step 1023 mount the component 2 on the base 1, and fix the interconnection structure 3 in the through hole 12 through the above-mentioned adhesive film.
  • Step 103 As shown in the diagram (c) in FIG. 2, the base body 1 on which the components 2 and the interconnection structure 3 are mounted is packaged to form a package body 4, and the two ends (31, 32) of the interconnection structure 3 ) Are exposed from the two mounting surfaces (41, 13) of the package body 4 away from each other, so as to be able to be interconnected with the stacked body 5 and the printed circuit board 6 respectively.
  • the surface of the base 1 facing away from the component mounting surface 11 is not covered by the package 4, and this surface is used as one of the mountings of the package 4 interconnected with the printed circuit board 6.
  • Surface 13 the base 1 can also be completely encapsulated in the package 4.
  • the manner of forming the package body 4 by the above-mentioned packaging is, for example, plastic packaging.
  • the package body 4 uses an ABF-like material, which has good adhesion with interconnecting materials such as copper, and meets the reliability requirements.
  • the package body 4 may be surface treated to facilitate interconnection with the stacked body.
  • the surface treatment may be an electroplating process such as chemical tin, chemical silver, nickel gold, surface anti-oxidation, nickel palladium gold, and the like.
  • step 103 after step 103, it further includes:
  • the interconnection structure 3 is a conductive pillar, and the opposite sides of the interconnection structure 3 respectively have two end portions (31, 32), which are the two end faces of the conductive pillar.
  • the interconnection structure 3 may also be any other structure such as a conductive sheet or a conductive frame, and the opposite sides of these structures have pads respectively.
  • the material used in the interconnect structure is, for example, copper.
  • the two ends (31, 32) of the interconnection structure 3 are exposed from the two mounting surfaces (41, 13) of the package 4 that are away from each other, which means the two ends
  • the parts (31, 32) are not covered by the package body 4.
  • the two end portions (31, 32) are respectively flush with the two mounting surfaces (41, 13) of the package body 4, or may also protrude relative to the two mounting surfaces (41, 13) .
  • each interconnection structure 3 has a pad on the opposite side.
  • the mask is removed, so that the two ends (31, 32) of the interconnect structure 3 are exposed.
  • Another method may be used to expose the two ends (31, 32) of the interconnect structure 3, and the method specifically includes:
  • step 103 after exposing the two ends (31, 32) of the interconnection structure 3 from the two mounting surfaces (41, 13) of the package 4 that are away from each other, the method further includes:
  • two pads (33a, 33b) are formed on the two mounting surfaces (41, 13) of the package body 4, respectively, which are interconnected with the two ends (31, 32). ).
  • the orthographic projection area of the two pads (33a, 33b) on the two mounting surfaces (41, 13) can be larger or smaller than that of the two ends (31, 32) respectively on the two mounting surfaces.
  • the orthographic projection area on (41,13) can meet different interconnection requirements.
  • the pads can be made by printing solder paste and reflow soldering.
  • the two pads (33a, 33b) are surface treated to protect the pad surface and make it easy to solder.
  • one of the pads 33 b is embedded in the base 1. Furthermore, the bottom surface of the pad 33b and the mounting surface 13 may be flush with each other, or may be recessed with respect to the mounting surface 13.
  • the method further includes:
  • a metal protective layer is made on the two pads (33a, 33b) respectively.
  • the metal protective layer can be made by electrochemical treatment, and the metal protective layer is, for example, a nickel-gold layer, a nickel-palladium-gold layer, a silver layer, an OSP layer, and so on.
  • a structure such as a ball grid array structure (Ball Grid Array Package, BGA) or a grid array structure (Land Grid Array, LGA) can be provided on both of the two pads (33a, 33b).
  • BGA Ball Grid Array Package
  • LGA grid array structure
  • the structure has the advantages of improving assembly yield and improving heat dissipation performance.
  • FIG. 2 it is a process diagram of completing the interconnection between the stacked body 5 and the printed circuit board 6.
  • the stacked body 5 is interconnected with the interconnection structure 3 through the pad 33a
  • the printed circuit board 6 is interconnected with the interconnection structure 3 through the pad 33b, thereby realizing the interconnection between the stacked body 5 and the printed circuit board 6.
  • this reduces interconnection paths and simplifies the packaging structure.
  • the stacked body 5 is interconnected with the interconnection structure 3 through the bonding pad 33a, and the printed circuit board 6 is interconnected with the interconnection structure 3 through the bonding pad 33b, but the present disclosure is not limited.
  • the stacked body 5 may also be interconnected with the interconnect structure 3 through the pad 33b, and the printed circuit board 6 may be interconnected with the interconnect structure 3 through the pad 33a.
  • the stacked body 5 includes a stacked package and/or stacked components.
  • stacked components include chips, capacitors, resistors, inductors, and so on.
  • the stacked package may be the same package as the package structure adopted in this embodiment.
  • wiring processing is performed on at least one of the two mounting surfaces (41, 13) of the package 4 to form a lead structure.
  • the lead structure can be used for interconnection between different stacks, and can also be used for interconnection with the stack 5 or the printed circuit board 6. In this way, the stacking of multiple devices can be realized and the space limitation is overcome.
  • the above-mentioned step 102 may also adopt other implementation methods, and the method specifically includes:
  • Step 1021' as shown in Figure 3 (a), a blind hole 14 of a specified depth is provided on the first surface of the base 1 (that is, the upwardly facing surface of the base 1 in Figure (a)).
  • the above-mentioned specified depth can be set according to the specific thickness of the base 1.
  • Step 1022' setting a colloid (not shown in the figure) at the bottom of the blind hole 14.
  • the above-mentioned colloid remains in the blind hole 14 without peeling.
  • the glue is, for example, epoxy glue.
  • Step 1023' mount the component 2 on the base 1, and fix the interconnection structure 3 in the blind hole 14 through the above-mentioned glue.
  • One end 32 of the above-mentioned interconnection structure 3 is located in the blind hole 14, and the other end 31 is located outside the blind hole 14.
  • step 103 specifically includes:
  • Step 1031 package the base 1 on which the components 2 and the interconnection structure 3 are mounted to form a package body 4, and make the end 31 outside the blind hole 14 self-mounting surface 41 exposed.
  • step 1032 as shown in (d) in FIG. 3, a pad 33a interconnected with the end portion 31 is formed on the mounting surface 41 of the package body 4.
  • Step 1033 As shown in the diagram (e) in FIG. 3, the second surface of the base 1 that is away from the first surface, that is, one of the mounting surfaces of the package 4 that is interconnected with the printed circuit board 6 13 is etched to open the blind hole 14 to form a through hole 14a.
  • the etching method specifically uses a patterned mask to etch the package body 4.
  • a laser can also be used to punch through the blind holes 14.
  • Step 1034 Remove the glue on the end 32 of the interconnect structure 3, so that the end 32 of the interconnect structure 3 is exposed through the through hole 14a.
  • the colloid can be removed by laser burning, for example.
  • the mounting surface 13 of the package body 4 is polished and thinned as a whole on the package body 4 until the end 32 of the interconnection structure 3 is flush with the mounting surface 13.
  • an extension portion 34 may be formed on the end portion 32 located in the through hole 14a, and at least a part of the extension portion 34 is used as a pad, and The other mounting surface 13 is exposed, that is, it is flush with the mounting surface 13 or protrudes relative to the mounting surface 13.
  • a pad with a larger welding area can also be made on the mounting surface 13 and interconnected with the extension part.
  • FIG. 3 it is a process diagram of completing the interconnection between the stacked body 5 and the printed circuit board 6.
  • the stacked body 5 is interconnected with the interconnection structure 3 through the pad 33a
  • the printed circuit board 6 is interconnected with the interconnection structure 3 through the extension portion 34, thereby realizing the interconnection between the stacked body 5 and the printed circuit board 6.
  • this reduces interconnection paths and simplifies the packaging structure.
  • the stacked body 5 is interconnected with the interconnection structure 3 through the pad 33a, and the printed circuit board 6 is interconnected with the interconnection structure 3 through the extension part 34, but the present disclosure is not limited Herein, in practical applications, the stacked body 5 may also be interconnected with the interconnection structure 3 through the extension portion 34, and the printed circuit board 6 may be interconnected with the interconnection structure 3 through the pad 33a.
  • An embodiment of the present disclosure also provides a package structure, which includes a base 1 and a package 4, wherein the base 1 is provided with a component 2 and two pads (33a , 33b) of the interconnection structure 3; the package body 4 is used to package the components 2, the interconnection structure 3 and the base body 4 as a whole, and the package body 4 is arranged so that the two pads (33a, 33b) are self-contained The two mounting surfaces of the package body 4 facing away from each other are exposed, so that the two pads (33a, 33b) can be interconnected with the stacked body 5 and the printed circuit board 6, respectively.
  • the base 1 is an organic packaging substrate.
  • the base 1 may also adopt any other structure, such as a frame structure.
  • the component 2 includes a chip, a capacitor, a resistor, an inductor, and so on.
  • the component 2 can be connected to the interconnection structure 3 by fabricating conductors in the package 4 by bonding, welding, wire bonding, etc.; or, at least a part of the component 2 is stacked on the pad and located inside the package 4 , And interconnect with the pad. In this way, the component 2 can be directly interconnected with the printed circuit board 6 through the interconnection structure 3.
  • the interconnection structure 3 includes a conductive pillar, a conductive sheet, or a conductive frame, etc.
  • two pads (33a, 33b) are respectively provided at the two ends of the conductive pillar.
  • the orthographic projected area of the two pads (33a, 33b) on the radial cross-section of the conductive cylinder is larger than the radial cross-sectional area of the conductive cylinder. In this way, the welding area can be expanded to meet welding needs.
  • the orthographic projection area of the two pads (33a, 33b) on the radial cross-section of the conductive cylinder can also be made smaller than the radial cross-sectional area of the conductive cylinder according to the needs of the cloth strip.
  • the first packaging structure 100a and the second packaging structure 100b there are two sets of packaging structures, the first packaging structure 100a and the second packaging structure 100b, respectively. They are stacked together in sequence, and the pads of the first package structure 100a and the second package structure 100b are interconnected, that is, the top pads of the first package structure 100a and the bottom pads of the second package structure 100b are interconnected. The bottom pad of the first package structure 100a is interconnected with the printed circuit board 6.
  • the pads on any side of one of the package structures can be interconnected with the pads on any side of the other package structure.
  • the pads on the side away from each other of the two adjacent packaging structures can be used for interconnection with the printed circuit board 6.
  • the base 1 is used to mount the components 2 and the interconnection structure 3, and the package 4 is used to package the base 1 on which the components 2 and the interconnection structure 3 are mounted as a whole, so as to realize the interconnection.
  • the connection structure 3 is fixed, and this fixing method is more stable than the prior art, so that the connection stability can be improved.
  • by exposing the two pads (33a, 33b) of the interconnection structure 3 from the two mounting surfaces of the package 4 that are away from each other they can be interconnected with the stacked body 5 and the printed circuit board 6 respectively.
  • the stacked body 5 can be directly interconnected with the printed circuit board 6 through the interconnection structure 3, thereby reducing interconnection paths and simplifying the packaging structure.
  • the shape and internal structure of the package structure provided in the above embodiment are only an example.
  • the package structure may also have other shapes and internal structures, which are not limited in this embodiment.
  • an embodiment of the present disclosure further provides a package module, which includes a package structure and a stacked body, wherein the stacked body is stacked on the package structure and is interconnected with one of the pads of the package structure.
  • the stacked body 5 is stacked on the package structure and is interconnected with one of the pads 33a of the package structure.
  • the package module provided in this embodiment can reduce interconnection paths, simplify the package structure, and improve connection reliability.
  • the devices mentioned in the foregoing embodiments include chips, passive devices, or flip-chips, etc. This embodiment does not specifically limit the types and shapes of packaged devices.
  • the base is used to install components and interconnection structures
  • the package is used to package the base on which the components and interconnect structures are mounted as a whole, thereby
  • the fixing of the interconnection structure is realized, and this fixing method is more stable than the prior art, so that the connection stability can be improved.
  • by exposing the two pads of the interconnection structure from the two mounting surfaces of the package away from each other they can be interconnected with the stacked body and the printed circuit board respectively. Therefore, the stacked body can be directly interconnected with the printed circuit board through the interconnection structure, thereby reducing the interconnection path and simplifying the packaging structure.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

提供一种封装方法、封装结构及封装模块，该封装方法包括：提供一基体（101）；在基体上安装元器件和互连结构，该互连结构的对侧分别具有焊盘（102）；对安装有元器件和互连结构的基体封装形成封装体，且使位于互连结构对侧的各焊盘分别自封装体相互背离的两个安装面暴露出来，以能够分别与堆叠体和印制电路板互连（103）。

Description

封装方法、封装结构及封装模块
相关申请的交叉引用
本公开要求享有2019年12月13日提交的名称为“封装方法、封装结构及封装模块”的中国专利申请CN201911283550.8的优先权，其全部内容通过引用并入本文中。
技术领域
本公开涉及电子封装技术领域，具体地，涉及一种封装方法、封装结构及封装模块。
背景技术
随着电子设备的高速发展，印制电路板(Printed Circuit board，以下简称PCB)上的电子元器件的密度越来越高，要求在同样甚至更小的空间内安装更多的电子元器件。
在某些情况中，存在一种封装体上堆叠封装体(Package on Package，简称PoP)的封装形式，例如，将衬底基板塑封形成封装体，然后通过对封装体进行激光打孔，并在孔中填充诸如锡膏、银浆等的导电介质，然后在封装体的外表面上制作焊盘。将封装体上的堆叠元器件依次通过焊盘、导电介质、铜柱与衬底基板中的电路电性互连。
但是，上述互连路径较长，且封装结构复杂，并且导电介质与封装体中的铜柱之间的连接处位于封装体的内部，连接可靠性较差。
发明内容
针对上述问题，本公开提出了一种封装方法、封装结构及封装模块，其可以减少互连路径，简化封装结构，提高连接可靠性。
为实现上述目的，本公开提供了一种封装方法，所述封装方法包括：
提供一基体；
在所述基体上安装元器件和互连结构，所述互连结构的对侧分别具有焊盘；
对安装有所述元器件和所述互连结构的所述基体封装形成封装体，且使位于所述互连结构对侧的各所述焊盘分别自所述封装体相互背离的两个安装面暴露出来，以能够分别与堆叠体和印制电路板互连。
作为另一个技术方案，本公开还提供一种封装结构，包括：
基体，在所述基体上设置有元器件和互连结构，所述互连结构的对侧分别设置有焊盘；
封装体，用于将所述元器件、所述互连结构和所述基体封装为一体，且所述封装体被 设置为使位于所述互连结构对侧的各所述焊盘分别自所述封装体相互背离的两个安装面暴露出来，以能够分别与堆叠体和印制电路板互连。
作为另一个技术方案，本公开还提供一种封装模块，包括：
本公开提供的上述封装结构；
堆叠体，堆叠在所述封装结构上，且与所述封装结构的其中一所述焊盘互连。
附图说明
图1为本公开实施例提供的封装方法的流程框图；
图2为本公开实施例提供的封装方法的一种过程图；
图3为本公开实施例提供的封装方法的另一种过程图；
图4为本公开实施例提供的封装结构的一种剖视图；
图5为本公开实施例提供的封装结构的另一种剖视图。
具体实施方式
为使本领域的技术人员更好地理解本公开的技术方案，下面结合附图对本公开提供的封装方法、封装结构及封装模块进行详细描述。
请一并参阅图1和图2，本公开实施例提供的封装方法，其包括：
步骤101、提供一基体1。
在本实施例中，基体1为封装基板(laminated substrate)，当然，在实际应用中，基体1还可以采用其他任意结构，例如框架(lead frame)。
基体1包括元器件安装面11，在安装元器件2之前，可以对元器件安装面11进行必要的表面处理，以便于实现元器件2的诸如焊接、打线等的互连工艺。
步骤102、在基体1上安装元器件2和互连结构3。
在一些实施方案中，元器件2包括芯片、电容、电阻和电感等等。而且，可以采用焊线、倒装焊、SMT表贴等的方式实现元器件2的焊接。另外，元器件2可以通过粘接、焊接、打线等方式与互连结构3进行互连，或者还可以直接焊接在互连结构3的焊盘上。
在本实施例中，步骤102具体包括：
步骤1021、如图2中的图(a)所示，在基体1中形成贯通该基体1的通孔12。
步骤1022、在基体1的与元器件2所在平面相背离的表面上设置胶膜(图中未示出)。该胶膜在经过UV光照射或者高温烘烤之后，会失去粘性，从而能够剥离下来。
步骤1023、如图2中的图(b)所示，将元器件2安装在基体1上，并将互连结构3通过上述胶膜固定在通孔12中。
需要说明的是，互连结构3与基体1之间没有电性互连。
步骤103、如图2中的图(c)所示，对安装有元器件2和互连结构3的基体1封装形成封装体4，且使互连结构3的两个端部(31,32)分别自封装体4相互背离的两个安装面(41,13)暴露出来，以能够分别与堆叠体5和印制电路板6互连。
需要说明的是，在本实施例中，基体1的背离元器件安装面11的表面未被封装体4包覆，该表面用作封装体4的与印制电路板6互连的其中一安装面13。当然，在实际应用中，也可以完全将基体1封装在封装体4中。
在一些实施方案中，上述封装形成封装体4的方式例如为塑封。
在一些实施方案中，封装体4采用类ABF材料，该材料与铜等的互连材料之间的附着力较好，满足可靠性要求。
在一些实施方案中，在步骤103之后，可以对封装体4进行表面处理，以便于与堆叠体进行互连。该表面处理可以是诸如化学锡、化学银、镍金、表面抗氧化、镍钯金等的电镀工艺。
在一些实施方案中，在步骤103之后，还包括：
去除胶膜。
这样，互连结构3完全由封装体4固定。这种固定方式相对于现有技术更加稳定，从而可以提高连接稳定性。
在本实施例中，互连结构3为导电柱体，互连结构3的对侧分别具有两个端部(31,32)，二者即为导电柱体的两个端面。但是，本公开并不局限于此，在实际应用中，互连结构3还可以为诸如导电片或者导电框架等的其他任意结构，这些结构的对侧分别具有焊盘。互连结构所采用的材料例如为铜。
需要说明的是，在本实施例中，互连结构3的两个端部(31,32)分别自封装体4相互背离的两个安装面(41,13)暴露出来，是指两个端部(31,32)未被封装体4包覆。在一些实施方案中，两个端部(31,32)分别与封装体4的两个安装面(41,13)相平齐，或者也可以相对于两个安装面(41,13)凸出。
还需要说明的是，在本实施例中，在同一基体1上具有两个互连结构3，但是，本公开并不局限于此，在实际应用中，在同一基体1上还可以设置一个或三个以上的互连结构3。并且，各互连结构3的对侧均具有焊盘。
下文中仅针对任意一个互连结构3进行详细描述。
在步骤103中，将互连结构3的两个端部(31,32)裸露的一种方法具体包括：
在两个端部(31,32)上均覆盖掩膜；
对安装有元器件2和互连结构3的基体1封装形成封装体4，且上述掩膜相对于封装 体4裸露；
去除掩膜，从而实现互连结构3的两个端部(31,32)的裸露。
或者，将互连结构3的两个端部(31,32)裸露还可以采用另一种方法，该方法具体包括：
对安装有元器件2和互连结构3的基体1封装形成封装体4，且使封装体4完全包覆互连结构3；
对封装体4的两个安装面(41,13)分别进行研磨，直至互连结构3的两个端部(31,32)相对于封装体4裸露。
在本实施例中，在步骤103中，在使互连结构3的两个端部(31,32)自封装体4相互背离的两个安装面(41,13)暴露出来之后，还包括：
如图2中的图(d)所示，在封装体4的两个安装面(41,13)上形成分别与两个端部(31,32)互连的两个焊盘(33a,33b)。在实际应用中，可以使两个焊盘(33a,33b)分别在两个安装面(41,13)上的正投影面积大于或者小于两个端部(31,32)分别在两个安装面(41,13)上的正投影面积以满足不同的互连需求。具体地，焊盘可以采用印刷锡膏，并通过回流焊接等的方式制作。
另外，在一些实施方案中，对两个焊盘(33a,33b)进行表面处理，以保护焊盘表面，并使之易于焊接。
在本实施例中，为了便于将基体1安装在印制电路板6上，其中一焊盘33b内嵌在基体1中。而且，焊盘33b的底面与安装面13可以相互平齐，或者相对于安装面13凹进。
在一些实施方案中，在完成两个焊盘(33a,33b)的制作之后，还包括：
分别在两个焊盘(33a,33b)上制作金属保护层。
在一些实施方案中，金属保护层可以采用电化学处理的方式制作，该金属保护层例如为镍金层、镍钯金层、银层、OSP层等等。
在一些实施方案中，在两个焊盘(33a,33b)上均可以设置诸如球珊阵列结构(Ball Grid Array Package，BGA)或者栅格阵列结构(Land Grid Array，LGA)等的结构，该结构具有提高组装成品率、提高散热性能等优点。
如图2中的图(e)所示，为完成堆叠体5和印制电路板6互连的过程图。其中，堆叠体5通过焊盘33a与互连结构3互连，印制电路板6通过焊盘33b与互连结构3互连，从而实现了堆叠体5与印制电路板6的互连。这与现有技术相比，减少了互连路径，简化了封装结构。
需要说明的是，在本实施例中，堆叠体5通过焊盘33a与互连结构3互连，印制电路板6通过焊盘33b与互连结构3互连，但是，本公开并不局限于此，在实际应用中，也可 以使堆叠体5通过焊盘33b与互连结构3互连，印制电路板6通过焊盘33a与互连结构3互连。
在实际应用中，堆叠体5包括堆叠封装体和/或堆叠元器件。具体地，堆叠元器件包括芯片、电容、电阻和电感等等。堆叠封装体可以是与本实施例采用的封装结构相同的封装体。
在本实施例中，在封装体4的两个安装面(41,13)中的至少一个安装面上进行布线处理，以形成引线结构。该引线结构可用于不同的堆叠体之间的互连，也可以用于与堆叠体5或者印制电路板6互连，这样可以实现多个器件的堆叠，克服了空间局限性。
在另一个实施例中，如图3所示，上述步骤102还可以采用其他实现方法，该方法具体包括：
步骤1021’、如图3中的图(a)所示，在基体1的第一表面(即，图(a)中基体1的朝上的表面)上设置指定深度的盲孔14。
上述指定深度可以根据基体1的具体厚度而设定。
步骤1022’、在盲孔14的底部设置胶体(图中未示出)。
上述胶体保留在盲孔14中，不进行剥离。该胶体例如为环氧树脂胶。
步骤1023’、如图3中的图(b)所示，将元器件2安装在基体1上，并将互连结构3通过上述胶体固定在盲孔14中。
上述互连结构3的其中一个端部32位于盲孔14中，而另一个端部31位于盲孔14的外部。
需要说明的是，互连结构3与基体1之间没有电性互连。
针对上述步骤102，步骤103具体包括：
步骤1031、如图3中的图(c)所示，对安装有元器件2和互连结构3的基体1封装形成封装体4，且使位于盲孔14之外的端部31自安装面41暴露出来。
步骤1032、如图3中的图(d)所示，在封装体4的安装面41上形成与端部31互连的焊盘33a。
步骤1033、如图3中的图(e)所示，对基体1的背离上述第一表面的第二表面，即，用作封装体4的与印制电路板6互连的其中一安装面13进行刻蚀，以将盲孔14打通，以形成通孔14a。刻蚀方法具体采用图形化掩膜对封装体4进行刻蚀。当然，在实际应用中，还可以采用激光打通盲孔14。
步骤1034、去除互连结构3的端部32上的胶体，这样，互连结构3的端部32通过通孔14a裸露出来。胶体的去除例如可以采用激光烧除。
在一些实施方案中，在步骤1034之后，将封装体4的安装面13对封装体4进行整体 研磨减薄，直至互连结构3的端部32与安装面13相平齐。或者，在步骤1034之后，如图3中的图(f)所示，还可以在位于通孔14a内的端部32上形成延伸部分34，该延伸部分34的至少一部分用作焊盘，且自其中另一安装面13暴露出来，即与安装面13相平齐或者相对于安装面13凸出。当然，在实际应用中，还可以在安装面13上制作焊接面积更大的焊盘，并与延伸部分互连。
如图3中的图(g)所示，为完成堆叠体5和印制电路板6互连的过程图。其中，堆叠体5通过焊盘33a与互连结构3互连，印制电路板6通过延伸部分34与互连结构3互连，从而实现了堆叠体5与印制电路板6的互连。这与现有技术相比，减少了互连路径，简化了封装结构。
需要说明的是，在本实施例中，堆叠体5通过焊盘33a与互连结构3互连，印制电路板6通过延伸部分34与互连结构3互连，但是，本公开并不局限于此，在实际应用中，也可以使堆叠体5通过延伸部分34与互连结构3互连，印制电路板6通过焊盘33a与互连结构3互连。
作为另一个技术方案，请参阅图4，本公开实施例还提供一种封装结构，其包括基体1和封装体4，其中，在基体1上设置有元器件2和具有两个焊盘(33a,33b)的互连结构3；封装体4用于将元器件2、互连结构3和基体4封装为一体，且该封装体4被设置为使两个焊盘(33a,33b)分别自封装体4相互背离的两个安装面暴露出来，以使两个焊盘(33a,33b)能够分别与堆叠体5和印制电路板6互连。
在本实施例中，基体1为有机封装基板，当然，在实际应用中，基体1还可以采用其他任意结构，例如框架式结构。
在一些实施方案中，元器件2包括芯片、电容、电阻和电感等等。该元器件2可以通过粘接、焊接、打线等方式在封装体4中制作导体与互连结构3进行互连；或者，元器件2的至少一部分叠置在焊盘的位于封装体4内侧的表面，并与焊盘互连。这样，元器件2可以通过互连结构3直接与印制电路板6互连。
在一些实施方案中，互连结构3包括导电柱体、导电片或者导电框架等等，在本实施例中，在导电柱体的两个端部分别设置有两个焊盘(33a,33b)，两个焊盘(33a,33b)在导电柱体的径向截面上的正投影面积大于导电柱体的径向截面面积。这样，可以扩大焊接面积，以满足焊接需求。当然，在实际应用中，也可以根据布条的需要，使两个焊盘(33a,33b)在导电柱体的径向截面上的正投影面积小于导电柱体的径向截面面积。
在另一个实施例中，封装结构为至少两套，例如，在本实施例中，如图5所示，封装结构为两套，分别为第一封装结构100a和第二封装结构100b，二者依次堆叠在一起，并且第一封装结构100a和第二封装结构100b的彼此相对的焊盘互连，即，第一封装结构100a 的顶部焊盘与第二封装结构100b的底部焊盘互连。第一封装结构100a的底部焊盘与印制电路板6互连。
需要说明的是，在实际应用中，对于各相邻的两个封装结构，其中一个封装结构的任意一侧的焊盘可以与其中另一个封装结构的任意一侧的焊盘互连。各相邻的两个封装结构的远离彼此一侧的焊盘均可以用于与印制电路板6互连。
本实施例提供的封装结构，基体1用于安装元器件2和互连结构3，而封装体4用于对安装有元器件2和互连结构3的基体1封装为一体，从而实现对互连结构3的固定，而且这种固定方式相对于现有技术更加稳定，从而可以提高连接稳定性。同时，通过使互连结构3的两个焊盘(33a,33b)分别自封装体4相互背离的两个安装面暴露出来，可以分别与堆叠体5和印制电路板6互连。由此，堆叠体5可以通过互连结构3直接与印制电路板6互连，从而减少了互连路径，简化了封装结构。
需要说明的是，上述实施例提供的封装结构的形状及内部结构仅为一种示例，除此之外，封装结构还可以有其它形状及内部结构，本实施例对此不进行限定。
作为另一个技术方案，本公开实施例还提供一种封装模块，其包括封装结构和堆叠体，其中，堆叠体堆叠在封装结构上，且与该封装结构的其中一焊盘互连。以图4示出的封装结构为例，堆叠体5堆叠在封装结构上，且与该封装结构的其中一焊盘33a互连。
本实施例提供的封装模块，可以减少互连路径，简化封装结构，提高连接可靠性。
需要说明的是，上述各实施例提及到的器件包括芯片、无源器件或倒装芯片等，本实施例不对封装器件的种类、形状进行具体限定。
总而言之，本公开提供的封装方法、封装结构及封装模块的技术方案，基体用于安装元器件和互连结构，而封装体用于对安装有元器件和互连结构的基体封装为一体，从而实现对互连结构的固定，而且这种固定方式相对于现有技术更加稳定，从而可以提高连接稳定性。同时，通过使互连结构的两个焊盘分别自封装体相互背离的两个安装面暴露出来，可以分别与堆叠体和印制电路板互连。由此，堆叠体可以通过互连结构直接与印制电路板互连，从而减少了互连路径，简化了封装结构。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开的保护范围。

Claims (17)

  1. 一种封装方法，其中，所述封装方法包括：
    提供一基体；
    在所述基体上安装元器件和互连结构，所述互连结构的对侧分别具有焊盘；
    对安装有所述元器件和所述互连结构的所述基体封装形成封装体，且使位于所述互连结构对侧的各所述焊盘分别自所述封装体相互背离的两个安装面暴露出来，以能够分别与堆叠体和印制电路板互连。
  2. 根据权利要求1所述的封装方法，其中，所述互连结构的对侧分别具有两个端部；各所述端部用作所述焊盘。
  3. 根据权利要求1所述的封装方法，其中，所述互连结构的的对侧分别具有两个端部；
    所述对安装有所述元器件和所述互连结构的所述基体封装形成封装体，且使位于所述互连结构对侧的各所述焊盘分别自所述封装体相互背离的两个安装面暴露出来，以能够分别与堆叠体和印制电路板互连的步骤，具体包括：
    对安装有所述元器件和所述互连结构的所述基体封装形成封装体，且使两个所述端部相对于所述封装体裸露；
    在所述封装体的两个所述安装面上形成与各所述端部互连的所述焊盘。
  4. 根据权利要求3所述的封装方法，其中，所述对安装有所述元器件和所述互连结构的所述基体封装形成封装体，且使两个所述端部分别自所述封装体相互背离的两个安装面暴露出来的步骤，具体包括：
    在两个所述端部上均覆盖掩膜；
    对安装有所述元器件和所述互连结构的所述基体封装形成封装体，且所述掩膜相对于所述封装体裸露；
    去除所述掩膜,使两个所述端部相对于所述封装体裸露。
  5. 根据权利要求3所述的封装方法，其中，所述对安装有所述元器件和所述互连结构的所述基体封装形成封装体，且使两个所述端部相对于所述封装体裸露的步骤，具体包括：
    对安装有所述元器件和所述互连结构的所述基体封装形成封装体，且使所述封装体完全包覆所述互连结构；
    对所述封装体的两个所述安装面分别进行研磨，直至所述互连结构的两个所述端部相对于所述封装体裸露。
  6. 根据权利要求2或3所述的封装方法，其中，所述在所述封装体的两个所述安装面上形成与各所述端部互连的所述焊盘的步骤之后，还包括：
    在所述焊盘上制作金属保护层。
  7. 根据权利要求1所述的封装方法，其中，在所述封装体的两个所述安装面中的至少一个所述安装面上进行布线处理，以形成引线结构。
  8. 根据权利要求1所述的封装方法，其中，所述在所述基体上安装元器件和互连结构，所述互连结构的对侧分别设置有焊盘的步骤，包括：
    在所述基体中形成贯通所述基体的通孔；
    在所述基体的与所述元器件所在表面相背离的表面上设置胶膜；
    将所述互连结构通过所述胶膜固定在所述通孔中；
    在所述对安装有所述元器件和所述互连结构的所述基体封装形成封装体，且使各所述焊盘自所述封装体的相应的安装面暴露出来，以能够分别与堆叠体和印制电路板互连的步骤之后，还包括：
    去除所述胶膜。
  9. 根据权利要求1所述的封装方法，其中，所述在所述基体上安装元器件和互连结构，所述互连结构的对侧分别设置有焊盘的步骤，包括：
    在所述基体的第一表面上设置指定深度的盲孔；
    在所述盲孔的底部设置胶体；
    所述互连结构通过所述胶体固定在所述盲孔中；
    所述对安装有所述元器件和所述互连结构的所述基体封装形成封装体，且使各所述焊盘自所述封装体的相应的安装面暴露出来，以能够分别与堆叠体和印制电路板互连的步骤，包括：
    对安装有所述元器件和所述互连结构的所述基体封装形成封装体，且使位于所述盲孔之外的所述焊盘自其中一所述安装面暴露出来；
    自所述基体的背离所述第一表面的第二表面将所述盲孔打通；
    去除所述胶体，以使位于所述盲孔内的所述焊盘自其中另一所述安装面暴露出来。
  10. 根据权利要求3-5任意一项所述的封装方法，其中，所述在所述基体上安装元器件和互连结构，所述互连结构的对侧分别设置有焊盘的步骤，包括：
    在所述基体的第一表面上设置指定深度的盲孔；
    在所述盲孔的底部设置胶体；
    所述互连结构通过所述胶体固定在所述盲孔中；
    所述对安装有所述元器件和所述互连结构的所述基体封装形成封装体，且使两个所述端部分别自所述封装体相互背离的两个安装面暴露出来的步骤，包括：
    对安装有所述元器件和所述互连结构的所述基体封装形成封装体，且使位于所述盲孔之外的所述端部自其中一所述安装面暴露出来；
    对所述基体的背离所述第一表面的第二表面进行刻蚀，以将所述盲孔打通；
    去除所述胶体，以使位于所述盲孔内的所述互连结构裸露；
    在位于所述盲孔内的所述端部上形成延伸部分，所述延伸部分的至少一部分用作所述焊盘，且自其中另一所述安装面暴露出来。
  11. 一种封装结构，其中，包括：
    基体，在所述基体上设置有元器件和互连结构，所述互连结构的对侧分别设置有焊盘；
    封装体，用于将所述元器件、所述互连结构和所述基体封装为一体，且所述封装体被设置为使位于所述互连结构对侧的各所述焊盘分别自所述封装体相互背离的两个安装面暴露出来，以能够分别与堆叠体和印制电路板互连。
  12. 根据权利要求11所述的封装结构，其中，所述互连结构包括导电柱体、导电片或者导电框架，其中，
    所述导电柱体的两个端部用作所述焊盘，或者在所述导电柱体的各所述端部分别设置有所述焊盘。
  13. 根据权利要求11所述的封装结构，其中，所述元器件通过设置在所述封装体中的导体与所述互连结构互连，或者所述元器件的至少一部分叠置在所述焊盘的位于所述封装体内侧的表面，并与所述焊盘互连。
  14. 根据权利要求11所述的封装结构，其中，在所述焊盘上设置有球珊阵列结构或者栅格阵列结构。
  15. 根据权利要求11所述的封装结构，其中，所述堆叠体包括堆叠封装体和/或堆叠元器件。
  16. 根据权利要求11所述的封装结构，其中，所述封装结构为至少两套，且依次堆叠在一起，并且各相邻的两套所述封装结构的彼此相对的所述焊盘互连。
  17. 一种封装模块，其中，包括：
    根据权利要求11-16任意一项所述的封装结构；
    堆叠体，堆叠在所述封装结构上，且与所述封装结构的其中一所述焊盘互连。
PCT/CN2020/135264 2019-12-13 2020-12-10 封装方法、封装结构及封装模块 WO2021115377A1 (zh)

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