WO2021115148A1 - 基准源电路、芯片、电源及电子设备 - Google Patents

基准源电路、芯片、电源及电子设备 Download PDF

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Publication number
WO2021115148A1
WO2021115148A1 PCT/CN2020/132741 CN2020132741W WO2021115148A1 WO 2021115148 A1 WO2021115148 A1 WO 2021115148A1 CN 2020132741 W CN2020132741 W CN 2020132741W WO 2021115148 A1 WO2021115148 A1 WO 2021115148A1
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transistor
resistor
electrically connected
current
source
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PCT/CN2020/132741
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English (en)
French (fr)
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杨毓俊
樊磊
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北京集创北方科技股份有限公司
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Priority to KR1020227021185A priority Critical patent/KR20220101186A/ko
Priority to JP2022522061A priority patent/JP7371244B2/ja
Publication of WO2021115148A1 publication Critical patent/WO2021115148A1/zh
Priority to US17/727,687 priority patent/US20220244749A1/en

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
    • G05F1/567—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/30—Regulators using the difference between the base-emitter voltages of two bipolar transistors operating at different current densities
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices

Definitions

  • the present disclosure relates to the field of integrated circuit technology, and in particular to a reference source circuit, chip, power supply, and electronic equipment.
  • the band gap reference source is the basic module in the integrated circuit system, and its purpose is to produce a voltage reference or current reference that has nothing to do with power and temperature.
  • the commonly used band gap reference inside the chip is a single band gap voltage source or a band gap current source. Since the resistance in the semiconductor process usually has a certain temperature coefficient, it is difficult to realize the band gap voltage source and the band gap current source in the related art at the same time, and two separate circuits need to be fabricated, which is costly and wastes chip area.
  • a reference source circuit which includes:
  • the first current generating unit is used to generate a first current
  • a reference voltage generating unit electrically connected to the first current generating unit, for generating a band gap reference voltage by using the first current
  • the reference current generating unit is electrically connected to the first current generating unit and the reference voltage generating unit, and is used for generating a band gap reference current by using the first current.
  • the reference voltage generating unit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a first resistor, a second resistor, a third resistor, and a first transistor.
  • Capacitor, second capacitor where:
  • the drain of the first transistor is electrically connected to the source of the second transistor, the source of the third transistor, and the voltage source, and the gate of the first transistor is electrically connected to the first end of the second resistor
  • the drain of the third transistor, the collector of the fifth transistor, and the start circuit are used to receive the start signal output by the start circuit, and the source of the first transistor is electrically connected to the first resistor of the first resistor.
  • One end, the first end of the first capacitor, the first end of the second capacitor, and the source of the first transistor is used to output the bandgap reference voltage
  • the second end of the first capacitor and the second end of the first resistor are electrically connected to the first current generating unit
  • the second end of the second resistor is electrically connected to the first end of the third capacitor
  • the drain of the second transistor is electrically connected to the gate of the second transistor, the gate of the third transistor, and the collector of the fourth transistor,
  • the first end of the third resistor is electrically connected to the first current generating unit
  • the base of the fifth transistor and the base of the fourth transistor are electrically connected to the first current generating unit
  • the emitter of the fifth transistor, the emitter of the fourth transistor, the second end of the third resistor, and the second end of the second capacitor are grounded.
  • the first current generating unit includes a fourth resistor, a fifth resistor, a sixth transistor, and a seventh transistor, where:
  • the first end of the fourth resistor is electrically connected to the second end of the first capacitor, the second end of the first resistor, the first end of the fifth resistor, and the base of the sixth transistor ,
  • the second end of the fourth resistor is electrically connected to the collector of the sixth transistor, the base of the seventh transistor, and the base of the fourth transistor,
  • the second end of the fifth resistor is electrically connected to the collector of the seventh transistor and the base of the fifth transistor,
  • the emitter of the sixth transistor and the emitter of the seventh transistor are electrically connected to the first end of the third resistor
  • the collector of the sixth transistor is used to generate the first current.
  • the reference current generating unit includes the second transistor, the fourth transistor, the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, the twelfth transistor, The thirteenth transistor, the fifth capacitor, the sixth resistor, the seventh resistor, and the eighth resistor, of which:
  • the gate of the eighth transistor is electrically connected to the gate of the second transistor, and the source of the eighth transistor is electrically connected to the source of the second transistor, the source of the twelfth transistor, The source of the thirteenth transistor and the drain of the eighth transistor are electrically connected to the collector of the ninth transistor,
  • the base of the ninth transistor is electrically connected to the source of the tenth transistor, the collector of the eleventh transistor, and the first end of the eighth resistor,
  • the gate of the tenth transistor is electrically connected to the first end of the sixth resistor, the collector of the ninth transistor, and the drain of the eighth transistor, and the second end of the sixth resistor is electrically connected At the first end of the fifth capacitor, the base of the eleventh transistor is electrically connected to the first end of the fourth resistor, the first end of the fifth resistor, and the base of the sixth transistor. And the second end of the first capacitor, the emitter of the eleventh transistor is electrically connected to the first end of the seventh resistor,
  • the second end of the fifth capacitor, the emitter of the ninth transistor, the second end of the seventh resistor, and the second end of the eighth resistor are grounded;
  • the gate of the twelfth transistor is electrically connected to the source of the twelfth transistor, the gate of the thirteenth transistor, and the drain of the tenth transistor,
  • the drain of the thirteenth transistor is used to output the band gap reference current.
  • the resistance of the third resistor is equal to the resistance of the fourth resistor and the fifth resistor in parallel, and the resistance of the fourth resistor is equal to that of the seventh resistor. Resistance.
  • a chip is provided, and the chip includes:
  • the reference source circuit The reference source circuit.
  • a power supply is provided, and the power supply includes:
  • the chip The chip.
  • an electronic device includes:
  • the power supply is the power supply.
  • the embodiment of the present disclosure can generate a bandgap reference voltage and a bandgap reference current in a reference source circuit, and multiplex the first current generation unit, can achieve high gain, dual loops work simultaneously, and can save costs. Compared with related technologies, designing two separate reference sources can save chip area.
  • Fig. 1 shows a schematic diagram of a reference source circuit according to an embodiment of the present disclosure.
  • Fig. 2 shows a schematic diagram of a reference source circuit according to an embodiment of the present disclosure.
  • FIG. 1 shows a schematic diagram of a reference source circuit according to an embodiment of the present disclosure.
  • the circuit includes:
  • the first current generating unit 10 is used to generate a first current
  • a reference voltage generating unit 20 electrically connected to the first current generating unit 10, for generating a band gap reference voltage by using the first current;
  • the reference current generating unit 30 is electrically connected to the first current generating unit 10 and the reference voltage generating unit 20 for generating a band gap reference current by using the first current.
  • the embodiment of the present disclosure can generate a bandgap reference voltage and a bandgap reference current in a reference source circuit, and multiplex the first current generation unit, can achieve high gain, dual loops work simultaneously, and can save costs. Compared with related technologies, designing two separate reference sources can save chip area.
  • the reference source circuit can be set in an electronic device, and the electronic device can also be called a mobile device.
  • the mobile device can refer to various forms of access mobile devices, subscriber units, user equipment, subscriber stations, mobile stations, and mobile stations. (Mobile Station, MS), remote station, remote mobile equipment, mobile equipment, user mobile equipment, terminal equipment (terminal equipment), wireless communication equipment, user agent or user device.
  • the user equipment can also be a cellular phone, a cordless phone, a Session Initiation Protocol (SIP) phone, a wireless local loop (Wireless Local Loop, WLL) station, a personal digital processing (Personal Digital Assistant, PDA), with wireless communication Functional handheld devices, computing devices, or other processing devices connected to wireless modems, in-vehicle devices, wearable devices, user equipment in the future 5G network, or future evolution of the public land mobile network (Public Land Mobile Network, PLMN) Mobile devices, etc., are not limited in the embodiments of the present disclosure.
  • SIP Session Initiation Protocol
  • WLL Wireless Local Loop
  • PDA Personal Digital Assistant
  • FIG. 2 shows a schematic diagram of a reference source circuit according to an embodiment of the present disclosure.
  • the reference voltage generating unit 20 may include a first transistor Q1, a second transistor Q2, a third transistor Q3, a fourth transistor Q4, a fifth transistor Q5, and a second transistor.
  • the drain of the first transistor Q1 is electrically connected to the source of the second transistor Q2, the source of the third transistor Q3 and the voltage source VDD, and the gate of the first transistor Q1 is electrically connected to the second transistor.
  • the first end of the resistor R2, the drain of the third transistor Q3, the collector of the fifth transistor Q5 and the start circuit are used to receive the start signal output by the start circuit, and the source of the first transistor Q1 Electrically connected to the first end of the first resistor R1, the first end of the first capacitor C1, and the first end of the second capacitor C2.
  • the source of the first transistor Q1 is used to output the Band gap reference voltage VBG,
  • the second end of the first capacitor C1 and the second end of the first resistor R1 are electrically connected to the first current generating unit 10,
  • the second end of the second resistor R2 is electrically connected to the first end of the third capacitor C3,
  • the drain of the second transistor Q2 is electrically connected to the gate of the second transistor Q2, the gate of the third transistor Q3, and the collector of the fourth transistor Q4,
  • the first end of the third resistor R3 is electrically connected to the first current generating unit 10,
  • the base of the fifth transistor Q5 and the base of the fourth transistor Q4 are electrically connected to the first current generating unit 10,
  • the emitter of the fifth transistor Q5, the emitter of the fourth transistor Q4, the second end of the third resistor R3, and the second end of the second capacitor C2 are grounded.
  • the first transistor Q1, the second transistor Q2, and the third transistor Q3 may be Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs), and the fourth transistor Q4 and the fifth transistor Q5 may be It is a triode.
  • MOSFETs Metal-Oxide-Semiconductor Field-Effect Transistors
  • the starter circuit may output a start signal to start the reference source circuit to generate the bandgap reference voltage and the bandgap reference current.
  • the start signal may be a pulse signal.
  • the first current generating unit may generate a proportional to absolute temperature (PTAT) current, that is, the first current may be a PTAT current.
  • PTAT proportional to absolute temperature
  • the first current generating unit 10 may include a fourth resistor R4, a fifth resistor R5, a sixth transistor Q6, and a seventh transistor Q7, where:
  • the first end of the fourth resistor R4 is electrically connected to the second end of the first capacitor C1, the second end of the first resistor R1, the first end of the fifth resistor R5, and the sixth
  • the base of the transistor Q6, the second end of the fourth resistor R4 is electrically connected to the collector of the sixth transistor Q6, the base of the seventh transistor Q7, and the base of the fourth transistor Q4,
  • the second end of the fifth resistor R5 is electrically connected to the collector of the seventh transistor Q7 and the base of the fifth transistor Q5,
  • the emitter of the sixth transistor Q6 and the emitter of the seventh transistor Q7 are electrically connected to the first end of the third resistor R3,
  • the collector of the sixth transistor is used to generate the first current I PTAT .
  • the magnitude of the first current may be:
  • R4 represents the resistance value of the fourth resistor R4
  • R5 represents the resistance value of the fifth resistor R5
  • the sixth transistor Q6 and the seventh transistor Q7 may be triodes, and the ratio of the numbers of the sixth transistor Q6 to the seventh transistor Q7 may be 1:n, and n is an integer greater than 1.
  • the present disclosure does not limit the specific number ratio of the sixth transistor Q6 to the seventh transistor Q7, which can be determined by those skilled in the art as required.
  • the bandgap reference voltage VBG may be: V BE + I PTAT ⁇ (R1 + R3), which is determined by Available:
  • V BE represents the base-emitter voltage of the sixth transistor
  • V BE is the negative temperature coefficient
  • R1 represents the first resistance resistance
  • R4 represents a resistance of the fourth resistor
  • R5 represents a resistance value of the fifth resistor
  • V T represents a temperature equivalent voltage
  • V T is a positive temperature coefficient
  • n represents the sixth transistor and a seventh transistor The ratio of the numbers.
  • the resistance value of the first resistor R1, the fourth resistor R4, and the fifth resistor R5 can be set to realize the zero temperature coefficient of the band gap reference voltage VBG.
  • the present disclosure does not limit the specific resistance values of the first resistor R1, the fourth resistor R4, and the fifth resistor R5, which can be determined by those skilled in the art according to actual conditions.
  • the reference current generating unit 30 may include the second transistor Q2, the fourth transistor Q4, the eighth transistor Q8, the ninth transistor Q9, and the tenth transistor.
  • the gate of the eighth transistor Q8 is electrically connected to the gate of the second transistor Q2, and the source of the eighth transistor Q8 is electrically connected to the source of the second transistor Q2, the twelfth transistor
  • the source of Q12, the source of the thirteenth transistor Q13, and the drain of the eighth transistor Q8 are electrically connected to the collector of the ninth transistor Q9,
  • the base of the ninth transistor Q9 is electrically connected to the source of the tenth transistor Q10, the collector of the eleventh transistor Q11, and the first end of the eighth resistor R8,
  • the gate of the tenth transistor Q10 is electrically connected to the first end of the sixth resistor R6, the collector of the ninth transistor Q9, and the drain of the eighth transistor Q8.
  • the second end is electrically connected to the first end of the fifth capacitor C5, and the base of the eleventh transistor Q11 is electrically connected to the first end of the fourth resistor R4 and the first end of the fifth resistor R5.
  • Terminal, the base of the sixth transistor Q6 and the second terminal of the first capacitor C1 the emitter of the eleventh transistor Q11 is electrically connected to the first terminal of the seventh resistor R7,
  • the second end of the fifth capacitor C5, the emitter of the ninth transistor Q9, the second end of the seventh resistor R7, and the second end of the eighth resistor R8 are grounded;
  • the gate of the twelfth transistor Q12 is electrically connected to the source of the twelfth transistor Q12, the gate of the thirteenth transistor Q13, and the drain of the tenth transistor Q10,
  • the drain of the thirteenth transistor Q13 is used to output the band gap reference current IBG.
  • the eighth transistor Q8, the tenth transistor Q10, the twelfth transistor Q12, and the thirteenth transistor Q13 may be MOSFETs, and the ninth transistor Q9 and the eleventh transistor Q11 may be triodes.
  • the transconductance of Q4 is equal to the transconductances of the fifth transistor Q5 and the ninth transistor Q9.
  • the reference voltage generation unit is a voltage series negative feedback, and the voltage closed-loop output impedance is 1/A1 times the open-loop output impedance. Therefore, the output bandgap reference voltage has a higher driving force.
  • the reference current generation unit is a current series negative feedback
  • the current closed-loop output impedance is A2 times the open-loop output impedance.
  • the reference voltage generation unit and the reference current generation unit of the embodiment of the present disclosure share the first current generation unit 10, and share the second transistor Q2 and the fourth transistor Q4, so that two bandgap references (bandgap references) can be generated in one circuit.
  • Reference voltage and bandgap reference current can be generated in one circuit.
  • the embodiments of the present disclosure can realize the simultaneous operation of high-gain dual-loops through dual op-amp loops, with lower cost and occupying layout area small.
  • the driving force of the bandgap reference voltage is relatively high, and the output impedance of the bandgap reference current is relatively large, which is beneficial to improving the working efficiency.
  • the sixth transistor Q6 and the third resistor R3 form a current mirror with the eleventh transistor Q11 and the seventh resistor R7. Therefore, the reference current generating unit 30 can use the first current I PTAT to obtain the band gap reference current.
  • IBG I CTAT + I PTAT , where ICTAT represents the current flowing through the eighth resistor R8, where
  • V BE represents the base-emitter voltage of the sixth transistor Q6, V BE is a negative temperature coefficient, R8 represents the resistance of the eighth resistor R8, R4 represents the resistance of the fourth resistor R4, and R5 represents the resistance of the fourth resistor R4.
  • V T represents the voltage equivalent of temperature
  • V T is the positive temperature coefficient
  • n represents the ratio of the number of the seventh transistor to the sixth transistor.
  • the resistance values of the eighth resistor R8 and the fourth resistor R4 can be adjusted to realize the zero temperature coefficient of the band gap reference current IBG.
  • the present disclosure may set the third resistor R3, the fourth resistor R4, the fifth resistor R5, and the seventh resistor R7 to satisfy the following relationship, so as to make the output bandgap reference in the embodiment of the present disclosure better Voltage and band gap reference current:
  • the resistance value of the third resistor is equal to the resistance value of the parallel connection of the fourth resistor and the fifth resistor
  • R5, R4 R7, where R3 represents the third resistor, R4 represents the fourth resistor, R5 represents the fifth resistor, and R7 represents the seventh resistor.
  • the embodiments of the present disclosure can simultaneously generate a zero temperature coefficient band gap reference current and a band gap reference voltage in one circuit. Compared with related technologies, the cost is lower and the layout area is smaller, which is beneficial to popularization and utilization. .

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Abstract

涉及基准源电路、芯片、电源及电子设备，电路包括：第一电流产生单元（10），用于产生第一电流；基准电压产生单元（20），电连接于第一电流产生单元（10），用于利用第一电流产生带隙基准电压；基准电流产生单元（30），电连接于第一电流产生单元（10）及基准电压产生单元（20），用于利用第一电流产生带隙基准电流。通过以上电路，可以在一个基准源电路中产生带隙基准电压和带隙基准电流，且复用第一电流产生单元，可以实现高增益、双环路同时工作，可以节约成本，相较于两个单独的基准源可以节约芯片面积。

Description

基准源电路、芯片、电源及电子设备 技术领域
本公开涉及集成电路技术领域，尤其涉及一种基准源电路、芯片、电源及电子设备。
背景技术
带隙基准源作为集成电路系统中的基本模块，其目的是产生一个与电源和温度无关的电压基准或电流基准。目前芯片内部常用的带隙基准为单独的带隙电压源或带隙电流源。由于半导体工艺中的电阻通常具有一定的温度系数，导致相关技术中的带隙电压源与带隙电流源难以同时实现，需要制作两个单独的电路，成本较高且浪费了芯片面积。
发明内容
有鉴于此，本公开提出了一种一种基准源电路，所述电路包括：
第一电流产生单元，用于产生第一电流；
基准电压产生单元，电连接于所述第一电流产生单元，用于利用所述第一电流产生带隙基准电压；
基准电流产生单元，电连接于所述第一电流产生单元及所述基准电压产生单元，用于利用所述第一电流产生带隙基准电流。
在一种可能的实施方式中，所述基准电压产生单元包括第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第一电阻、第二电阻、第三电阻、第一电容、第二电容，其中：
所述第一晶体管的漏极电连接于所述第二晶体管的源极、第三晶体管的源极及电压源，所述第一晶体管的栅极电连接于所述第二电阻的第一端、所述第三晶体管的漏极、所述第五晶体管的集电极及启动电路，用于接收启动电路输出的启动信号，所述第一晶体管的源极电连接于所述第一电阻的第一 端、所述第一电容的第一端、所述第二电容的第一端，所述第一晶体管的源极用于输出所述带隙基准电压，
所述第一电容的第二端、所述第一电阻的第二端电连接于所述第一电流产生单元，
所述第二电阻的第二端电连接于所述第三电容的第一端，
所述第二晶体管的漏极电连接于所述第二晶体管的栅极、所述第三晶体管的栅极、所述第四晶体管的集电极，
所述第三电阻的第一端电连接于所述第一电流产生单元，
所述第五晶体管的基极、所述第四晶体管的基极电连接于所述第一电流产生单元，
所述第五晶体管的射极、所述第四晶体管的射极、所述第三电阻的第二端、所述第二电容的第二端接地。
在一种可能的实施方式中，所述第一电流产生单元包括第四电阻、第五电阻、第六晶体管、第七晶体管，其中：
所述第四电阻的第一端电连接于所述第一电容的第二端、所述第一电阻的第二端、所述第五电阻的第一端、所述第六晶体管的基极，所述第四电阻的第二端电连接于所述第六晶体管的集电极、所述第七晶体管的基极、所述第四晶体管的基极，
所述第五电阻的第二端电连接于所述第七晶体管的集电极、所述第五晶体管的基极，
所述第六晶体管的射极、所述第七晶体管的射极电连接于所述第三电阻的第一端，
其中，所述第六晶体管的集电极用于产生所述第一电流。
在一种可能的实施方式中，所述基准电流产生单元包括所述第二晶体管、所述第四晶体管、第八晶体管、第九晶体管、第十晶体管、第十一晶体管、第十二晶体管、第十三晶体管、第五电容、第六电阻、第七电阻、第八电阻，其中：
所述第八晶体管的栅极电连接于所述第二晶体管的栅极，所述第八晶体管的源极电连接于所述第二晶体管的源极、所述第十二晶体管的源极、所述第十三晶体管的源极，所述第八晶体管的漏极电连接于所述第九晶体管的集电极，
所述第九晶体管的基极电连接于所述第十晶体管的源极、所述第十一晶体管的集电极、所述第八电阻的第一端，
所述第十晶体管的栅极电连接于所述第六电阻的第一端、所述第九晶体管的集电极、所述第八晶体管的漏极，所述第六电阻的第二端电连接于所述第五电容的第一端，所述第十一晶体管的基极电连接于所述第四电阻的第一端、所述第五电阻的第一端、所述第六晶体管的基极及所述第一电容的第二端，所述第十一晶体管的射极电连接于所述第七电阻的第一端，
所述第五电容的第二端、所述第九晶体管的射极、所述第七电阻的第二端、所述第八电阻的第二端接地，
所述第十二晶体管的栅极电连接于所述第十二晶体管的源极、所述第十三晶体管的栅极、所述第十晶体管的漏极，
所述第十三晶体管的漏极用于输出所述带隙基准电流。
在一种可能的实施方式中，所述第三电阻的阻值等于所述第四电阻与所述第五电阻的并联的电阻值，所述第四电阻的阻值等于所述第七电阻的阻值。
根据本公开的另一方面，提出了一种芯片，所述芯片包括：
所述的基准源电路。
根据本公开的另一方面，提出了一种电源，所述电源包括：
所述的芯片。
根据本公开的另一方面，提出了一种电子设备，所述电子设备包括：
所述的电源。
通过以上电路，本公开实施例可以在一个基准源电路中产生带隙基准电压和带隙基准电流，且复用第一电流产生单元，可以实现高增益、双环路同时工作，可以节约成本，相较于相关技术设计两个单独的基准源可以节约芯 片面积。
根据下面参考附图对示例性实施例的详细说明，本公开的其它特征及方面将变得清楚。
附图说明
包含在说明书中并且构成说明书的一部分的附图与说明书一起示出了本公开的示例性实施例、特征和方面，并且用于解释本公开的原理。
图1示出了根据本公开一实施方式的基准源电路的示意图。
图2示出了根据本公开一实施方式的基准源电路的示意图。
具体实施方式
以下将参考附图详细说明本公开的各种示例性实施例、特征和方面。附图中相同的附图标记表示功能相同或相似的元件。尽管在附图中示出了实施例的各种方面，但是除非特别指出，不必按比例绘制附图。
在这里专用的词“示例性”意为“用作例子、实施例或说明性”。这里作为“示例性”所说明的任何实施例不必解释为优于或好于其它实施例。
另外，为了更好的说明本公开，在下文的具体实施方式中给出了众多的具体细节。本领域技术人员应当理解，没有某些具体细节，本公开同样可以实施。在一些实例中，对于本领域技术人员熟知的方法、手段、元件和电路未作详细描述，以便于凸显本公开的主旨。
请参阅图1，图1示出了根据本公开一实施方式的基准源电路的示意图。
如图1所示，所述电路包括：
第一电流产生单元10，用于产生第一电流；
基准电压产生单元20，电连接于所述第一电流产生单元10，用于利用所述第一电流产生带隙基准电压；
基准电流产生单元30，电连接于所述第一电流产生单元10及所述基准电压产生单元20，用于利用所述第一电流产生带隙基准电流。
通过以上电路，本公开实施例可以在一个基准源电路中产生带隙基准电压和带隙基准电流，且复用第一电流产生单元，可以实现高增益、双环路同 时工作，可以节约成本，相较于相关技术设计两个单独的基准源可以节约芯片面积。
所述基准源电路可以设置在电子设备中，所述电子设备也可以称为移动设备，移动设备可以指各种形式的接入移动设备、用户单元、用户设备、用户站、移动站、移动台(Mobile Station，MS)、远方站、远程移动设备、移动设备、用户移动设备、终端设备(terminal equipment)、无线通信设备、用户代理或用户装置。用户设备还可以是蜂窝电话、无绳电话、会话启动协议(Session Initiation Protocol，SIP)电话、无线本地环路(Wireless Local Loop，WLL)站、个人数字处理(Personal Digital Assistant，PDA)、具有无线通信功能的手持设备、计算设备或连接到无线调制解调器的其它处理设备、车载设备、可穿戴设备，未来5G网络中的用户设备或者未来演进的公用陆地移动通信网络(Public Land Mobile Network，PLMN)中的移动设备等，本公开实施例对此并不限定。
下面对基准源电路中各个单元的可能实现方式进行介绍。
请参阅图2，图2示出了根据本公开一实施方式的基准源电路的示意图。
在一种可能的实施方式中，如图2所示，所述基准电压产生单元20可以包括第一晶体管Q1、第二晶体管Q2、第三晶体管Q3、第四晶体管Q4、第五晶体管Q5、第一电阻R1、第二电阻R2、第三电阻R3、第一电容C1、第二电容C2，其中：
所述第一晶体管Q1的漏极电连接于所述第二晶体管Q2的源极、第三晶体管Q3的源极及电压源VDD，所述第一晶体管Q1的栅极电连接于所述第二电阻R2的第一端、所述第三晶体管Q3的漏极、所述第五晶体Q5管的集电极及启动电路，用于接收启动电路输出的启动信号，所述第一晶体管Q1的源极电连接于所述第一电阻R1的第一端、所述第一电容C1的第一端、所述第二电容C2的第一端，所述第一晶体管Q1的源极用于输出所述带隙基准电压VBG，
所述第一电容C1的第二端、所述第一电阻R1的第二端电连接于所述第 一电流产生单元10，
所述第二电阻R2的第二端电连接于所述第三电容C3的第一端，
所述第二晶体管Q2的漏极电连接于所述第二晶体管Q2的栅极、所述第三晶体管Q3的栅极、所述第四晶体管Q4的集电极，
所述第三电阻R3的第一端电连接于所述第一电流产生单元10，
所述第五晶体管Q5的基极、所述第四晶体管Q4的基极电连接于所述第一电流产生单元10，
所述第五晶体管Q5的射极、所述第四晶体管Q4的射极、所述第三电阻R3的第二端、所述第二电容C2的第二端接地。
其中，第一晶体管Q1、第二晶体管Q2、第三晶体管Q3可以为金属-氧化物半导体场效应晶体管(Metal-Oxide-Semiconductor Field-Effect Transistor,MOSFET)，第四晶体管Q4、第五晶体管Q5可以为三极管。
应该说明的是，本公开实施例对启动电路的具体实施方式不做限定，本领域技术人员可以参照相关技术实现。
在一个示例中，当需要产生带隙基准电压和带隙基准电流时，启动电路可以输出启动信号以启动基准源电路产生带隙基准电压和带隙基准电流。
在一个示例中，所述启动信号可以为脉冲信号。
在一种可能的实施方式中，所述第一电流产生单元可以产生与绝对温度成正比(proportional to absolute temperature，PTAT)电流，即所述第一电流可以为PTAT电流。
在一种可能的实施方式，如图2所示，所述第一电流产生单元10可以包括第四电阻R4、第五电阻R5、第六晶体管Q6、第七晶体管Q7，其中：
所述第四电阻R4的第一端电连接于所述第一电容C1的第二端、所述第一电阻R1的第二端、所述第五电阻R5的第一端、所述第六晶体管Q6的基极，所述第四电阻R4的第二端电连接于所述第六晶体管Q6的集电极、所述第七晶体管Q7的基极、所述第四晶体管Q4的基极，
所述第五电阻R5的第二端电连接于所述第七晶体管Q7的集电极、所述 第五晶体管Q5的基极，
所述第六晶体管Q6的射极、所述第七晶体管Q7的射极电连接于所述第三电阻R3的第一端，
其中，所述第六晶体管的集电极用于产生所述第一电流I PTAT。
在一个示例中，所述第一电流的大小可以为：
Figure PCTCN2020132741-appb-000001
其中，R4表示所述第四电阻R4的阻值，R5表示所述第五电阻R5的阻值，V T表示温度的电压当量，其中，V T＝kT/q，其中k为波耳兹曼常数(1.38×10–23J/K)，T为热力学温度，即绝对温度，q为电子电荷(1.6×10–19C)。在常温下，VT≈26mV。
在一种可能的实施方式中，第六晶体管Q6、第七晶体管Q7可以为三极管，且第六晶体管Q6与第七晶体管Q7的数目之比可以为1：n，n为大于1的整数。当然，本公开对第六晶体管Q6与第七晶体管Q7的具体数目之比不做限定，本领域技术人员可以根据需要确定。
在一种可能的实施方式中，如图2所示，所述带隙基准电压VBG可以为：V BE+I PTAT·(R1+R3)，由
Figure PCTCN2020132741-appb-000002
可得：
Figure PCTCN2020132741-appb-000003
其中，“·”表示乘法操作，“||”表示并联，“+”表示加法操作，V BE表示所述第六晶体管的基射电压，V BE为负温度系数，R1表示所述第一电阻的阻值，R4表示所述第四电阻的阻值，R5表示所述第五电阻的阻值，V T表示温度的电压当量，V T为正温度系数，n表示第七晶体管与第六晶体管的个数比值。
本公开实施例可以通过设置第一电阻R1、第四电阻R4、第五电阻R5的阻值大小以实现带隙基准电压VBG的零温度系数。当然，本公开对第一电阻R1、第四电阻R4、第五电阻R5的具体阻值不做限定，本领域技术人员可以根据实际情况确定。
在一种可能的实施方式，如图2所示，所述基准电流产生单元30可以包括所述第二晶体管Q2、所述第四晶体管Q4、第八晶体管Q8、第九晶体管Q9、第十晶体管Q10、第十一晶体管Q11、第十二晶体管Q12、第十三晶体管Q13、第五电容C5、第六电阻R6、第七电阻R7、第八电阻R8，其中：
所述第八晶体管Q8的栅极电连接于所述第二晶体管Q2的栅极，所述第八晶体管Q8的源极电连接于所述第二晶体管Q2的源极、所述第十二晶体管Q12的源极、所述第十三晶体管Q13的源极，所述第八晶体管Q8的漏极电连接于所述第九晶体管Q9的集电极，
所述第九晶体管Q9的基极电连接于所述第十晶体管Q10的源极、所述第十一晶体管Q11的集电极、所述第八电阻R8的第一端，
所述第十晶体管Q10的栅极电连接于所述第六电阻R6的第一端、所述第九晶体管Q9的集电极、所述第八晶体管Q8的漏极，所述第六电阻R6的第二端电连接于所述第五电容C5的第一端，所述第十一晶体管Q11的基极电连接于所述第四电阻R4的第一端、所述第五电阻R5的第一端、所述第六晶体管Q6的基极及所述第一电容C1的第二端，所述第十一晶体管Q11的射极电连接于所述第七电阻R7的第一端，
所述第五电容C5的第二端、所述第九晶体管Q9的射极、所述第七电阻R7的第二端、所述第八电阻R8的第二端接地，
所述第十二晶体管Q12的栅极电连接于所述第十二晶体管Q12的源极、所述第十三晶体管Q13的栅极、所述第十晶体管Q10的漏极，
所述第十三晶体管Q13的漏极用于输出所述带隙基准电流IBG。
在一种可能的实施方式中，第八晶体管Q8、第十晶体管Q10、第十二晶体管Q12、第十三晶体管Q13可以为MOSFET，第九晶体管Q9、第十一晶体管Q11可以为三极管。
在一个示例中，第一晶体管Q1、第二晶体管Q2、第三晶体管Q3，第四晶体管Q4、第五晶体管Q5形成基准电压产生单元中的运算放大器，其运放增益约为A1＝gm4·(ro3||ro5)，其中，ro3表示第三晶体管Q3的漏源小信号输出 阻抗，ro5表示第五晶体管Q5的漏源小信号输出阻抗，gm4表示第四晶体管Q4的跨导，且第四晶体管Q4的跨导与第五晶体管Q5、第九晶体管Q9的跨导相等。可以看出，基准电压产生单元为电压串联负反馈，电压闭环输出阻抗是开环输出阻抗的1/A1倍，因此，输出的带隙基准电压的驱动力较高。
在一个示例中，第二晶体管Q2、第四晶体管Q4、第八晶体管Q8、第九晶体管Q9、第十晶体管Q10形成基准电流产生单元的运算放大器，其运放增益约为A2＝gm4·(ro8||ro9)，其中，ro8表示第八晶体管Q8的漏源小信号输出阻抗，ro9表示第九晶体管Q9的漏源小信号输出阻抗。可以看出，基准电流产生单元为电流串联负反馈，电流闭环输出阻抗是开环输出阻抗的A2倍。
本公开实施例的基准电压产生单元、基准电流产生单元通过共用第一电流产生单元10、且共用第二晶体管Q2和第四晶体管Q4，可以实现在一个电路中产生两种带隙基准(带隙基准电压和带隙基准电流)，相较于相关技术中不采用运算放大器实现基准源，本公开实施例通过双运放环路，可以实现高增益双环路同时工作，成本较低且占用版图面积小。且，本公开实施例的基准源电路，带隙基准电压的驱动力较高，带隙基准电流的输出阻抗较大，有利于提高工作效率。
如图2所示，第六晶体管Q6及第三电阻R3，与第十一晶体管Q11及第七电阻R7形成了电流镜，因此基准电流产生单元30可以利用第一电流I PTAT得到带隙基准电流IBG＝I CTAT+I PTAT，其中，ICTAT表示流经第八电阻R8的电流，其中
Figure PCTCN2020132741-appb-000004
因此，可以得到
Figure PCTCN2020132741-appb-000005
其中，V BE表示所述第六晶体管Q6的基射电压，V BE为负温度系数，R8表示所述第八电阻R8的阻值，R4表示所述第四电阻R4的阻值，R5表示所述第五电阻R5的阻值，V T表示温度的电压当量，V T为正温度系数，n表示第七晶体管与第六晶体管的个数比值。
本公开实施例可以通过调整第八电阻R8和第四电阻R4的电阻值，以实 现带隙基准电流IBG的零温度系数。
当然，本公开实施例对第八电阻R8和第四电阻R4具体阻值不做限定，本领域技术人员可以根据实际情况设定。
在一种可能的实施方式中，本公开可以设置第三电阻R3、第四电阻R4、第五电阻R5、第七电阻R7满足以下关系，以使得本公开实施例中更好的输出带隙基准电压和带隙基准电流：
所述第三电阻的阻值等于所述第四电阻与所述第五电阻的并联的电阻值，所述第四电阻的阻值等于所述第七电阻的阻值，即，R3＝R4||R5，R4＝R7，其中，R3表示所述第三电阻，R4表示所述第四电阻，R5表示所述第五电阻，R7表示所述第七电阻。
通过以上电路，本公开实施例可以在一个电路中同时产生零温度系数的带隙基准电流和带隙基准电压，相较于相关技术，成本较低、且占用版图面积较小，有利于推广利用。
以上已经描述了本公开的各实施例，上述说明是示例性的，并非穷尽性的，并且也不限于所披露的各实施例。在不偏离所说明的各实施例的范围和精神的情况下，对于本技术领域的普通技术人员来说许多修改和变更都是显而易见的。本文中所用术语的选择，旨在最好地解释各实施例的原理、实际应用或对市场中的技术的改进，或者使本技术领域的其它普通技术人员能理解本文披露的各实施例。

Claims (8)

  1. 一种基准源电路，其特征在于，所述电路包括：
    第一电流产生单元，用于产生第一电流；
    基准电压产生单元，电连接于所述第一电流产生单元，用于利用所述第一电流产生带隙基准电压；
    基准电流产生单元，电连接于所述第一电流产生单元及所述基准电压产生单元，用于利用所述第一电流产生带隙基准电流。
  2. 根据权利要求1所述的电路，其特征在于，所述基准电压产生单元包括第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第一电阻、第二电阻、第三电阻、第一电容、第二电容，其中：
    所述第一晶体管的漏极电连接于所述第二晶体管的源极、第三晶体管的源极及电压源，所述第一晶体管的栅极电连接于所述第二电阻的第一端、所述第三晶体管的漏极、所述第五晶体管的集电极及启动电路，用于接收启动电路输出的启动信号，所述第一晶体管的源极电连接于所述第一电阻的第一端、所述第一电容的第一端、所述第二电容的第一端，所述第一晶体管的源极用于输出所述带隙基准电压，
    所述第一电容的第二端、所述第一电阻的第二端电连接于所述第一电流产生单元，
    所述第二电阻的第二端电连接于所述第三电容的第一端，
    所述第二晶体管的漏极电连接于所述第二晶体管的栅极、所述第三晶体管的栅极、所述第四晶体管的集电极，
    所述第三电阻的第一端电连接于所述第一电流产生单元，
    所述第五晶体管的基极、所述第四晶体管的基极电连接于所述第一电流产生单元，
    所述第五晶体管的射极、所述第四晶体管的射极、所述第三电阻的第二端、所述第二电容的第二端接地。
  3. 根据权利要求2所述的电路，其特征在于，所述第一电流产生单元包括第四电阻、第五电阻、第六晶体管、第七晶体管，其中：
    所述第四电阻的第一端电连接于所述第一电容的第二端、所述第一电阻的第二端、所述第五电阻的第一端、所述第六晶体管的基极，所述第四电阻的第二端电连接于所述第六晶体管的集电极、所述第七晶体管的基极、所述第四晶体管的基极，
    所述第五电阻的第二端电连接于所述第七晶体管的集电极、所述第五晶体管的基极，
    所述第六晶体管的射极、所述第七晶体管的射极电连接于所述第三电阻的第一端，
    其中，所述第六晶体管的集电极用于产生所述第一电流。
  4. 根据权利要求3所述的电路，其特征在于，所述基准电流产生单元包括所述第二晶体管、所述第四晶体管、第八晶体管、第九晶体管、第十晶体管、第十一晶体管、第十二晶体管、第十三晶体管、第五电容、第六电阻、第七电阻、第八电阻，其中：
    所述第八晶体管的栅极电连接于所述第二晶体管的栅极，所述第八晶体管的源极电连接于所述第二晶体管的源极、所述第十二晶体管的源极、所述第十三晶体管的源极，所述第八晶体管的漏极电连接于所述第九晶体管的集电极，
    所述第九晶体管的基极电连接于所述第十晶体管的源极、所述第十一晶体管的集电极、所述第八电阻的第一端，
    所述第十晶体管的栅极电连接于所述第六电阻的第一端、所述第九晶体管的集电极、所述第八晶体管的漏极，所述第六电阻的第二端电连接于所述第五电容的第一端，所述第十一晶体管的基极电连接于所述第四电阻的第一端、所述第五电阻的第一端、所述第六晶体管的基极及所述第一电容的第二端，所述第十一晶体管的射极电连接于所述第七电阻的第一端，
    所述第五电容的第二端、所述第九晶体管的射极、所述第七电阻的第二端、所述第八电阻的第二端接地，
    所述第十二晶体管的栅极电连接于所述第十二晶体管的源极、所述第十 三晶体管的栅极、所述第十晶体管的漏极，
    所述第十三晶体管的漏极用于输出所述带隙基准电流。
  5. 根据权利要求4所述的电路，其特征在于，所述第三电阻的阻值等于所述第四电阻与所述第五电阻的并联的电阻值，所述第四电阻的阻值等于所述第七电阻的阻值。
  6. 一种芯片，其特征在于，所述芯片包括：
    如权利要求1～5任一项所述的基准源电路。
  7. 一种电源，其特征在于，所述电源包括：
    如权利要求6所述的芯片。
  8. 一种电子设备，其特征在于，所述电子设备包括：
    如权利要求7所述的电源。
PCT/CN2020/132741 2019-12-09 2020-11-30 基准源电路、芯片、电源及电子设备 WO2021115148A1 (zh)

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